Deeply Scaled CMOS for RF Power Applications
by
J*rg Scholvin
B.S., Massachusetts Institute of Technology (2001)
M.Eng., Massachusetts Institute of Technology (2001)
Submitted to the Department of
Electrical Engineering and Computer Science
in Partial Fulfillment
of the Requirements for the Degree of
MASSACHUISETS INSTITUTE
OF TECHNOLOGY
Doctor of Philosophy
NOV 0,2 2006
at the
LIBRARIES
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2006
© 2006 Massachusetts Institute of Technology. All rights reserved.
Author
1% I
0
s
Department of Electrical Engineering and Computer Science
May 23 2006
Certified by
.. ..
Jesuis A. del Alamo
essor of Electrical Engineering
Thesis Supervisor
Certified by
Arthur C. Smith
Chairman, Department Committee on Graduate Thesis
ARCHIVES
Deeply Scaled CMOS for RF Power Applications
by
J6rg Scholvin
Submitted to the Department of Electrical Engineering and Computer Science in Partial
Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electrical
Engineering
Abstract
The microelectronics industry is striving to reduce the cost, complexity, and form factor of wireless systems through
single-chip integration of analog, RF and digital functions. Driven by the requirements of the digital system
components, the 90 nm and 65 nm technology nodes are currently emerging as platforms for highly integrated
systems. Achieving such integration while minimizing the cost of adding specialized RF modules places high
demands on the base CMOS technology. In this regard, the integration of the power amplifier (PA) function
becomes an increasing challenge as technology geometries and supply voltages scale down. Gate length (Lg) scaling
yields improved frequency response, promising higher power-added efficiency (PAE), a key RF PA consideration.
This benefit comes at the cost of a lower drain voltage, which demands a higher output current and thus wider
devices in order to produce a given output power level (Po,,).
In this work, we have investigated the potential of deeply scaled CMOS for RF power applications, from 0.25 um
down to 65 nm. We demonstrate the frequency and power limitations that the different CMOS technologies face,
and describe the physical mechanisms that give rise to these limitations. We find that layout considerations, such as
splitting a single large device into many smaller parallel devices, become increasingly important as the technology
scales down the roadmap, both for power and frequency. We also show that parasitic resistances associated with the
back-end wiring are responsible for placing an upper limit on the RF power that can be obtained for a single bond
pad.
We demonstrate a power density of 31 mW/mm for the 65 nm node, with PAE in excess of 60% at 4 GHz and 1 V.
Similar results are obtained in 90 nm, where a peak PAE of 66% was measured at 2.2 GHz and 1 V, with a power
density of 24 mW/mm.
We find that efficient integrated PA functionality for many applications can be achieved even in a deeply-scaled
logic CMOS technology. For low power levels (below 50 mW), we find that the 65 nm CMOS devices offer
excellent efficiency (>50%) over a broad frequency range (2-8 GHz). Their RF power performance approaches that
of 90 nm devices both in peak PAE and output power density. This is possible without costly PA-specific add-ons,
or the use of higher voltage input-output (I/O) device options. However, since I/O devices are often included as part
of the process, they represent a real option for PA integration because they allow for higher power densities. The
0.25 /im I/O device that is available in the 90 nm process, when biased at Vdd = 2.5 V showed excellent results, with
a peak PAE of 60% and an output power of 75 mW (125 mW/mm) at 8 GHz.
Thesis Supervisor: Jesuis A. del Alamo
Title: Professor
Acknowledgements
The past several years working on this thesis have been an amazing experience of learning and
del
working with extraordinary people. I would like to thank my thesis advisor, Prof. Jesus
and
Alamo, for giving me the privilege to work in his group and to learn from him the skills
been an
knowledge I have acquired in the past years. Being able to learn from a great teacher has
invaluable resource.
for
I would also like to thank my thesis readers, Prof. Joel Dawson and Prof. Charles Sodini
thesis. I
providing valuable guidance that helped me to improve the work presented in this
deeply appreciate the feedback and suggestions that I have received.
This work would not have been possible without the generous support of IBM, through the PhD
del
fellowship program and faculty awards. I would like to thank my mentor at IBM and former
tireless
Alamo student, David Greenberg, for making this collaboration possible through his
Jack
efforts and help. I also want to thank David Harame, Scott Parker, Greg Freeman and
IBM
at
Pekarik for their enthusiastic support of the project. I have spent three summers working
Burlington VT, and Fiskill NY, on projects directly related to this thesis. Among the many great
device
people I have met at IBM, I would like to thank Susan Sweeney and Jae Rascoe for their
measurement expertise, and Ramana Malladi for many interesting conversations about my work.
I want to thank everyone in the del Alamo research group for their support, inputs and outputs:
former students Jim Fiorenza and Samuel Mertens, Niamh Waldron, Joyce Wu, Anita
Villanueva, Melinda Wong, Jungwoo Joh, and post-doc's Tetsuya Suemitsu and Dae-Hyun Kim,
as well as visiting scientist Joerg Appenzeller. They helped to make the office- and lab-life
enjoyable.
I would like to thank my wife Sylvie for being there for me and understanding the sometimes
erratic work-schedule of a graduate student.
And sometimes, great wisdom can be found in the most unexpected places:
0 A.
...
.........
Contents
1. Introduction
1.1. Literature Background: State of the Art
1.2. Application Space for RF Power CMOS
1.3. Thesis Goals
1.4. Outline
2. Experimental
2.1. Technology Description
2.2. Device Layout
2.3. DC and S-Parameter Characterization
2.4. Power Characterization
3. 90 nm Technology
3.1. Results
3.1.1. RF Power Performance of the 90 nm Logic Device
3.1.2. RF Power Performance of Other Device Options
3.2. Discussion
3.3. Conclusion
4. 65 nm Technology
4.1. Experiments
4.2. Discussion
4.3. Technology Scaling: 65, 90 and 250 nm
5. First Order RF Power Model
5.1. Model Structure
5.2. Parameter Extraction
5.3. Model Results
6. Discussion
6.1. Frequency and Power Limits of
65 nm, 90 nm and 250 nm technologies
7. Conclusions
Appendix
A Power Measurement Theory
89
B Load-pull Setup
101
C Device Library
105
Bibliography
117
List of Figures
1.1
Number of power-amplifier research results published in IEEE journals and conferences in 1993 (top) and
2003 (bottom), by materialand device types. In 2003, 16% of the overall activity was taking place in CMOS
technology.
1.2
Research activity as a function of time by material(left) and within silicon (right) by device type.
1.3
Power density as a function of bias voltage. Boundaries of different materials and device types are shown.
CMOS is able to operate at voltages below 5 V, and demonstrates power densities comparable to the other
materials.
19
Physical gate length of CMOS power devices and amplifiers, as a function of time, for IEEE published
research. The trend towards scaling the gate exists even in RF power CMOS, as the data suggests. The
CMOS technology nodes are marked by the arrows. Shorter gates generally result in higher gain (through
transconductance)and therefore better efficiency and performance - though at the cost of reduced bias
voltage and output power (see Figs. 1.3, 1.5).
19
Physicalgate length as a function of operationfrequency for CMOS RF power devices and amplifiers. Device
operationat higherfrequencies requires a shortergate, as can be seen from the data.
17
18
1.4
1.5
20
1.6
Impact of gate length scaling on power added efficiency for class A to B devices, in a selected frequency
band. Efficiency improves with shorter gates, due to higher transconductance and improved gain and
frequency response. Data includes MESFET and HEMT type devices.
20
1.7
Overview of the different applications that require RF power. The sketch shows the broad range of
frequencies and power levels that are required in different applications.
22
1.8
Technology landscape in the frequency-power space. Silicon based technologies occupy the low frequency
regions, while compound semiconductors are used for higherfrequencies and power levels.
1.9
2.1
2.2
22
Illustration of how RF CMOS devices exhibit limitations of power andfrequency. The goal of this thesis is to
identify these limits, and study how they can be pushed out.
26
Vertical drain layout (source = red, drain = blue, gate=green).The structure is symmetric, and only half is
shown. The symmetry plane is indicated.The layout design is patentpending.
29
DC sweep for the standard90 nm device (1x48x16 pm), with Vgs from 0.4V to 1V in 0.1V steps.
30
2.3
2.4
S-parameters (0.5-50 GHz) for the standard90 nm device (1x48x16 pm), biased at Vds=1V, Vgs=0.58V. S11
and S22 are plotted on the left, and S21 and 50 times S12 are plotted on the right.
31
A typical power sweep, showing the power added efficiency (PAE) and the transducergain, as a function of
the measured output power. This measurement shows the 65 nm standarddevice (768 Am width), at 4 GHz in
class AB bias.
33
3.1
Power performance at 2.2 GHz of a thin-oxide 90 nm device (1x48x16 Am) and a device array (8x48x16 Am),
both biased at Vdd = 1 V and Id = 26 mA/mm. Impedances were optimized for the best linearity-efficiency
tradeoff.
37
3.2
Peak PAE and output power at peak PAE as a function offrequency for the standard90 nm device (1x48x16
Alm). All measurement points were taken at Vdd = I V, Id = 26 mA/mm, and impedances were reoptimized at
eachfrequency. The output power is roughly independent of frequency, while the peak PAE is dropping as
the frequency increases.
3.3
Gain, PAE and output power density at peak PAE point as a function of Vdd for thin oxide devices of three
different gate lengths at 8 GHz. Impedances and input power drive were re-optimized at each Vddfor each
device.
3.4
Gain, PAE and output power density at peak PAE as a function of Vddfor 250 nm devices with three different
gate oxide thicknesses at 8 GHz. Impedances and input power drive were re-optimized at each Vddfor each
device.
3.5
Gain, PAE and output power density at peak PAE point as a function of Vdd when scaling both L, and gate
oxide thickness at 8 GHz. Impedances and input power drive were re-optimized at each Vddfor each device.
3.6
Comparison of the 90 nm thin and 250 nm thick oxide devices. Both devices can achieve similarpeak PAE
levels, though at different operating voltages and power densities, as indicated.
3.7
Comparison off,, for the devices in Table I operating at Vnomina. Small width devices (right axis) with their
pad parasiticsde-embedded offer a peak f, of 100 to 200 GHz. The f,. of the power devices (left axis) used
in this paperare not de-embedded, and show a much lower f,, due to the class AB bias (Id = 26 mA/mm) and
the parasiticsassociatedwith the pads, the large number offingers and their width (e.g. R, and Cgd).
3.8
Load-line comparisonfor the 90 nm thin and 250 nm thick oxide devices. MeasuredDC I-V characteristicsof
the two devices are shown, with the approximate Vd,,sa indicated. The 90 nm device's Vds,sat is lower than that
of the 250 nm device. Load-lines, based on the impedances used in the power measurements of Fig. 3.5, are
also shown at Vdd = 1V and 2.5V.
38
40
41
42
42
43
45
4.1
4.2
Power characteristicsof two 65 nm devices with a total gate width of 768 lm at 4 GHz. The 12 cell device
delivers a peak PAE of 65.7% at a power of 13.8 dBm (31.2 mW/mm) at a voltage of 1 V.
50
Power performancefor the 12x16x4 Alm, 65 nm device at 8 GHz vs. Vd. For each Vdd the device is tuned to
peak PAE. The gain is the small signal gain.
51
4.3
Output characteristicsof the 12x16x4 pm, 65 nm device for V, = 0.2 to 1 V in 0.2 V steps. Forsmall values
of Vgs and high values of Vds, impact ionization effect can be seen. Overlapping the device characteristicsis
the load line correspondingto a biaspoint of I V.
4.4
Performanceof a 65 nm device (12x16x4 tm) as a function of bias current. Idq is the quiescent drain current
(no Pin), and Id is the drain currentat peak PAE. The device is self biasing and the peak PAE, Pout and Gain
do not change much with bias current.
4.5
Powerperformance as a function of device size for 65 nm devices (1, 2, 3, 4 and 6 parallelcells of 64x12 Alm
each) and 90 nm devices (1, 2, 4 and 8 cells of 48x16 Atm). As the number of cells and thus device width
increasesfor the 65 nm devices, PAE drops while Pout saturates. The behavior of 90 nm is very different as
Pout continues to increase with device size. Given the independence of power on frequency over the range that
is studied in this work (see Fig. 4.13), we have included a data pointfor a very wide 90 nm device (6.1 mm)
that was measuredat 2.2 GHz.
52
52
53
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
5.1
(a, left) Simplified model schematic to create a multi-cell device from a number of single cell devices (b,
right). The intrinsic device cells of the single cell and the multi-cell device are identical. Adding parallel
single cell devices requires parasitic resistances to match the increased wire resistance of the multi-cell
device's backend. The model parameterswere extracted using S-parametermeasurementsfrom a single cell
and the multi-cell device.
54
Y11 comparison of a two-cell device (2x48x16 Am) with the model. When using two parallel 1x48x16 Am
device measurements, the match with the two-cell device is mediocre. Adding parasiticresistances on the
source, gate and drain,as shown in Fig. 4.6b, results in a much better match with the two-cell measurements.
The other Y-parameters exhibit a similarpicture and are omitted to preserve clarity in the graph.
54
Small signal extracted parasitic scaling resistances (R, and Rs+Rd). To construct a multi-cell device from
single-cell devices, these resistance must be added into the single cell unit (NFx WF = 48x12 ALm = 768 jm)
as shown in Fig. 4.6b.
56
Model of the peak PAE (left) and Pou, performance (right) with scaling, matched to the 768 jm device, and
using the resistances from Fig. 4.8. The graph also shows the ideal scaling behavior, as well as that of
reducing the extracted resistance by 50%.
57
Correlation of peak PAE with f m,, (extracted at Vgs = 0.4 V and Vds= V) for the 5 different 65 nm device
sizes (each cell is a 65 nm device of 64x12 im), as well as the optimized device layout (12 cells 16x4 jlm
devices)
60
f,,, vs. unit finger width for a 1 cell device, keeping overall width the same (NF x WG,F = 768 jm). Large
finger width hurts fm,a because of R,. Narrow finger width hurts because of distributedeffects involving the
large number of device fingers that must be parallelized.
60
Breaking the 65 nm device up into multiple cells in parallel, both the number offingers and their unit width
are scaled down at the same time. This method can achieve higherf,,, values (51.4 GHz vs. 43.7 GHz) at
identical bias conditions. However, too many cells in parallel hurt performance due to the excessive wiring
required,as seen by the drop in fm,x as the number of cells increases beyond 50.
61
Performance comparison of the 90 nm and 65 nm devices as a function of frequency. Both devices have a
total width of :768 Am (65 nm: 64x12 Am and 90 nm: 48x16 jLm). The output power is independent of
frequency, and essentially identical for both devices, while the peak PAE for this 65 nm device is slightly
lower.
62
Peak PAE and output power density at 8 GHz as afunction of Vddfor three different CMOS technologies
64
DC characteristicsof the 90-nm device (1x48x16 Am) with indicated load-lines. The model mustfocus on the
device regions that the load-line occupies. The DC data shows self heating effects for high Vds, Id values.
68
5.2
Full device model (top) and simplified equivalent model (bottom). The R-C networks on the drainand gate
are simplified into a singlefrequency dependent resistor. The assumption is that the reactive components of
the device are resonatedout by the source and load impedances. The other model elements include the
currentgenerator(k, VT, exp), the breakdown voltage (BV) and the on-resistance(Ron).
69
5.3
Examplefit of the subthresholdcurve at Vds= IlV, for the 90 nm device. The extracted values for VT, k and exp
are shown in Table 5.1.
71
5.4
Measuredoutput resistance (Real(Y22)) as a function of Vgs, for two frequencies at Vd= I V. The data shows
that Ro is bias dependent. The model assumes a bias-independentRdo• Choosing a constant value around
threshold (indicated)provides the best compromise.
72
5.5
Measuredinput resistance (Real(Y11)) as a function of Vg, for two frequenciesat Vds= 1 V. The data shows
that Rgs is largely bias independent. Model parameters were chosen at V,= VT.
72
5.6
Model performance comparison with measuredpowerperformance, as a function offrequency. The model
uses the parametersof Table 5.1. The model for each technology roughly matches the behavior of the data.
The output power is frequency independentup to very high frequencies, while the peak PAE decreases.
74
5.7
6.1
6.2
6.3
6.4
7.1
Model performance compared to the 65 nm device scaling measurements. Depending on the parasitic
resistancefor the overall device, the drop in peak PAE and the maximum output power can vary significantly.
The model assumes a constant backend resistance that does not scale with the number of cells.
74
Constant PAE contours illustrating the output power that can be achieved at a given frequency. The higher
the desired PAE, the lower the power and frequency. The power has an upper limit set by the backend
parasitics,while the frequency has an upper limit related to the device gain andf,,• The values in the graph
are based on the 90 nm technology, which we expect to be able of delivering 140 mW of power (Pat,) with a
maximum power at Nc.sa,=12 , and a maximum operatingfrequency of 21 GHz (fa).
80
Impact of device layout on the device fn,,. The standardsingle cell device is shown in the solid bars. Using
an optimized device layout by breaking the device up into multiple smaller cells, f,,a can be improved
significantly. This becomes more critical as the technology is scaled down.
82
Estimated contour of 50% peak PAE, for three different technologies, illustrating the power vs. frequency
behavior. The estimates are based on extrapolationof measureddata. The limited power of the 65 nm device
in chapter 4 can be expected to improve with a different layout design (shown as dotted lines).
82
Estimated 50% peak PAE contours, from Fig. 6.2, redrawn taking the device layout optimization into
account. Layout optimization can help to push out the frequency limit for the PA device. The 65 nm
technology profitsfrom optimized layout the most, as seen in Fig. 6.3.
84
Expected 50% peak PAE contours, from Fig. 6.4. This figure assumes an optimized backend layout for
the 65 nm devices, resulting in an improved width scaling. We expect the maximum power of the 65 nm
devices to come close to that of the 90 nm devices.
88
List of Tables
2.1
3.1
3.2
4.1
5.1
Key device and process parametersfor thefour device types in this thesis
28
Gate length, oxide thickness and gate dimensionsfor the devices characterizedin this work. The device size
refers to the number offingers x unitfinger width. Sizes have been chosen to give identical drive current
for the 90 nm thin-, 130 nm medium-, and 250 nm thick-oxide devices.
36
Performance comparison of standard 90 nm device and a parallel combination of 8 standard devices.
Impedances were optimized for the best linearity-efficiency tradeoff.
36
Overview of the devices used in this chapter,fabricated in either 65 or 90 nm technologies. The gate length
refers to the equivalentpolysilicon halfpitch dimension.
49
Model parametersextractedfrom DC measurements,for the 65 nm and 90 nm technologies.
71
Chapter 1.
Introduction
This work will perform a detailed comparative study of the RF power potential of CMOS
technology. The broader context of this research is the attractiveness of using logic CMOS as a
platform for wireless system-on-chip applications. This enables true single-chip solutions for
portable wireless systems with significant consequences in form factor and module design. Logic
CMOS is the ideal platform for system-on-chip integration. Logic CMOS is the lowest cost
technology, and the digital baseband in wireless systems is already being implemented in logic
CMOS. CMOS modeling, simulation, design and verification tools are very mature and broadly
available. Additionally, CMOS designs port relatively well from fab to fab and generation to
generation. Particularly important for RF wireless systems, great progress has been shown
recently in enabling RF functions with CMOS. Not surprisingly, there is a lot of interest in
exploring the RF potential of logic CMOS.
The microelectronics industry is striving to reduce the cost, complexity, and time to market of
wireless systems through single-chip integration of mixed-signal RF/digital functions. Achieving
such integration, while minimizing the increased cost of technology add-ons, places high
demands on the base CMOS technology. In this regard, the integration of the power amplifier
(PA) function remains a particular challenge as technology geometries scale down.
Over the past decade, silicon technology has made a strong entry into the RF power amplifier
field.
Figure 1.1 shows the growth of silicon and CMOS in published research on device
technologies for RF power amplifiers. In the commercial sector, CMOS has captured substantial
market share for RF power amplifier applications. These include portable wireless systems, such
as bluetooth and wireless LAN. The use of CMOS is because of cost and integration pressure.
With cost a central issue in most high-volume applications, the digital portions of these
applications will continue to be scaled down. As one example, the migration of CDMA chipsets
onto 65 nm started in 2005. While this migration takes place only for the digital chips, it shows
that any future integration requires the analog/RF chips to be implemented in deeply scaled
technologies.
Through a combination of detailed RF power characterization and analysis, in this thesis, we
will study the RF power performance of deeply scaled CMOS, and determine its performance
limits. We focus on conducting as opposed to switching type amplifiers. We will consider both
the standard digital devices of each node, as well as available 1/O (thick gate oxide) devices. The
answers to this study are necessarily complex because this is a multidimensional space: power
level, frequency, linearity, power efficiency and reliability.
1.1.
Literature Background: State of the Art
To better illustrate the role of CMOS in RF power amplifiers, we have conducted a literature
study of IEEE publications concerning power amplifiers operating in the RF above 900 MHz.
Results from over 950 papers spanning the past 40 years were collected.
Fig. 1.1
Number of power-amplifier research results published in IEEE journals and conferences in
1993 (top) and 2003 (bottom), by material and device types. In 2003, 16% of the overall activity
was taking place in CMOS technology. [31-1006]
The growing importance of silicon based power amplifiers can be seen in Figs. 1.1 and 1.2.
Between 1993 and 2003, the portion of silicon based power amplifiers in publications has taken a
substantial share of the overall PA research. CMOS based power amplifiers make up about 50%
of the PA activity taking place in silicon today (Fig. 1.2b). Clearly offering the cheapest and
most integratable technology, CMOS also is able to deliver performance at low voltages [1]. Fig.
1.3 shows the power density as a function of the bias voltage for a variety of semiconductor
technologies. CMOS is competitive with respect to the other technologies such as GaAs HEMT
and MESFETs, up to about 3 Volts. With the sharp increase in portable consumer electronics
operating at frequencies below 5 GHz and voltages below 3V, CMOS has become an important
candidate for integrated PAs, able to challenge competing technologies. Currently, research is
mostly focused on circuit design techniques, such as linearization techniques and integrated
transceivers [2-4]. Much less research has been done on CMOS technology itself [5-7]. This is
the object of this work.
The trend towards scaling of RF power CMOS is apparent from Figs 1.4-1.6. Over time,
publications concerned with power CMOS have continued to follow the CMOS roadmap and
used shorter gate lengths (Fig. 1.4). There are two important reasons why scaling makes sense.
First, as the gate length is scaled down, operation at higher frequencies is possible (Fig. 1.5). In
addition, scaling holds benefits even if the frequency of operation is not changed, as shown in
Fig. 1.6. Due to the increase in transconductance and power gain that comes with shorter
channels, scaled devices achieve higher power added efficiency and improved performance [1].
Inn
-
Research Activity in Silicon
40
> 75o.
-
30-
N Si BJT
SiGe HBT
LDMOS
S CMOS
SS
S50-
by Device Type
-
20a-
250
10E
0-
Year
SI'#'ill Ill
Fig. 1.2a (left), 1.2b (right)
Research activity as a function of time by material (left) and within silicon (right) by device
type. [31-1006]
4 r~r.
IUU
E
10
E
Si
,
0.1 -
o
0..
0.001
0
0
0.0001
··
0.1·
10
0.1
100
Vdd [V]
Fig. 1.3
Power density as a function of bias voltage. Boundaries of different materialsand device types
are shown. CMOS is able to operate at voltages below 5 V, and demonstrates power densities
comparable to the other materials.[31-1006]
IU.UU
CMUS Scaling
1.00
0
o
0o o o
S
-
0.35 pm
o *--
0.25 pm
-So-
0.10
0.01
1990
o
-
1995
2000
0.18pm
0.13 pm
90 nm
2005
Year
Fig. 1.4
Physical gate length of CMOS power devices and amplifiers, as a function of time, for IEEE
published research. The trend towards scaling the gate exists even in RF power CMOS, as the
data suggests. The CMOS technology nodes are marked by the arrows. Shorter gates generally
result in higher gain (through transconductance) and therefore better efficiency and
performance- though at the cost of reduced bias voltage and output power (see Fig. 1.3, 1.5).
~n nn
IU.00
1.00
¢•
-. ~f-lg
0 "-.
06 4,,
0.10
o
0
4,
o
0.01
4,
·
1.0
10.0
Frequency [GHz]
Fig. 1.5
Physical gate length as a function of operationfrequency for CMOS RF power devices and
amplifiers. Device operation at higherfrequencies requires a shortergate, as can be seen from
the data.
60
Impact of Scaling on Efficiency
(27 GHz < freq < 50 GHz)
-
8
.40
I6
-
4,1Q
( 20
-
4,
S
0
i
0.0
0.2
0.4
0.6
0.8
1.0
LG [um]
Fig. 1.6
Impact of gate length scaling on power added efficiency in a selected frequency band.
Efficiency improves with shorter gates, due to higher transconductanceand improved gain and
frequency response. Data includes MESFET and HEMT based amplifiers.
1.2.
Application Space for Power Amplifiers
Two of the most important requirements for a power amplifier are the output power
level and the frequency of operation.
We would like to illustrate the application
demands on these two parameters. Fig. 1.7 shows this, by sketching the current RF
power application landscape into the frequency-power space. The applications span 1100 GHz in frequency, and 10 mW to 100 W in output power level. Because of this
broad range of frequencies and power levels, no single one technology dominates this
space. In Fig. 1.8 we overlap technologies shown in the previous section (Fig. 1.1) onto
this space. Silicon based technologies dominate the low frequency space, with CMOS
occupying the low power, low frequency corner. LDMOS devices are suitable to higher
power levels, and SiGe HBTs allow for higher frequencies.
100
10
1
0.1
AV.,A I
'""'''
'
'
'
"""
`
"""'
10
100
"~-"'
1000
Frequency [GHz]
Fig. 1.7
Overview of the different applicationsthat require RF power. The sketch shows the broadrange
offrequencies andpower levels that are requiredin different applications.
100
10
1
0.1
U.V I
10
100
1000
Frequency [GHz]
Fig. 1.8
Technology landscape in the frequency-power space. Silicon based technologies occupy the low
frequency regions, while compound semiconductors are used for higherfrequencies and power
levels.
1.3.
Thesis Goals
This thesis is attempting to develop fundamental understanding about the RF power potential
of logic CMOS. Through a combination of detailed RF power characterization and analysis, we
wish to answer the following questions:
* What is the RF power potential of logic CMOS?
* How does the RF power performance of CMOS evolve
as the technology is scaled down the road map?
* What is the impact of device layout on RF power performance?
The answers to these questions are necessarily complex because this is a multidimensional
space: power level, frequency, power efficiency, layout considerations and device biasing
choices.
Fig. 1.9. illustrates this goal.
We would like to identify the boundary of RF CMOS to
accomplish the power amplifier function, both in terms of frequency and output power. In
addition, the goal is to identify methods to push out these boundaries.
We will accomplish the goals mentioned in the introduction by studying a variety of aspects
which combined will give an excellent insight into RF power capability of deeply scaled CMOS:
A
Technology
Our evaluation will focus on the 90 nm and 65 nm nodes. We will study different device options
commonly available at these nodes: thin/medium/thick gate oxides (equivalent to 65 nm, 90 nm,
0.13 tm and 0.25 tpm devices), variation of gate length, and device layout variations. The
analysis will include measurement of power and efficiency. This will then enable us to quantify
the tradeoffs between the standard CMOS devices and more complex but potentially better
performing alternative devices.
B
Technology Scaling
By including various oxide thicknesses on a 90 nm wafer, we are essentially able to study
devices of the 90 nm, 130 nm and 250 nm nodes. In addition, devices from a 65 nm wafer allow
us to also study the 65 nm node. These two wafers give us a wide range of different technologies
along the CMOS roadmap. The impact of scaling on power added efficiency and output power
for conduction type amplifiers will be studied.
C
Layout Design
We will develop new device layouts to improve RF power performance. Important
considerations for developing RF power layouts are RF and DC parasitic concerns. The impact
of the layouts on performance and frequency response will be investigated.
D
Power Capability
We will study the ability of the technology to produce high output power by studying how device
size relates to performance. The output power can saturate with device size for several reasons,
such as gate resistance, self heating, inefficient power combining, and impedance mismatches.
We will study a wide range of device widths that should allow us to identify the limiting factors.
Different options of achieving large devices will be studied: changes in the device aspect ratio
(number of fingers / unit finger width), changes in total device width, and the effectiveness of
combining smaller devices (individual cells) to form a large total width device.
E
Frequency Capability
We will study how the performance degrades with frequency, as we approach fmax. This study
will not only show the range of frequency operation for the device, but also establish a relation
between fmax and a frequency giving acceptable device performance (e.g. good gain and PAE).
F
Modeling
In order to better understand the behavior of the observed power measurements, we will develop
a simple, physics based device model.
The model should capture the major dependencies
observed in the data, and help in estimating the capabilities of the different CMOS technologies.
1.4.
Outline
We will start by a brief description of the experimental setup in Chapter 2. This includes the
device layout, and the notations used to describe it, as well as the experimental setup for
performing the different measurements.
Chapter 3 will discuss the performance of 90 nm
devices, and studies the impact of gate oxide and gate length scaling.
It compares the
performance of 90 nm, 130 nm and 250 nm technologies. Chapter 4 studies the performance of
65 nm devices, and also addresses the question of output power scaling. It shows the importance
of device layout when scaling output power. A simple device model is developed in Chapter 5,
which allows us to describe all the major trends seen in Chapters 3 and 4. We will combine all
the results from the measurements and models in Chapter 6, which aims at illustrating the power
and frequency limitations of CMOS technology for RF power.
4hh#'
I-
10
r--
SAT
1:
I
-I
ac
a.
0.1
Deeply Scaled
• CMOS
"Performance
: Space
0.01
-- ,
0.1
i......
-,
-
m a i i.....
I
1
H
, ,
I
I
I
I
10
1
'I
100
I
I
I
I
I I I1 I
1000
Frequency [GHz]
Fig. 1.9
Illustration of how RF CMOS devices exhibit limitations of power and frequency. The goal of
this thesis is to identify these limits, and study how they can be pushed out.
Chapter 2.
Experimental
This chapter describes the devices and technologies used, as well as the types of experiments
carried out on them. I will first describe the device technologies used and the types of devices. I
will then broadly describe the three types of characterizations carried out on the devices: DC, Sparameter, and RFI power characterization. All measurements were performed on-wafer using
standard RF probes (ground-signal-ground).
2.1.
Technology Description
The technology that has been studied in this work is a foundry 90 nm and 65 nm CMOS
technology manufactured at IBM [6]. Table 2.1 shows the different devices fabricated. We will
label these devices by their ITRS equivalent technology node: Lg,inn = 65 nm, 90 nm, 130 nm
and 250 nm, with the understanding that the physical gate length will be below those values,
particularly at the 90 nm node. The 65 nm wafer has devices with a nominal gate oxide thickness
between 11 and 13
A and Lg,min = 65 nm (Vdd
= 1.0 V). For the 90 nm wafer, in addition to the
standard 90 nm NFET (Lg,min = 90 nm) with a nominal gate oxide thickness of 14
A (Vdd =
1.0
V), there is an intermediate oxide I/O FET (tox = 22 A, Lg,min = 130 nm) equivalent to a standard
130 nm node logic device (Vdd = 1.2 V), and a thick oxide I/O FET (tox = 51
A, Lg,nmn = 250 nm)
equivalent to that of the 250 nm node (Vdd = 2.5 V). Depending on the process details, the
additional mask count required to offer the I/O device options is between 1 and 3.
The 90 nm devices were taped out May 2003, when the technology was ramped up for
production. The 65 nm devices were taped out in August 2004, at which stage the
technology was still undergoing development. The presence of the I/O devices allowed
us to compare the performance of essentially four different CMOS technology nodes (65
nm, 90 nm, 0.13 ýtm and 0.25 Fam). The 0.13 [am medium oxide device, however, is not
completely independently optimized. It shares some process steps with the nominal
thin oxide 90 nm device. Therefore, it does not truly represent a 0.13 ý.m node, and its
performance may differ. Table 2.1 highlights the key process parameters for these
technologies:
Parameter
65 nm
90 nm
130 Ipm
0.25 ýtm
on 90 nm wafer
on 90 nm wafer
0.25 pm
ITRS Equivalent Node, Lgmin
Physical Lphysical
65 nm
40 nm
90 nm
63 nm
0.13 tm
120 nm
Oxide Thickness
11-13 A
14 A
22 A
Nominal Voltage
1.0 V
1.0 V
1.2 V
240 nm
52 A
2.5 V
Standard Cell (NFxWG,F)
64x12 pm 48x16 pm 34x16 pm
30x20 pm
Table 2.1. Key device and process parametersfor thefour device types in this thesis
2.2.
Device Layout
We have fabricated devices with a variety of layouts providing a broad range of total device
widths. The unit cell dimensions were given in Table 2.1. In general, the device layout consists
of several multi-finger device cells in parallel. The total device width (WG,TOT) is the product of a
number of parallel device cells (Nc), times the number of device fingers (NF) per cell, times the
unit finger width (WG,F). We will label devices as WG,TOT = NC X NF x WG,F.
Because the device fingers are very wide, electromigration concerns can arise due to the high
current densities. A standard multi-finger device layout was modified to allow for better current
flow in and out of the drain/source contacts, reducing the peak current within the device
metallization layers.
The layout uses a double-sided gate access to the device, as well as a
double sided source access. The drain is routed out vertically. This metallization is done with 4
levels of metal. Thicker levels are then used to route the gate, source and drain to the RF pads.
An illustration of the device layout is shown in Fig. 2.1.
plane of
symmetry
Fig. 2.1
Vertical drain layout (source = red, drain = blue, gate=green).The structure is symmetric, and
only half is shown. The symmetry plane is indicated. The layout design is patent pending.
2.3.
DC and S-Parameter Characterization
Measurements of the devices under DC conditions were performed at MIT using an HP4145B
parameter analyzer. A sample Id-Vds sweep is shown in Fig. 2.2. This data was taken for the
standard 90 nm device. S-parameter measurements were performed at IBM, on an automated
probe station up to 80 GHz. From the S-parameter measurements, ft and fmax estimates were
extracted. A typical S-parameter measurement result is shown in Fig. 2.3, for the 90 nm standard
device.
400
300
200
100
0
0
1
2
3
Vds [V]
Fig. 2.2
DC sweep for the standard90 nm device (1x48x16 tim), with Vgs from 0.4V to 1V in 0.1V steps.
The DC measurements exhibit self-heating, which can be seen by the higher Ro as Vgs increases.
Therefore, the Ro values seen in DC measurements for high Vgs and Id will differ slightly from
those relevant to the RF operation of the device.
50x S12
D
Fig. 2.3
S-parameters (0.5-50 GHz) for the standard 90 nm device (lx48x16 pIm), biased at Vds=lV,
Vgs=0.58V. S11 and S22 are plotted on the left, and S21 and 50 times S12 are plotted on the
right.
2.4.
Power Characterization
RF power characterization was carried out primarily at 8 GHz on a Maury load-pull system.
We chose 8 GHz for the bulk of our work to explore the high-frequency potential of deeply
scaled CMOS technologies. Measurements at higher frequencies also avoid device oscillations.
The higher the gain, the more susceptible the device becomes to oscillations. If the impedances
are tuned to maximize the gain at a high frequency, they will typically present a mismatch at
lower frequencies. As the gain drops with frequency, this helps to flatten the gain vs. frequency
behavior. This helps to avoid very high gain values at any frequency, and therefore reduces the
risk of oscillations. The measurement theory and system design is described in more detail in
Appendices A and B. The system creates a single RF frequency that is applied to the gate.
Mechanical tuners set the source (gate side) and load (drain side) impedances to the device. The
RF input and output power as well as the bias currents are measured, and allow computation of
the relevant figures of merit (Id,PAE, Gain, Pout, Pin).
Power measurements were optimized for peak PAE, by alternating source- and load-pull
measurements backed off a few dB from the input power level giving peak PAE. This
optimization was repeated for each change of device setup variables (for example, when
measuring the same device at different values of Vdd). A typical power measurement sweep is
shown in Fig. 2.4. As the device enters compression, the grain drops, while the output power
saturates. The PAE is defined as
PAE= out - Pin
Pdc
(Gain - 1)
Pout
Pd,
Gain
=
Eq. 2.1
Pc
where Pin and Pout is the RF power in and out of the device, and PDc is the DC power into the
device. As the input power is increasing, the PAE will rise. However, in compression the gain
drops as the output power is saturating. This will eventually result in the PAE beginning to drop,
reaching a maximum PAE typically between 1-5 dB in compression.
Often, we performed a series of power sweeps with one variable changing (e.g. frequency).
The results of this series of sweeps were reported as the peak PAE and output power at peak
PAE of each of the power sweeps.
Separately, we also performed linearity measurements for the standard 90 nm device at 2.2
GHz on an ATN load pull system, at IBM.
Throughout this thesis, we will be quoting the bias condition as a combination of Vds and Id.
The value of Idis the DC drain current without the presence of input power. This current is
achieved with a gate bias Vg. During the power measurement, this gate bias is held constant,
rather than the actual Idvalue. In conduction type amplifiers, it is common to observe that as the
input power is increased, the DC drain current measured into the device will also increase. The
origin of the self biasing is the non-linearity that enters when the input signal swings below the
device's threshold voltage [30]. While the average Vg remains at its bias value, swinging the
input below Vt will not result in a negative drain current, but rather in zero current. This
introduces the asymmetry.
While a swing to higher Vg will result in higher drain current,
swining Vg below Vt will not result in less (more negative) drain current. Therefore, the average
DC current increases, despite the fact that the average voltage on the gate is unchanged.
70
-
.
60
50
40
PAE
30
20
10
0
-10
-5
0
5
10
15
20
Pout [dBm]
Fig. 2.4.
A typical power sweep, showing the power added efficiency (PAE) and the transducergain, as a
function of the measured output power. This measurement shows the 65 nm standard device
(768 im width), at 4 GHz in class AB bias.
Chapter 3
90 nm Technology
The technology that has been studied in this work is a foundry 90 nm CMOS technology
manufactured at I]BM [8]. In addition to the standard 90 nm NFET with a nominal gate oxide
thickness of 14
A (Vdd =
1.0 V), there is an intermediate oxide I/O FET (tox = 22
A) equivalent to
a standard 130 nmn node logic device (Vdd = 1.2 V), and a thick oxide I/O FET (tox = 51
A)
equivalent to that of the 250 nm node (Vdd = 2.5 V). Additionally, devices with three different
gate lengths are available. We label these by the half pitch of their equivalent technology node:
90 nm, 130 nm and 250 nm, with the understanding that the physical gate length will be below
those values, particularly at the 90 nm node. Not all combinations of oxide thickness and gate
length are implemented. Table 3.1 gives all available device options. Depending on the process
details, the additional mask count required to offer these device options is between 1 and 3.
We have fabricated devices with a variety of layouts providing a broad range of total device
widths. The unit cell dimensions are given in Table 3.1. In general, the device layout consists of
several multi-finger device cells in parallel. The total device width (WG,TOT) is the product of a
number of parallel device cells (Nc), times the number of device fingers (NF) per cell, times the
unit finger width (WG,F). We will label devices as WG,TOT = NC X NF X WG,F.
Oxide Thickness
thin (nominal) (14 A)
medium (22 A)
thick (51 A)
1.0 V
1.2 V
2.5 V
Addl. Mask
0
1 to 3
1 to 3
48 x 16 jm
n/a
n/a
L, = 90 nm
34 x 16 tm
34 x 16 tm
n/a
L,= 130 nm
30 x 20 /m
30 x 20 m
30 x 20 m
L, = 250 nm
Table 3.1: Gate length, oxide thickness and gate dimensionsfor the devices characterizedin this
work. The device size refers to the number offingers x unit finger width. Sizes have been chosen
to give identical drive currentfor the 90 nm thin-, 130 nm medium-, and 250 nm thick-oxide
devices.
Nominal Vdd
90 nm Standard
Device
Bias
lx48x16 /m
8x48x16 im
Vdd = 1 V
Id= 25 mA
2.2 GHz
66 %
12.5 dBm
21.2 dB
25 dBm
14 %
6 dBm
11 dBm
Vdd = V
Id= 200 mA
2.2 GHz
59 %
20.2 dBm
14 dB
30 dBm
12 %
12 dBm
18 dBm
Frequency
Peak PAE
Pout at peak PAE
Small signal gain
OIP3
PAE at IM 3=-35dBc
Pot at IM 3=-35dBc
Pout at 1 dB
compression
Table 3.2: Performance comparison of standard 90 nm device and a parallelcombination of 8
standarddevices. Impedances were optimizedfor the best linearity-efficiencytradeoff
Power measurements were optimized for peak PAE, by alternating source- and load-pull
measurements backed off a few dB from the input power level giving peak PAE. This
optimization was repeated for each change of device setup variables (for example, when
measuring the same device at different values of Vdd).
Separately, we also performed linearity measurements at 2.2 GHz on an ATN load pull system.
Additionally, S-parameter measurements were performed up to 80 GHz.
3.1. Results
We will first discuss the RF power performance of the standard logic device (thin oxide, Lg= 9 0
nm), followed by a discussion of the performance impact of other device options that involve
scaling the gate oxide thickness (tox) and gate length (Lg). In the following section we discuss the
physical origin of the various results that have been obtained.
3.1.1.
RF Power Performance of the 90 nm Logic Device
The 2.2 GHz power performance of two standard digital 90 nm devices (biased at Vdd=1 V)
with different total[ gate widths is shown in Fig. 3.1, and summarized in Table 3.2. We compare
the performance of a single cell device (1x48x16 Im) to that of another device consisting of
70
0
60
-20
,.50
-40
< 40
M 30
-60
20
-80
10
-100
0
-30
-20
-10
0
10
20
30
Pout [dBm]
Fig. 3.1
Power performance at 2.2 GHz of a thin-oxide 90 nm device (1x48x16 /Am) and a device array
(8x48x16 iLm), both biased at Vdd = 1 V and Id = 26 mA/mm. Impedances were optimized for the
best linearity-efficiency tradeoff.
eight of these cells wired in parallel (8x48x16 Am), giving an eightfold increase in WG,TOT. For
the 1x48x16 Am device, a peak PAE in class AB operation of about 66% is obtained at an output
power of 12.7 dBm (18.6 mW, or 24.2 mW/mm). The 8x48x16 Am device achieved a peak PAE
of 59% at an output power of 20.2 dBm (104 mW, or 17.0 mW/mm), indicating a good scaling
of Pot with cell count. A slight decrease in PAE, power gain and output power density can be
seen. This indicates that an upper limit on power scaling exists. The PAE at linearity (in terms of
IM 3) of -35 dBc is 14% and 12% for the lx48x16 Am device and the 8x48x16 Am device,
respectively.
To put these results in context, a WCDMA power amplifier driver requires about 14 dBm at 1
dB compression power, with an OIP 3 of 24 dBm [9]. From Table 3.2 we see that the 8x48x16
Am device exceeds these requirements by a safe margin. The results of Table 3.2 suggest that 90
nm CMOS is quite suitable for a wide range of integrated PA
D
-
IV0
'out
Air=
80 10 m
.0
0
w
60
c
40 -
-
21.
-5
,"
0
20
1x4 8x16)
V dd=1 V, Id= 2 6 rA/mm
0 -
I
I
I
0
5
10
15
-0
20
Frequency [GHz]
Fig. 3.2
Peak PAE and output power at peak PAE as a function of frequency for the standard 90 nm
device (1x48x16 ALm). All measurement points were taken at Vdd = V, Id = 26 mA/mm, and
impedances were reoptimized at each frequency. The output power is roughly independent of
frequency, while the peak PAE is dropping as the frequency increases.
applications, such as WLANs, bluetooth and cellular PA drivers, giving acceptable efficiency
under linear conditions.
Measurements at 8 GHz for the standard 90 nm thin-oxide device at Vdd = 1 were also
performed. The standard device (1x48x16 rim) achieved a peak PAE of 56.8% at 13.4 dBm (21.9
mW, or 28.5 mW/mm) output power with an associated gain of 14.6 dB. These results at 8 GHz
are slightly better than the performance reported at 2.2 GHz above. This is due to using a
different measurement system that is able to present a better source and load match.
We have also measured the power performance of the standard device (1x48x16
rpm) as a
function of frequency. The results are shown in Fig. 3.2. The output power is constant with
frequency over a broad range, while the peak PAE is dropping with frequency. Operating the
device at higher frequencies reduces the power gain and results in lower peak PAE.
Across-wafer uniformity measurements of
18 devices were also performed. These
measurements were carried out with constant impedances, input power and bias points (Vdd = 1
V,ld = 26 mA/mm) at 8 GHz. The data includes both the probe contact uncertainty as well as the
device variation across the wafer. The device geometry used was lx96x8 Jim. Excellent
uniformity was obtained across the entire 8" wafer, with a measured PAE of 59.3%±0.6%, and
an output power of 14.2 dBm ± 0.1 dB, as well as a small signal gain of 16.3 dB ± 0.3 dB. This
difference in performance is due to the different device layout (1x96x8 Axm vs. lx48x16 Am).
RF Power Performance of Other Device Options
3.1.2.
We have studied the RF power suitability of the different device options as a function of the
drain bias, Vdd. This provides a fair performance comparison as the different devices will show
optimal operation at different voltages.
Fig. 3.3 compares in detail the peak PAE power performance of the thin oxide devices for the
three different gate lengths, as a function of Vdd at 8 GHz (Id= 26 mA/mm). The graph shows the
small signal gain, the peak PAE and the corresponding output power density normalized to a 1
mm device width. At any one value of Vdd, there is not much difference between the 90 nm and
the 130 nm devices, while the 250 nm device gives much lower performance. As Vdd increases,
7u -
IUUV
--
---
o
60-
0)
50 -
-
-
Lg=90nm
Lg=130nm
-Lg=250nm
PAE
100
E
40 a
Em
S30-
-100.C E
30 -
<
C
)
-vdd7
20
1
freq = 8 GHz
10 -
thin oxide
0
Id = 26 mA/mmrr5:-
I
0.1
1
ifW
I
1.0
Vdd [V]
i
i
i
1
I
10.0
Fig. 3.3
Gain, PAE and output power density at peak PAE point as a function of Vdd for thin oxide
devices of three different gate lengths at 8 GHz. Impedances and input power drive were reoptimized at each Vddfor each device.
'·
IVVV
Iu
-c--Thin Oxide
"
C
,"
60-
--
-
Medium Oxide
Thick(
50-
100
E MAO
2
.Vdd
-
S20 -
10
freq = 8 GHz
C.
Id = Z6 mA/mm
lx30x20 pm
L.g
= 250 nm
0
i
i
i
0.1
,
i
l
ii
1.0
l
,
1
i i
10.0
Vdd [VI
Fig. 3.4
Gain, PAE and output power density at peak PAE as a function of Vddfor 250 nm devices with
three different gate oxide thicknesses at 8 GHz. Impedances and input power drive were reoptimized at each Vddfor each device.
all devices show a higher output power density. The dependence is quadratic, and agrees with the
behavior seen in chapter 1 (Fig. 1.3). The gain at peak PAE changes only slightly with Vdd and is
not very different from one device to the other. For the 90 and 130 nm devices, the peak PAE is
rather flat across a broad range of Vdd. The 250 nm gate length devices, however, not only show
a much lower peak PAE, but the PAE starts to rapidly drop as Vdd is reduced. The performance
of the Lg=250 nm devices is limited by the low voltage capability of the thin oxide. We discuss
the physics of this in section 4.
Fig. 3.4 shows the impact of gate oxide thickness, keeping Lg constant at 250 nm. Decreasing
the oxide thickness without changing the gate length results in lower gain and lower PAE.
However, the power density for a given Vdd is increasing slightly. The reason for this is
discussed in Section 4.
----
Lg=90nm, Thin Ox
70 - ---- Lg=130nm, Med Ox
1000
-L-- l=250nm, Thick Ox
60 50 -
100 i
40 -
aC)
30 -
,",-Vdd
2
10
2010 -
freq = 8 GHZ
h~-~·~ac~brhca~-~
.uCIII
I 1 · · I·I
r
a-
Id= 26 mA/mm
I
1
0.1
·
1 I · 1I r
1.0
Vdd [V]
1
1
10.0
Fig. 3.5
Gain, PAE and output power density at peak PAE point as a function of Vdd when scaling both
Lg and gate oxide thickness at 8 GHz. Impedances and input power drive were re-optimized at
each Vddfor each device.
S-
Vdd
=
1V
Vdd = 2.5 V
60 90 nrr
thin o:
50 [fllUK OXIUU
40 -
30
10
100
1000
Output Power Density [mW/mm]
Fig. 3.6
Comparisonof the 90 nm thin and 250 nm thick oxide devices. Both devices can achieve similar
peak PAE levels, though at different operatingvoltages andpower densities, as indicated.
Finally, Fig. 3.5 shows the RF power performance when we both scale oxide thickness and Lg.
This is equivalent to comparing three generations of CMOS technology. For high enough
and
voltage, the 250 nm I/O devices and the 90 nm devices reaches identical levels of peak PAE
gain. The advantage of the 250 nm device is that its thicker oxide allows higher overall power
levels. At Vdd = 2.5V, the device achieves a peak PAE of 59.5 %, at a power of 18.7 dBm (74.2
mW or 124 mW/mm). The performance obtained in these 250 nm I/0 devices is better than
reports available in the literature for nominal 250 nm node logic CMOS devices [10].
When comparing all of the devices, two devices clearly emerge as the best performing ones: 90
nm standard device and 250 nm logic device. Fig. 3.6 shows a comparison of these two devices,
using power and PAE as our variables. The optimum device choice for RF power applications
Vu
0nn
-·-
-
AA-
Lg= 90 nm
E Lg = 130 nm
E Lg =250 nm
50 N
I
. 40
- 150
A'
Ca
; :···
·:::..
o 304-
~:·::
-r_,
20a-
- 100
0-
E:
10
10-
: : ·
`:·::·
:: ':
-F
v
-
thin
a-50
medium
thick
Gate Oxide Thickness
Fig. 3.7
Comparison of fma for the devices in Table 1 operating at Vnominal. Small width devices (right
axis) with their pad parasitics de-embedded offer a peak fma of 100 to 200 GHz. The figure
shows the strong impact of the device layout on the performance. The fm of the power devices
(left axis) used in this paper are not de-embedded, and show a much lower fm due to the low
bias (Id = 26 mA/mm) and the parasitics associatedwith the pads, the large number of fingers
and their width (e.g. R, and Cgd).
depends on the system design constraints. If an optimum voltage can be used, Fig. 3.6 suggests
that the thick oxide 250 nm device operating at higher voltages delivers a higher output power
density than any of the thin-oxide devices, while operating with identical peak efficiency. For
low voltage operation, the thin oxide devices are preferable because their lower knee voltage
leads to a higher peak PAE, as seen in Figs. 3.4 and 3.5.
3.2. Discussion
In order to understand the RF power performance, it is very useful to study the behavior of
fmax. In our research and in other research it is shown that fmax provides a very strong correlation
with peak PAE [ 11]. In order to understand the physical origin of the results shown in Figs. 3.33.5, we have measured ft and fmax for all these devices at their nominal Vdd (given in Table 3.1)
and at IL= 26 mA/mm. The fmax results are graphed in Figs. 3.7. The fmax values are relatively
low because the current bias point is not optimal for fmax, and because additional parasitics such
as Rg and back-end parasitics penalize very wide devices. The fmax data is not de-embedded,
because pad and wiring parasitics are an unavoidable part of the PA. For comparison, the fmax of
typical small analog devices in this process is also shown in this graph. These devices have the
pad and wiring parasitics de-embedded. The standard 90 nm logic device attains an optimum fmax
of about 200 GHz, which is characteristics of state-of-the-art 90 nm technology [12-14]. In
contrast, the power device at the optimum power point only attains 32 GHz.
This data helps us to understand many aspects of the results shown in the previous section. An
approximate formula [15] for fmax using the device's ft as well as gate resistance (Rg), channel
resistance (Ri), output conductance (gd) and gate-drain capacitance (Cgd) is given by
f
3.1
ft
=
fn 2(Rg + R)(gd +24fCgd
Fig. 3.3 shows the impact of Lg on performance. The Lg = 90 and 130 nm devices show about the
same performance, while Lg = 250 nm gives a much worse performance due to the low fmax (gain
at 8 GHz). Fig. 3.7 shows that the 90 and 130 nm thin oxide power devices have an identical
fmax. These two devices show the same fmax because as Lg is increased, the effects of lower
parasitic gate resistance (Rg) can cancel out with the lower ft (Equation 1). The 250 nm thin
oxide device, however, shows a much lower fmax. This is equivalent to lower power gain and
subsequently leads to a lower peak PAE, as observed in Fig. 3.3'. The results of this comparison
indicate that the optimum device Lg for power performance may not necessarily be the minimum
Lg. As Lg is increased, the device's ft decreases. But at the same time, the parasitic gate
resistance is reduced. Thus, a sweet-spot can exist where fmax reaches a maximum in the tradeoff
between ft and Rg. For the 90 nm process, as Fig. 3.3 shows, that optimum gate length seems to
be somewhere between the 90 nm and 130 nm nominal gate lengths.
250 nm, thick oxide
90 nm, thin oxide
OW
i
00
e-•5
400
400
300
300
S200
200
100
100
0
- 0 AX/
0
0
0
2
1
Vds V]
3
0
2
1
3
Vds [V]
Fig. 3.8: Load-line comparisonfor the 90 nm thin and 250 nm thick oxide devices. MeasuredDC
I-V characteristicsof the two devices are shown, with the approximate Vds,sat indicated. The 90
nm device's Vds,sat is lower than that of the 250 nm device. Load-lines, based on the impedances
used in the power measurements of Fig. 3.5, are also shown at Vdd = IV and 2.5V. Self-heating
is present in the DC characteristicsof both devices.
The impact of the oxide thickness in power performance (Fig. 3.4) is not as dramatic as that of
Lg in Fig. 3.3. The use of a thinner gate oxide will reduce the voltage capability of the device.
Therefore, while the performance is not dramatically different at a constant Vdd the thin oxide
devices cannot be operated at the same high Vdd values. The thick oxide device can therefore
achieve the to best overall peak PAE and output power density due to higher Vdd. Decreasing the
gate oxide thickness without changing anything lowers fmax (Fig. 3.7). This explains that the
thick oxide device shows a slightly better peak PAE at any given Vdd.
The comparison of the three device technologies (90 nm thin-, 130 nm medium- and 250 nm
thick-oxide) was shown in Fig. 3.5. If we compare the devices at a fixed Vdd, we notice that the
power density of the 250 nm thick oxide device is lowest. Further, the peak PAE for the 90 nm
thin oxide device is independent of Vdd down to about 0.5 V, while the 250 nm thick oxide
device's PAE begins to drop below Vdd = 1.5 V.
This difference in behavior can be explained by plotting the load lines at the peak PAE point,
as shown in Fig. 3.8 on top of the output characteristics. The load lines were calculated from the
load-impedances, and superimposed on measured DC characteristics. In this figure, we compare
the 90 nm thin oxide to the 250 nm thick oxide devices. The thin oxide device has a lower Vds,sat.
Therefore, if both devices are operated at Vdd=lV, the load-line for the 250 nm thick oxide
device intercepts Vds,sat earlier. This results in earlier and softer compression, and therefore lower
output power density and PAE. If, on the other hand, Vdd for the 250 nm thick oxide is raised to
its nominal voltage of 2.5 V, the relative impact of Vds,sat on the load-line is reduced. The device
will now compress later and sharper than at Vdd=IV, allowing it to achieve PAE levels
comparable to the 90 nm thin oxide device. The output power density will be higher than that of
the 90 nm thin oxide device at Vdd=lV, because Vdd is 2.5-times higher. This can be seen in Fig.
3.5.
3.3. Conclusions
We have studied the RF power suitability of the various device options offered in a typical 90
nm digital CMOS foundry process. We have demonstrated excellent performance at 2.2 and 8
GHz that allows implementation of integrated PAs for several wireless consumer applications.
We have found that for low voltages the 90 nm nominal devices offer the best output power and
peak PAE, but 130 nm thin-oxide devices closely match it. For higher voltage operation, the 250
nm thick-oxide devices offer the highest output power and peak PAE.
Chapter 4.
65 nm Technology
The 65 nm devices studied in this chapter were fabricated in near-production 65 nm CMOS
[16] technology flrom IBM. We compare the RF power performance of this technology with
similar devices made in IBM's 90 nm process and 0.25 tm I/O devices fabricated in the same 90
nm technology [1], which were introduced in Chapter 3. A summary of the devices is given in
Table 4.1. We have fabricated devices with a variety of layouts providing a broad range of total
device widths.
Technology
Lg (nm)
Tox (A)
65 nm
65
11-13
Vdd (V)
1.0
90 nm
90
14
1.0
90 nm
250
51
2.5
Table 4.1: Overview of the devices used in this chapter,fabricatedin either 65 or 90 nm
technologies. The gate length refers to the equivalentpolysilicon halfpitch dimension.
4.1.
Experiments
Fig. 4.1 shows the RF power performance of two standard 65 nm digital devices at 4 GHz and
a bias of Vdd = 1 V with Idq = 26 mA/mm. Both devices have the same total gate width of 768
Am but different layout configurations. The first device is made up of 12 parallel cells consisting
each of 16 fingers with 4 Am unit finger width (we will use the notation: 12x16x4 Atm). This
device shows an output power of 13.8 dBm (31.2 mW/mm) at a peak PAE of 65.7% when biased
at the nominal voltage of 1 V. The small-signal gain is 17.1 dB. The second device uses a single
cell (1x64x12/zm). Its peak PAE is 62% with 13.8 dBm of Pout and a small signal gain of 14 dB.
The lower performance of this second device suggests that the optimum gate finger width for this
technology is closer to 4 jtm rather than 12 .Lm.
While the PAE results are high, Pout per unit gate width is smaller than for lower-integrationlevel, higher-voltage technologies [17-21], which can exceed power densities of 1000 mW/mm.
Many applications, such as PA drivers or wireless LAN PA's require absolute power levels in
excess of 20 dBm. In principle, there are three ways to accomplish this: increasing Vdd,
increasing bias current (Idq), or increasing overall device width (WG,TOT). We have examined all
three approaches for the 65 nm CMOS node.
/U
60
2. 50
c 40
o 30
< 20
10
0
-10
-5
0
5
10
15
20
Pout [dBm]
Fig. 4.1
Power characteristicsof two 65 nm devices with a total gate width of 768 Jim at 4 GHz. The 12
cell device delivers a peak PAE of 65.7% at a power of 13.8 dBm (31.2 mW/mm) at a voltage of
I V.
ou -
Fren=rS GHz~V..=1 V. L=2A mAlmm
12x16Cx~pm
*1l***
50 -20
0~~
40
-
-
W. (5
-10
I,
I
< -20 -
a.
-Vdd
J
E
C,
10 -
00.01
-10
I
I
I
I
I
I
I
0.1
I
Vdd
IT i 7I
I
i
1
I
I
.I I
--10
10
Fig. 4.2
Power performancefor the 12x16x4 AIm, 65 nm device at 8 GHz vs. Vdd. Foreach Vdd, the device
is tuned to peak PAE. The gain is the small signal gain.
Fig. 4.2 shows the RF power performance of the 65 nm logic device as a function of Vdd at 8
GHz. The device is biased at a constant current and tuned to the peak PAE point for each change
in Vdd. We find that Pout increases quadratically with Vdd, as expected from simple theory. PAE
exhibits a broad plateau with a best value of 53 %being obtained at around the nominal voltage
of 1 V. PAE is found to drop for very low values of Vdd as well as for Vdd beyond 1 V. At low
voltages, PAE is limited by Vds,sat and at high voltage by impact ionization. This can be seen in
the output characteristics of this device in Fig. 4.3. Since reliability is also expected to be rapidly
compromised for Vdd>l V [1], 1 V represents a reasonable limit for Vdd for this technology in
this application.
Fig. 4.4 shows the power performance as a function of the bias drain current, Idq, at 8 GHz and
at Vdd=l V. The figures shows PAE, Pout, the small signal gain, as well as actual DC drain
,'
,~
V.3I
0.2
r-o
0.1
0
0.2
0
0.4
0.6
0.8
1
1.2
Vdd [V]
Fig. 4.3
V steps. For
Output characteristicsof the 12x16x4 Itm, 65 nm device for Vg = 0.2 to 1 V in 0.2
small values of Vgs and high values of Vds, impact ionization effect can be seen. Overlapping the
device characteristicsis the load line correspondingto a biaspoint of 1 V.
V
r% A
<
E 50
25
20 0f
45
U, 40
a
t-
15
35
10
a030
E
5
25
1
10
100
IDQ [mA]
Fig. 4.4
Performanceof a 65 nm device (12x16x4 jtm) as a function of bias current. Idq is the quiescent
drain current (no Pin), and Id is the drain currentat peak PAE. The device is self biasing and the
peak PAE, Pout and Gain do not change much with bias current.
current flowing through the device at the peak PAE point (Idq refers to the DC current without
RF signal being applied). Interestingly, the RF power performance is broadly insensitive to the
actual value of Idq. The peak PAE only varies from 50 % to 52 %, and Pout from 20 to 26 mW,
over an 1 x increase in Idq. This is because of the high degree of device self-biasing that is taking
place. While Idq increases by more than a decade in this figure, the actual DC current at the peak
PAE point only increases by about 30 %, from 36 mA to 47 mA.
The third and potentially most effective way to attain more power is through gate width
scaling. Fig 4.5 shows the impact of WG,TOT scaling on the RF power performance. In this figure,
WG,TOT is varied by connecting increasing numbers (Nc) of fixed-size 64x12 tim cells in parallel.
As WG,TOT increases, Pout increases initially but then saturates to a maximum power
-
-
S-
nf\
V
50 - 150
40 -
eq = 2.2 GHz
w 30 -
- 100
nm ..
20 -
-
LE
-
- 50
10 -
Freq = 8 GHz
Vdd = 1V, Id= 26 mA/mm
00
O
-
11.11.<.
1
4
5
6
2
3
Total Device Width [mm]
7
8
Fig. 4.5
Powerperformance as afunction of device size for 65 nm devices (1, 2, 3, 4 and 6 parallelcells
of 64x12 jim each) and 90 nm devices (1, 2, 4 and 8 cells of 48x16 Jim). As the number of cells
and thus device width increasesfor the 65 nm devices, PAE drops while Po,t saturates. The
behavior of 90 nm is very different as Pot continues to increase with device size. Given the
independence of power on frequency over the range that is studied in this work (see 4.), we have
includeda data pointfor a very wide 90 nm device (6.1 mm) that was measuredat 2.2 GHz.
A*AA
.Ik
Fig. 4.6
(a, left) Simplified model schematic to create a multi-cell device from a number of single cell
devices (b, right). The intrinsic device cells of the single cell and the multi-cell device are
identical. Adding parallel single cell devices requires parasitic resistances to match the
increased wire resistance of the multi-cell device's backend. The model parameters were
extracted using S-parametermeasurementsfrom a single cell and the multi-cell device.
E
7.
Frequency [Hz]
1(
Frequency [Hz]
Frequency [Hz]
Fig. 4.7
Y11 comparison of a two-cell device (2x48x16 Aim) with the model. When using two parallel
1x48x16 /m device measurements, the match with the two-cell device is mediocre. Adding
parasiticresistances on the source, gate and drain, as shown in Fig. 4.6b, results in a much
better match with the two-cell measurements. The other Y-parameters exhibit a similar picture
and are omitted to preserve clarity in the graph.
level of about 49 mW. PAE drops correspondingly. This is an anomalous behavior which
deserved further study. Regardless of its origin, the power level of about 50 mW that was
attained is nevertheless sufficient to enable lower-power system-on-chip applications such as
Bluetooth Class 2 and 3 [22].
We have obtained excellent efficiencies and gains at very small voltages and relatively high
frequencies. However, power scaling through device size appears to be limited to about 50 mW.
The next section will discuss the cause we believe is responsible for this phenomenon, and
suggest ways to mitigate it.
4.2.
Discussion
In order to understand the origin of this maximum power limit for large multi-cell devices, we
have carried out S--parameter measurements and extracted a small signal equivalent circuit model
for these devices as a function of the number of cells that are placed in parallel. We have
measured the S-and Y-parameters for a single cell device. Ideally, a multi-cell (Nc) device
should exhibit the same Y-parameters as Nc individual single-cell devices wired in parallel (Fig.
4.6a). However, when we do this in the simulation environment, we find significant
discrepancies (Fig. 4.7). These differences between the multi-cell device and Nc single cells in
parallel must arise from differences in the backend wiring parasitics, as the intrinsic device is
identical. Fig 4.7 also shows the performance of a revised multi-cell model (Fig 4.6b) that take
into account the added parasitics in a multi-cell device. Parasitic resistances in the gate, drain,
and source of each individual cell were required. We optimized these resistances for a close
C
4u
En
YE
-0
a:>
0
1
2
3
4
5
6
7
Number of Cells
Fig. 4.8
Small signal extracted parasitic scaling resistances (Rg and Rs+Rd). To construct a multi-cell
device from single-cell devices, these resistance must be added into the single cell unit (NFx WF
= 48x12 tim = 768 lim) as shown in Fig. 4.6b..
match with the measured Y-parameters of the multi-cell device. We are assuming that the added
source and drain resistances are the same, because their impact on the Y-parameters is very
similar, which makes it hard for the optimizer to distinguish them. The presence of the
resistances helps to improve the Y-parameter match, as we saw in Fig. 4.7.
Fig 4.8 plots the evolution of the additional back-end parasitic resistance associated with the
gate and the source plus drain. This resistance is required in order to match the multi-cell Yparameter measurement with an increasing number of single cells, placed in parallel. As the
number of cells increases, the parasitic BEOL resistances per unit cell increase as well. This is
because, due to pads, backend wiring, and geometry constraints, not all metal wire sections scale
in proportion with the number of cells. The increased resistance results in source degeneration
and resistive power loss, and therefore lower PAE, gain and Pout.
Cr\
OU -
""
/uu
ideal
40-
150 100 -
a.
-x 20010
ideal
CL
50 -
-
ai
0
l
l
l
8 10
2 4 6
Total Device Width [mm]
s
12
I
0
0
I
I
I
I
I
2 4 6 8 10 12
Total Device Width [mm]
Fig. 4.9
Model of the peak PAE (left) and Pout performance (right) with scaling, matched to the 768 1lm
device, and using the resistancesfrom Fig. 4.8. The graph also shows the ideal scaling behavior,
as well as that of reducing the extracted resistanceby 50%.
To prove this, Fig. 4.9 shows the RF power performance prediction of a simple model, based
on the same resistances shown in Fig. 4.8, as well as half of that resistance. These simulations
have also been carried out in ADS. The model assumes that the performance of each unit cell is
identical, except that the parasitic drain and source resistances (Rparasitic) reduce the fraction of
DC power (PDc) that is converted into RF power (Pout) in the device. The DC power will scale
with the number of cells:
PDoc, = Nc IDOVdd
Eq. 4.1
where Nc is the number of parallel device cells, and IDO is the drain current for a single cell
device. Because of the parasitic resistance, some of this power will be lost, and not all the DC
power reaches the intrinsic device. If we denote Ppa. as the DC power lost in the resistor, we
have:
Ppara = c(Nc ID )2RN
Eq. 4.2
where c is a constant depending on the waveform, typically between 1 and 2, RN is the additional
parasitic resistance for the Nc cell device, PAEo is the peak PAE for the single cell device, and
PDCN is the total DC power for the Nc cell device. The RF output power will then depend on the
amount of DC power into the intrinsic device, as well as the efficiency of the device to convert it
into RF power:
Eq. 4.3
Pout,N = (PDC,N - Ppr )PAEo
where Pout,N is the output power for the Nc cell device. Finally, the NC cell PAE is computed
from the RF power and overall DC power:
PAE
PouN
Eq. 4.4
out
PDC,N
where PAE is the power added efficiency for the Nc cell device. For a fixed PDc, the loss in Pout
results in a lower PAE. The power loss is proportional to the RN, and Pout is a linear function of
RN. The model is optimistic, as it does not take into account source degeneration, nor the nonideal shape of the output waveform. It also omits the self-biasing aspects, which will impact the
load-line. In spite of these shortcomings, the model captures the relevant scaling behavior and
shows the sensitivity of performance to the resistance. Fig. 4.10 shows the behavior of the peak
PAE and Pout as a function of device width. We can combine the equations 1-4 to obtain more
compact expressions for PAE and Pout:
PAE = (
clR
Nvdd
NC
PAE o
Pout,N =(Nc IDooV, -c(Nc
Io)2 R )PAEo
Eq. 4.5
Eq. 4.6
The scaling behavior with Nc is now easier to analyze. Eq. 4.5 shows that PAE falls linearly
with Nc, as seen 'in Fig. 4.6. Eq. 4.6 shows that the output power follows a parabolic shape.
Therefore, a maximum for Nc can be found, which is given by:
N
Eq. 4.7
Vdd
2clIoRN
PAENsat =
IPAEo
2
S2
Psat
4cRN
Eq. 4.8
PAE
Using this, we can compute the output power and PAE at the maximum power level. These
values are shown in Eq. 4.8. It is interesting to note that when the peak output power is reached,
the model predicts the PAE to have dropped to 1/2 of its original (Nc small) value. This simple
model shows the critical impact of the interconnect resistance on the RF output power that can be
achieved. Carefull layout optimization and use of existing 4x-thickness upper metal levels for
cell wiring should ameliorate this deleterious effect and enable the 65 nm node to scale the
power level in a similar fashion to the 90 nm node, at equal supply voltage. The increased
inductance or capacitance of the additional metal can, in principle, be resonated out with the
source and load impedances.
The model also suggests that an improvement in the efficiency will allow the designer to wire
more devices in parallel and achieve a higher overall power level before PAE drops below the
desired minimum. In Eq. 4.6, the output power is roughly proportional to the single cell PAE
(PAEo).
60 50-
Freq = 8 GHz
Vdd=l V, ld= 2 6 mA/mm
=
1
12xl 6x4pm
U
1 cell
64x12pr
cell
'40-
ells
9 30-
s
6 cells
n 20-
10
0
20
40
30
50
fmax [GHz]
Fig. 4.10
Correlationof peak PAE with fm (extracted at V8s = 0.4 V and Vds=l V) for the 5 different 65
nm device sizes (each cell is a 65 nm device of 64x12 im), as well as the optimized device layout
(12 cells 16x4 tm devices)
I,,'
V0 -
standard cell
e4'f~jrf'ftC
_9 40N
I
03
20
m
1xNFxWC
Ar_
__
• •
65nm: Vdd=lV, Vg=U.tj V
90nm: Vdd=lV, Vg=0. 7 5 V
I
I
I
I
I
65 nm
I
i
I
I
10
I II100
100
Unit Finger Width (WG,F) [um]
Fig. 4.11
fmax vs. unit finger width for a 1 cell device, keeping overall width the same (NF x WG,F = 768
jpm). Large finger width hurts fm because of Rg. Narrow finger width hurts because of
distributedeffects involving the large number of device fingers that must be parallelized
We are interested in studying in detail the dependence of PAE on various layout decisions.
Doing this with sets of power measurements is difficult, because time constraints would limit the
number of bias points and devices that could be studied. Instead, we are using fmax as a predictor
for PAE, which has a high correlation with the measured peak PAE. This can be seen in Fig.
4.10, which compares the peak PAE and fmax for devices of various total width. The peak PAE
performance and f.x are highly correlated. If fmx, is much larger than the frequency of operation,
the peak PAE eventually levels off to a rather high value. Because fmax correlates so tightly with
PAE, we will next discuss strategies to improve fmax (and therefore power performance) through
layout optimization. Fig. 4.11 and Fig. 4.12 show the impact of device layout on fmax for a device
Total width: 768 um
IE2I
V
E50
U-
C40
'
20
E 100
0
1
10
100
1000
Number of Cells (Nc)
Fig. 4.12
Breaking the 65 nm device up into multiple cells in parallel, both the number offingers and their
unit width are scaled down at the same time. This method can achieve higherfax values (51.4
GHz vs. 43.7 GHz) at identical bias conditions. However, too many cells in parallel hurt
performance due to the excessive wiring required,as seen by the drop in fmx as the number of
cells increases beyond 50.
with a fixed WG,TOT = 768 Am. While the fa for small logic devices is well above 200 GHz
[23,24], it is substantially lower for the large power devices. This is very similar to what we
observed in the 90 nm node [1].
Fig. 4.11 shows the impact of the device aspect ratio of a single cell device on fma. The
abscissa plots the unit finger width. As this increases, the number of fingers that must be placed
in parallel to obtain a given total width has to decrease. An optimum value of unit finger width is
obtained at about 6 um. For narrow fingers, the number of fingers that must be parallelized is
large and this introduces increasing distributive losses. For wider fingers than the optimum, the
finger gate resistance increases and this degrades fmax.
In Fig. 4.12 we show the impact of device cell size, as we break a cell into many sub-cells in
parallel. We can see a large improvement in fmax when going from a single cell with many wide
fingers to an array of many cells with shorter and fewer fingers per cell. Throughout this
4
D
Iuu --
r out
80 Qn nm
m
60 40 -
a.
20 0 0
6Vdd
0
-5 a-
Vdd---
0
Id= 26 mA/mm
a
a
:
5
10
15
20
Frequency [GHz]
Fig. 4.13
Performance comparison of the 90 nm and 65 nm devices as a function of frequency. Both
devices have a total width of 768 ALm (65 nm: 64x12 Alm and 90 nm: 48x16 Alm). The output
power is independent offrequency, and essentially identicalfor both devices, while the peak PAE
for this 65 nm device is slightly lower.
experiment, the total device size WG,TOT (N x NF x WG,F) remains constant. The data of Fig. 4.12
explains the results of Fig. 4.1: a large improvement in fma can be obtained by connecting many
smaller devices (cells) in parallel. Fig. 4.12 suggests that the optimum cell size is 16x4 Itm, with
12 cells in parallel achieving a total width of 768 jm.
4.3.
Technology Scaling: 65, 90 and 250 nm
We now compare the RF performance of three different generations of CMOS technologies,
combining the 65 nm results with those obtained on a 90 nm wafer [25] containing 90 and 250
nm devices. The longer 250 nm devices on the 90 nm wafer are used to drive input/output pads
and approximate both the structure and performance of its corresponding CMOS generation. The
device geometries are 1x64x12 /.tm, 1x48x16 gm, and 1x30x20 Jm for the 65 nm, 90 nm and
250 nm devices, respectively. The change in finger width is necessary to compensate for the
increasing gate resistance as Lg is decreased.
Fig. 4.13 shows the peak PAE and Pout performance as a function of frequency, for single cell
nominal 90 nm and 65 nm devices. While the peak PAE performance of both devices drops
rapidly with frequency, the Pout at the peak PAE point is largely unchanged. This is expected.
There is no substantial difference in behavior between the 90 and 65 nm devices, though the 65
nm device has a slightly lower peak PAE across all frequencies. The similarities of the two
technologies can also be seen in Fig. 4.11, where the two standard cells (1x64x12 utm and
lx48x16 /m) achieve roughly identical fx,, figures.
Fig. 4.14 shows the Vdd behavior of the three technologies. This graphs shows the peak PAE
and output power density vs. Vdd at 8 GHz for devices with an identical WG,TOT. We note that, at
-L/U
Lg=65nm (1x64x12 um)
'- m
Ia
4-AC-4
60
,- 50
100
LU 40
0
o E
-30
a)
20
10
0-
10
0
0.1
1.0
10.0
Vdd [V]
Fig. 4.14
Peak PAE and output power density at 8 GHz as a function of Vdd for three different CMOS
technologies.
their respective nominal voltage of Vdd = 1 V, the 65 nm devices have a somewhat lower
performance than the 90 nm and the 250 nm device on the 90 nm wafer, likely due to the higher
interconnect resistance described above. For high values of Vdd, the 65 nm device exhibits
slightly inferior performance when compared to the 90 nm and 250 nm devices. However, up to
about Vdd = 1 V, the 65 nm device has similar performance as the 90 nm device. The 250 nm
device yields a lower power density at a fixed Vdd, but because it is able to operate at a much
higher Vdd, the maximum power density that it can achieve is the largest of all three
technologies.
While the device performance of the 65 nm and 90 nm devices is very similar with respect to
Vdd and frequency, a significant difference in performance was seen when looking at the device
width scalability (Fig. 4.5). Both technologies show a decreasing PAE with increasing device
width. However, as noted earlier, the power level of the 65 nm devices saturates while that of
the 90 nm devices continues to rise as the number of cells in parallel increases. While some of
this arises from back-end scaling, the largest difference between the 90 nm and 65 nm
experiments is a change in the metal routing used for the multi-cell device layout. It is important
to note that the use of the thicker back-end metal process options, wider metallization and a
layout that scales well with the number of cells, should allow a more mature 65 nm technology to
perform on par with the 90 nm technology. Optimizing the source and load impedances will
resonate out the additional parasitic capacitances and inductances.
For low power levels (below 16 dBm or 40 mW), the 65 nm technology CMOS node offers
excellent efficiency over a broad frequency range (up to about 10 GHz). Its RF power
performance approaches that of 90 nm devices both in peak PAE and output power density. The
relatively high back-end resistance of the BEOL of 65 nm CMOS leads to difficulty in scaling
output power by wiring many fingers and cells in parallel. A maximum power level of 47 mW at
Vdd = 1 V has been obtained. Simulations indicate that further optimization of device layout,
including the use of stacked or thicker upper metal levels should mitigate the negative effects of
BEOL resistance scaling. Through this, the 65 nm node can provide efficient integrated power
amplifier functionality for many applications, even in a deeply-scaled logic CMOS technology
without costly PA.-specific adders.
Chapter 5.
Power Device Model
In chapters 3 and 4 we discussed the RF power performance for many different device
geometries and technologies (65 nm, 90 nm, 130 nm and 250 nm). We also demonstrated how
the power performance varied as a function of bias and frequency. This chapter introduces a
simple device model that provides understanding of the different dependencies that have been
observed. The goal is not to create a highly accurate but complex model - but rather to have a
very simple, physics-based model that is able to predict the correct trends in the power
performance and that helps us to chart the capabilities of future CMOS generations.
Fig. 5.1 shows the measured DC characteristics of the standard 90 nm device (1x48x16 .tm), as
well as the sketch of a typical load-line in compression. This figure shows the regions of the IV
characteristics one needs to focus on when developing a device model for RF power. We can see
from the figure that the load-line sweeps through the sub-threshold region at high Vds>>Vdd. For
Vds<<Vdd, the device enters the linear region (Vds<Vds,sat) and the load-line will extend until the
on-resistance (Ron) limits the drain current. The model must be able to capture these key regions
of the DC characteristics. Other concerns in power operation are the maximum Vds that the
device can operate: at (breakdown voltage), and the RF loss on the gate and drain as a function of
frequency. The model described below captures all these critical parameters. We will use this
model to simulate: device behavior in Agilent ADS, using harmonic balance simulations. This
helps us to get a more accurate picture into why performance deteriorates with frequency, and
how the output power scaling seen in chapter 4 exhibits a limit as the number of cells is
increased.
4UU
300
200
100
0
0
2
1
3
Vds [V]
Fig. 5.1
DC characteristicsof the 90-nm device (1x48x16 lim) with indicatedload-lines. The model must
focus on the device regions that the load-line occupies. The DC data shows self heating effects
for high Vds, Id values.
5.1. Model Structure
The basic model is shown in Fig. 5.2. The model contains 7 parameters which are described
next. The voltage-controlled current generator requires three parameters.
It consists of the
threshold voltage (VT), below which the device is non-conducting. The exponent term (exp) is
needed because the transconductance is not constant with bias (we will discuss this in section
5.2.). The current term is proportional to the factor k.
The maximum current will be limited by the device's on-resistance (Ron), and the breakdown
voltage (BV) is implemented as a diode that turns on sharply at BV.
The model also includes the input and output impedance networks. They consist of pad,
interconnect and intrinsic gate-to-source and drain-to-source parasitics, as well as the output
conductance of the intrinsic device. In a load-pull setup, we can assume that the reactance of the
device is resonated out by the impedance matching network, leaving only the resistive
components. Therefore, for the purposes of RF power estimates, the aggregate of the gate and
, -
, - Dain
R.O NII
Fig. 5.2
Full device model (top) and simplified equivalent model (bottom). The model is a large signal
model. The R-C networks on the drain and gate are simplified into a single frequency dependent
resistor. The assumption is that the reactive components of the device are resonated out by the
source and load impedances. The other model elements include the current generator(k, VT,
exp), the breakdown voltage (BV) and the on-resistance (Ron).
drain parasitics can be modeled as a frequency dependent resistor, RGS = Real{ Zs(f) } and Ro =
Real {ZDs(f,Bias) }.
5.2. Parameter Extraction
Model parameters are extracted with the help of DC and S-parameter measurements. DC
measurements of the output and subthreshold characteristics allow for extraction of VT, BV, Ron
as well as k and exp. Typical values for the 65 nm and 90 nm standard devices are shown in
Table 5.1. The parameters for k, exp and VT are extracted by matching the subthreshold curve at
Vdd=lV, shown in Fig. 5.3. The parameters are treated as matching parameters, with the goal of
providing an accurate match of the subthreshold current around VT.
The on-resistance (R.o) is extracted from the measurement with V,s=l V, Vds=0.01 V, where
Ron = Vds/Id. The RGS and Ro values are extracted from the output impedance of the device at the
frequency of interest. For this, in Fig. 5.4 the output resistance extracted from small signal
measurements, 1/Real(Y22), is plotted as a function of VGS for VDos=VDD. We observe that this
parameter is strongly bias point dependent. For low VGS, the device is turned off and Ro is large.
For values of VGs below threshold, Ro rapidly drops and then levels off. Our simple model
requires a fixed value for Ro.
The load line sweeps through different regions of device
operations (Fig. 5.1). This makes the choice of Ro challenging. We have found that a good
choice for Ro is around the class AB bias current (indicated in Fig. 5.4). Using a non-uniform
value of Ro is difficult to implement in the simulation environment, because of discontinuity
concerns [26]. It would also introduce additional complexity to the model. The extraction of Rgs
is easier because there is no strong bias point dependence (Fig. 5.5) unlike the case for Ro.
Therefore, Rgs simply is the input resistance to the gate, 1/Real(Yi ), measured at the appropriate
frequency and Vds=lV, Vgd=VT.
Parameter
65 nm Device
VT (V)
K (S)
Exp
0.27
0.39
90 nm Device
0.40
0.55
2.32
1.60
Ron (Q)
BV (V)
2.3
3.5
2.3
Rgs at 8 GHz (Q)
Ro at 8 GHz (2)
246
120
4
215
110
Table 5.1
Model parametersextractedfrom DC measurements,for the 65 nm and 90 nm technologies.
1
0.1
0.01
0.001
0
0.5
1
Vgs [V]
Fig. 5.3
Example fit of the subthresholdcurve at Vds= 1V, for the 90 nm device. The extracted values for
VT, k and exp are shown in Table 5.1.
10000
1000
100
10
1
0
0.2
0.4
0.6
0.8
1
Fig. 5.4
Measured output resistance (Real(Y22)) as a function of Vgs, for two frequencies at Vds=1V. The
data shows that Ro, is bias dependent. The model assumes a bias-independentRdos. Choosing a
constant value around threshold (indicated)provides the best compromise.
-
IUUU
values used in model
r
1000 -
2 GHz
8GHz
100-
10 -
I
0
I
I
I
0.2
0.4
0.6
0.8
Vs IV]
Fig. 5.5
Measured input resistance (Real(YDl)) as a function of Vgs, for two frequencies at Vds= V. The
data shows that Rgs is largely bias independent.Model parameterswere chosen at Vgs= VT.
5.3. Model Results
Model simulations were performed at ADS.
Because the model assumed that reactive
components can be resonated out, the lack of capacitances or inductors allowed the actual ADS
simulation to be done at an arbitrary frequency. The model Rgs and Ro were set according to the
power device frequency that was simulated. The simulation optimized for both peak PAE and
output power, using Vgs, Rsource and Rload as parameters. Fig. 5.6 compares the ADS simulations
and measurements of the peak PAE and output power as a function of frequency. The general
trends of the measurements are present in the simulations, such as the frequency independence of
the output power (until the gain approaches unity at very high frequencies) and the drop of peak
PAE with frequency.
Also, both the 65 nm and 90 nm devices show very similar model
performance.
We can now apply the model to the question of device scaling. Fig. 5.7 shows the model
performance for different values of parasitic resistance for the 65 nm scaling experiment
discussed in Chapter 4. As the simple model of Chapter 4 suggested, the peak PAE is dropping
with the number of parallel devices, while the output power rises and eventually levels off and
decreases. The model is different from the analytical one introduced in Chapter 4. The circuit
model presented here relies on device predictions using harmonic balance simulations. It is able
to properly take the full impact of the parasitic backend resistances into account, such as source
degeneration for example. The model only required DC and S-parameter measurements, which
are readily available. It does not require RF power measurements. The analytical model in
100
80
15 E
a1.
60
10 0
.O.
40
5
0
20
0
0
20
15
10
5
Frequency [GHz]
Fig. 5.6
Model performance comparison with measured power performance, as a function offrequency.
The model uses the parametersof Table 5.1. The model for each technology roughly matches the
behavior of the data. The output power is frequency independent up to very high frequencies,
while the peak PAE decreases.
250
45
200
o30
150
&a
I.
Cz
7
E
100
w
n
LL·
50
0
0
2
4
6
8
Number of Cells (Nc)
Fig. 5.7
Model performance compared to the 65 nm device scaling measurements. Depending on the
parasiticresistancefor the overall device, the drop in peak PAE and the maximum output power
can vary significantly. The model assumes a constant backend resistance that does not scale
with the number of cells.
Chapter 4, on the other hand, is based entirely on adjusting the output power (Pojt) and PAE
equations, using only the RF power measurement results.
The simple circuit model presented here also highlights the sensitivity to the parasitic
resistance, as seen in Fig. 5.7. If the backend contains a fixed 0.25 Ohm resistance associated
with the device pads (it is independent of Nc) in the source, drain and gate, the model predicts
peak power levels above 100 mW. However, if this resistance increases to 1 Ohm, the power
will be limited to less than 30 mW.
This model allows us to estimate the maximum output power that can be achieved in a given
technology. It is clear that the limiting mechanisms are the parasitic resistances, which dissipate
power and result in an I-R drop. In the best case scenario, the lowest resistance is achieved with
a metal plane above the device directly connecting to the bond pad. Assuming a square device
area, this would require a minimum of two to three metal squares. The sheet resistance of a thick
metal layer is approximately 25 mQ/o. Therefore, we can expect about 75 mQ of parasitic Rs
and Rd. Another contributing resistance would be the bond wire resistance, which is estimated at
around 103 mQ [27] for a 2 mm long wire of 1.0 mil diameter. It is therefore conceivable that
the lowest parasitic resistance is about Rs=Rd=Rg=180 m92. Extrapolating Fig. Fig. 5.7, this
would place the maximum power for the 65 nm device to about 100-150 mW.
At the maximum power level, the peak PAE will have dropped significantly from its single-cell
value (the simple model suggested a drop to ½2 its original value in Eq. 4.8). In Figs. 4.5 and 4.9
we saw the peak PAE decreasing with the number of cells. Design requirements may dictate a
minimum acceptable value for peak PAE. Therefore, this also places a limit on the number of
parallel cells, consequently also limiting the total output power to less than its maximum
possible. This hold especially true for higher frequencies, where the single-cell peak PAE is
already quite low (see Fig. 4.13).
We would like to find the maximum output power at a given frequency, subject. to a required
peak PAE level. Clearly, as the demands on peak PAE rise, the maximum output power at that
PAE level will be reduced. The next chapter will discuss how we can develop a picture that is
able to capture all of these tradeoffs.
Chapter 6.
Discussion
Chapters 3 and 4 have shown measurements that establish the trends of the output power and
peak PAE with frequency and multi-cell scaling. The models developed in chapter 4 and 5 help
us to formulate the trends seen in the measurements. This chapter will draw on this to derive
empirical expressions for the output power and peak PAE, as a function of device size and
frequency of operation. This will allow us to derive a compact picture that helps us to
understand the impact of CMOS scaling on the power performance.
From Fig. 3.3 we saw that the peak PAE is roughly linearly decreasing with frequency (f),
extrapolating to zero at a maximum frequency (f,,t), and roughly its class-B theoretical value
(id4) at DC. We can capture this as:
PAE =-
1
Eq. 6.1
This is the efficiency for a single cell device. If we start to place multiple devices (Nc) in
parallel, the peak PAE will drop even further due to the parasitic resistance as discussed in
chapter 4. Depending on the parasitic resistance and its scaling behavior, there is a maximum
number of cells in parallel beyond which the output power is no longer increasing (Nsat). Fig. 4.5
and the simple model described in chapter 4 suggest that the peak PAE will drop linearly with
the number of cells. At Nc = Nsat, the peak PAE has dropped by half, so that for Nc = 2 Nsat it is
reduced to zero. Therefore, we can modify Eq. 6.1 to take this into account:
PAE =
- -
t
1
Eq. 6.2
sat
Similar considerations can be done for the output power. Fig. 4.13 demonstrated that the
output power is independent of frequency. Therefore, it will only be impacted by the number of
parallel cells, and the parasitic resistances. A single cell device produces PNc=1 of power. At Nc
= Nsat, the power has saturated to the maximum possible (Psat), which can be found either from
the measurements in chapter 4, or the model results from chapter 4 and 5. A first order
expression of the simple model in chapter 4 was found as:
Nsa,
2
V•
clooRN
(Eq. 4.7)
and
Psat, =
RN PAEo
4cR,
(Eq. 4.8)
We can use these equations, or choose values based on the measurement observations if a more
accurate fit without an analytical solution is needed.
Based on the simple model in chapter 4, and the more detailed model discussed in chapter 5,
we will assume that the power increases from PceIn to Psat in a quadratic way. Therefore, we can
capture this as
S ce
Na
a1
-N
Eq. 6.3
This expression captures the peak in output power, and for Nc>Nsat, the power starts to
decrease, as seen in Figs. 4.5 and 4.9. We can now use the equations for peak PAE and output
power (Eq. 6.1 and Eq. 6.3) to graph constant PAE contours in the power-frequency space. We
can combine the two equations to give a single expression for output power, using frequency and
desired PAE as its variables:
Pout
Eq. 6.4
PNc= + (P,, - P,, X)(1 - a2)
with
-
PAE
1
a
11-1/Nsat
-
This is shown in Fig. 6.1. For a fixed level of PAE, as the frequency increases, the maximum
possible output power will decrease, as Fig. 6.1 shows. From the figure, we see that as the
frequency is increased, the peak PAE gradually drops and will eventually reach zero at feut. The
output power shows an upper limit, set by Psat. It is important to note that when approaching this
limit, the PAE rapidly drops. In fact, Eq. 6.2 and 6.3 illustrate this: the power reaches its
maximum at Nc=Nsat. At low frequencies, the PAE from Eq. 6.2 then simplifies at its peak
power level to:
PAE(Pa
)= - Na=
4(
39.2%
Eq. 6.5
2Nsat4
Therefore, unlike the frequency limit at which PAE gradually dropped to zero, the maximum
power limit at low frequencies shows a peak PAE of 39.2%. This can be seen in Fig. 6.1, as the
sharp drop of PAE as the output power reaches Psat.
~nnST~nT
e'-U
~~r_
C~)rllOLlr~i
180
160
,140
E 120
3 100
o
LL80
a
60
40
20
1
10
Frequency [GHz]
100
Fig 6.1.
Constant PAE contours using the model, illustrating the output power that can be achieved at a
given frequency. The higher the desired PAE, the lower the power andfrequency. The power
has an upper limit set by the backend parasitics,while the frequency has an upper limit related
to the device gain andf,,. The values in the graph are based on the 90 nm technology, which we
2
expect to be able of delivering 140 mW of power (Psat) with a maximum power at Nc,sat=1 , and
a maximum operatingfrequency of 21 GHz (fsat).
6.1.
Frequency and Power Limits of 65 nm, 90 nm and
250 nm technologies
With the insights developed in the previous section, we can now complete the picture of the
CMOS application space from the introduction (Fig. 1.9). Both from chapter 4 and the model
results shown in Fig 6.1, we can get an estimate on the maximum power level that can be
achieved by combining multiple device cells. For the 90 nm node, this is estimated to be about
140 mW at PAE = 50% for low frequencies, based on the measurements shown in Fig. 4.5. The
65 nm node saw a peak power level of about 50 mW (chapter 4). From the literature [28,29] and
Fig. 1.3, we estimate the 0.25 jim technology to give about 1W. The frequency limit for a single
cell device in the three technologies is estimated to be roughly identical.
We draw this
conclusion from the measured fmax for the standard devices, seen in Fig. 3.7 and Fig. 6.2.
We can now estimate the power capability. Fig. 6.3 shows the 50 % PAE contours in the
frequency/power space, for 65 nm, 90 nm and 250 nm technologies. As the technology is scaled
down, the maximum output power decreases due to the lower Vdd (consistent with Fig. 1.3). The
power capabilities of 65 nm still include a good portion of the application space, but leave out
the higher power applications. The backend layout issues seen in Chapter 5 cause the maximum
power level in the 65 nm node to be lower then that of the 90 nm node.
WG,TOT = 768 pm
50
Id = 26 mA/mm
Optimized Layout
Vdd = Vnominal
40
'1(D
,6 30
S20
0L10
65 nm
90 nm
Gate Length
250 nm
I
Fig 6.2.
Impact of device layout on the device f,. The standard single cell device is shown in the solid
bars. Using an optimized device layout by breaking the device up into multiple smallercells, fa
can be improved significantly. This becomes more critical as the technology is scaled down.
I I
h
1
0.1
0.01
1
10
100
Frequency [GHz]
Fig 6.3.
Estimated contour of 50% peak PAE, for three different technologies, illustrating the power vs.
frequency behavior. The estimates are based on extrapolationof measureddata.
In chapter 3 we saw the impact of the device layout on fmax. Fig 6.2 also includes measured fmax
data for the best layout we fabricated (using many smaller devices in parallel as opposed to s
single cell). Here, we can see that if we re-optimize the single cell standard device, the 65 nm
technology shows the largest potential for pushing into higher frequencies. For the 0.25 Am
device, we expect the layout decisions to be less important, because the unit cell is relatively
small with respect to the intrinsic device dimensions (the gate aspect ratio, WG,F /Lg in only 80:1
for the 0.25 Am device, as opposed to about 230:1 for the 90 nm device).
If using an optimized layout, then the maximum frequency limit will improve as we scale the
technology. This leads us to revise Fig. 6.3 into the results shown in Fig. 6.4.
We expect the output power limit to decrease as technology is scaled. This is primarily due to
the Vdd scaling. Because the nominal voltage between the 65 nm and 90 nm devices has changed
only marginally (both quote Vdd=l V but the 65 nm device has a somewhat lower breakdown
voltage), their output power performance should be very similar. On the other hand, the 250 nm
device has a much higher Vdd of 2.5 V, and is therefore able to produce higher output power
levels. This picture is consistent with Fig 1.3. The frequency limit can be pushed out with
scaling technology.
However, in order to realize this improvement, careful layout design
considerations have to be made, because the reduction of Vdd results in an increase of bias
current and vulnerability to I-R losses in the backend, as we saw in chapter 4 and 5.
Based on our measurements and the model estimates, we were able to identify the trade-offs
that exist when scaling CMOS devices for RF power. The reduction of Vdd will directly translate
into a lower output power. On the other hand, device scaling increases the speed of the intrinsic
device, which can translate into higher frequency performance. But in order to capture this
1
o
a.
u-
0.1
U.01
I
1
I
I
1
I
I III
I
10
I
I
Iiir~l
100
Frequency [GHz]
Fig 6.4.
Estimated 50% peak PAE contours,from Fig. 6.2, redrawn taking the device layout optimization
into account. Layout optimization can help to push out the frequency limit for the PA device.
The 65 nm technology profitsfrom optimized layout the most, as seen in Fig. 6.3.
improvement in the frequency response, a careful layout of the device is essential. Layout is also
critical in reducing parasitic resistances that can substantially limit the possible output power.
We demonstrated that the device layout decisions are becoming increasingly important as CMOS
is scaled down, substantially reducing the output power if not properly optimized. If the layout is
properly taken into consideration, the loss of output power due to multi-cell scaling can be
lowered, and scaling will push out the operating frequency. The loss of power density due to a
lower Vdd, however, is fundamental, and therefore scaled CMOS will always result in a reduction
of the maximum possible output power.
Chapter 7.
Conclusions and
Recommendations
We have studied the RF power suitability of CMOS technology from 250 nm to 65 nm. Both
the 65 nm and 90 nm technologies have a nominal voltage of 1 V. At a bias of 1 V, the 90 nm
nominal devices offer the best output power and peak PAE, but 65 nm devices closely match it.
The 90 nm technology achieved a peak PAE of 59% at 8 GHz, with a power density of 28
mW/mm. The 65 nm technology achieved a peak PAE of 53% at a similar power density of 29
mW/mm at 8 GHz. If one allows for optimum voltage selection, the 250 nm thick-oxide devices
offer the best output power and efficiency at the highest voltages, with 59% peak PAE at 124
mW/mm output power density at 8 GHz and Vdd = 2.5 V.
We have shown that the device layout has a large impact in the power performance. A single
cell 65 nm device exhibited a peak PAE of 62% at 4 GHz. Breaking it up into many smaller
cells, but of the same total width, increased the peak PAE to 66% while maintaining the same
output power.
We also demonstrated that in order to increase the overall output power, scaling the device
width is very effective. This is best done by wiring together many smaller unit cells. However,
as the device size increases, parasitic resistances start playing an important role and eventually
limits the maximum output power that can be achieved through width scaling. We also showed
that as the device width increases, the peak PAE decreases due to the loss in the parasitic
resistances. This results in a tradeoff between output power and peak PAE, as we change the
device width.
Another important tradeoff we have shown is the frequency dependence of the power
performance. The peak PAE drops roughly linearly with frequency, while the output power is
independent of frequency over a broad frequency range. All three technologies are capable of
amplifying signals up to about 20 GHz, although the PAE drops significantly as the frequency
approaches this boundary.
Through measurements and model predictions, we were able to analyze how gate length
scaling impacts the power performance. We found that the reduction of Vdd associated with
scaling causes the output power density, and therefore the output power, to drop. Lowering Vdd
also makes the device more susceptible to parasitic resistances, because for a constant amount of
power, higher currents are needed.
Device scaling increases the speed of the intrinsic device, which translates into a higher fax
and higher PAE at a given frequency. But in order to capture this improvement in the frequency
response, a careful layout of the device is essential. Layout is also critical in reducing parasitic
resistances that can substantially limit the maximum possible output power. We demonstrated
that the device layout decisions are becoming increasingly important as CMOS is scaled down.
If the layout is properly taken into consideration, scaling can be instrumental in enhancing the
operating frequency of CMOS.
Designers using a deeply scaled CMOS technology have to decide which device to choose
for the power amplifier. The first question to consider is whether thicker oxide I/O0 devices or
higher voltages are available in the design. This is mostly a question of cost, likely to be
determined by other system components. If thick I/O devices are available, it makes sense to
choose them for lower frequency applications, such as 2-5 GHz, because of their higher power
capability. If the frequency of operation is approaching the limits of the thick-oxide devices (1020 GHz), the design can benefit by using the nominal thin-oxide devices, because they offer
better frequency performance. If both the frequency and power demands on the application are
very relaxed (e.g. in a low power bluetooth design), the choice of the device type should be
guided by non-technology factors, such as existence of previous designs, cost or convenience.
Future research can focus on many issues discussed in this thesis. Device layout decisions are
very important. However, a most important contribution to understanding the capability of
CMOS would be to populate the frequency-power tradeoff estimates in Fig. 6.1 with actual
device measurements. If this is done for different technologies, designers could understand and
compare technologies and their limitations, by using a set of very simple but powerful figures.
The results of each technology could be combined into a graph similar to Fig. 6.4. In Chapter 4
we saw that the output power of the 65 nm device was limited by layout issues in the width
scaling. With proper layout, we expect the 65 nm device's output power performance to be
similar to that of the 90 nm device. This is indicated in Fig. 7.1.
Populating Fig. 7.1 with actual measurements, a single graph would be able to show the
benefits and tradeoffs of different CMOS technologies. Ultimately, one could also include
alternative technologies to CMOS, such as SiGe HBTs or III-V semiconductors to provide a
comparison on an even broader choice of technology.
__
10
i
,·
a3U-
n- 0.1
0.01
1
10
100
Frequency [GHz]
Fig 7.1.
Expected 50% peak PAE contours,from Fig. 6.4. This figure assumes an optimized backend
layout for the 65 nm devices, resulting in an improved width scaling. We expect the maximum
power of the 65 nm devices to come close to that of the 90 nm devices.
Appendix A
Measurement Theory
This section describes the measurement configuration and calibration procedures. In a single
tone power measurement, shown in a simplified form below (Fig. A.1), we are typically
interested in the following measurement parameters:
is not
The available RF input power to the device under test (DUT). If the device
perfectly matched, some of this power will be reflected back to the source, and the actual
Pin
power entering the device will be reduced.
Pout
Vgs
The RF output power that leaves the DUT
The gate-source bias (or Vbe for BJTs). This is the voltage applied on the source side of
the device, also is commonly referred to as Viow
Ig
The current entering the gate. Also referred to as I'ow
Vds
side of the
The drain-source bias (or Vce for BJTs). This is the voltage applied on the load
device, also is commonly referred to as Vhigh
Id
The current entering the drain. Also referred to as Ihigh
Drain Bias
Network
Gate Bias
Network
V
DUT
RF Input
Power
DC Supply:
Gate
RLoad
DC Supply:
Drain
Load
Fig.A.1: Basic setup of the power measurementsystem. The device (DUT) is biased with a bias
network ("Bias-Tee") and RF power is inserted into the gate. The load is connected on the
drain.
From the above parameters, we can compute several figures (all numbers in SI units, not dB or
dBm):
Gain The power gain of the RF output power, relative to the available RF input power:
Pt
(unitless)
Gain = "t
Pin
The drain efficiency, a measure of how much DC power is converted into RF output
1r
power:
(in %)
Pout
S out -
gVgs +IdVds
Doc
PAE The power added efficiency, a measure of how much DC power is converted into RF
output power, taking into account the RF power that enters the device:
PAE=
o-u
in
Poc
out,
n
gV + Id Vds
Pou
-
Gain)
IgV, + IdVds
If the power levels are expressed in term of dBm, the above become:
(in dB)
Gain = Pout - Pi
=
10P,,/ 0-3
gg
(in %)
d+
IVg, ++IdV
PAE -
10
*,,1o-3
_-104,/10-3
IV•, +IdVd
(in %)
(in %)
At RF frequencies, however, the setup in Fig. A.1 is incomplete. We need to take into account
the fact that the source and load impedances have a significant impact on the device
performance. Therefore, adjustable tuners are inserted right before the gate (source) and drain
(load) of the device. In addition, a directional coupler is placed after the RF source, so to get a
more accurate reading of the source power. The complete schematics of the source and load side
of the measurement system are shown in Figs. 2 and 3, including RF cables:
rigner mr-loss results in
worsening of the system's
maximum achievable VSWR.
Cable
I
Connector
SEquipment
Fig. A.2: The system setup on the source side. The RF inputpower is read by using a directional
coupler. The RF power is then combined with the DC bias. The source tunerpresents a variable
impedance to the DUT.
Cable
Connector
worsening of the system's
maximum achievable VSWR.
Equipment
Fig. A.3: The system setup on the load side. The load tunerpresents a variableimpedance to the
DUT, and the RFpower is measuredat the RF end of the Bias-Tee.
Measurement De-Embedding
Out of the 6 measurement parameters mentioned in the previous paragraphs (Pin, Pout, Vds, Vgs,
Id, Ig)
we can only directly observe Idand Ig.The methods and challenges in observing the other
parameters are described below:
The voltages Vds and V, are measured at the DC bias source, and therefore any I-R drops
between the DC source and the DUT will reduce the actual voltage at the DUT plane. Using a
"force-sense" setup (one probe delivering current, and a second probe measuring voltage) is not
possible, the voltage sensing probe would deteriorate the RF matching to the device. However,
for small currents, the I-R drops in the measurement cables are insignificant. This is, of course,
particularly true for the gate - where Igis negligible in this context. On the drain side however,
for very large devices that require high current at low Vds, this might become a concern. The
measurement system cannot offer a solution to this problem, other than keeping the cable length
between the Bias-Tee and the DUT plane at a minimum.
In order to find the input and output power to the device (Pin, Pont), we need to realize that the
power measured (Figs. A.2 and A.3) differs from the true Pin and Pot due to the RF elements
inserted between the DUT plane and the power meter. However, all of the RF blocks between the
DUT plane and the power meter are linear 2-port elements. We can use S-Parameter analysis to
de-embed their effects, and obtain the true value of the power levels at the DUT plane. The
computational details are described in the next sections.
De-Embedding and S-Parameter Analysis
The load side of the measurement system is shown in Fig. A.4 below. The power leaving the
DUT enters into a series of cascaded S-parameter blocks. These are: the fixture (which includes
the probes and the cable connecting them to the tuner), the tuner itself, and the Bias-Tee (and any
cables connected to it). The power meter terminates this series, and is characterized by its
reflection coefficient (Fpower-meter = Si 1).
Tuner
Fixture
Bias T and
Power Meter
(Probe and Cable)
Cables
Sl
Fig. A.4: The load-side of the setup, as a series of cascaded S-parameter blocks. The port
numbers are indicatedabove the 2-port blocks.
To simplify this picture, we will first combine the 2-port S-Parameter blocks into a single
equivalent block.
Cascading two S-parameter blocks
Two S-Parameter blocks connected in series can be combined into a single block by using chain
scattering parameters (T-Parameters). The conversion between S- and T-parameters for 2-port
blocks is shown below [1]:
Ts_(S
)=
[ S 12
S 21 -
S 1 S 22
S22
ST-4S
T
T i2)
Ti1
S
1
T22
- Tl2
-T21
•T2
lx
S21
1
T22
Fig A.5: Using T-parameters, the two cascaded S-parameter blocks (SA and SB) can be
combined into a single S-parameterblock (SA+B).
We can make use of the fact that the T-parameters of two blocks connected in series satisfy:
TA+B = TA .TB
Cascading two S-parameter blocks therefore is done by converting them into T-parameters and
performing a matrix multiplication of the two. The result is then converted back to S-parameters:
Cascade(SA, SB) = SrTs (TS-T (SA)
-Ts T (SB))
This result now allows us to simplify the setup that was shown in Fig. A.4, the resulting
setup is illustrated in Fig. A.6:
S Equiv = Cascade(SFture, Cascade(STu,,er, S B•,,-))
= STT-S (Ts--T (SFixture )
- Ts.T (STuner ) - Ts•T
(SBiasT ))
Equivalent
Power Meter
S-Parameters
S11
Fig. A.6: Cascading all of the 2-port S-Parameter blocks of Fig. A.4, we can simplify the
measurement system into the DUT connected to the power meter through a single S-Parameter
block. The port numbers are indicatedabove the 2-port block.
Input impedance of a terminated S-parameter block
Before we can find the power that leaves the DUT, we need to compute the impedance that is
presented to the DUT in Fig. A.6 (by the S-parameter block terminated by the power meter). The
equivalent reflection coefficient of the setup shown in Fig. A.7 is found to be [2]:
Equiv
=
+ S12 S
S
1-
Sz,
_s2,
Load
S12]
S22]
S22•Load
**
rLoad
--
-Equiv
Fig. A. 7: Finding the impedancepresented by an S-parameterblock terminatedon the 2 nd port.
Finding the amount of power delivered into the load
For the network shown in Fig. A.8, we can compute the power delivered to the load, given the
power that leaves the DUT [3]. The ratio of the two will give us the gain (or attenuation)
between the two power levels:
Equivalent
Power Meter
S-Parameters
Sl
Fig A.8: Block-setup for computing the power delivered to the load.
m 2
1
_ IS2Ll
IS21
PLoad
avail
-
,
)x1- S 2
1o)
with S11 , S12, S21, S22 are the S-Parameters from SEquiv, and PLoad is the power delivered to the
load, and Pavail is the power that is available from the DUT. FLoad is the reflection coefficient (S 1)
of the power meter. FIN was defined in the previous paragraph, as
FIN
=
=
Fuiv (S, Load ) S
12 21 Load
1- S22* rLoad
The gain in dB between the measured power (PLoad) and the power leaving the DUT (PAvail) is:
Load
Gain = GAT, (S , FIad ) = 10 x log Pa
I
availi
IS21 2 X(1- IrL' I)
= 10 x log
1-
S
1-2 21
12
I-
S22
Load
Load
x
-
S221Load
)1
Therefore, at the device plane, the power level is expressed as
Pout = POut,DUT
POut,Measured
-
-Gain=
POut,Measured - GAT
(SEquiv' Load )
Where POut,Measured is the power meter measurement. The power leaving the DUT (Pout) is larger
than what is read off the power meter (POut,Measured) because of the loss and mismatch of the
elements between the DUT and power meter. The Gain in the above equation is a negative dB
number.
Calculating the Input Power at the Device Plane
The input power de-embedding follows a similar concept. Fig A.9 shows the S-parameter
schematic of the source side of the measurement system. The power available from the source is
measured through the directional coupler (see Fig. A.2). Given the source power, we find the
power entering the DUT similar to the approach used for the load side. We first combine the 2port S-parameter blocks into a single equivalent block (Fig. A.10).
1
2
Power Source
Bias T and
2
1
Tuner
2
1
Fixture
(Probe and Cable)
S,,
Cables
S-parameter blocks. The port
cascaded
of
a
series
as
the
setup,
of
source-side
Fig. A.9: The
numbers are indicated above the 2-port blocks.
Power Source
Equivalent
Sl
S-Parameters
Fig. A.1O: Combining the S-parameterblocks of Fig. A.9, to simplify the source side setup. This
setup is very similarto the one presented in Fig. A.8.
The gain in dB between the source power (Psource) and the power available to the DUT (PAV,DUT)
is, similar to equations [XYZ]:
Gain = Garr (SEquv"'Fsrc)= 0lx log PSource
PAv,DUT
SrcI2)
S2 12XX(1
=10xlog
1-S+
S12 S21
1- S22 -
src
Src
x 1- S22 Src
I
The difference in this analysis with that of the output power is that we are working in the
opposite direction: given the power at the termination (Source: power source S 11), we need to
find the power into the network (PAV,DUT). This is inverse of the output power problem, where
we needed to solve for the power at the termination (Load: power meter S11) given the power
into the network
(Pout,DUT).
Therefore, the power available to the device is lower than the power
available from the source, due to mismatch and loss. The equation for the available input power
(PIN = PAv,DUT) to the device then becomes:
P, = PAv,DIUT
= PSource,Measured
+
Gain =
Psource,Measured +
GA
E(SEquiv
ource
Where Psource,Measured is the available power from the source, measured through the coupler in Fig.
A.2 (or, in alternative system setups, known through calibration).
Finally, we need to relate the source power (PSource,Measured) to the actual reading of the input
power meter in Fig. A.2 (PIn,Measured). The two are different because the power meter is reading
the actual source power through the connection of cables and the directional coupler. Therefore,
the power arriving at the power meter will be attenuated, from the original source power level.
We will call this attenuation the coupling between the power source (PSource,Measured) and the
power meter (PIn,Nleasured):
Coupling = PSource,Measured -
Pn,Measured
Thus, the input power equation can be rewritten as:
PI,, = PIn,Measured +Gain -Coupling = P=n,Meaured +GA,(S
qsource
)- Coupling
Determining the Source Coupling
The coupling factor is found through calibration. The probes are connected to a through line,
with known (measured) S-parameters. We can then compute the input and output power at the
device plane shown (Fig. A.11), which will refer to exactly the same quantity. A simplified
schematic is shown in Fig. A.12. Both power levels must be equal, and we can compute the
coupling factor.
Probe
Probe
Si
Power.
5" S1,,2SIS21 S2]
Source
Power
Bias T and
S11
Cables
j
F.
S
[S S,,S ,1
S22 S22
S12
SS21
Fixture
Source Tuner
(Probe
andCable)'
,, S12
22
S2' S22
Through Line
S , S,
LS
Fixture
(Probe and Cable)
S , S,1
Load Tuner
5,
S,2
SSi
POW
Bias T and
Power Meter
Cables
S11
Fig. A.11: S-parameterschematic forfinding the couplingfactor. The power crossing the dotted
line from the source to the load side is identical to Pin as well as Pout. We can thus set up
equationsto solve for the coupling.
Probe
Probe I
S1i
Power
s-s,,s,,s,,sl S
Source
S11
[--*
21
2
1
[S1
S2
12
I
2
S
Power
Meter
Power Source
Equivalent
Equivalent
Power Meter
S,,
Source
Load
S11
Fig. A.12: Simplified S-parameterblock setup of Fig. A.11, by cascadingthe 2-port networks.
First, the equivalent S-parameters for the source and load side are found using the S and T
parameter transforms:
SEquivSource = Cascade(SFxuresource, Cascade(STunerurce
, Saourc ))
= S'TIS (TSarT (S xuriSource ).-TS-+ (STunerSource
)
Tsar(SBiasTSource))
SEquivad = Cascade(SThroughne, Cascade(S
= ST-S (TS+T (SThroughine )
Cascade(STunerLoad, SBiasM)ad )Fturead,
TST (S itureLoad) TS-T (STunerLoad ) TS-+T (SBiasTLoad))
Finding the power levels at the plane of reference, from both sides, gives:
PRight = POut,Measured - GATr (SEquivLoad 9SI ,PowerMeter)
PLeft = P,easured + GAT (SEquivSource S,PowerSour )- Coupling
Where Pin,Measured and POut,Measured are the power readings from the power meters (Fig. A.2 and 3),
SEquivLoad and SEquivSource are the combined S-parameter blocks from the equations above, and
Sll,PowerMeter and S11,PowerSource are the reflection coefficients (S 11 measurements) of the output
power meter and the power source. The coupling factor is found to be:
Coupling = PIn,Measured
-
POut,Measured +
GATT (SEquivSource
S
lPowerSource)+ GATT (SEquivLoad 'S
1.PowerMeter)
We have now found equations relating the readings of the input and output power meters to the
actual power available to the device (Pin) and the available power leaving the device (Pout). These
values are to be used in the computation of Gain, PAE and rid shown in be beginning of this
chapter.
Measuring the Reflected Power
In a general load-pull system, the reflected power from the gate of the device can also be
measured. For this, an additional power sensor needs to be inserted into the source side through a
coupler. This sensor will couple and measure the power reflected from the gate back into the
source. The mathematics for determining the reflected power will be identical to that of the
output power, as the setup will be identical to that shown in Figs. A.3 and A.8, with the insertion
of a directional coupler. To avoid having to create a 3-port model for the coupler, the power
meter reference plane (equivalent S11 and loss terms used in the setup shown in Fig. A.8) is best
established directly after the tuner. This typically coincides with the power source S11 (unless
the bias Tee and cables are treated as separate S-parameter blocks).
References
Ed., Wiley, pp. 206-212
[1]
D.M. Pozar, "Microwave Engineering",
n
2 d
[2]
D.M. Pozar, "Microwave Engineering",
2 nd Ed.,
Wiley, p. 216
[3]
D.M. Pozar, "Microwave Engineering",
2 nd Ed.,
Wiley, pp. 606-609
100
Appendix B
Measurement Equipment
This appendix lists the equipment used for the measurements and their manufacturers, as well
as a detailed system configuration:
Equipment List
Note: Not all equipment is used at the same time in the setup
Eauioment
Load Pull System
1.8-18 GHz Tuners
Manufacturer
PartNumber(s)
Tuner Controller
Measurement Software
Additional Measurement Software
MT982A02
Maury Microwave
MT986B02
Maury Microwave
Maury Microwave
Customized Software (written in VB.net)
Probe Station
8" Manual Probe Station
Noise Isolation Table (Airtable)
RF probes (GSG)
Cascade Microtech
Vibraplane
GGB Industries (PicoProbe)
Summit 11102B
Kinetic Systems
40M-GSG-126-PLL
2-18 GHz
Amplifier 2-4 GHz
Amplifier 4-8 GHz
Amplifier 8-18 GHz
Step Attenuator
HP
Hughes
Hughes
Hughes
HP
2-18 GHz, High power
Agilent
8672B
1177H01
1277H02
1177H15
11713A, 11716C,
8494H,8496H, 8120-2703
E8257C Opts 1El & 1EA
Power Source
Cables
Network Analyzer Calibration Cables
Probe-to-Tuner cables
All other cables
DC (coax)
Triax-to-coax DC adapters
Gore
GDOAKZ3G0520
Gore
G2KOD01008.0
Semflex
Y1N3HPT19036 0419, M119BFSM300360 414, M119BFSM30018
0414, M119BFSM30072 0415, M119BFSM30024 0414,
N119BFSN10018 0414, M219BFSM10018 0447
Trompeter
Off-the-shelf
ADBJ20-E2-PL75 0420
Trompeter
101
Passives
Directional Coupler
RF Isolator 2-4 GHz
RF Isolator 4-8 GHz
RF Isolator 8-18 GHz
Bias-Tees
Narda Microwave
Narda Microwave
Narda Microwave
Narda Microwave
Agilent
5292
4913
4914
IGS-8018
11612A
Maury Microwave
Maury Microwave
Maury Microwave
Maury Microwave
Maury Microwave
Maury Microwave
Maury Microwave
8022B 1
8022A1
2625B
7927D
2606D
2606C
8023D1
HP
HP
Agilent
Agilent
Agilent
6628A
4145B
E4419B
E9300A
E9300H
RF Adaptors
3.5mm(m)-ACP7
3.5mm(f)-ACP7
SMA(m)-ACP7
2.4mm(m)-3.5mm(f)
N(m)-ACP7
N(f)-ACP7
N(m)-3.5mm(m)
Other Major Equipment
DC Bias Source (drain)
DC Bias Source (gate)
Power Meter (dual channel)
Power Sensor (20 dBm, Input)
Power Sensor (30 dBm, Output)
Source Configuration A: Low Power RF Source
I
8"
RF Source
8672B
i"~-~r~
WT PA
127"I-12
~??
I
I
Power Meter
E4419B, E9300A
S
Isolator
IGS-8018
8022B1
Sr
RFProbe
Tuner
40M-GSG-125-PLL
ourT982A2
8022A1
G2KOD01008.0
Fig. B.1: Source-side setup for 8-18 GHz.
102
Source Configuration B: High Power RF Source
I
I
Power Meter
E41B E30
==
-m
24"
8022A1
-I
I
RF Sourc
8022A1
E8257C
18"
M219BFSM10018
RF Probe
8022A1
140M-GSG-125-PLL
ADBJ20-PL75
Fig. B.2: Source-side setup for 1.8-18 GHz.
Power Meter
E4419B, E9300H
I
Y1N3HPT19036
I
8022B1
RF Probe
LoadTuner
40M-GSG-125-PLL
MT982A02
G2KOD01008.0
8022A1
Fig. B.3: Load-side setup.
103
Input
PowerMeter
E4419B, E9300A
Y1N3HPT19036
Reflection
Power Meter
E4419B, E9300A
s3"
Y1N3HPT19036
Dual
Directional
Coupler
8022A
24"
_ _
_--
_"_
OUKK0024.0
8022A1
s18"
M219BFSM10018
Plane for Power Meter S,1 and Loss
I
-j
_
RF Probe
40M-GSG-125-PLL
Source Tuner
MT982A02
Bias Tee
11612A
G2KOD01008.0
8022A1
_
_
Bias
_Gate
ADBJ20-PL75
Fig. B.4: Possible modification of the source-side setup for 1.8-18 GHz to include a reflected
power measurement. The calibration plane for the reflection power meter is indicated.
104
Appendix C
Device Library
65 nm Devices
This section gives an overview of the devices fabricated in 65 nm technology for this work.
Sizing considerations as well as groups of possible sets of experiments are listed. Devices are
have an identifier number (id) to help locate them on the wafer. A map of the device locations is
shown at the end of the section.
Determining Device Sizes
The center device is sized to achieve a certain power range. This range is computed under the
following assumptions:
1.
desired output power = 100 mW (20 dBm)
2.
3.
at a PAE of 50%, and Vdd = 1 V, this requires a DC current of 200 mA
this current is estimated to be to 1/2 (class A) to 1/3 of In. Thus an Ion of 400 mA is
needed
with a current density of Io = 475 gA/jm, this corresponds to a width of 842 gim
the device size is chosen to be close to this number, with a roughly square layout and
number of fingers and unit finger width being divisible by powers of two (for ease of
scaling). A good fitting pair of numbers is 64 fingers at 12[tm finger width. The
finger width was kept low at 12gpm because of electromigration concerns. This device
has a total width of 768p.m.
4.
5.
Group 1
Aspect Ratio Changes
How does the aspect ratio of the layout (number of fingers versus unit finger width) impact the
RF performance of the device? The total width of the devices is held constant, so DC they should
all behave identical. But device parasitics will differ, as well as the current density in the wiring.
105
This set is also suitable to study electromigration (EM), since the aspect ratio change helps to
trade off the current density in the drain and source wires. Devices with many fingers have wide
source and narrow drain metal, while devices with high unit finger width have narrow source and
wide drain metal.
The RF performance may suggest a certain aspect ratio (e.g. square, 1:1) but EM may suggest a
different ratio, due to the asymmetric source and drain. We can also find out the maximum
device size that EM allows (max. wf determined by EM in source wire, and max nf determined
by the accumulation of current in the top drain metal (M4 or higher).
This device group includes the devices:
id
size
aspect ratio (NF * pitch / WO)
103
102
101
100
104
105
8 x 96 pan
16 x 48 gm
32 x 24 jun
64 x 12 pun
128 x 6 tm
256 x 3pm
1/46.2
1/11.5
1/2.88
1.39
5.55
22.2
Group 2
Power Cell Scaling
Two different approaches of combining multiple cells have been laid out. We wish to answer
which style is better performing, and how far scaling of power will be applicable - if we double
the number of cells, will we double the power? Do we pay a price in performance (PAE,
Linearity)? While theoretically the scaling should be linear, we will have to deal with different
devices or cells presenting different impedances to match to - potentially to a point where the
performance is degraded because the impedance necessary is out of the range of the matching
networks (or load-pull tuners).
This group includes 2-D structures and 1-D vertical layout. The vertical layout has less overlap
capacitance but also cannot scale to as big devices as the 2-D layout.
Each cell is sized NF x WF,G = 64 x 12 jim
1-D Vertical Layout:
id
106
107
108
109
110
# cells total width
1 768 gim
2 1536 gm
3 2304 gim
4 3072 gm
6 4608 gm
106
2-D Layout
id XbYY
200
201
202
203
204
205
206
207
208
209
210
308
309
310
cells
xl
x2
x3
x4
x6
xl
x2
x3
x4
x6
xl
x2
x4
x6
total width
1
768 plm
2
1536 pm
3
2304 jm
4
3072 pm
6
4608 pm
2
1536 pm
4
3072 gm
6
4608 pm
8
6144 pm
12
9216 pm
3
2304 pm
6
4608 pm
12
9216 pm
18
13824 pLm
Group 3
Power Cell Sizing
Besides trying to study the scaling behavior of power, we are also interested to know how the
cell size affects the performance. Issues here are parasitics, electro-migration and self-heating.
Starting with the standard cell, we device it up into multiple cells of smaller device size, but
overall hold the total width constant.
For example, a very large cell may suffer from distributed effects (Rg), self-heating and
electromigration. On the other hand, it will have fewer external parasitics. Therefore, there must
be an optimum cell size.
Devices are sized to give a square aspect ratio. Devices in this group include:
id
400
401
402
403
404
405
406
407
size
56 x 13.7 pm
38 x 10.2 prn
32 x 8 pgm
22 x 5.8 pm
16 x 4 pm
14 x 3 Ipm
8x 1.9 mun
4x 1 •m
individual widthX by Y # cells
1
lxl
767.2 jLm
2
2x 1
387.6 p.m
3x1
3
256 pLm
3x2
6
127.6 plm
3x4
12
64 gim
3x6
18
42 glm
5 x 10
50
15.2 gim
510x 18
180
4 plm
I
10x18
total width
767.2 plm
775.2 gpm
768.0 gim
765.6 gpm
768.0 pm
756.0 jgm
760.0 gLm
720.0 pm
The last two layouts (406 and 407) will be useful to study the impact of self-heating and EM,
since they should not express these effects due to their small size. However, parasitic
capacitances may be very high.
107
Group 4
L, and T,, Variations
This set studies the impact of the gate length and oxide thickness (i.e. I/O FETs). How much RF
power can each drive? We may support higher voltages at the I/O0 devices, but at the cost of
lower ft and fmax. This set is a good indicator of device performance as a function of technology
node, since the intrinsic device performance of the 1/O options is close to the older technologies
(0.251tm, 0.131im, etc). We are also able to determine if a performance loss/gain is due to the Tox
or the Lg increase.
Comparing this set of devices to the same I/O devices on the 90 nm wafers can be interesting,
since intrinsic device performance should be identical. However, the groundrules have changed,
and we can compare EM and performance with the differently sized backend metals in 65 and 90
nm.
Devices have constant total width, but aspect ratio adjusted. They include:
id
500
501
502
503
504
type
DGNFET
EGNFET
NFET
EGNFET
NFET
size
36 x 21 pm
38 x 20 •m
38 x 20 •m
43 x 18 pm
46 x 16 pm
width
756 pm
760 pm
760 pm
774 pm
736 pm
Li
0.24 pm
0.24 pm
0.24 pm
0.12 pm
0.12 pm
Group 5
Test Structures for Circuits
These experiments include a cascade (CS-CG) configuration as well as a grid of 2x2 cells where
only certain devices have the input connected to the gate. The other gates are connected to a DC
pad for biasing. This should help to study how the PAE behaves at low power levels if we simply
switching cells on/off. The performance will be not as good because the switched off devices still
contribute their drain parasitics to the output. Can we find a single matching network that
provides good performance for the 2x2 cell with 0,1,2 and 3 devices turned off? This is
important for applications where we require high PAE at different output power levels.
id
302
description
cascode, with Vbias of common-gate stage on a separate DC pad.
id
cell
on vs. off
206 4 vertical 4/4 on
304 4 vertical 3/4 on
303 4 vertical 2/4 on
302 4 vertical 1/4 on
Devices that are off have their gate connected to the DC pad instead of port 1 on the RF padset.
108
Group 6
Special Devices
This group includes devices with separate body contacts and experiments on isolation and EM.
Body Contact
300 standard device, but with body contact connected to DC pad
301 same as 300, but body contact at greater distance away from device
* study the impact of body voltage on performance, and impact of substrate resistance. Also
useful in model development
De-embedding
408 de-embedding structure: standard device, OPEN
409 de-embedding structure: standard device, SHORT
410 standard device, no contacts to the drain and source. use for measuring the backend
capacitances
Isolation
505 standard device, with M1/M2 ground plane under gate and drain.
506 standard device, but with body contact running from top/bottom shielding the gate side of
the device from the drain side
* study how isolation and ground planes affect the matching and performance
Current Flow
507
1 gim of vias and M3 over the source
508 vias and M3 fully over the source
509 vias and M3 fully over the source, and maximum width (factor 2.2x) M2 and M3 source
wires
* use these to study the tradeoff of increased source current density (by reducing peak current in
M2) and parasitic drain-source capacitance
Other
510 CA landing on PC aligned with the gate
* fewer CAs, but directly centered at the gate fingers. Does this improve performance? In the
standard device, PC gate fingers sometimes start in-between two CAs, increasing gate resistance.
Group 7
EM Lines
These structures are to study the EM behavior of a M1-M2 line under DC and AC+DC current.
They consist of a thin metal line on M1 connected to M2 by the number of vias mentioned.
607
608
M1 - 2x V1 - M2
M1 - 5x V1 - M2
609
Ml - 5x VI - M2, with short fins
109
610 Ml - 5x V1 - M2, with long fins
The fins in 609 and 610 are used to study how heating affects EM. They are intended as heat
sinks.
Device Summary
id
100
101
102
103
104
105
106
107
108
109
110
200
201
202
203
204
205
206
207
208
209
210
300
301
302
303
304
305
Grcaup(s) device size
1
64 x 12
1
32 x 24
1
16 x 48
1
8 x 96
1
128 x 6
1
256 x 3
2
64 x 12
2
64 x 12
2
64 x 12
2,5
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64 x 12
2
64x 12
6
64 x 12
6
64 x 12
5
64 x 12
5
64 x 12
5
64 x 12
5
64 x 12
306,307 - do not exist
308 2
64 x 12
309 2
64 x 12
310 2
64x12
400 3
56 x 13.7
401 3
38 x 10.2
402 3
32 x 8
403 3
22 x 5.8
404 3
16 x 4
c4~11(s)
specials
standard cell
1 vertical
2 vertical
3 vertical
4 vertical
6 vertical
1 xl
1 x2
1 x3
1 x4
1 x6
2 xl
2 x2
2 x3
2 x4
2 x6
3 xl
body contact (standard)
body contact (far)
4 vertical 1 device on, 3 connected to DC pad
4 vertical 2 device on, 2 connected to DC pad
4 vertical 3 device on, 1 connected to DC pad
2 in cascode cascade (CS-CG) with CG's gate at DC pad
3 x2
3 x4
3 x6
1 xl
2 xl
3 xl
3 x2
3 x4
110
405 3
406 3
407 3
408 6
409 6
410 6
500 4
501 4
502 4
503 4
504 4
505 6
506 6
507 6
508 6
509 6
510 6
600-606 - do not
607 7
608 7
609 7
610 7
14 x 3
3x6
8 x 1.9
5x10
10 x 18
4x 1
64 x 12
64 x 12
64 x 12
36 x 21
38 x 20
38 x 20
43 x 18
46 x 16
64 x 12
64 x 12
64 x 12
64 x 12
64 x 12
64 x 12
OPEN
SHORT
No Source/Drain CA
DGNFET, LG=0.24um
EGNFET, LG=0.24um
NFET, LG=0.24um
EGNFET, LG=0.12um
NFET, LG=0.12um
Ml ground plane
body contact isolation
part M3 source wire over M2
full M3 source wire over M2
M2/M3 source wire at 2.2x width
PC/CA aligned
exist
2 vias
5 vias
5 vias, short fin
5 vias, long fin
Device ILocation in Macros
There are three macros (ac_pwrl-3) and one long horizontal macro with two device rows. The
devices are found:
AC PWR1
-other-other-other-other-other-other510
100
101
102
103
AC PWR2 AC PWR3
200
500
201
501
202
502
203
503
204
504
205
505
206
506
207
104
208
105
209
408
210
409
AC_PwrHoriz (no label b/c of space issues)
400
401
402
403
404
405
406
407
308
309
410
310
300
301
302
303
304
305
106
107
108
109
110
507
508
509
The 607-610 macro is found on the side of the block containing the above horizontal macro.
111
90 nm Devices
Devices on the 90 nm wafer are grouped the same way as previously the 65 nm devices in 2.1.1.
Only new aspects compared to the ones mentioned above in the 65 nm section are shown below:
Group 1
Aspect Ratio Changes
id
size
aspect ratio (nf * pitch / wf)
102
12 x 64 jim
1/14.8
101
100
103
104
24 x 32 gm
48 x 16 Lm
96 x 8 gim
192 x 4 gm
1/3.7
1.08
4.32
17.28
Group 2
Power Cell Scaling
1-D Vertical Layout:
id
# cells total width
200
201
202
2
3
4
1536 ptm
2304 gtm
3072 gLm
2-D Layout
id
X by Y
109
203
204
205
1x2
2 x1
2x2
2x4
# cells total width
2
2
4
8
1536 gtm
1536 gm
3072 gim
6144 jlm
Group 3
Power Cell Sizing
id
105
106
107
206
207
size
32 x 12 pm
24 x 8 jm
16 x 6 jm
12 x 16 pm
24 x 16 gm
individual widthX by Y # cells
384 im
2 x1
2
192 gm
96 gm
192 jim
384 gm
2x2
2x4
2x 4
2x2
4
8
8
4
112
total width
768 jLm
768 jim
768 jim
1536 ptm
1536 jlm
208
209
203
210
96 x 16 [Lm
48 x 8 jm
48 x 16 gm
48 x 32 Wmn
1536 jim
384 jim
768 jlm
1536 gim
1536 gim
1536 gm
1536 gm
1536 gm
2x2
2x1
206-210 are used to study the tradeoff of expanding the cell along the number of fingers or unit
finger width axis (device size and id number in parenthesis):
48x8
(209)
12x16 24x16 48x16 96x16
(206) (207) (203) (208)
48x32
(210)
Alternatively, instead of 203 for the 48x16 center, 109 can also be used (the difference is the way
the two 48x16 cells are arranged).
Group 4
Lg and T.x Variations
id
400
401
402
403
404
----
tvDe
m
NFET
NFET
EGNFET
EGNFET
DGNFET
width
544 jm
x 20 11m 600 jlm
x 16 9im 544 jim
x 20 jim 600 jm
x 20 9lm 600 gm
size
x 16 jim
0.12
0.24
0.12
0.24
0.24
jlm
jlm
jlm
jlm
Group 5
Test Structures for Circuits
There are no structures of this group in 90 nm.
Group 6
Special Devices
This group includes devices with separate body contacts and experiments on isolation and EM.
Body Contact
300 standard device, but with body contact connected to DC pad
301 same as 300, but body contact at greater distance away from device
113
De-embedding
304
de-embedding structure: standard device, OPEN
305 de-embedding structure: standard device, SHORT
110 de-embedding structure: standard device, THROUGH
Isolation
These devices should help to study how much the ground plane shielding impacts efficiency
(PAE).
305
standard device, with M1/M2 ground plane under gate and drain.
311
standard device, but without any ground plane under the gate and drain pads
Maximum Width
To study the behavior of cell vs. single device for very large devices, as well as the power limits
of CMOS.
id
308
309
size
cell width
192 x 64 pm 12288 gm
64 x 24 pm 1536 gm
cell
1
2x4
total width
12288 gtm
12288 gtm
Capacitance and EM
Can widening the MI source metal improve performance by reducing gate-to-drain feedback
capacitance? What is the impact of increasing the gate pitch and widening the metal M1 and M2
going to the source?
308
G/S overlap: widen M1 as much as groundrules permit
307
increase the spacing of the gate, so that the metal can be thicker
109
flipped source and drain routing into the device. Source comes in vertical now. Helps in
EM investigation and study of parasitics.
Other
303 Layout using the standard RF PCell. Answers the question how much improvement in
performance and EM reliability the layouts have brought compared to a simple (naive?)
layout.
Group 7
EM Lines
There are no structures of this group in Tomcat.
114
Device Summary
Summary device size cell(s)
Group(s)
Device
100
,48 x 16
id
101
102
103
104
105
106
107
108
109
110
200
201
202
203
204
205
206
207
208
209
210
300
301
302
303
304
305
306
307
308
309
310
400
401
402
403
404
specials
standard cell
24 x 32
12 x 64
96 x 8
192x 4
32 x 12
24 x 8
16 x 6
48 x 16
2x1
2x2
2x4
1x2
flip s/d
through
48 x 16
48x 16
48 x 16
48 x 16
48 x 16
48 x 16
48 x 16
48 x 16
12 x 16
24 x 16
96x 16
48 x 8
48 x 32
48 x 16
48 x 16
48 x 16
48x 16
48 x 16
48 x 16
48 x 16
48x 16
192 x 64
64 x 24
48 x 16
34 x 16
30 x 20
34x 16
30 x 20
30 x 20
2 verti cal
3 verti cal
4 vertical
2x1
2x2
2x4
2x4
2x2
2x2
2x4
separate body contact
separate body contact, far from device
IBM RF PCell
open
short
ground plane
increased metal 1 and 2, gate pitch
G/S overlap on M1
maximum width
maximum width in cells
no ground plane under pads
NFET, Lg = 0.12um
NFET, Lg = 0.24um
EGNFET, Lg = 0.12um
EGNFET, Lg = 0.24um
DGNFET, Lg = 0.24um
115
Device Location in Macros
There are four macros (ac_pwrl-4) The devices are arranged as follows:
AC_PWR1 AC PWR2 AC_PWR3 AC PWR4
100
200
300
400
101
201
301
401
102
202
109
402
103
203
410**
403
104
204
310
404
105
205
305
405**
306
406**
106
206
107
207
307
407**
108
208
308
305***
302
209
309
409**
110
210
304
303
** non-functional, as source and drain are shorted together
*** wrong device
116
Bibliography
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
J. Scholvin, D.R. Greenberg, J.A. del Alamo, "RF power potential of 90 nm CMOS:
device options, performance, and reliability", IEEE International Electron Devices
Meeting, Dec 2004, pp. 4 5 5 -4 5 8 .
W. Schuchter et al., IEEE RFIC, June 2001, pp. 183-186
I. Aoki et al., IEEE CICC, May 2001, pp. 57-60
Y Zhang et al., IEEE RFIC, June 2004, pp. 563-566
D. Su et al., IEEE CICC, May 1997, pp. 189-192
H.M. Hsu et al., IEEE Trans. MTT, Dec 2002, pp. 2873-2881
M. Ferndahl, H.O. Vickes, H. Zirath, I. Angelov, F. Ingvarson, A. Litwin; "90-nm CMOS
for microwave power applications", Microwave and Wireless Components Letters, IEEE,
Volume: 13, Issue: 12, Dec. 2003, pp. 523 - 525.
D. James, "2004- The Year of 90-nm: A Review of 90 nm Devices", IEEE/SEMI
Advanced Semiconductor Manufacturing Conference and Workshop, Apr. 2005, pp. 7276.
RF2681, preliminary product data sheet, RF Micro Devices, Rev A8 040512, pp. 529 536
E. Chen, D. Heo, M Hamai, J. Laskar, D. Bien; "0.24-um CMOS technology for
Bluetooth power applications", IEEE Radio and Wireless Conference, 2000, pp. 163 166.
J. Scholvin, D.R. Greenberg, and J.A. del Alamo, "Performance and limitations of 65 nm
CMOS for integrated RF power applications", IEEE Int. Electron Devices Meeting, 2005,
pp. 369-372
W. Jeamsaksiri, D. Linten, S. Thijs, G. Carchon, J. Ramos, A. Mercha, X. Sun, P.
Soussan, M. Dehan, T. Chiarella, R. Venegas, V. Subramanian, A. Scholten, P.
Wambacq, R. Velghe, G. Mannaert, N. Heylen, R. Verbeeck, W. Boullart, I. Heyvaert,
M. I. Natarajan, G. Groeseneken, I. Debusschere, S. Biesemans, S. Decoutere, "A lowcost 90nm RF-CMOS platform for record RF circuit performance", IEEE 2005
Symposium on VLSI Technology, pp. 60 - 61.
L.F. Tiemeijer, R.J. Havens, R. De Kort, A.J. Scholten, R. Van Langevelde, D.B.M.
Klaassen, G.T. Sasse, Y. Bouttement, C. Petot, S. Bardy, D. Gloria, P. Scheer, S. Boret,
B. Van Haaren, C. Clement, J.F. Larchanche, I.S. Lim, A. Zlotnicka, A. Duvallet,
"Record RF performance of standard 90 nm CMOS technology", IEEE International
Electron Devices Meeting, Dec 2004, pp. 441-444.
B. Jagannathan, R. Groves, D. Goren, B. Floyd, D. Greenberg, L. Wagner, S. Csutak, S.
Lee, D. Coolbaugh, J. Pekarik, "RF CMOS for Microwave and MM-wave Applications",
IEEE 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp.
259-264.
P.H. Woerlee, M.J. Knitel, R. van Langevelde, D.B.M. Klaassen, L.F. Tiemeijer, A.J.
Scholten, A.T.A. Zegers-van Duijnhoven, "RF-CMOS Performance Trends", IEEE
Transactions on Electron Devices, Vol. 48, No. 8, Aug 2001, pp. 1776-1782.
IBM 65 nm press coverage
http://www.eet.com/news/semi/showA rticle.jhtml?articlelD=164302481
117
[17]
[18]
[19]
[20]
[21]
[22]
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
E. Alekseev, et al, Trans. MTT, Oct 2000, pp. 1694-1700
P. Kurpas, et al, IEDM 2002, pp. 681-684
F. van Raay, et al, MTT-S 2003, pp. 451-454
H. Brech, et al, MTT-S 2003, pp. 209-212
I.P. Smorchkova, et al, Trans. MTT, Feb 2003, pp. 665-668
E. Ferro, F Potorti, "Bluetooth and Wi-Fi Wireless Protocols: A Survey and A
Comparison", IEEE Wireless Communications, Feb. 2005, pp. 12-26.
B. Jagannathan, R. Groves, D. Goren, B. Floyd, D. Greenberg, L. Wagner, S. Csutak, S.J.
Lee, D. Coolbaugh, J. Pekarik, "RF CMOS for microwave and MM-wave applications",
IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2006,
pp. 259-264.
C.S. Chang, C.P. Chao, G.J. Chern, Y.C. Sun, "Advanced CMOS Technology Portfolio
for RF IC Applications", IEEE Transactions on Electron Devices, Vol. 52, No. 7, July
2005, pp. 1324-1334.
D. Buss, B.L. Evans, J. Bellay, W. Krenik, B. Haroun, D. Leipold, K. Maggio, J.Y. Yang,
T. Moise, "SOC CMOS Technology for Personal Internet Products", IEEE Transactions
on Electron Devices, Vol. 50, No. 3, March 2003, pp. 5 4 6 -5 5 6
UC Berkeley BSIM documentation:
http://www-device.eecs.berkeley.edul~-bsim31
Bond Wire
C. Yoo, Q. Huang, "A Common-Gate Switched 0.9-W Class-E Power Amplifier with
41% PAE in 0.25-ym CMOS", IEEE Journal of Solid State Circuits, Vol. 36, No. 5, May
2001, pp. 823-830.
T.C. Kuo, B.B. Lusignan, "A 1.5W Class-F RF Power Amplifier in 0.2 jtm CMOS
Technology", ISSCC 2001, pp. 154 - 15 5 .
S.C. Cripps, "RF Power Amplifiers for Wireless Communications", Artech House, 1st
Edition, 1999, pp. 54-60
The following is a list of references used in compiling the power data in chapter 1. The
references are abbreviated to save space and only mention the authors, publication and year.
[31]
SP Knight, DA Daly, M Caulton ; IEEE ISSCC; 1/1968
[32]
PT Chen, HP; IEEE ISSCC; 1/1973
[33]
[34]
L Napoli, R DeBrecht ; IEEE MTT-S; 6/1973
PT Chen ; IEEE J SS Circ; 7/1974
[35]
[36]
YS Wu, HT Yuan, JB Kruger ; IEEE ISSCC; 1/1976
HQ Tserng, V Sokolov, HM Macksey, WR Wissman ; IEEE MTT-S; 6/1976
[37]
Y Arai, T Kouno, T Horimatsu, H Komizo ; IEEE Trans MTT; 6/1976
[38]
[39]
[40]
[41]
[42]
[43]
[44]
[45]
[46]
[47]
[48]
[49]
JG Oakes, RA Wickstrom, DA Tremere, TMS Heng ; IEEE Trans MTT; 6/1976
M Fukuta, K Suyama, H Suzuki, Y Nakayama, H Ishikawa ; IEEE Trans MTT; 6/1976
Y Saito, S Akasaka, S Fukuda, I Haga ; IEEE MTT-S; 6/1978
HT Yuan, YS Wu ; IEEE MTT-S; 6/1978
PT Ho ; IEEE MTT-S; 6/1978
KB Niclas, RB Gold, WT Wilser, WR Hitchens ; IEEE J SS Circ; 7/1978
V Sokolov, RE Williams, DW Shaw ; IEEE ISSCC; 1/1979
PT Ho, CM Pham, RL Mencik ; IEEE MTT-S; 4/1979
RA Pucel, P Ng, J Vorhaus ; IEEE MTT-S; 4/1979
S Aihara, Y Fujiki, S Fukuda, S Akasaka, I Haga ; IEEE MTT-S; 4/1979
H Abe, Y Aono ; IEEE Trans MTT; 4/1979
JTC Chen, CP Snapp ; IEEE Trans MTT; 4/1979
118
[50]
[51]
[52]
[53]
[54]
[55]
[56]
[57]
[58]
[59]
[60]
[61]
[62]
[63]
[64]
[65]
[66]
[67]
[68]
[69]
[70]
[71]
[72]
[73]
[74]
[75]
[76]
[77]
[78]
[79]
[80]
[81]
[82]
[83]
[84]
[85]
[86]
[87]
[88]
[89]
[90]
[91]
[92]
[93]
[94]
[95]
[96]
[97]
[98]
[99]
[100]
[101]
[102]
[103]
Y Kadowaki, M Nakatani, T Ishii, S Mitsui, K Shirahata ; IEEE MTT-S; 12/1979
M Nakatani, Y Kadowaki, T Ishii ; IEEE Trans MTT; 12/1979
JA Higgins, RL Kuvas ; IEEE Trans MTT; 1/1980
KB Niclas, WT Wilser, RB Gold, WR Hitchens; IEEE Trans MTT; 3/1980
JL Vorhaus, RA Pucel, Y Tajima, W Fabian ; IEEE ISSCC; 1/1981
Y Mitsui, M Kobiki, M Wataze, K Segawa, M Otsubu, T Ishii ; IEEE Trans MTT; 4/1981
J Sone, Y Takayama ; IEEE Trans MTT; 4/1981
D Laighton, J Sasonoff, J Selin ; IEEE MTT-S; 6/1981
RL Camisa, JB Klatskin, A Mikelsons ; IEEE MTT-S; 6/1981
V Sokolov, RC Bennett; IEEE MTT-S; 6/1981
SR Mazumder, T Dao, TL Tsai, WC Tsai ; IEEE MTT-S; 6/1982
J Goel, G Oransky, S Yuan, P O'Sullivan, J Burch; IEEE MTT-S; 6/1982
T Tsukii, Y Tajima, PD Miller, R Mozzi, EK Tong ; IEEE ISSCC; 1/1983
A Barzeghi, F Oggionni, G Pratesi ; IEEE MTT-S; 6/1983
F Sechi, R Brown, P Jozwiak, G Rolland, J Brown, E Mykietyn; IEEE MTT-S; 6/1983
RG Gels, RD Standley, DL Wilson, R Trambarulo ; IEEE MTT-S; 6/1983
T Noguchi, Y Aono, K Watanabe, S Kameda ; IEEE J Sel A Com; 9/1983
Y Tokumitsu, T Saito, N Okubo, Y Kaneko; IEEE Trans MTT; 3/1984
BM Kim, HQ Tserng, P Saunier ; IEEE Trans MTT; 3/1984
Y Ayasli, LD Reynolds, RL Mozzi, LK Hanes ; IEEE Trans MTT; 3/1984
Y Hirachi, Y Takeuchi, M Igarashi, K Kosemura, S Yamamoto ; IEEE Trans MTT; 3/1984
CD Palmer, P Saunier, RE Williams; IEEE MMWMC; 4/1984
CD Chang, SK Wang, LCT Liu, M Siracusa, H Yamasaki, JM Schellenberg ; IEEE MMWMC; 4/1985
P Saunier, HQ Tserng, B Kim, GH Westphal ; IEEE MMWMC; 6/1985
HM Macksey, HQ Tserng, HD Shih ; IEEE MMWMC; 6/1985
DM Drury, DC Zimmermann, DE Zimmerman ; IEEE MTT-S; 6/1985
A Ezzeddine, HLA Hung HC Huang ; IEEE MTT-S; 6/1985
AAM Saleh, MF Wazowicz ; IEEE Trans MTT; 7/1985
E Belohoubek, R Brown, H Johnson, A Fathy, D Bechtle, D Kalokitis, E Mykietyn ; IEEE MTT-S; 6/1986
SK Wang, KG Wang, CD Chang; IEEE MMWMC; 6/1986
JR Lane, RG Freitag, JE Degenford, M Cohn ; IEEE MTT-S; 6/1986
KB Bhasin, IDJ Connolly ; IEEE Trans MTT; 10/1986
D Bechtle, J Klatskin, G Taylor, M Eron, SG Liu, RL Camisa, H Dudley ; IEEE MTT-S; 6/1987
S Nishiki, T Nojima ; IEEE MTT-S; 6/1987
HLA Hung, A Ezzeddine, LB Holdeman, FR Phelleps, JF Allison, AB Cornfeld, T Smith, HC Huang;
IEEE MMWMC; 6/1987
JJ Komiak; IEEE GaAs IC; 1/1988
E Nakanishi, J Shibata, O Ohsawa; IEEE; 1/1988
AE Geissberger, IJ Bahl, EL Griffin, RA Sadler ; IEEE TED; 4/1988
BD Geller, PE Goettle ; IEEE MTT-S; 4/1988
B Kopp, DD Heston ; IEEE MTT-S; 4/1988
M Avasarala, DS Day, S Chan, P Gregory, JR Basset ; IEEE MTT-S; 4/1988
T Nojima, S Nishiki ; IEEE MTT-S; 4/1988
Y Oda, S Arai, T Yoshida, H Nakamura, S Yanagawa, S Hori, K Kamei ; IEEE MTT-S; 6/1988
C Peignet, Y Mancusco, G LeMeur, L Remiro, A Bert, JF Jouen, P Savary ; IEEE MTT-S; 6/1988
SD Pritchett ; IEEE MMWMC; 6/1988
G Hegazi, HLA Hung, JL Singer, FR Phelleps, AB Cornfeld, T Smith, JF Bass, HE Carlson, HC Huang;
IEEE MMWMC; 6/1988
N Camilleri, B Kim, HQ Tserng, HD Shih ; IEEE MMWMCS; 6/1988
RB Culbertson, DC Zimmermann; IEEE; 6/1988
JA Higgins ; IEEE GaAs IC; 10/1988
P Saunier, HQ Tserng, N Camilleri, K Bradshaw, HD Smith ; IEEE GaAs IC; 10/1988
HLA Hung, G Hegazi, KE Peterson, FR Phelleps, HC Huang ; IEEE GaAs IC; 10/1988
MJ Schindler, JP Wendler, MP Zaitlin, ME Miller, JR Dormail ; IEEE Trans MTT; 12/1988
KH Snow, JJ Komiak, DA Bates ; IEEE Trans MTT; 12/1988
HLA Hung, GM Hegazi, TT Lee, FR Phelleps, JL Singer, HC Huang ; IEEE Trans MTT; 12/1988
119
[104]
[105]
[106]
[107]
[108]
[109]
[110]
[111]
JL Vorhaus ; IEEE MTT-S; 6/1989
KE Peterson, HL Hung, FR Phelleps, TF Noble, HC Huang ; IEEE MTT-S; 6/1989
IJ Bahl, R Wang, A Geissberger, E Griffin; IEEE MMWMCS; 6/1989
M Avasarala, DS Day, S Chan, C Hua, JR Basset ; IEEE MMWMCS; 6/1989
Y Oda, T Yoshida, K Kai, S Arai, S Yanagawa; IEEE MMWMCS; 6/1989
AL Riley, D Rascoe, V Lubecke, J Huang, L Duffy ; IEEE MMWMCS; 6/1989
FS Auricchio, RA Rhodes, DS Day; IEEE MTT-S; 6/1989
DW Ferguson, PM Smith, PC Chao, LF Lester, RP Smith, P Ho, A Jabra, JM Ballingall ; IEEE MTT-S;
6/1989
[112] YC Shih, K Tan, K Kasel, KK Yu, SK Wang ; IEEE MTT-S; 6/1989
[113] PM Smith, MY Kao, P Ho, PC Chao, KHG Duh, AA Jabra, RP Smith, JM Ballingall ; IEEE MTT-S;
6/1989
[114] AP Long, IH Goodridge, JP King, AJ Holden, JG Metcalfe, RF Hayes, R Nicklin, RC Goodfellow ; IEEE
Elec Letters; 7/1989
[115] S Sriram, RC Clarke, RL Messham, TJ Smith, MC Driver ; IEEE HSSDC; 7/1989
[116] IJ Bahl, EL Griffin, AE Geissberger, C Andricos, TF Brukiewa ; IEEE Trans MTT; 9/1989
[117] N Camilleri, P Chye, R Prioriello ; IEEE GaAs IC; 10/1989
[118] M Avasarala, DS Day, C Hua, S Chan, JR Basset ; IEEE GaAs IC; 10/1989
[119] B Bayraktaroglu, MA Khatibzadeh, RD Hudgens; IEEE GaAs IC; 10/1989
[120] AW Swanson, PM Smith, PC Chao, KH Duh, JM Ballingall ; IEEE; 12/1989
[121] VD Hwang, YC Shih, TY Chi, DC Wang ; IEEE; 1/1990
[122] B Bayraktaroglu, MA Khatibzadeh, RD Hudgens ; IEEE; 1/1990
[123] AK Ezzeddine, HLA Hung, HC Huang ; IEEE Trans MTT; 4/1990
[124] M Minowa, M Onoda, E Fukuda, Y Daido ; IEEE Veh Tech Conf; 4/1990
[125] MA Khatibzadeh, HQ Tserng ; IEEE ; 4/1990
[126] MA Khatibzadeh, B Bayraktaroglu ; IEEE; 4/1990
[127] RD Boesch, JA Thompson ; IEEE ; 6/1990
[128] T Ho, F Phelleps, G Hegazi, K Pande, H Huang, P Rice, P Pages; IEEE MILCOM; 10/1990
[129] B Geller, J Tyler, L Holdeman, F Phelleps, P Cline, G Laird ; IEEE GaAs IC; 10/1990
[130] H Le, YC Shih, T Chi, K Kasel, DC Wang; IEEE ; 10/1990
S Sriram, RL Messham, TJ Smith, HM Hobgood, MC Driver ; IEEE ; 10/1990
[131]
[132] SR LeSage, MJ Mendes, MJ Sullivan ; IEEE; 10/1990
[133] R Ramachandran, M Nijar, A Podell, E Stoneham, S Mitchell, NL Wang, WJ Ho, MF Chang, GJ Sullivan,
JA Higgins, PM Asbeck, T Cisco ; IEEE; 10/1990
[134] M Avasarala, DS Day, S Chan, C Hua, JR Basset ; IEEE; 10/1990
[135] JJ Komiak ; IEEE Trans MTT; 12/1990
[136] DC Streit, KL Tan, RM Dia, JK Liu, AC Han, JR Velebir, SK Wang, TQ Trinh, PMD Chow ; IEEE EDL;
4/1991
[137] DT Bryant ; IEEE MTT-S; 6/1991
[138] JA Lester, WL Jones, PD Chow ; IEEE MTT-S; 6/1991
[139] G Hegazi, E Chang, J Singer, F Phelleps, P McNally, K Pande ; IEEE MTT-S; 6/1991
[140] H Takeuchi, M Muraoka, T Hatakeyama, A Matsuoka, M Honjou, S Miyazaki, K Tanaka, T Nakata ; IEEE
MTT-S; 6/1991
[141] J Ozaki, K Arai, M Miyauchi, S Watanabe, S Kamihashi ; IEEE MMWMCS; 6/1991
A Asensio, F Perez; IEEE ISSCC; 6/1991
[142]
[143] H Le, YC Shih, V Hwang, T Chi, K Kasel, DC Wang; IEEE; 6/1991
[144] M Gat, DS Day, JR Basset; IEEE; 6/1991
[145] DW Ferguson, SA Allen, MY Kao, PM Smith, PC Chao, MAG Upton, JM Ballingall ; IEEE ; 6/1991
[146] FW Smith, CL Chen, LJ Mahoney, MJ Manfra, DH Temme, BJ Clifton, AR Calawa ; IEEE ; 6/1991
[147] D Helms, JJ Komiak, WF Kopp, P Ho, PM Smith, RP Smith, D Hogue ; IEEE ; 6/1991
[148] KE Peterson, HLA Hung, FR Phelleps, EY Chang, JL Singer, HE Carlson, AB Cornfeld ; IEEE ; 6/1991
[149] M Gat, DS Day, JR Basset ; IEEE ; 6/1991
[150] B Maoz, BE Bedard, A Oki ; IEEE BCTM; 9/1991
[151] HM Le, YC Shih, VD Hwang, TY Chi, KJ Kasel, DC Wang ; IEEE; 10/1991
[152] P Bartusiak, T Henderson, T Kim, A Khatibzadeh, B Bayraktaroglu ; IEEE Elec Letters; 10/1991
120
[153]
[154]
[155]
[156]
[157]
[158]
[159]
[160]
[161]
[162]
[163]
[164]
[165]
[166]
[167]
[168]
[169]
[170]
[171]
[172]
[173]
[174]
[175]
[176]
[177]
[178]
[179]
[180]
[181]
[182]
[183]
[184]
[185]
[186]
[187]
[188]
[189]
[190]
[191]
[192]
[193]
[194]
[195]
[196]
[197]
[198]
[199]
[200]
H Yang, RM Herman, KW Angel, AM Chao, MJ Schindler, M Adlerstein, Y Tajima, DM Danzilio ; IEEE
GaAs IC; 10/1991
M Gat, DS Day, S Chan, C Hua, JR Basset ; IEEE ; 10/1991
HM Le, YC Shih, T Chi, L Fong, K Kasel ; IEEE; 10/1991
TC Cheng ; IEEE IEE Coil on SSPA; 12/1991
D Ryan, G Railton ; IEEE IEE Coll on SSPA; 12/1991
GJ Ayling, JS Joshi ; IEEE IEE Coil on SSPA; 12/1991
G Collinson, CW Suckling ; IEEE IEE Coll on SSPA; 12/1991
G Hegazi, K Pande, F Phelleps, E Chang, A Cornfeld, P Rice, M Ghahremani, P Pages ; IEEE MWGW
Letters; 1/1992
J Mondal, J Geddes, D Carlson, M Vickberg, S Bounnak, C Anderson ; IEEE ; 3/1992
T Takagi, Y Ikeda, K Seino, G Toyoshima, A Inoue, N Kasai, M Takada ; IEEE MMWMCS; 6/1992
MA Khatibzadeh, B Bayraktaroglu, T Kim; IEEE MMWMCS; 6/1992
M Cicolani ;IEEE MTT-S; 6/1992
TH Miers, VA Hirsch ; IEEE MTT-S; 6/1992
J Goel, KL Tan, DI Stones, RW Chan, DC Streit, S Peratoner, J Schellenberg ; IEEE MTT-S; 6/1992
D Raicu, BM Kraemer, DS Day, JR Basset, J Wei, C Hua, Y Chung, CS Chang; IEEE MTT-S; 6/1992
K Johnson, A Lum, S Nelson, E Reese, K Salzman ; IEEE ; 6/1992
HQ Tserng, P Saunier, TC Kao ; IEEE; 6/1992
R Actis, KB Nichols, RW Chick, RA McMorran ; IEEE; 6/1992
JM Schellenberg, KL Tan, RW Chan, CH Chen, TS Lin, DC Streit, PH Liu ; IEEE ; 6/1992
GS Dow, K Tan, N Ton, J Abell, M Siddiqui, B Gorospe, D Streit, P Liu, M Sholley ; IEEE; 6/1992
M Easton, R Basset, DS Day, C Hun, CS Chang, J Wei ; IEEE ; 6/1992
T Ho, G Metze, A Cornfeld, T Lee, K Pande, H Huang, P Ferguson, M Foisy ; IEEE MWGW Letters;
7/1992
JI Upshur, PE Goettle, BD Geller, RK Gupta, F Phelleps ; IEEE Midwest CSC; 7/1992
JP Mondal, JJ Geddes, RC Becker, A Contolatis, M Vickberg, D Carlson, SS Bounnak, C Anderson, V
Sokolov; IEEE J SS Circ; 10/1992
H Wang, DC Yang, MV Aust, EA Rezek, BR Allen, LA Fletcher, RC Becker ; IEEE J SS Circ; 10/1992
WJ Soo Hoo, RF Tenney, G Besenyei, PL Ritchie, DR Daugherty, AE Buchanan ; IEEE MILCOM;
10/1992
A Platzker, KT Hetzler, J Bradford Cole ; IEEE ; 10/1992
CK Pao, GL Lan, CS Wu, A Igawa, M Hu, JC Chen, YC Smith ; IEEE ; 10/1992
T Ho, K Pande, F Phelleps, J Singer, P Rice, J Adair, M Ghahremani ; IEEE Elec Letters; 10/1992
TH Chen, KL Tan, GS Dow, H Wang, KW Chang, TN Ton, B Allen, J Berenz, PH Liu, D Streit, G
Hayashibara ; IEEE GaAs IC; 10/1992
PJ Bartusiak, T Henderson, T Kim, B Bayraktaroglu ; IEEE; 10/1992
T Arell, TK Hongsmatip ; IEEE; 10/1992
M Goldfarb, B Erfany, P Bernkopf ; IEEE; 10/1992
JJ Komiak, D Helms ; IEEE; 10/1992
S Cooper, K Anderson, K Salzman, R Culbertson, J Mason, D Bryant, P Saunier ; IEEE; 10/1992
S Murai, T Sawai, T Yamaguchi, S Matsushita, Y Harada ; IEEE; 10/1992
WJ Ho, NL Wang, MF Chang, JA Higgins ; IEEE ; 10/1992
NL Wang, WJ Ho, JA Higgins ; IEEE; 10/1992
GW Wroblewski, F McMahon, M Kleidermacher, DW Ferguson ; IEEE; 12/1992
NL Wang, WJ Ho, AL Sailer, JA Higgins ; IEEE MWGW Letters; 3/1993
M Gillick, S Lucyszyn, U Karacaoglu, ID Robertson, AH Aghvami ; IEEE RAMSSSSA; 3/1993
M Matloubian, AS Brown, LD Nguyen, MA Meledes, LE Larson, MJ Delaney, MA Thompson, RA
Rhodes, JE Pence ; IEEE ; 4/1993
D Ngo, B Beckwith, P O'Neil, N Camilleri ; IEEE MTT-S; 6/1993
JW Gipprich, LE Dickens, JA Faulkner; IEEE MTT-S; 6/1993
N Camilleri, J Costa, D Lovelace, D Ngo ; IEEE MTT-S; 6/1993
K Kurdoghlian, CS Wu, W Yau, J Chen, M Hu, C Pao, D Bosch; IEEE; 6/1993
MV Aust, B Allen, GS Dow, R Kasody, G Luong, M Biedenbender, K Tan; IEEE; 6/1993
S Hara, H Sato, JK Twynam, M Akagi, N Nambu, N Tanba, K Yoshikawa, T Kinosada, M Yagura, H
Tsuji, T Shinozaki, T Yoshimasu, T Miyajima, T Tomita; IEEE; 6/1993
121
[201]
[202]
[203]
[204]
[205]
[206]
[207]
[208]
[209]
[210]
[211]
[212]
[213]
[214]
[215]
[216]
[217]
[218]
[219]
[220]
[221]
[222]
[223]
[224]
[225]
[226]
[227]
[228]
[229]
[230]
[231]
[232]
[233]
[234]
[235]
[236]
[237]
[238]
[239]
[240]
[241]
[242]
[243]
[244]
JJ Komiak, LW Yang, RS Brozovich, ST Fu, DP Smith; IEEE; 6/1993
R Yarborough, P Saunier, HQ Tserng, K Salzman, B Smith, D Heston; IEEE; 6/1993
CH Chen, HC Yen, K Tan, L Callejo, G Onak, DC Streit, PH Liu, JM Schellenberg ; IEEE ; 6/1993
DT Bryant, K Salzman, R Hudgens ; IEEE; 6/1993
M Muraguchi, M Nakatsugawa, M Aikawa ; IEEE ; 6/1993
C Duvanaud, P Bouysse, JM Nebus, L Lapierre, JP Villotte ; IEEE ; 6/1993
S Toyoda ; IEEE ; 6/1993
H Wang, C Pinatel, M Tsouli, JO Plouchart, A Konczykowaska, M Riet, S Vuye, P Berdaguer ; IEEE ;
6/1993
HQ Tserng, P Saunier ; IEEE ; 6/1993
RN Simons, RQ Lee ; IEEE; 6/1993
M Mochizuki, Y Itoh, M Kohno, H Masuno, T Takagi; IEEE; 6/1993
M Matloubian, L Larson, A Brown, L Jelloian, L Nguyen, M Lui, T Lui, J Brown, M Thompson, W Lam,
A Kurdoghlian, R Rhodes, M Delaney, J Pence; IEEE; 6/1993
LE Larson, MM Matloubian, JJ Brown, AS Brown, R Rhodes, D Crampton, M Thompson ; IEEE; 7/1993
F Ali, M Salib, A Gupta; IEEE ; 7/1993
C Duvanaud, S Dietsche, G Pataut, J Obregon ; IEEE; 7/1993
M Salib, A Gupta, F Ali, D Dawson ; IEEE; 9/1993
FJ McGrath, P O'Sullivan, E Heaney, G Dawe, G St Onge, K Jackson, C Kermarrec, B Fahey ; IEEE
WESCON; 9/1993
CK Pao, WS Wong, WD Gray, C Liu, DC Wang, CP Wen ; IEEE EPEP; 10/1993
T Arell, TK Hongsmatip ; IEEE; 10/1993
B Hughes, J Orr, G Martin; IEEE GaAs IC; 10/1993
F Ali, M Salib, A Gupta, D Dawson ; IEEE GaAs IC; 10/1993
MD Biedenbender, JL Lee, KL Tan, PH Liu, A Freudenthal, DC Streit, G Luong, R Lai, MV Aust, B
Allen, TS Liu, HC Yen; IEEE GaAs IC; 10/1993
H Sato, M Miyauchi, K Sakuno, M Akagi, M Hasegawa, JK Twynam, K Yamamura, T Tomita; IEEE
GaAs IC; 10/1993
M Funabashi, K Hosoya, K Ohata, K Onda, N Iwata, M Kuzuhara; IEEE GaAs IC; 10/1993
A Kurdoghlian, W Lam, C Chou, L Jellian, A Igawa, M Matloubian, L Larson, A Brown, M Thompson, C
Ngo ; IEEE GaAs IC; 10/1993
D Deakin, WJ Ho, EA Sovero, J Higgins; IEEE GaAs IC; 10/1993
ST Fu, JJ Komiak, LF Lester, KHG Duh, PM Smith, PC Chao, TH Yu ; IEEE GaAs IC; 10/1993
JC Huang, W Boulais, A Platzker, T Kazior, L Aucoin, S Shanfield, A Bertrand, M Vafides, M
Niedzwiecki ; IEEE GaAs IC; 10/1993
P O'Sullivan, G St Onge, E Heaney, F McGrath, C Kermarree ; IEEE GaAs IC; 10/1993
W Lam, M Matloubian, A Kurdoghlian, L Larson, A Igawa, C Chou, L Jelloian, A Brown, M Thompson, C
Ngo; IEEE; 10/1993
S D'Agostino, C Paoloni ; IEEE; 10/1993
M Hanczor, M Kumar ; IEEE Trans MTT; 12/1993
TC Ho, SW Chen, K Pande, PD Rice; IEEE Trans MTT; 12/1993
T Yoshimasu, N Tanba, S Hara; IEEE; 3/1994
Y Ota, C Adachi, H Takehara, M Yanagihara, H Fujimoto, H Masato, K Inoue ; IEEE Elec Letters; 4/1994
JA Lester, P Huang, M Ahmadi, M Dufault, D Ingram, TH Chen, D Garske, PD Chow ; IEEE MTT-S;
6/1994
M Schlechtweg, W Reinert, A Bangert, J Braunstein, PJ Tasker, R Bosch, WH Haydl, W Bronner, A
Huelsmann, K Koehler, J Seibel, R Yu, M Rodwell ; IEEE MTT-S; 6/1994
SW Duncan, A Eskandarian, D Gill, B Golja, B Power, DW Tu, S Svensson, S Weinreb, M Zimmerman, N
Byer ; IEEE MTT-S; 6/1994
M Faulkner, P Chye, R Hansen ; IEEE MTT-S; 6/1994
H Okazaki, K Horikawa, M Tanaka ; IEEE MTT-S; 6/1994
K Tateoka, A Sugimura, H Furukawa, M Yuri, N Yoshikawa, K Kanazawa ; IEEE MTT-S; 6/1994
L Marosi, D Yamauchi, J Goel, G Onak, DI Stones, A Sharma, K Tan, B Brunner, J Mancini ; IEEE MTTS; 6/1994
M Rofougaran, A Rofougaran, C Olgaard, AA Abidi ; IEEE VLSI; 6/1994
FM Ghannouchi, GX Zhao, F Beauregard ; IEEE ; 6/1994
122
[245]
[246]
[247]
[248]
[249]
[250]
[251]
[252]
[253]
[254]
[255]
[256]
[257]
[258]
[259]
[260]
[261]
[262]
[263]
[264]
[265]
[266]
[267]
[268]
[269]
[270]
[271]
[272]
[273]
[274]
[275]
[276]
[277]
[278]
[279]
[280]
[281]
[282]
[283]
[284]
[285]
[286]
[287]
[288]
[289]
[290]
[291]
[292]
[293]
[294]
P Berini, M Desgagne, FM Ghannouchi, RG Bosisio ; IEEE ; 6/1994
RM Wohlert, G Jackson, MG Adlerstein ; IEEE ; 6/1994
M Campovecchio, B Le Bras, M Lajugie, J Obregon ; IEEE ; 6/1994
A Khatibzadeh, W Liu, T Henderson, J Sweder, S Pierce ; IEEE ; 6/1994
F Ali, A Gupta, M Salib, B Veasel, D Dawson ; IEEE ; 6/1994
AK Sharma, cG Onak, R Lai, KL Tan ; IEEE ; 6/1994
K Sakuno, M Akagi, H Sato, M Miyauchi, M Hasegawa, T Yoshimasu, S Hara ; IEEE; 6/1994
T Yoshimasu, N Tanba, S Hara ; IEEE ; 6/1994
T Kunihisa, T Yokoyama, H Fujimoto, K Ishida, H Takehara, O Ishikawa ; IEEE; 6/1994
S Makioka, K Tateoka, M Yuri, N Yoshikawa, K Kanazawa; IEEE; 6/1994
M Ida, H Suzaki, T Tamanaka, T Nishikawa ; IEEE ; 6/1994
AK Sharma, G Onak, D Yamauchi, DI Stones, J Goel, R Lai, KL Tan ; IEEE ; 6/1994
PM Smith, CT Creamer, WF Kopp, DW Ferguson, P Ho, JR Willhite ; IEEE ; 6/1994
TH Chen, PD Chow, KL Tan, JA Lester, G Zell, M Huang ; IEEE ; 6/1994
B Kraemer, R Basset, C Baughman, P Chye, D Day, J Wei; IEEE; 6/1994
K Ishii, T Okamoto, H Ishida, N Tanibe, Y Dooi, H Maeda, M Shigaki, T Katoh ; IEEE ; 6/1994
S Toyoda ; IEEE ; 6/1994
J Shu, J Wei, R Basset, Y Chung, C Hua, C Meng, P Chye, J Hall, D Day; IEEE; 6/1994
JS Cardinal, FM Ghannouchi ; IEEE ; 6/1994
M Nagaoka, T Inoue, K Kawakyu, S Obayashi, H Kayano, E Takagi, Y Tanabe, M Yoshimura, K Ishida, Y
Kitaura, N Uchitomi ; IEEE ; 6/1994
W Boulais, RS Donahue, A Platzker, J Huang, L Aucoin, S Shanfield, M Vafidaes ; IEEE ; 6/1994
S Bouthillette, A Platzker, L Aucoin ; IEEE ; 6/1994
B Kraemer, R Basset, P Chye, D Day, J Wei; IEEE; 6/1994
P Chinoy, N Jain, P Li, J Goodrich, C Souchuns ; IEEE ; 6/1994
A Werthof, T Grave, W Kellner ; IEEE MTT-S; 6/1994
SC Wang, MY Kao, SMJ Liu, P Ho, KG Duh ; IEEE DRC; 6/1994
JO Plouchart, H Wang, C Pinatel, M Riet, P Berdaguer, C Doubon-Chevallier ; IEEE MTT-S; 6/1994
TH Wang, CC Liang, JS Hsu, CS Wu ; IEEE EDMS; 7/1994
W Lam, M Matloubian, A Igawa, C Chou, A Kurdoghlian, C Ngo, L Jelloian, A Brown, M Thompson, L
Larson; IEEE; 7/1994
W Liu, A Khatibzadeh, T Kim, J Sweder ; IEEE; 9/1994
RE Kasody, GS Dow, AK Sharma, MV Aust, D Yamauchi, R Lai, M Biedenbender, KL Tan, BR Allen;
IEEE; 9/1994
M Maeda, M Nishijima, H Takehara, C Adachi, H Fujimoto, 0 Ishikawa ; IEEE J SS Circ; 10/1994
NL Wang, WJ Ho, JA Higgins ; IEEE; 10/1994
CE Weitzel, JW Palmour, CH Carter, KJ Nordquist; IEEE EDL; 10/1994
JJ Komiak ; IEEE Workshop Nonlin MW; 10/1994
M Campovecchio, R Hilal, B Le Bras, M Lajugie, J Obregon ; IEEE Workshop Nonlin MW; 10/1994
C Duvanaud, P Bouysse, S Dietsche, JM Nebus, JM Paillot, D Roques ; IEEE Workshop Nonlin MW;
10/1994
C Pinatel, S Vuye, C Dubon-Chevalier, H Wang ; IEEE Workshop Nonlin MW; 10/1994
CE Weitzel, JW Palmour, CH Carter, KJ Nordquist ; IEEE EDL; 10/1994
T Sowlati, CAT Salama, J Sitch, G Rabjohn, D Smith; IEEE GaAs IC; 10/1994
J Naber, J Griffiths, J Salvey ; IEEE GaAs IC; 10/1994
T Quach, J Staudinger ; IEEE GaAs IC; 10/1994
JJ Komiak, LW Yang ; IEEE GaAs IC; 10/1994
H Wang, GS Dow, M Aust, KW Chang, R Lai, M Biedenbender, DC Streit, BR Allen; IEEE GaAs IC;
10/1994
LW Yang, JJ Komiak, MY Kao, DE Houston, DP Smith, KJ Norheden; IEEE IEDM; 12/1994
AK Sharma, GP Onak, R Lai, KL Tan ; IEEE; 12/1994
F Ali, A Gupta, M Salib, BW Veasel, DE Dawson ; IEEE Trans MTT; 12/1994
K Matsunaga, Y Okamoto, M Kuzuhara; IEEE IEDM; 12/1994
Y Tateno, H Yamada, S Ohara, S Kato, H ohnishi, T Fujii, J Fukaya ; IEEE IEDM; 12/1994
T Yokoyama, T Kunihisa, H Fujimoto, H Takehara, K Ishida, H Ikeda, O Ishikawa; IEEE Trans MTT;
12/1994
123
[295]
[296]
[297]
[298]
[299]
[300]
[301]
[302]
[303]
[304]
[305]
[306]
[307]
[308]
[309]
[310]
[311]
[312]
[313]
[314]
[315]
[316]
[317]
[318]
[319]
[320]
[321]
[322]
[323]
[324]
[325]
[326]
[327]
[328]
[329]
[330]
[331]
[332]
[333]
[334]
[335]
[336]
[337]
[338]
[339]
[340]
M Aust, H Wang, M Biedenbender, R Lai, DC Streit, PH Liu, GS Dow, BR Allen ; IEEE MWGW Letters;
1/1995
JCL Chi, JA Lester, Y Hwang, PD Chow, MY Huang ; IEEE MWGW Letters; 1/1995
S Tanaka, E Hase, A Nakajima, K Sugano, T Fujioka, Y Imakado, K Fujiwara, T Okamoto, Y Shigeno, K
Sato, I Arai, M Yamane, C Kusano, K Sakamoto, J Nakagawa, M Koya; IEEE ISSCC; 1/1995
CS Wu, CK pao, W Yau, H Kanber, M Hu, SX Bar, A Kurdoghlian, Z Bardai, D Bosch, C Seashore, M
Gawronski ; IEEE Trans MTT; 1/1995
FM Ghannouchi, F Beauregard, GX Zhao ; IEEE IMTC; 4/1995
DC Miller, RA Sadler, AH Peake ; IEEE MTT-S; 6/1995
H Wang, Y Hwang, TH Chen, M Biedenbender, DC Streit, DCW Lo, GS Dow, BR Allen ; IEEE MTT-S;
6/1995
J Hubert, J Schoenberg, ZB popovic ; IEEE MTT-S; 6/1995
L Marosi, M Sholley, J Goel, A Faris, M Siddiqui, DI Stones, K Tan ; IEEE MTT-S; 6/1995
M Kumar, M Hanczor, H Voigt, G Cambigianis, R Sachs, C Bonilla; IEEE MTT-S; 6/1995
M Knox, R Youmans, M Kumar, L Forker, H Voigt, P Brand; IEEE MTT-S; 6/1995
Y Kalayci, R Tempel, W Luetke, M Akpinar, I Wolff; IEEE MTT-S; 6/1995
S Weinreb, E Fischer, B Kane, N Byer, M Zimmerman ; IEEE MMWMCS; 6/1995
BT Agar, DS Bowser, KV Buer, DW Corman, CD Grondahl ; IEEE MMWMCS; 6/1995
JD Huang, D Zhang ; IEEE MTT-S; 6/1995
JM Dieudonne, B Adelseck, P Narozny, H Daembkes ; IEEE MTT-S; 6/1995
SW Chen, PM Smith, SMJ Liu, WF Kopp, TJ Rogers ; IEEE MWGW Letters; 6/1995
J Schoenberg, T Mader, B Shaw, ZB Popovic ; IEEE MTT-S; 6/1995
G Jackson, D Teeter, D Bradford, M Cobb ; IEEE MTT-S; 6/1995
A Platzker, S Bouthillette ; IEEE MTT-S; 6/1995
K Matsunaga, Y Okamoto, M Kuzuhara ; IEEE MTT-S; 6/1995
G Ferrell, L Dickens, J Gipprich, B Hayes, F Sacks ; IEEE MTT-S; 6/1995
F Ali, A Gupta, M Salib, B Veasel ; IEEE MTT-S; 6/1995
S Toyada ; IEEE MTT-S; 6/1995
M Maeda, H Takehara, M Nakamura, Y Ota, 0 Ishikawa ; IEEE MTT-S; 6/1995
SJ Maeng, CS Lee, KH Youn, JL Lee, HM Park ; IEEE MTT-S; 6/1995
H Masato, M Maeda, H Fujimoto, S Morimoto, M Nakamura, Y Yoshikawa, H Ikeda, H Kosugi, Y Ota;
IEEE MTT-S; 6/1995
J Griffiths, V Sadhir ; IEEE MTT-S; 6/1995
M Muraguchi, M Nakatsugawa, H Hayashi, M Aikawa ; IEEE MTT-S; 6/1995
JJ Komiak, LW Yang ; IEEE MTT-S; 6/1995
S Sriram, R Barron, AW Morse, TJ Smith, G Augustine, AA Burk, RC Clarke, RC Glass, HM Hobgood,
PA Orphanos, RR Siergiej, CD Brandt, MC Driver, RH Hopkins ; IEEE DRC; 6/1995
N Yoshikawa, K Tateoka, K Miyatsuji, S Makioka, K Kanazawa; IEEE ISSCC; 6/1995
RG Freitag, HG Henry, EK Lee, M Pingor, HL Salvo ; IEEE Trans MTT; 7/1995
JS Cardinal, FM Ghannouchi ; IEEE Trans MTT; 7/1995
PM Smith, SMJ Liu, MY Kao, P Ho, SC Wang, KHG Duh, ST Fu, PC Chao ; IEEE MWWC Letters;
7/1995
RC Clarke, RR Siergiej, AK Agarwal, CD Brandt, AA Burk, A Morse, PA Orphanos ; IEEE HSSDC;
7/1995
D Lovelace, D Ngo, J Costa, N Camilleri ; IEEE PIMRC; 9/1995
T Mader, M Markovic, ZB Popovic ; IEEE PIMRC; 9/1995
T Sowlati, CAT Salama, J Sitch, G Rabjohn, D Smith ; IEEE J SS Circuits; 10/1995
H Wang, R Lai, M Biedenbender, GS Dow, BR Allen ; IEEE J SS Circuits; 10/1995
Y Itoh ; IEEE ISSSE; 10/1995
K Ohata, T Saito; IEEE ISSSE; 10/1995
A Martin, A Mortazawi, BC De Loach ; IEEE MWGW Letters; 10/1995
Y Hasegawa, Y Ogata, I Nagasaki, K Inosaki, N Iwata, M Kanamori, T Itoh ; IEEE GaAs IC; 10/1995
P Narozny, H Tobler, GK Kornfeld, RA Nunn, B Adelseck, M Ludwig, G Eggers; IEEE GaAs IC;
10/1995
H Hayashi, M Nakatsugawa, M Muraguchi ; IEEE Trans MTT; 10/1995
124
[341]
K Kamozaki, S Tanaka, E Hase, A Nakajima, T Fujioka, K Sugano, Y Imakado, K Fujiwara, T Okamoto,
K Sato, Y Shigeno, I Arai, M Yamane, H Kundoh ; IEEE Conf on Universal Personal Communications;
[342]
[343]
[344]
N Kasai, M Noda, K Ito, K Yamamoto, K Maemura, Y Ohta, T Ishikawa, Y Yoshii, M Nakayama, H
Takano, O Ishihara; IEEE GaAs IC; 10/1995
P Walters, P Lau, K Buehring, J Penney, C Farley, P McDade, K Weller ; IEEE GaAs IC; 10/1995
R Lai, M Biedenbender, J Lee, K Tan, D Streit, PH Liu, M Hoppe, B Allen ; IEEE GaAs IC; 10/1995
[345]
PM White, TM O'Leary; IEEE GaAs IC; 10/1995
[346]
[347]
[348]
[349]
[350]
YC Chen, CS Wu, CK Pao, M Cole, Z Bardai, LD Hou, TA Midford, TC Cisco ; IEEE GaAs IC; 10/1995
JM Schellenberg ; IEEE GaAs IC; 10/1995
H Wang, M Sayed ; IEEE MWGW Letters; 12/1995
I Ohbu, T Tanimoto, S Tanaka, H Matsumoto, A Terano, M Kudo, T Nakamura ; IEEE IEDM; 12/1995
RR Siergiej, RC Clarke, AK Agarwal, CD Brandt, AA Burk, A Morse, PA Orphanos ; IEEE IEDM;
12/1995
S Ohara, H Yamada, T Iwai, Y Yamaguchi, K Imanishi, K Joshin ; IEEE IEDM; 12/1995
K Riepe, H Leier, U Seiler, A Marten, H Sledzik ; IEEE IEDM; 12/1995
N Constantin, FM Ghannouchi ; IEEE Trans MTT; 12/1995
M Maeda, H Masato, H Takehara, M Nakamura, S Morimoto, H Fujimoto, Y Ota, O Ishikawa ; IEEE
Trans MTT; 12/1995
U Erben, M Wahl, A Schueppen, H Schumacher ; IEEE MWGW Letters; 12/1995
Y Itoh, M mochizuki, M Kohno, H Masuno, T Tagaki, Y Mitsui ; IEEE MWGW Letters; 12/1995
SK Wang, CD Chang, M Siracusa, LCT Liu, RG Pauley, P Asher, M Sokolich ; IEEE Trans MTT; 12/1995
A Gupta, F Ali, D Dawson, P Smith ; IEEE MWGW Letters; 1/1996
MJ McCullagh, NB Roberts ; IEEE SSPAG; 1/1996
K Riepe, H Leier, U Seiler, A Marten, H Sledzik ; IEEE MWGW Letters; 1/1996
F Deshours, E Bergeault, G Berghoff, C Pinatel, C Dubon-Chevallier ; IEEE MWGW Letters; 1/1996
K Yamamoto, K Maemura, Y Ohta, N Kasai, M Noda, H Yuura, Y Yoshii, M Nakayama, N Ogata, T
Takagi, M Otsubo; IEEE ISSCC; 1/1996
JJ Brown, JA Pusl, M Hu, AE Schmitz, DP Docter, JB Shealy, MG Case, MA Thompson, LD Nguyen;
IEEE MWGW Letters; 1/1996
PC Abernathy, JR Dobrazanski, MC Smith, MS Griswold, MG Brunsed, JR Sherman ; IEEE Southeastcon;
4/1996
S Makioka, N Yoshikawa, K Kanazawa; IEEE Trans MTT; 4/1996
KM Simon, RM Wohlert, JP Wendler, LM Aucoin, DW Vye ; IEEE MMWMCS; 6/1996
M Nakayama, K Mori, N Ogata, Y Mitsui, H Yuura, Y Yoshii, K Yamamoto, K Maemura, O Ishida ; IEEE
MTT-S; 6/1996
W Titus, M Shifrin, V Aparin, B Bedard; IEEE MMWMCS; 6/1996
JA Lester, Y Hwang, J Chi, R Lai, M Biedenbender, PD Chow ; IEEE MMWMCS; 6/1996
J Goel, G Onak, DI Stones, D Yamauchi, A Sharma, K Tan, J Mancini ; IEEE MTT-S; 6/1996
S Bouthillette, A Platzker ; IEEE MTT-S; 6/1996
S Makioka, S enomoto, H Furukawa, K Tateoka, N Yoshikawa, K Kanazawa; IEEE MTT-S; 6/1996
V Jair, S Tehrani, D Halchin, E Glass, E Fisk, M Majerus ; IEEE MTT-S; 6/1996
R Yarborough, P Saunier, HQ Tserng ; IEEE MTT-S; 6/1996
WL Pribble, EL Griffin ; IEEE MTT-S; 6/1996
M Cardullo, C Page, D Teeter, A Platzker ; IEEE MTT-S; 6/1996
Y Hwang, PI) Chow, J Lester, J Chi, D Garske, M Biedenbender, R Lai ; IEEE MTT-S; 6/1996
B Nelson, S Cripps, J Stevenson Kenney, AF Podell ; IEEE MTT-S; 6/1996
J Sweder, G .Austin Truitt, SR Nelson, JS Mason ; IEEE MTT-S; 6/1996
H Ono, Y Umemoto, M Mori, M Miyazaki, A Terano, M Kudo ; IEEE MTT-S; 6/1996
H Yamada, S Ohara, T Iwai, Y yamaguchi, K Imanishi, K Joshin ; IEEE MTT-S; 6/1996
S Toyoda ; IEEE MTT-S; 6/1996
JA Pusl, JJ Brown, JB Shealy, M Hu, AE Schmitz, DP Docter, MG Case, MA Thompson, LD Nguyen;
IEEE MTT-S; 6/1996
K Matsunaga, Y Okamoto, I Miura, M Kuzuhara ; IEEE MTT-S; 6/1996
MK Siddiqui, AK Sharma, LG Callejo, CH Chen, K Tan, HC Yen ; IEEE MTT-S; 6/1996
DW Wu ; IEEE MTT-S; 6/1996
10/1995
[351]
[352]
[353]
[354]
[355]
[356]
[357]
[358]
[359]
[360]
[361]
[362]
[363]
[364]
[365]
[366]
[367]
[368]
[369]
[370]
[371]
[372]
[373]
[374]
[375]
[376]
[377]
[378]
[379]
[380]
[381]
[382]
[383]
[384]
[385]
[386]
125
[387]
[388]
[389]
[390]
[391]
[392]
[393]
[394]
[395]
[396]
[397]
[398]
[399]
[400]
[401]
[402]
[403]
[404]
[405]
[406]
[407]
[408]
[409]
[410]
[411]
[412]
[413]
[414]
[415]
[416]
[417]
[418]
[419]
[420]
[421]
[422]
[423]
[424]
[425]
S Tanaka, S Murakami, Y Amamiya, H Shimawaki, N Furuhata, N Goto, K Honjo, Y Ishida, Y Saito, K
Yamamoto, M Yajima, R Temino, Y Hisada ; IEEE MTT-S; 6/1996
A Mallet, T Peyretaillade, R Sommet, D Floriot, S Delage, JM Nebus, J Obregon ; IEEE MTT-S; 6/1996
B Ingruber, W Pritzl, G Magerl ; IEEE MTT-S; 6/1996
T Sowlati, Y Greshishchev, C Andre, T Salama ; IEEE Elec Letters; 9/1996
TM Roh, Y Suh, B Kim, W Park, JB Lee, YS Kim, GY Lee ; IEEE Elec Letters; 9/1996
JB Vincent, DG van der Merwe ; IEEE AFRICON; 9/1996
R Lai, GI Ng, DCW Lo, T Block, H Wang, M Biedenbender, D Streit, PH Liu, RM Dia, EW Lin, HC Yen;
IEEE MWGW Letters; 10/1996
L Sjogren, J Choe, D Garske, R Duprey, K Kono, L Ma, D Tamura, C Gandhi, E Boyd, PD Chow, L Rowe
; IEEE ISPAST; 10/1996
R Wang, M Cole, LD Hou, P Chu, CD Chang, TA Midford, T Cisco ; IEEE GaAs IC; 10/1996
R Lai, M Nishimoto, Y Hwang, M Biedenbender, B Kasody, C Geiger, YC Chen, G Zell; IEEE GaAs IC;
10/1996
RJ Trew, MW Shin, V Gatto ; IEEE GaAs IC; 10/1996
S Murakami, S Tanaka, Y Amamiya, H Shimawaki, N Goto, K Honjo, Y Ishida, Y Saitoh, M Yajima, Y
Hisada; IEEE GaAs IC; 10/1996
OSA Tang, KHG Duh, SMJ Liu, PM Smith, WF Kopp, TJ Rogers, DJ Pritchard ; IEEE GaAs IC; 10/1996
M Hirose, K Nishihori, M Nagaoka, Y Ikeda, A Kameyama, Y Kitaura, N Uchitomi ; IEEE GaAs IC;
10/1996
MJ Martinez, E Schirmann, M Durlam, D Halchin, R Burton, JH Huang, S Tehrani, A Reyes, D Green, N
Cody ; IEEE GaAs IC; 10/1996
MF O'Keefe, GN Henderson, TE Boles, P Noonan, JM Sledziewski, B Brown ; IEEE EDMO; 10/1996
M Yajima, Y Hisada, Y Ishida, Y Saito, K Yamamoto, S Murakami, S Tanaka, N Goto, K Honjo ; IEEE
EDMO; 10/1996
K Yamamoto, K Maemura, N Kasai, Y Yoshii, Miyazaki, M Nakayama, N Ogata, T Takagi, M Otsubo;
IEEE J SS Circ; 12/1996
A Wood, C Dragon, W Burger ; IEEE IEDM; 12/1996
AK Agarwal, G Augustine, V Balakrishna, CD Brandt, AA Burk, LS Chen, RC Clarke, PM Esker, HM
Hobgood, RH Hopkins, AW Morse, LB Rowland, S Seshadri, RR Siergiej, TJ Smith, S Sriram; IEEE
IEDM; 12/1996
L Andrieux, A Cazarre, JP Bailbe, A Marty ; IEEE Proc CDS; 12/1996
H Yamada, S Ohara, T Iwai, Y Yamaguchi, K Imanishi, K Joshin ; IEEE Trans MTT; 12/1996
E Schirmann, R Baeten, J Costa, DL Green, D Halchin, MJ Martinez, A Reyes ; IEEE MTTWAD; 1/1997
S Yamamoto, T Yokoyama, T Kunihisa, M Nishijima, M Nishitsuji, K Nishii, O Ishikawa; IEEE
MTTWAD; 1/1997
BJ Bulk, MW Green, AW Dearn, AP Long, SP Melvin, LM Devlin, JC Clifton ; IEEE RFMCCWA;
1/1997
D Hill, R Yarborough, T Kim, HF Chau ; IEEE MWGW Letters; 1/1997
V Radisic, ST Chew, Y Qian, T Itoh ; IEEE MWGW Letters; 1/1997
HP Trost, W Simbuerger, DH Wohlmuth, H Knapp, P Weger, AL Scholz ; IEEE RF and MW Circ for
Comm WL Appl; 1/1997
T Tanaka, H Furukawa, H Takenaka, T Ueda, T Fukui, D Ueda ; IEEE Trans MTT; 3/1997
CW Kim, N Hayama, N Goto, K Honjo ; IEEE EDL; 4/1997
T Sowlati, YM Greshishchev, CAT Salama ; IEEE J of Solid State Circ; 4/1997
YC Chen, R Lai, E Lin, H Wang, T Block, HC Yen, D Streit, W Jones, PH Liu, RM Dia, TW Huang, PP
Huang, K Stamper ; IEEE MWGW Letters; 4/1997
YC Chen, R Lai, H Wang, HC Yen, D Streit, RM Dia, W Jones, T Block, PH Liu, TW Huang, YC Chou, K
Stamper ; IEEE IPRM; 4/1997
WL Chen, TS Kim, HF Chau, T Henderson ; IEEE IPRM; 4/1997
D Su, W McFarland ; IEEE Custom IC; 4/1997
Y Hwang, J lester, G Schreyer, G Zell, S Schrier, D Yamauchi, G Onak, B Kasody, R Kono, YC CHen, R
Lai ; IEEE MTT-S; 6/1997
MR HeDann, M Jones, G Wilcox, J McLeod, SC Miller ; IEEE MTT-S; 6/1997
AR Barnes, MT Moore, MB Allenson ; IEEE MTT-S; 6/1997
MD Pollman, C Trantanella, M Shifrin, V Aparin, D Upton; IEEE MTT-S; 6/1997
126
[426]
[427]
[428]
[429]
[430]
[431]
[432]
[433]
[434]
[435]
[436]
[437]
[438]
[439]
[440]
[441]
[442]
[443]
[444]
[445]
[446]
[447]
[448]
[449]
[450]
[451]
[452]
[453]
[454]
[455]
[456]
[457]
[458]
[459]
[460]
[461]
[462]
[463]
[464]
[465]
[466]
JA Lester, J Chi, R Lai, M Biedenbender, D Garske, R Rordan, PD Chow ; IEEE MTT-S; 6/1997
H Kayano, S Obayashi, T Maeda, Y Suzuki; IEEE MTT-S; 6/1997
YC Wang, JM Kuo, JR Lothian, F Ren, HS Tsai, JS Weiner, J Lin, A Tate, WE Mayo, YK Chen ; IEEE
DRC; 6/1997
H Izadpanah, RC Malkemes, DD Chukurov, RR Cordell ; IEEE Trans CircSys; 6/1997
P Huang, E Lin, R Lai, M Biedenbender, TW Huang, H Wang, C Geiger, T Block, PH Liu ; IEEE MTT-S;
6/1997
DL Ingram, DI Stones, TW Huang, M Nishimoto, H Wang, M Siddiqui, D Tamura, J Elliott, R Lai, M
Biedenbender, HC Yen, B Allen; IEEE MTT-S; 6/1997
GN Henderson, MF O'Keefe, TE Boles, P Noonan, JM Sledziewski, BM Brown ; IEEE MTT-S; 6/1997
M Kimishima, K Hayashi, M Takahashi; IEEE MTT-S; 6/1997
W Abey, T Kawai, I Okamoto, M Suzuki, C Khandavalli, W Kennan, Y Tateno, M Nagahara, M Takikawa
;IEEE MTT-S; 6/1997
DW Wu, R Parkhurst, SL Fu, J Wei, CY Su, SS Chang, D Moy, W Fields, P Chye, R Levitsky ; IEEE
MTT-S; 6/1997
M Nagaoka, H Wakimoto, K Kawakyu, K Nishihori, Y Kitaura, T Sasaki, A Kameyama, N Uchitomi;
IEEE MTT-S; 6/1997
E Glass, JH Huang, J Abrokwah, B Bernhardt, M Majerus, E Spears, R Droopad, B Ooms ; IEEE MTT-S;
6/1997
K Yamaguchi, TB Nishimura, N Iwata, T Takemura, M Kuzuhara, Y Miyasaka ; IEEE MTT-S; 6/1997
J Morikawa, K Asano, K Ishikura, H Oikawa, M Kanamori, M Kuzuhara ; IEEE MTT-S; 6/1997
I Takenaka, H Takahashi, K Asano, J Morikawa, K Ishikura, M Kanamori, M Kuzuhara, H Tsutsui ; IEEE
MTT-S; 6/1997
JJ Komiak, SC Wang, TJ Rogers ; IEEE MTT-S; 6/1997
S Toyoda ; IEEE MTT-S; 6/1997
V Radisic, Y Qian, T Itoh ; IEEE MTT-S; 6/1997
KI Jeon, YS Kwon, SC Hong ; IEEE MTT-S; 6/1997
P Cameron, W Pan, C hanz, R Nicklaus, P Chu, D Wong, T Cisco; IEEE MTT-S; 6/1997
JP Viaud, M Lajugie, R Quere, J Obregon ; IEEE MTT-S; 6/1997
RJ Trew ; IEEE MTT-S; 6/1997
S Sriram, TJ Smith, LB Rowland, AA Burk, G Augustine, V Balakrishna, HM Hobgood, CD Brandt;
IEEE DRC; 6/1997
S Tanaka, Y Amamiya, S Murakami, H Shimawaki, N Goto, Y Takayama, K Honjo; IEEE MMWaves;
7/1997
T Inoue, K Hosoya, K Ohata ; IEEE MMWaves; 7/1997
B Bayraktaroglu, M Salib ; IEEE MWGW Letters; 7/1997
Y Tkachenko, D Bartle, P DiCarlo, D Mitchell, D Petzold ; IEEE WCC; 7/1997
YL Lai, EY Chang, CY Chang, TH Liu, SP Wang, HT Hsu ; IEEE MWGW Letters; 7/1997
FM Rotella, Z Yu, R Dutton, B Troyanovsky, G Ma ; IEEE SISPAD; 9/1997
YL Lai, EY Chang, CY Chang, MC Tai, TH Liu, SP Wang, KC Chuang, CT Lee ; IEEE EDL; 9/1997
HF Chau, G Wilcox, W Chen, M Tutt, T Henderson ; IEEE MWGW Letters; 9/1997
OSA Tang, KHG Duh, SMJ Liu, PM Smith, WF Kopp, TJ Rogers, DJ Pritchard ; IEEE J SS Circ; 9/1997
JE Mueller, T Grave, HJ Siweris, M Kaerner, A Schaefer, H Tischer, H Riechert, L Schleicher, L
Verweyen, A Bangert, W Kellner, T Meier; IEEE J SS Circ; 9/1997
Ph Eudeline, P Perez, JP Lemette ; IEEE Radar; 10/1997
YA Tkachenko, CJ Wei, D Bartle ; IEEE GaAs Reliab Wksp; 10/1997
RS Virk, MY Chen, C Nguyen, T Liu, M Matloubian, DB Rensch ; IEEE MWGW Letters; 10/1997
M Nagoka, H Wakimoto, T Seshita, K Kawakyu, Y Kitaura, A Kameyama, N Uchitomi ; IEEE GaAs IC;
10/1997
JE Mueller, P Baureis, O Berger, T Boettner, N Bovoloon, G Packeiser, P Zwicknagl ; IEEE GaAs IC;
10/1997
K Kamozaki, N Kurita, W Hioe, T Tanimoto, H Ohta, T Nakamura, H Kondoh ; IEEE GaAs IC; 10/1997
T Yoshimasu, M Akagi, N Tanba, S Hara ; IEEE GaAs IC; 10/1997
DR Greenberg, M Rivier, P Girard, E Bergeault, J Moniz, D Ahlgren, G Freeman, S Subbanna, SJ Jeng, K
Stein, D Nguyen-Ngoc, K Schonenberg, J Malinowski, D Colavito, DL Harame, B Meyerson ; IEEE
IEDM; 12/1997
127
Y Itoh, A Tsuchiko, M Kasahara, K Inami, J Udomoto, S Tsuji ; IEEE APMC; 12/1997
JW Lee, WY Kim, YS Kim, TM Rho, BM Kim ; IEEE Trans MTT; 12/1997
D Hill, TS Kim ; IEEE Trans MTT; 12/1997
PP Huang, TW Huang, H Wang, EW Lin, YH Shu, GS Dow, R Lai, M Biedenbender, JH Elliott ; IEEE
Trans MTT; 12/1997
[471] DL Ingram, DI Stones, JH Elliott, H Wang, R Lai, M Biedenbender ; IEEE Trans MTT; 12/1997
[472] I Yoshida ; IEEE IEDM; 12/1997
[473] Q Ren, Y Gao, I Wolff ; IEEE Asia Pacific MW Conf; 12/1997
[474] S Piotrowicz, C Gaquiere, B Bonte, E Bourcier, D Theron, X Wallart, Y Crosnier ; IEEE MWGW Letters;
1/1998
[475] V Radisic, Y Qian, T Itoh ; IEEE MWGW Letters; 1/1998
[476] S Tanaka, Y Amamiya, S Murakami, H Shimawaki, N Goto, Y Takayama, K Honjo ; IEEE TED; 1/1998
[477] J Portilla, H Garcia, E Artal ; IEEE J SS Circ; 1/1998
[478] K Yamamoto, T Moriwaki, Y Yoshii, T Fujii, J Otsuji, Y Sasaki, Y Miyazaki, K Nishitani ; IEEE ASPDAC; 1/1998
[479] I Yoshida, M Katsueda, M Morikawa, Y Matsunaga, T Fujioka, M Hotta, Y Nunogawa, K Kobayashi, S
Shimuzu, M Nagata ; IEEE ISSCC; 1/1998
[480] RC Clarke, CD Brandt, S Sriram, RR Siergiej, AW Morse, AK Agarwal, LS Chen, V Balakrishna, AA
Burk; IEEE DSC; 1/1998
[481] Q Chen, JW Yang, R Gaska, MA Khan, MS Shur, GJ Sullivan, AL Sailor, JA Higgins, AT Ping, I Adesida
; IEEE EDL; 1/1998
[482] K Yamaguchi, N Iwata, M Kuzuhara, T Takayame ; IEEE TED; 1/1998
[483] JG McRory, GG Rabjohn, RH Johnston ; IEEE J SS Circ; 1/1998
[484] A Rofougaran, G Chang, JJ Rael, JYC Chang, M Rofougaran, PJ Chang, M Djafari, MK Ku, EW Roth, AA
Abidi, H Samueli ; IEEE J SS Circ; 4/1998
[485] JN Burghartz, JO Plouchart, KA Jenkins, CS Webster, M Soyuer ; IEEE EDL; 4/1998
[486] W Wojtasiak, D Gryglewski, T Morawski, E Sedek; IEEE ICMR; 4/1998
[487] R Goetzfried, F Beisswanger, S Gerlach, A Schueppen, H Dietrich, U Seiler, KH Bach, J Albers ; IEEE
Trans MTT; 4/1998
[488] SS Taylor; IEEE MTT-S; 6/1998
[489] HN Ma, R Singh, KT Yan, SJ Fang, FJ Lin, KS Tan, J Shibata, A Tamura, H Nakamura ; IEEE MTT-S;
6/1998
[490] M Nakayama, K Horiguchi, K Yamamoto, Y Yoshii, S Sugiyama, N Suematsu, T Takagi ; IEEE MTT-S;
6/1998
[491] HJ Siweris, A Werthof, H Tischer, U Schaper, A Schaefer, L Verweyen, T Grave, G Bloeck, M
Schlechtweg, W Kellner ; IEEE MTT-S; 6/1998
[492] T Yokoyama, M Nishijima, T Kunihisa, S Yamamoto, 0 Ishikawa ; IEEE MTT-S; 6/1998
[493] M Komaru, H Hoshi, H Kurusu, Y Notani, T Katoh, T Ishida, T Oku, T Ishikawa, Y Mitsui ; IEEE MTT-S;
6/1998
[494] SHL Tu, C Toumazou ; IEEE ISCAS; 6/1998
[495] J Shu, T Hwang, D Nguyen, R Pumares, P Chye, P Khanna ; IEEE MTT-S; 6/1998
[496] A Wood, W brakensiek, C Dragon, W Burger ; IEEE MTT-S; 6/1998
[497] H Ashoka, J Ness, A Robinson, M Gourlay, J Logan, P Woodhead, D reuther ; IEEE MTT-S; 6/1998
[498] S Wong, S Luo, L Hadley ; IEEE ISSCC; 6/1998
[499] T Tanimoto, I Ohbu, S Tanaka, A Kawai, M Kudo, A Terano, T Nakamura ; IEEE TED; 6/1998
[500] T Iwai, S Ohara, H Yamada, Y Yamaguchi, K Imanishi, K Joshin ; IEEE TED; 6/1998
[501] T Budka, A Ketterson, HQ Tserng, L Stiborek, L Heinrich, R Smith, B Ables, C Kyhl, K Worthen, G
Brehm, J Reddick ; IEEE MWGW Letters; 6/1998
[502] AL Martin, A Mortazawi, BC DeLoach ; IEEE Trans MTT; 6/1998
[503] B Ingruber, W Pritzl, D Smely, M Wachutka, G Magerl ; IEEE Trans MTT; 6/1998
[504] T Seshita, K Kawakyu, H Wakimoto, M Nagaoka, Y Kitaura, N Uchitomi ; IEEE MTT-S; 6/1998
[505] H Asano, S Hara, S Komai ; IEEE MTT-S; 6/1998
[506] DL Ingram, L Sjogren, J Kraus, M Nishimoto, M Siddiqui, S Sing, K Cha, M Huang, R Lau ; IEEE MTTS; 6/1998
[507] DC Yang, JM Yang, H Wang, P Huang ; IEEE MTT-S; 6/1998
[508] D Smely, B Ingruber, M Wachutka, G Magerl ; IEEE MTT-S; 6/1998
[467]
[468]
[469]
[470]
128
[509]
[510]
[511]
[512]
[513]
[514]
[515]
[516]
[517]
[518]
[519]
[520]
[521]
[522]
[523]
[524]
[525]
[526]
[527]
[528]
[529]
[530]
[531]
[532]
[533]
[534]
[535]
[536]
[537]
[538]
[539]
[540]
[541]
[542]
[543]
[544]
[545]
[546]
[547]
[548]
[549]
[550]
[551]
[552]
[553]
V Radisic, Y Qian, T Itoh ; IEEE MTT-S; 6/1998
T Iwai, S Ohara, T Miyashita, K Joshin ; IEEE MTT-S; 6/1998
M Nishida, S Murai, H Uda, H Tominaga, T Sawai, A Ibaraki ; IEEE MTT-S; 6/1998
TB Nishimura, N Iwata, K Yamaguchi, K Takemura, Y Miyasaka ; IEEE MTT-S; 6/1998
MK Siddiqui, AK Sharma, LG Callejo, R Lai ; IEEE MTT-S; 6/1998
J Schnellenberg ; IEEE MTT-S; 6/1998
M Salib, A Gupta, A Ezis, M Lee, M Murphy ; IEEE MTT-S; 6/1998
JA Pusl, RF Widman, JJ Brown, M Hu, N Kaur, M BeZaire, LD Nguyen ; IEEE MTT-S; 6/1998
H Tsutsui, I Takenaka, H Takahashi, K Asano, J Morikawa, K Ishikura, M Kuzuhara ; IEEE MTT-S;
6/1998
K Nishihori, Y Kitaura, M Hirose, M Mihara, M Nagaoka, N Uchitomi ; IEEE TED; 7/1998
JL Lee, HC Kim, KY Mun, SJ Maeng ; IEEE EDL; 7/1998
P Perugupalli, M Trivedi, K Shenai, SK Leong ; IEEE TED; 7/1998
TA Boes, U Lott, W Baechtold ; IEEE RAWCON; 7/1998
A Wood, W Brakensiek ; IEEE RAWCON; 7/1998
J Staudinger, G Norris, R Sherman, G Sadowniczak ; IEEE RAWCON; 7/1998
E Jaervinen ; IEEE RAWCON; 7/1998
D Helms, M Testa, N Vladimirsky, D Wills ; IEEE RAWCON; 7/1998
YG Kim, SJ Maeng, JH Lee, CS Park ; IEEE RAWCON; 7/1998
IM Abolduyev, AM Zubkov, VM Minnebaev ; IEEE ICSC; 9/1998
R String, A Agarwal, T Smith, R Messham, S Mani, V Hegde, M Hanes, H Nathanson, P Potyraj, K
Petrosky, T Knight, P Brabant ; IEEE SMICRF; 9/1998
JE Mueller, P Baureis, O Berger, T Boettner, N Bovolon, R Schultheis, G Packeiser, P Zwicknagel ; IEEE J
SS Circ; 9/1998
T Yoshimasu, M Akagi, N Tanba, S Hara ; IEEE J SS Circ; 9/1998
R Goetzfried, F Beisswanger, S Gerlach ; IEEE J SS Circ; 9/1998
TB Mader, EW Bryerton, M Markovic, M Forman, Z Popovic ; IEEE Trans MTT; 10/1998
FJ Ortega-Gonzalez, JL Jimenez-Martin, A Asensio-Lopez, G Torregrosa-Penalva ; IEEE MWGW Letters;
10/1998
RJ Trew ; IEEE ISSEE; 10/1998
D Barataud, C Arnaud, B Thubaud, M Campovecchio, JM Nebus, JP Villotte ; IEEE Trans Inst Meas;
10/1998
M Yu, M Matloubian, P Petre, L Hamilton, R Bowen, M Lui, HC Sun, C Ngo, P Janke, D Baker, R
Robertson ; IEEE GaAs IC; 10/1998
JJ Komiak, W Kong, PC Chao, K Nichols; IEEE GaAs IC; 10/1998
S Goto, K Fujii, H Morishige, S Suzuki, S Sakamoto, N Yoshida, N Tanino, K Sato ; IEEE GaAs IC;
10/1998
I Takenaka, H Takahashi, K Asano, K Ishikura, J Morikawa, K Sato, I Takano, K Hasegawa, K Tokunaga,
F Emori, M Kuzuhara; IEEE GaAs IC; 10/1998
BY Majlis, A Ariffin, AFA Mat, S Jaafar, S Bujang, MR Yahya ; IEEE ICSE; 10/1998
K Choumei, K Yamamoto, N Kasai, T Moriwaki, Y Yoshii, T Fujii, J Otsuji, Y Miyazaki, N Tanino, K
Sato ; IEEE GaAs IC; 10/1998
B Ingruber, J Baumgartner, D Smely, M Wachutka, G Magerl, FA Petz ; IEEE Trans MTT; 10/1998
YC Chen, DL Ingram, R Lai, M Barsky, R Grunbacher, T Block, HC Yen, DC Streit; IEEE MWGW
Letters; 10/1998
WR Deal, V Radisic, YX Qian, T Itoh ; IEEE MWGW Letters; 10/1998
GH Yun, HK Park ; IEEE Antennas Propag; 12/1998
DK Su, WJ McFarland; IEEE J SS Circ; 12/1998
SL Wong, S Luo ; IEEE J SS Circ; 12/1998
P Parikh, J Ibbetson, U Mishra, D Docter, M Le, K Kiziloglu, D Grider, J Pusl, D Widman, L Kehias, T
Jenkins ; IEEE Trans MTT; 12/1998
MK Siddiqui, AK Sharma, LG Callejo, R Lai ; IEEE Trans MTT; 12/1998
G Berghoff, E Bergeaullt, B Huyart, L Jallet ; IEEE Trans MTT; 12/1998
SS Lu, YW Hsu, CC Meng, LP Chen; IEEE EDL; 1/1999
HS Tsai, P Roux, JL Giguet, YK Chen ; IEEE Tech for Wireless Appl; 1/1999
RG Freitag, KM Renaldo, HG Henry, JE Degenford ; IEEE Tech for Wireless Appl; 1/1999
129
[554]
[555]
[556]
[557]
[558]
[559]
[560]
[561]
[562]
[563]
[564]
[565]
[566]
[567]
[568]
[569]
[570]
[571]
[572]
[573]
[574]
[575]
[576]
[577]
[578]
[579]
[580]
[581]
[582]
[583]
[584]
[585]
[586]
[587]
[588]
[589]
[590]
[591]
[592]
[593]
[594]
[595]
D Streit, A Oki, R Lai, V Medvedev, K Kobayashi ; IEEE Tech for Wireless Appl; 1/1999
M Bopp, M Alles, M Arens, D Eichel, S Gerlach, R Goetzfried, F Gruson, M Kocks, G Krimmer, R
Reimann, B Ross, M Siegle, J Zieschang ; IEEE ISSCC; 1/1999
B Ballweber, R Gupta, DJ Allstot; IEEE ISSCC; 1/1999
W Simbuerger, HD Wohlmuth, P Weger; IEEE ISSCC; 1/1999
CF Campbell; IEEE MWGW Letters; 3/1999
LJ Zhang ; IEEE Radar Conf; 4/1999
K Yamamoto, T Moriwaki, T Fujii, J Otsuji, M Miyashita, Y Miyazaki, K Nishitani ; IEEE J SS Circ;
4/1999
ST Sheppard, K Doverspike, WL Pribble, ST Allen, JW Palmour, LT Kehias, TJ Jenkins ; IEEE EDL;
4/1999
YC Wang, M Hong, JM Kuo, JP Mannaerts, HS Tsai, J Kwo, JJ Krajewski, YK Chen, AY Cho ; IEEE Elec
Letters; 4/1999
YC Chen, P Chin, D Ingram, R Lai, R Grundbacher, M Barsky, T Block, M Wojtowicz, L Tran, V
Medvedev, HC Yen, DC Streit, A Brown ; IEEE IPRM; 4/1999
CH Chen, K Krishnamurthy, S Keller, G parish, M Rodwell, UK Mishra, YF Wu ; IEEE Elec Letters;
4/1999
S Morimoto, M Maeda, T Tokoyama, H Ishida, M Nakamura, Y Ota, D Ueda ; IEEE MTT-S; 6/1999
NS Cheng, TP Dao, MG Case, DB Rensch, RA York ; IEEE MTT-S; 6/1999
K Ishida, H Ikeda, H Kosugi, M Nishijima, T Uwano ; IEEE MTT-S; 6/1999
DW Baker, RS Robertson, RT Kihm, M Matloubian, M Yu, R Bowen ; IEEE MTT-S; 6/1999
JR Lamberg, MJ Gawronski, JJ Geddes, WR Carlyon, RA Hart, GS Dow, EW Holmes, MY Huang ; IEEE
MTT-S; 6/1999
J Lulja, H Mattila; IEEE MTT-S; 6/1999
K Nishikawa, K Kamogawa, I Toyoda, T Tokumitsu, M Tanaka; IEEE MTT-S; 6/1999
XW Wang, J Cao, B Liang, ES Khoo, H Nakamura, R Singh; IEEE MTT-S; 6/1999
YF Wu, BJ Thibeault, JJ Xu, RA York, S Keller, BP Keller, UK Mishra ; IEEE DRC; 6/1999
JJ Komiak, W Kong, PC Chao, K Nichols; IEEE MTT-S; 6/1999
MK Siddiqui, AK Sharma LG Callejo, R Lai ; IEEE MTT-S; 6/1999
A Ishimaru, M Maeda, T Yoshida, J Ozaki, S Kamihashi ; IEEE MTT-S; 6/1999
T Satoh, A Betti-Berutto, C Poledrelli, C Khandavalli, J Nikaido, S Kuroda, T Yokoyama, J Fukaya; IEEE
MTT-S; 6/1999
J Schellenberg, H Dy-Ky ; IEEE MTT-S; 6/1999
TB Nishimura, N Iwata, G Hau ; IEEE MTT-S; 6/1999
N Miyazawa, H Itoh, Y Nakasha, T Iwai, T Mitashita, S Ohara, K Joshin ; IEEE MTT-S; 6/1999
S Yoshida, Y Wakabayashi, M Kohno, K Uemura; IEEE MTT-S; 6/1999
MD Weiss, Z Popovic ; IEEE MTT-S; 6/1999
CY Hang, V Radisic, YX Qian, T Itoh ; IEEE MTT-S; 6/1999
K Krishnamurthy, SI Long, MJW Rodwell ; IEEE MTT-S; 6/1999
K Yamamoto, T Shimura, T Asada, T Okuda, K Mori, K Choumei, S Suzuki, T Miura, S Fujimoto, R
Hattori, H Nakano, K Hosogi, J Otsuji, A Inoue, K Yajima, T Ogata, Y Miyazaki, M Yamanouchi; IEEE
MTT-S; 6/1999
T Saso, Y Hasegawa, Y Saito, Y Kakuta; IEEE MTT-S; 6/1999
DL Ingram, YC Chen, J Kraus, B Brunner, B Allen, HC Yen, KF Lau; IEEE MTT-S; 6/1999
J Zhang, HY Jia, PH Tsien, TC Lo ; IEEE EDL; 7/1999
KC Tsai, PR Gray ; IEEE J SS Circ; 7/1999
JJ Xu, YF Wu, S Keller, G Parish, S Heikman, BJ Thubeault, UK Mishra, RA York ; IEEE MWGW
Letters; 7/1999
T Melly, AS Porret, CC Enz, M Kayal, E Vittoz ; IEEE LPED; 7/1999
J Staudinger, Gilsdorf, D Newman, G Norris, G Sadowniczak, R Sherman, T Quach, V Wang; IEEE
RAWCON; 7/1999
EA Sovero, YW Kwon, DS Deakin, J Hong; IEEE RAWCON; 7/1999
D Barataud, F Blache, A Mallet, PP Bouysse, JM Nebus, JP Villotte, J Obregon, J Verspecht, P Auxemery
; IEEE Trans Inst Meas; 7/1999
YF Wu, RA York, S Keller, BP Keller, UK Mishra ; IEEE MWGW Letters; 7/1999
130
[596]
[597]
[598]
[599]
[600]
[601]
[602]
[603]
[604]
[605]
[606]
[607]
[608]
[609]
[610]
[611]
[612]
[613]
[614]
[615]
[616]
[617]
[618]
[619]
[620]
[621]
[622]
[623]
[624]
[625]
[626]
[627]
[628]
[629]
[630]
[631]
[632]
[633]
[634]
[635]
[636]
YC Wang, JM Kuo, F Ren, JR Lothian, HS Tsai, JS Weiner, HC Kuo, CH Lin, YK Chen, WE Mayo;
IEEE Trans MTT; 7/1999
WR Deal, V Radisic, YX Qian, T Itoh ; IEEE Trans MTT; 7/1999
DA Brown, FM Edwards, PM Jupp, JD Birkbeck, DC Pennington, CR Green, HP Forstner ; IEEE WCNC;
9/1999
PD Tseng, LY Zhang, GB Gao, MF Chang; IEEE BCTM; 9/1999
KK Lee, D An, JK Rhee, HC Park, YS Toon ; IEEE TENCON; 9/1999
I Takenaka, K Ishikura, H Takahashi, K Asano, J Morikawa, K Satou, K Kishi, K Hasegawa, K Tokunaga,
F Emori, M Kuzuhara ; IEEE J SS Circ; 9/1999
M Yu, M Matloubian, P Petre, LR Hamilton, R Bowen, M Lui, HC Sun, CM Ngo, P Janke, DW Baker, RS
Robertson; IEEE J SS Circ; 9/1999
TJ Jenkins, L Kehias, P Parikh, J Ibbetson, U Mishra, D Docter, M Le, J Pusl, D Widman ; IEEE J SS Circ;
9/1999
JM Nam, JW Ho, CM Rea, LY Hyun ; IEEE TENCON; 9/1999
D Ngo, WM Huang, JM Ford, D Spooner ; IEEE SOI Conf; 10/1999
K Eisenbeiser, D Droopad, JH Huang ; IEEE EDL; 10/1999
CY Hang, WR Deal, YX Qian, T Itoh ; IEEE Elec Letters; 10/1999
JCM Hwang, LT Kehias, JA Cook, MC Calcatera, ST Sheppard ; IEEE GaAs IC; 10/1999
LW Yang, KW Kobayashi, DC Streit, AK Oki, HC Yen, PC Grossman, TR Block, LT Tran, A
GuiterrezAitken, LG Callejo, J Macek, S Maas ; IEEE GaAs IC; 10/1999
L Loval, A Darbandi, H Buret, M Soulard, F Michard ; IEEE GaAs IC; 10/1999
K Krishnamurthy, MJW Rodwell, SI Long ; IEEE GaAs IC; 10/1999
T Sasaki, Y Takada, Y Tanabe, T Nitta, Y Kakiuchi, M Yoshimura, K Fujieda, T Suzuki, H Kayano, M
Hirose, Y Kitaura ; IEEE GaAs IC; 10/1999
CF Campbell, SA Brown ; IEEE GaAs IC; 10/1999
SMJ Liu, OSA Tang, W Kong, K NIchols, J Heaton, PC Chao ; IEEE GaAs IC; 10/1999
YC Chen, DL Ingram, D Yamauchi, B Brunner, J Kraus, M Barsky, R Grundbacher, SK Cha, R Lai, T
Block, M Wojtowicz, TP Chin, B Allen, HC Yen, DC Streit ; IEEE GaAs IC; 10/1999
K Matsunaga, I Miura, N Iwata; IEEE GaAs IC; 10/1999
A Tessmann, L Verweyen, M Neumann, H Massler, WH Haydl, A Huelsmann, M Schlechtweg ; IEEE
GaAs IC; 10/1999
H Kondoh, K Sekine, S Takatani, K Takano, H Kuroda, R Dabkowski ; IEEE GaAs IC; 10/1999
G Hau, TB Nishimura, N Iwata; IEEE GaAs IC; 10/1999
GK Wong, SI Long ; IEEE GaAs IC; 10/1999
H Ishida, T Yokoyama, H Furukawa, T Tanaka, M Maeda, S Morimoto, Y Ota, D ueda, C Hamaguchi;
IEEE IEDM; 12/1999
KW Kobayashi, L Yang, A Guiterrez Aitken, E Kaneshiro, FM Yamada, HC Yen, TR Block, AK Oki, DC
Streit; IEEE IEDM; 12/1999
AP Long, GD Edwards, JR Suffolk, WA Phillips, SD Wadsworth ; IEEE APMW Conf; 12/1999
W Simbuerger, HD Wohlmuth, P Weger, A Heinz ; IEEE J SS Circ; 12/1999
NS Cheng, PC Jia, DB Rensch, RA York ; IEEE Trans MTT; 12/1999
Y Hoshino, M Morikawa, S Kamohara, M Kawakami, T Fujioka, Y Matsunaga, Y Kusakari, S Ikeda, I
Yoshida, S Shimizu; IEEE IEDM; 12/1999
JS Lim, SC Kang, SW Nam; IEEE MW Conference; 12/1999
J Cao, R Singh, B Liang, XW Wang, KE Sze, H Nakamura ; IEEE MW Conference; 12/1999
Y Tkachenko, Y Zhao, A Klimashov, CJ Wei, D Bartle ; IEEE MW Conference; 12/1999
TH Ng, BL Ooi, MS Leong, JY Ma, HS Ong, ST Chew ; IEEE MW Conference; 12/1999
AL Martin, A Mortazawi ; IEEE Trans MTT; 1/2000
M Kumar, Y Tan, J Sin, LX Shi, J Lau; IEEE ISSCC; 1/2000
J Carroll, R Flynt, S Brown ; IEEE ETS; 4/2000
JN Burghartz, M Hargrove, CS Webster, RA Groves, M Keene, KA Jenkins, R Logan, E Nowak ; IEEE
TED; 4/2000
P Colantonio, F Giannini, E Limiti, G Saggio; IEEE Elec Letters; 4/2000
C Pobanz, M Matloubian, V Radisic, G Raghavan, M Case, M Micovic, M Hu, C Nguyen, S Weinreb, L
Samoska; IEEE IPRM; 4/2000
131
[637]
[638]
[639]
[640]
[641]
[642]
[643]
[644]
[645]
[646]
[647]
[648]
[649]
[650]
[651]
[652]
[653]
[654]
[655]
[656]
[657]
[658]
[659]
[660]
[661]
[662]
[663]
[664]
[665]
[666]
[667]
[668]
JR Guthrie, M urteaga, D Scott, D Mensa, T Mathew, Q Lee, S Krishnan, S Jagananthan, Y Betser, MJW
Rodwell ; IEEE IPRM; 4/2000
KW Kobayashi, AK Oki, LW Yang, A Guiterrez Aitken, P Chin, D Sawdai, W Okamura, J Lester, E
Kaneshiro, PC Grossman, K Sato, TR Block, HC Yen, DC Streit ; IEEE IPRM; 4/2000
D Cui, D Sawdai, D pavlidis, SSH Hsu, P Chin, T Block ; IEEE IPRM; 4/2000
H Wang, L Samoska, T Gaier, A Peralta, HH Liao, YC Leong, S Weinreb, YC Chen, M Nishimoto, R Lai;
IEEE MTT-S; 6/2000
J Cao, XW Wang, CK Quek, R Singh, H Nakamura ; IEEE MTT-S; 6/2000
HJ Siweris, A Werthof, H Tischer, T Grave, H Werthmann, RH Rasshofer, W Kellner; IEEE MTT-S;
6/2000
CP McCarroll, GD Alley, S Yates, R Matreci ; IEEE MTT-S; 6/2000
KI Jeon, JH Lee, SW Paek, DW Kim, WS Lee, CR Lim, HY Cha, HK Choi, KW Chung ; IEEE MTT-S;
6/2000
YJE Chen, M Hamai, D Heo, A Sutono, S Yoo, J Laskar ; IEEE MTT-S; 6/2000
T Satoh, T Shimura, S Ichikawa, A Betti-Berutto, C Poledrelli, Y Furukawa, Y Hasegawa, S Kuroda, J
Fukaya ; IEEE MTT-S; 6/2000
JH Jeong, YW Kwon, SY lee, CY Cheon, EA Sovero ; IEEE MTT-S; 6/2000
J Staudinger, B Gilsdorf, D Newman, G Norris, G Sadowniczak, R Sherman, T Quach ; IEEE MTT-S;
6/2000
YC Leong, S Weinreb ; IEEE MTT-S; 6/2000
JJ Xu, S Keller, G Parish, S Heikman, YK Mishra, RA York ; IEEE MTT-S; 6/2000
YF Wu, D Kapolnek, JB Ibbetson, P Parikh, BP Keller, UK Mishra ; IEEE MTT-S; 6/2000
ST Sheppard, WL Pribble, DT Emerson, Z Ring, RP Smith, ST Allen, JW Palmour ; IEEE DRC; 6/2000
EY Chang, ES Fuh, CC Meng, KB Wang, SH Chen; IEEE TED; 6/2000
YW Kwon, KJ Kim, A Sovero, DS Deakin; IEEE Trans MTT; 6/2000
A Giry, JM Fournier, M Pons ; IEEE MTT-S; 6/2000
JP Fraysse, JP Viaud, M Campovecchio, P Auxemery, R Quere ; IEEE MTT-S; 6/2000
CY Hang, WR Deal, YX Qian, T Itoh ; IEEE MTT-S; 6/2000
S Tanaka, S Yamanouchi, Y Amamiya, K Hosoya, H Shimawaki, K Honjo; IEEE MTT-S; 6/2000
N Escalera, W Boger, P Denisuk, J Dobosz ; IEEE MTT-S; 6/2000
G Hau, TB Nishimura, N Iwata ; IEEE MTT-S; 6/2000
K Inoue, K Ebihara, H Haematsu, T Igarashi, H Takahashi, J Fukaya ; IEEE MTT-S; 6/2000
W Simbuerger, A Heinz, HD Wohlmuth, J Boeck, K Aufinger, M Rest ; IEEE MTT-S; 6/2000
XD Zhang, C Saycocie, S Munro, G Henderson; IEEE MTT-S; 6/2000
MJ Matilainen, KLI Nummila, EA Jaervinen, SJK Kalajo ; IEEE MTT-S; 6/2000
K Mori, S Shinjo, F Kitabayashi, A Ohta, Y Ikeda, 0 Ishida ; IEEE MTT-S; 6/2000
T Iwai, K Kobayashi, Y Nakasha, T Miyashita, S Ohara, K Joshin ; IEEE MTT-S; 6/2000
T Murae, K Fujii, T Matsuno ; IEEE MTT-S; 6/2000
SLG Chu, A Platzker, M Borkowski, R Mallavarpu, M Snow, A Bowlby, D Teeter, T Kazior, K Alavi;
IEEE MTT-S; 6/2000
[669]
[670]
[671]
[672]
[673]
[674]
[675]
[676]
[677]
[678]
[679]
[680]
DL Ingram, YC Chen, I Stones, D Yamauchi, B Brunner, P Huang, M Biedenbender, J Elliott, R Lai, DC
Streit, KF Lau, HC Yen ; IEEE MTT-S; 6/2000
AL Martin, A Mortazawi ; IEEE MTT-S; 6/2000
CS Yoo, QT Huang ; IEEE VLSI; 7/2000
RA Sadler, ST Allen, WL Probble, TS Alcorn, JJ Sumakeris, JW Palmour ; IEEE Cornell Conf on HPD;
7/2000
N Matsuno, H Yano, Y Suzuki, T Watanabe, S Tsubaki, T Toda, K Honjo ; IEEE Trans MTT; 7/2000
K Yamamoto, S Suzuki, K Mori, T Asada, T Okuda, A Inoue, T Miura, R Hattori, M Yamanouchi, T
Shimura ; IEEE J SS Circ; 7/2000
BM Green, KK Chu, JA Smart, V Tilak, HT Kim, JR Shealy, LF Eastman ; IEEE MWGW Letters; 7/2000
E Chen, D Heo, M Hamai, J Laskar, D Bien ; IEEE RAWCON; 9/2000
HGA Huizing, F van Rijs, PHC Magnee, DMH Hartskeerl ; IEEE BCTM; 9/2000
EC Glass, JH Huang, J Staudinger, M Shields, MJ Martinez, OL Hartin, W Valentine, E Lan ; IEEE J SS
Circ; 9/2000
K Krishnamurthy, R Vetury, S Keller, U Mishra, MJW Rodwell, SI Long; IEEE J SS Circ; 9/2000
K Matsunaga, I Miura, N Iwata ; IEEE J SS Circ; 9/2000
132
[681]
[682]
[683]
[684]
[685]
[686]
[687]
[688]
[689]
[690]
[691]
[692]
[693]
[694]
[695]
[696]
[697]
[698]
[699]
[700]
[701]
[702]
[703]
[704]
[705]
[706]
[707]
[708]
[709]
[710]
[711]
[712]
[713]
[714]
[715]
[716]
[717]
[718]
[719]
[720]
[721]
[722]
[723]
[724]
OSA Tang, SMJ Liu, PC Chao, WMT Kong, KC Hwang, K Nichols, J Heaton; IEEE J SS Circ; 9/2000
CS Whelan, PF Marsh, WE Hoke, RA McTaggart, PS Lyman, PJ Lemonias, SM Lardizabal, RE Leoni, SJ
Lichwala, TE Kazior ; IEEE J SS Circ; 9/2000
PD Tseng, LY Zhang, GB Gao, MF Chang; IEEE J SS Circ; 9/2000
XN Zhu, XJ Chen, JT Ling ; IEEE ICMMT; 9/2000
TS Chen, Y Shen, FX Li, XJ Chen, Nanjing Uni; IEEE ICMMT; 9/2000
Y Tan, M Kumar, JKO Sin, LX Shi, J Lau; IEEE J SS Circ; 10/2000
E Alekseev, D Pavlidis, NX Nguyen, C Nguyen, DE Grider ; IEEE J SS Circ; 10/2000
A Sutono, D Heo, E Chen, K Lim, J Laskar ; IEEE Conf El Perf of Electronic Packaging; 10/2000
H Kawamura, K Sakuno, T Hasegawa, M Hasegawa, H Koh, H Sato; IEEE GaAs IC; 10/2000
T Moriuchi, W Abey, R Hajji, W Kennan, T Nakamura, S Maruyama, T Kitawada, Y Nonaka, E Mitani;
IEEE GaAs IC; 10/2000
WCB Peatman, 0 Hartin, B Knappenberger, M Miller, R Hooper; IEEE GaAs IC; 10/2000
Y Butel, T Adam, B Cogo, M Soulard ; IEEE GaAs IC; 10/2000
W Okamura, LW Yang, A Guiterrez Aitken, E Kaneshiro, J Lester, D Sawdai, PC Grossman, K Kobayashi,
HC Yen, A Oki, P Chin, T Block ; IEEE GaAs IC; 10/2000
SA Brown, JM Carroll ; IEEE GaAs IC; 10/2000
WMT Kong, SC Wang, PC Chao, DW Tu, K Hwang, OSA Tang, SM Liu, P Ho, K Nichols, J Heaton;
IEEE EDL; 10/2000
K Krishnamurthy, S Keller, UK Mishra, MJW Rodwell, SI Long ; IEEE GaAs IC; 10/2000
A Bessemoulin, H Massler, A Huelsmann, M Schlechtweg ; IEEE MWGW Letters; 12/2000
YF Wu, PM Chavarkar, M Moore, P Parikh, BP Keller, UK Mishra ; IEEE IEDM; 12/2000
A Darbandi, H Buret, F Lavielle, M Peschoud ; IEEE Sem on RF PA; 12/2000
P Asbeck, C Fallesen ; IEEE ICECS; 12/2000
BX Gao, Y Wang; IEEE APMW Conf; 12/2000
T Tokumitsu; IEEE APMW Conf; 12/2000
T Ohguru, M Saito, E Morifuji, Koji Murakami, K Matsuzaki, T Yoshitomi, T Morimoto, HS Momose, Y
Katsumata, H Iwai ; IEEE TED; 12/2000
K Mori, S Shinjo, F Kitabayashi, A Ohta, Y Ikeda, 0 Ishida ; IEEE Trans MTT; 12/2000
K Matsunaga, K Ishikura, I Takenaka, W Contrata, A Wakejima, K Ota, M Kanamori, M Kuzuhara ; IEEE
IEDM; 12/2000
EY Chang, DH Lee, SH Chen ; IEEE APMC; 12/2000
MS Uhm, DP Jang, IB Yom, SP Lee; IEEE APMC; 12/2000
Y Trachenko, Y Zhao, C Wei, A Klimashov, D Bartle ; IEEE APMC; 12/2000
WY Kim, MC Chung, KH Lee, YG Yang, SH Kang, BM Kim ; IEEE APMC; 12/2000
BS Virdee, AS Virdee ; IEEE APMC; 12/2000
JY Lee, SG Han, JC Lee, B Lee, JH Kim, NY Kim, KI Chun ; IEEE APMC; 12/2000
HK Choi, JC Lee, B lee, JH Kim, NY Kim, US Hong ; IEEE APMC; 12/2000
G Hau, TB Nishimura, N Iwata ; IEEE MWWC Letters; 1/2001
C Fallesen, P Asbeck ; IEEE ISSCC; 1/2001
T Sowlati, D Leenaerts ; IEEE ISSCC; 1/2001
R Gupta, BM Ballweber, DJ Allstot ; IEEE J SS Circ; 1/2001
G Simin, X Hu, N Ilinskaya, J Zhang, A Tarakji, A Kumar, J Yang, M Asif Khan, R Gaska, MS Shur;
IEEE EDL; 1/2001
TC Kuo, BB Lusignan; IEEE ISSCC; 1/2001
A Shirvani, DK Su, BA Wooley ; IEEE ISSCC; 1/2001
EM Chumbes, AT Schremer, JA Smart, Y Wang, NC MacDonald, D Hogue, JJ Komiak, SJ Lichwalla, RE
Leoni, JR Shealy ; IEEE TED; 3/2001
SC Binari, K Ikossi, JA Roussos, W Kruppa, D Park, HB Dietrich, DD Koleske, AE Wickenden, RL Henry
; IEEE TED; 3/2001
LF Eastman, V Tilak, J Smart, BM Green, EM Chumbes, R Dimitrov, HT Kim, OS Ambacher, N
Weimann, T Prunty, M Murphy, WJ Schaff, JR Shealy ; IEEE TED; 3/2001
SY Lee, BA Cetiner, H Torpi, SJ Cai, J Li, K Alt, YL Chen, CP Wen, KL Wang, T Itoh ; IEEE TED;
3/2001
M Micovic, A Kurdoghlian, P Janke, P Hashimoto, DWS Wong, JS Moon, L McCray, C Nguyen ; IEEE
TED; 3/2001
133
[725]
[726]
[727]
[728]
[729]
[730]
[731]
[732]
[733]
[734]
[735]
[736]
[737]
[738]
[739]
[740]
[741]
[742]
[743]
[744]
[745]
[746]
[747]
[748]
[749]
[750]
[751]
[752]
[753]
[754]
[755]
[756]
[757]
[758]
[759]
[760]
[761]
[762]
[763]
[764]
[765]
[766]
[767]
[768]
[769]
[770]
[771]
M Touirat, M Roger, JC Pesant, S Ajram, Y Crosnier, G Salmer ; IEEE EDL; 4/2001
SC Yang, HC Chiu, FT Chien, YJ Chan, JM Kuo ; IEEE EDL; 4/2001
YM Hsin, CH Lin, CC Fan, ST Su, MHT Yang, JCH Huang, KC Lin ; IEEE IPRM; 4/2001
I Aoki, SD Kee, D Rutlede, A Hajimiri ; IEEE CICC; 4/2001
CS Yoo, QT Huang ; IEEE J SS Circ; 4/2001
T Quach, W Okamura, A Guiterrez Aitken, T Jenkins, E Kaneshiro, L Kehias, A Oki, D Sawdai, P Watson,
R Welch, R Worley, HC Yen ; IEEE IPRM; 4/2001
TB Nishimura, M Tanomura, K Azuma, K Nakai, Y Hasegawa, H Shimawaki ; IEEE MTT-S; 6/2001
W Bischof, M Alles, S gerlach, A Kruck, A Schueppen, J Sinderhauf, HJ Wassener; IEEE MTT-S; 6/2001
W Schuchter, G Krasser, V Schultheiss, G Hofer; IEEE MTT-S; 6/2001
D Gerna, A Giry, D Manstretta, D Belot, D Pache ; IEEE MTT-S; 6/2001
A Raghavan, E Gebara, CH Lee, S Chakraborty, D Mukherjee, J Battacharjee, D Heo, J Laskar ; IEEE
MTT-S; 6/2001
F Temcamani, P Pouvil, 0 Noblanc, C Brylinski, P Bannelier, B Darges, JP Prigent ; IEEE MTT-S; 6/2001
E Ebihara, K Inoue, H Haematsu, F Yamaki, H Takahashi, J Fukaya ; IEEE MTT-S; 6/2001
T Murae, K Fujii, T Matsuno ; IEEE MTT-S; 6/2001
CH Lee, A Sutono, S Han, J Laskar ; IEEE MTT-S; 6/2001
Y Sasaki, H Kurusu, H Hoshi, T Hisaka, Y Mitsui ; IEEE MTT-S; 6/2001
J Estes, P Piel, G Shapiro, A Pavio, M Hurst, J Call, G Funk ; IEEE MTT-S; 6/2001
MP van der Heijden, HC de Graaf, LCN de Vreede, JR Gajadharsing, JN Burghartz ; IEEE MTT-S; 6/2001
H Darabi, S Khorram, HM Chien, MA Pan, S Wu, S Moloudi, JC Leete, JJ Rael, M Syed, R Lee, B
Ibrahim, M Rofougaran, A Rofougaran ; IEEE J SS Circ; 6/2001
S Matsumoto, Y Hiraoka, T Sakai; IEEE TED; 6/2001
D Barataud, M Campovecchio, JM Nebus ; IEEE Trans MTT; 6/2001
CY Hang, WR Deal, YX Qian, T Itoh ; IEEE Trans MTT; 6/2001
H Okazaki, T Ohira, K Araki ; IEEE Trans MTT; 6/2001
G Hau, TB Nishimura, N Iwata ; IEEE Trans MTT; 6/2001
J Caldinhas Vaz, J Costa Freire ; IEEE Trans MTT; 6/2001
D Heo, A Sutono, E Chen, Y Suh, J Laskar ; IEEE MWWC Letters; 6/2001
P Colantonio, F Giannini, G Leuzzi, E Limiti ; IEEE MTT-S; 6/2001
YE Chen, YK Yoon, J Laskar, M Allen; IEEE MTT-S; 6/2001
R Emrick; IEEE MTT-S; 6/2001
R Purpas, F Brunner, R Doerner, B Janke, P Heymann, A Maasdorf, W Doser, P Auxemery, H Blanck, D
Pons, J Wuerfl, W Heinrich ; IEEE MTT-S; 6/2001
I Takenaka, K Ishikura, H Takahashi, K Kishi, Y ogasawara, K Hasegawa, H takahashi, F Emori, N Iwata;
IEEE MTT-S; 6/2001
C Fallesen, P Asbeck ; IEEE MTT-S; 6/2001
D Heo, A Sutono, E Chen, E Gebara, S Yoo, Y Suh, J Laskar, E Dalton, EM Tentzeris ; IEEE MTT-S;
6/2001
W Abey, T Moriuchi, R Hajii, T Nakamura, Y Nonaka, E Mitani, W Kennan, H Dang ; IEEE MTT-S;
6/2001
SY Zhang, J Cao, R Mcmorrow ; IEEE MTT-S; 6/2001
M Iwamoto, A Williams, PF Chen, A Metzger, CZ Wang, LE Larson, PM Asbeck; IEEE MTT-S; 6/2001
S Bousnina, FM Ghannouchi ; IEEE MTT-S; 6/2001
H Kobayashi, J Hinrichs, PM Asbeck ; IEEE MTT-S; 6/2001
C Duperrier, M Campovecchio, L Russel, M Lajugie, R Quere ; IEEE MTT-S; 6/2001
M Salib, HK Hahn, J Kositz, J Zingaro, A Ezis, A Gupta ; IEEE MTT-S; 6/2001
CY Hang, YX Qian, T Itoh ; IEEE MTT-S; 6/2001
E McShane, K Shenai, SK Leong ; IEEE MTT-S; 6/2001
BM Green, V Tilak, SJ Lee, HT Kim, JA Smart, KJ Webb, JR Shealy, LF Eastman ; IEEE MTT-S; 6/2001
F Fortes, MJ do Rosario ; IEEE Trans MTT; 7/2001
S Matsumoto, Y Hiraoka, T Sakai, T Tachi, T Ishiyama, T Kosugi, H Kamitsuna, M Murahuchi ; IEEE
TED; 7/2001
M Kim, JB Hacker, RE Mihailovich, JF DeNatale ; IEEE MWWC Letters; 7/2001
ZQ Ma, S Mohammadi, LH Lu, P Bhattacharya, LPB Katehi, SA Alterovitz, GE Ponchak ; IEEE MWWC
Letters; 7/2001
134
[772]
[773]
[774]
[775]
[776]
[777]
[778]
[779]
[780]
[781]
[782]
[783]
[784]
[785]
[786]
[787]
[788]
[789]
[790]
[791]
[792]
[793]
[794]
[795]
[796]
[797]
[798]
[799]
[800]
[801]
[802]
[803]
[804]
[805]
[806]
[807]
[808]
[809]
[810]
[811]
[812]
[813]
[814]
[815]
[816]
[817]
S Chakraborty, CH Lee, S Yoo, D Heo, A Raghavan, D Mukherjee, J Bhattacharjee, J Laskar ; IEEE
RAWCON; 7/2001
JH Kim, B Palmer, R Harjani ; IEEE RAWCON; 7/2001
T Bito, T Kato, N Iwata ; IEEE TED; 7/2001
K Yamamoto, T Heima, A Furukawa, M Ono, Y Hashizume, H Komurasaki, S Maeda, H Sato, N Kato;
IEEE J SS Circ; 7/2001
CC Hsiao, CW Kuo, YJ Chan; IEEE RAWCON; 7/2001
YS Noh, CS Park; IEEE RAWCON; 7/2001
MH Hella, M Ismail ; IEEE MWSCAS; 7/2001
P Baureis, M Peter, H Hein, F Oehler ; IEEE SMIC RF; 9/2001
JR Shealy ; IEEE SMIC RF; 9/2001
ZQ Ma, S Mohammadi, P Bhattacharya, LPB Katehi, SA Alterovitz, GE Ponchak ; IEEE SMIC RF; 9/2001
S Luo, T Sowlati ; IEEE Trans MTT; 9/2001
L Kehias, T Jenkins, T Quach, P Watson, R Welch, R Worley, AK Oki, HC Yen, A Guiterrez Aitken, W
Okamura, E ]Kaneshiro ; IEEE MWWC Letters; 9/2001
JW Lee, KJ Webb ; IEEE MWWC Letters; 9/2001
Y Chung, S Cai, W Lee, Y Lin, CP Wen, KL Wang, T Itoh ; IEEE Elect Letters; 9/2001
T Senju, T Asano, H Ishimura ; IEEE BCIES; 9/2001
S Lam, WH ]Ki, MS Chan ; IEEE SOI Conf; 10/2001
YC Lee, CS ]Park; IEEE SSICT; 10/2001
Z Feng, XB Gao, CQ Wang; IEEE SSICT; 10/2001
HC Chiu, SC Yang, YJ Chan ; IEEE TED; 10/2001
A Sutono, DH Heo, YJE Chen, J Laskar ; IEEE Trans MTT; 10/2001
P Savary, A Girardot, G montoriol, F Dupis, B Thibaud, R Jaoui, L Chapoux, V Esnault, L Cornibert, O
Izumi, D Hill, M Sadaka, H Henry, E Yu, M Tutt, M Majerus, R Uscola, F Clayton, C Rampley, S
Klingbeil, K Rajagopalan, A Mitra, A Reyes ; IEEE GaAs IC; 10/2001
R Lai, R Grundbacher, M Barsky, A Oki, M Siddiqui, B Pitman, R Katz, P Tran, L Callejo, D Streit ; IEEE
GaAs IC; 10/2001
T Quach, P Watson, W Okamura, E Kaneshiro, A Guiterrez Aitken, T Block, J Eldredge, T Jenkins, L
Kehias, A Oki, D Sawdai, R Welch, R Worley ; IEEE GaAs IC; 10/2001
T Tokumitsu ; IEEE Trans MTT; 10/2001
T Takagi, K Yamauchi, Y Itoh, S Urasaki, M Komaru, Y Mitsui, H Nakaguro, Y Kazekami ; IEEE Trans
MTT; 10/2001
T Hirayama, N Matsuno, M Fujii, H Hida ; IEEE GaAs IC; 10/2001
P Blount, J Cuggino, J McPhee ; IEEE GaAs IC; 10/2001
R Tayrani ; IEEE GaAs IC; 10/2001
JH Yoon, CH Seo ; IEEE MWWC Letters; 10/2001
CS Kim, JW Park, HK Yu ; IEEE IEDM; 12/2001
JW Lee, BM Green, V Tilak, SJ Lee, JR Shealy, LF Eastman, KJ Webb ; IEEE SDRC; 12/2001
W Walthes, A Pascht, M Berroth ; IEEE SDRC; 12/2001
DC Streit, D Sawdai, R Grunbacher, R Tsai, R Lai, A Guiterrez Aitken, A Oki ; IEEE APMC; 12/2001
S Chaki, T Hisaka, T Hirai, Y Sasaki, S Sakamoto, Y Mitsui ; IEEE APMC; 12/2001
S Halder, ZY Xiong, GI Ng, H Wang, HQ Zheng, K Radhakarishnan, JCM Hwang ; IEEE Trans MTT;
12/2001
VTS Vintola, MJ Matilainen, SJK Kalajo, EA Jaervinen ; IEEE Trans MTT; 12/2001
M Iwamoto, A Williams, PF Chen, AG Metzger, LL Larson, PM Asbeck ; IEEE Trans MTT; 12/2001
H Kobayashi, JM Hinrichs, PM Asbeck ; IEEE Trans MTT; 12/2001
BM Green, V Tilak, SJ Lee, HT Kim, JA Smart, KJ Webb, JR Shealy, LF Eastman ; IEEE Trans MTT;
12/2001
K Yamauchi, Y Iyama, M Yamaguchi, Y Ikeda, S Urasaki, T Takagi ; IEEE Trans MTT; 12/2001
SC Yang, HC Chiu, YJ Chan, HH Lin, JM Kuo ; IEEE TED; 12/2001
S Matsumoto, T Sakai ; IEEE TED; 12/2001
F Carrara, A Scuderi, G Tontodonato, G Palmisano ; IEEE IEDM; 12/2001
CW Kuo, CC Hsiao, YJ Chan; IEEE APMC; 12/2001
SH Chen, EY Chang, YC Lin ; IEEE APMC; 12/2001
HC Chiu, SC Yang, FT Chien, YJ Chan; IEEE EDL; 1/2002
135
[818]
[819]
[820]
[821]
[822]
[823]
[824]
[825]
[826]
[827]
[828]
[829]
[830]
[831]
[832]
[833]
[834]
[835]
[836]
[837]
[8381
[839]
[840]
[841]
[842]
[843]
[844]
[845]
[846]
[847]
[848]
[849]
[850]
[851]
[852]
[853]
[854]
[855]
[856]
[857]
[858]
[859]
[860]
KLR Mertens, MSJ Steyaert ; IEEE J SS Circ; 1/2002
YG Yang, YY Woo, BM Kim ; IEEE Trans MTT; 1/2002
JG Fiorenza, JA del Alamo ; IEEE TED; 4/2002
ZQ Ma, S Mohammadi, P Bhattacharya, LPB Katehi, SA Alterovitz, GE Ponchak; IEEE Trans MTT;
4/2002
HC Chiu, MJ Hwu, SC Yang, YJ Chan ; IEEE EDL; 4/2002
W Bakalski, W Simbuerger, D Kehrer, HD Wohlmuth, M Rest, AL Scholtz ; IEEE ISCAS; 4/2002
R Tayrani ; IEEE MTT-S; 6/2002
HC Huang, A Ezzeddine, A Darwish, B Hsu, J Williams, S peak ; IEEE MTT-S; 6/2002
T Matsuno, K Nishii, S Sonetaka, Y Toyoda, N Iwamoto; IEEE MTT-S; 6/2002
T Merkle, A Tessmann, S Ramberger ; IEEE MTT-S; 6/2002
EJ Crescenzi ; IEEE MTT-S; 6/2002
M Iwamoto, CP Hutchinson, JB Scott, TS Low, M Vaidyanathan, PM Asbeck, DC D'Avanzo ; IEEE MTTS; 6/2002
JM Schellenberg ; IEEE MTT-S; 6/2002
Y Wei, SM Lee, K Sundararajan, M Dahlstrom, M Urteaga, M Rodwell ; IEEE MTT-S; 6/2002
A Inoue, S Nakatsuka, R Hattori, Y Matsuda ; IEEE MTT-S; 6/2002
N Escalera, R Emrick, S Franson, B Farber, G Garrison, J Holmes, S Rockwell, B Bosco ; IEEE MTT-S;
6/2002
CH Lee, S Chakraborty, A Sutono, S Yoo, D Heo, J Laskar ; IEEE MTT-S; 6/2002
M Kaerkkaeinen, M Varonen, J Riska, P Kangaslahti, V Porra ; IEEE MTT-S; 6/2002
K Yamamoto, T Asada, S Suzuki, T Miura, A Inoue, S Miyakuni, J Otsuji, R Hattori, Y Miyazaki, T
Shimura ; IEEE MTT-S; 6/2002
A Jitwin, 0 Bengtsson, J Olsson ; IEEE MTT-S; 6/2002
S Mohammadi, ZQ Ma, JH Park, P Bhattacharya, LPB Katehi, GE Ponchak, SA Alterovitz, KM Strohm,
SF Luy ; IEEE MTT-S; 6/2002
MT Doan, Q Yin, KE Sze, PB Khannur, SC Rustagi, SJ Pang, D Foo, AB Ajjikuttira ; IEEE MTT-S;
6/2002
Y Mimino, K Nakamura, Y Hasegawa, Y Aoki, S Kuroda, T Tokumitsu ; IEEE MTT-S; 6/2002
K Fujii, M Adamski, P Bianco, D Gunyan, J Hall, R Kishimura, C Lesko, M Schefer, S Hessel, H Morkner,
A Niedzwiecki ; IEEE MTT-S; 6/2002
WL Pribble, JW Palmour, ST Sheppard, RP Smith, ST Allen, TJ Smith, Z Ring, JJ Sumakeris, AW Saxler,
JW Milligan ; IEEE MTT-S; 6/2002
A Shirvani, DK Su, BA Wooley ; IEEE J SS Circ; 6/2002
YK Chung, CY Hang, SJ Cai, YX Qian, CP Wen, KL Wang, T Itoh ; IEEE MTT-S; 6/2002
JP Fraysse, 0 Vendier, M Soulard, P Auxemery ; IEEE MTT-S; 6/2002
JM Schellenberg ; IEEE MTT-S; 6/2002
E Glass, M Shields, A Reyes ; IEEE MTT-S; 6/2002
J Staudinger, R Sherman, T Quach, M Miller, L Frye; IEEE MTT-S; 6/2002
S Kusunoki, K Yamamoto, T Hatsugai, K Tagami, H Nagaoka, N Tominaga, K Osawa, K Tanabe, S
Sakurai, T lida ; IEEE MTT-S; 6/2002
L Zhao, A Pavio, B Stengel, B Thompson ; IEEE MTT-S; 6/2002
JJ Komiak, W Kong, K Nichols ; IEEE MTT-S; 6/2002
F Carrara, A Castorina, A Scuderi, G Palmisano ; IEEE MTT-S; 6/2002
A Raghavan, DH Heo, MK Maeng, A Sutono, KT Lim, J Laskar ; IEEE MTT-S; 6/2002
H Jaeger, A Grebennikov, E Heaney, R Weigel ; IEEE MTT-S; 6/2002
E Lan, E Johnson, B Knappenberger, M Miller ; IEEE MTT-S; 6/2002
RC Clarke, JW Palmour ; IEEE Proc IEEE; 6/2002
UK Mishra, P Parikh, YF Wu ; IEEE Proc IEEE; 6/2002
ST Sheppard, RP Smith, WL Pribble, Z Ring, T Smith, ST ALlen, J Milligan, JW Palmour ; IEEE DRC;
6/2002
A Aleeksov, M Kubovic, N Kaeb, U Spitzberg, I Daumiller, T Bauer, M Schreck, B Stritzker, E Kohn;
IEEE DRC; 6/2002
A Agarwal, C Capell, B Phan, J Milligan, JW Palmour, J Stambaugh, H Bartlow, K Brewer ; IEEE HPD;
7/2002
136
[861]
[862]
[863]
[864]
[865]
[866]
[867]
[868]
[869]
[870]
[871]
[872]
[873]
[874]
[875]
[876]
[877]
[878]
[879]
[880]
[881]
[882]
[883]
[884]
[885]
[886]
[887]
[888]
[889]
[890]
[891]
[892]
[893]
[894]
[895]
[896]
[897]
[898]
[899]
[900]
[901]
[902]
[903]
Y Wei, K Sundararajan, M Urteaga, Z Griffith, D Scott, V paidi, N Parthasarathy, M Rodwell ; IEEE HPD;
7/2002
KW Ho, HC Luong ; IEEE MWSCAS; 7/2002
S Lam, WH Ki, C Shen, PK Ko, M Chan; IEEE ICMMWT; 7/2002
JH Kim, JH Kim, YS Noh, CS Park ; IEEE ICMMWT; 7/2002
TK Quach, PM Watson, W Okamura, EN Kaneshiro, A Guiterrez Aitken, TR Block, JW Eldredge, TJ
Jenkins, LT Kehias, AK Oki, D Sawdai, RJ Welch, RD Worley ; IEEE J SS Circ; 9/2002
ZQ Ma, S Mohammadi, P Bhattacharya, LPB Katebi, SA Alterovitz, GE Ponchak ; IEEE BCTM; 10/2002
MM Hella, M Ismail ; IEEE Proc CDS; 10/2002
M Tomaska, M Krnac, R Vazny ; IEEE ASDAM; 10/2002
HZ Liu, CC Wang, YH Wang, WL Huang, CH Chang, W Wu, CL Wu, CS Chang ; IEEE GaAs IC;
10/2002
KS Kong, D Boone, M King, B Nguyen, M Vernon, E Reese, G Brehm; IEEE GaAs IC; 10/2002
A Bessemoulin, J Dishong, G Clark, D White, P Quentin, H Thomas, D Geiger ; IEEE GaAs IC; 10/2002
J Dunn, G Freeman, D Harame, A Joseph, D Coolbaugh, R Groves, K Stein, R Volant, S Subbanna, VS
Marangos, S St Onge, E Eshun, P Cooper, J Johnson, J Rieh, V Ramachandran, D Ahlgren, D Wang, X
Wang; IEEE GaAs IC; 10/2002
JH Kim, JH Kim, YS Noh, YS Kim, SG Kim, CS Park ; IEEE GaAs IC; 10/2002
S Rockwell, R Emrick, B Bosco, S Franson, M Miller, E Johnson, J Crowder ; IEEE GaAs IC; 10/2002
A Bessemoulin, H Massler, R Quay, S Ramberger, M Schlechtweg ; IEEE GaAs IC; 10/2002
M Zargari, DK Su, CP Yue, S Rabii, D Weber, BJ Kaczynski, SS Mehta, K Singh, S Mendis, BA Wooley;
IEEE J SS Circ; 12/2002
A Tessmann, S Kudszus, T Feltgen, M Riessle, C Sklarczyk, WH Haydl ; IEEE Trans MTT; 12/2002
YS Noh, JH Kim, JH Kim, CS Park; IEEE Electr Letters; 12/2002
HM Hsu, JG Su, CW Chen, DD Tang, CH Chen, YC Sun ; IEEE Trans MTT; 12/2002
R Kurpas, A Maassdorf, W Doser, P Heymann, B Janke, F Schnieder, H Blanck, P Auxemery, D Pons, W
Heinrich, J Wuerfl ; IEEE IEDM; 12/2002
P Admane, M Patasani, B Viswanathan ; IEEE VLSI; 1/2003
S Sarkar, P Sen, A Raghavan, S Chakarborty, J Laskar ; IEEE VLSI; 1/2003
A Zolfaghari, B Razavi ; IEEE J SS Circ; 1/2003
CC Yen, HR Chuang ; IEEE MWWC Letters; 1/2003
BM Green, V Tilak, VS Kaper, JA Smart, JR Shealy, LF Eastman ; IEEE Trans MTT; 1/2003
V Paidi, SX Xie, R Coffie, B Moran, S Heikman, S Keller, A Chini, SP DenBaars, UK Mishra, S Long,
MJW Rodwell ; IEEE Trans MTT; 1/2003
YK Chung, CY Hang, SJ Cai, YX Qian, CP Wen, KL Wang, T Itoh ; IEEE Trans MTT; 1/2003
W Nagy, J Brown, R Borges, S Singhal ; IEEE Trans MTT; 1/2003
IP Smorchkova, M Wojtowicz, R Sandhu, R Tsai, M Barsky, C Namba, PS Liu, R Dia, MD Truong, D Ko,
J Wang, H Wang, A Khan ; IEEE Trans MTT; 1/2003
W Bakalski, N Ilkov, O Dernovsck, R Matz, W Simbuerger, P Weger, AL Scholz ; IEEE Elect Letters;
1/2003
N Vellas, C Gaquiere, A Minko, V Hoel, JC DeJaeger, Y Cordier, F Semond ; IEEE MWWC Letters;
3/2003
HY Tu, TH Chou, YS Lin, HC Chiu, PY Chen, WC Wu, SS Lu ; IEEE EDL; 3/2003
HY Chang, H Wang, M Yu, YH Shu ; IEEE MWWC Letters; 4/2003
F Villard, JP Prigent, E Morvan, C Dua, C Brylinski, F Temcamani, P Pouvil ; IEEE Trans MTT; 4/2003
H Komurasaki, T Sano, T Heima, K Yamamoto, H Wakada, I Yasui, M Ono, T Miwa, H Sato, T Miki, N
Kato ; IEEE J SS Circ; 4/2003
TT Hung, MN ElGamal ; IEEE ISCAS; 4/2003
Y Ando, Y Okamoto, H Miyamoto, T Nakayama, T Inoue, M Kuzuhara ; IEEE EDL; 4/2003
KJ Herrick, CS Whealan, PF Marsh, SM Lardizabal ; IEEE IPRM; 4/2003
L Zhao, A Pavio, W Thompson ; IEEE MTT-S; 6/2003
J Udomoto, T Matsuzuka, S Chaki, K Kanaya, T Katoh, Y Notani, T Hisaka, T Oku, T Ishikawa, M
Komaru, Y Matsuda ; IEEE MTT-S; 6/2003
C Dragon, W Brakensiek, D Burdeaux, W Burger, G Funk, M Hurst, D Rice; IEEE MTT-S; 6/2003
K Matsunaga, H Shimawaki ; IEEE MTT-S; 6/2003
M Morgan, S Weinreb ; IEEE MTT-S; 6/2003
137
[904]
[905]
[906]
[907]
[908]
[909]
[910]
[911]
[912]
[913]
[914]
[915]
[916]
[917]
[918]
[919]
[920]
[921]
[922]
[923]
[924]
[925]
[926]
[927]
[928]
[929]
[930]
[931]
[932]
[933]
[934]
[935]
[936]
[937]
[938]
[939]
[940]
[941]
[942]
[943]
[944]
[945]
[946]
[947]
[948]
[949]
AP Zhang, LB Rowland, EB Kaminsky, JW Kretchmer, V Tilak, AF Allen, BJ Edward ; IEEE MTT-S;
6/2003
F van Raay, R Quay, R Kiefer, M Schlechtweg, G Weimann ; IEEE MTT-S; 6/2003
HM Park, SH Cheon, JW Park, SC Hong ; IEEE MTT-S; 6/2003
NL Wang, C Dunnrowicz, X Chen, W Ma, HF Chau, X Sun, Y Chen, B Lein, IL Lo, CH Huang, MHT
Yang; IEEE MTT-S; 6/2003
SQ Chen, E Reese, KS Kong ; IEEE MTT-S; 6/2003
K Fujii, H Morkner ; IEEE MTT-S; 6/2003
PS Wu, TW Huang, H Wang; IEEE MTT-S; 6/2003
M Varonen, M Kaerkkaeinen, P Kangaslahti, V Porra ; IEEE MTT-S; 6/2003
Y Wai, M Urteaga, Z Griffith, D Scott, SX Xie, V Paidi, N Parthasartathy, M Rodwell ; IEEE MTT-S;
6/2003
P Juurakko, V Saari, J Ryynaenen, K Halonen; IEEE MTT-S; 6/2003
PB Khannur; IEEE MTT-S; 6/2003
S Shinjo, HO Ueda, T Sugano, M Nakanishi, M Inoue, N Suematsu ; IEEE MTT-S; 6/2003
R Point, Z Li, W Foley, B Ingersoll, J Borelli, D Segarra, D Donoghue, C Liss, M Mendes, J Feigin, A
Georgiadis, M Valery, E Dawe, D Losanno, R Quintal, M Nikitin, R Jabor, M Morin, KK O, G Dawe;
IEEE MTT-S; 6/2003
M Ugajin, A Yamagishi, J Kodate, M Harada, T Tsukahara ; IEEE VLSI; 6/2003
K Tanaka, K Mochizuki, C Takubo, H matsumoto, T Tanoue, I Ohbu; IEEE MTT-S; 6/2003
JH Cha, YO Yang, BJ Shin, BM Kim ; IEEE MTT-S; 6/2003
KJ Herrick, SM Lardizabal, PF Marsh, CS Whelan ; IEEE MTT-S; 6/2003
H Brech, W Burger, C Dragon, B Pryor ; IEEE MTT-S; 6/2003
A Scuderi, F Carrara, A Castorina, G Palmisano ; IEEE MTT-S; 6/2003
Y Bito, T Ishigaki, H Shimawaki, Y Nashimoto ; IEEE MTT-S; 6/2003
T Niwa, T Ishigaki, H Shimawaki, Y Nashimoto; IEEE MTT-S; 6/2003
FY Colomb, A Platzker ; IEEE MTT-S; 6/2003
T Shimura, T Satoh, Y Hasegawa, J Fukaya ; IEEE MTT-S; 6/2003
unknown ; IEEE MTT-S; 6/2003
JH Kim, JH Kim, YS Noh, CS Park ; IEEE MTT-S; 6/2003
K Fujita, K Shirakawa, N Takahashi, Y Liu, T Oka, M Yamashita, K Sakuno, H Kawamura, M Hasegawa,
H Koh, K Kagoshima, H Kijima, H Sato ; IEEE MTT-S; 6/2003
HC Chiu, TJ Yeh, SC Yang, MJ Hwu, YJ Chan ; IEEE TED; 6/2003
SY Zhang, P Brechko, J Mokoro, R McMorrow; IEEE MTT-S; 6/2003
N Tanzi, J Dykstra, K Hutchinson ; IEEE MTT-S; 6/2003
T Biondi, F Carrara, A Scuderi, G Palmisano ; IEEE MTT-S; 6/2003
I Aoki, S Kee, D Rutledge, A Hajimiri ; IEEE MTT-S; 6/2003
S Pajic, ZB Popovic ; IEEE Trans MTT; 7/2003
SX Xie, V Paidi, R Coffie, S Keller, S Heikman, B Moran, A Chini, SP DenBaars, U Mishra, S Long,
MJW Rodwell ; IEEE MWWC Letters; 7/2003
HC Chiu, SC Yang, CK Lin, MJ Hwu, YJ Chan ; IEEE TED; 7/2003
A Keerti, A Pham ; IEEE Elect Letters; 7/2003
T Oka, K Fujita, K Shirakawa, N Takahashi, Y Liu, M Yamashita, H Kawamura, M Hasegawa, H Koh, H
Kagoshima, H Kijima, K Sakuno ; IEEE ISCS; 7/2003
T Sowlati, DMW Leenaerts ; IEEE J SS Circ; 7/2003
JA O'Sullivan, C Delabie, KG McCarthy, A Murphy, PJ Murphy ; IEEE HFPSC; 9/2003
CK Chu, HK Huang, CC Wang, YH Wang, CC Hsu, W Wu, CL Wu, CS Chang ; IEEE ESSCIRC; 9/2003
W Bakalski, A Vasylyev, W Simbuerger, R Thueringer, HD Wohlmuth, AL Scholz, P Weger ; IEEE
BCTM; 9/2003
A Wakejima, K Ota, K Matsunaga, M Kuzuhara ; IEEE TED; 9/2003
V Adivarahan, M Gaevski, WH Sun, H Fatima, A Koudymov, S Saygi, G Simin, J Yang, M Afir Khan, A
Tarakji, MS Shur, R Gaska ; IEEE TED; 9/2003
A Bessemoulin, R Quay, S Ramberger, H Massler, M Schlechtweg ; IEEE J SS Circ; 9/2003
M Spirito, LCN de Vreede, LK Nanver, S Weber, JN Burghartz ; IEEE J SS Circ; 9/2003
R Negra, R Vogt, W Baechtold ; IEEE IMOC; 9/2003
S Hamedi Hagh, CAT Salama ; IEEE CICC; 9/2003
138
[950]
[951]
[952]
[953]
[954]
[955]
[956]
[957]
[958]
[959]
[960]
[961]
[962]
[963]
[964]
[965]
[966]
[967]
[968]
[969]
[970]
[971]
[972]
[973]
[974]
[975]
[976]
[977]
[978]
[979]
[980]
[981]
[982]
[983]
[984]
[985]
[986]
[987]
[988]
[989]
[990]
[991]
[992]
[993]
[994]
[995]
A Adahl, H Zirath ; IEEE EMC; 10/2003
K Seeman, S Ramberger, A Tessmann, R Quay, J Schneider, M Riessle, H Walcher, M Kuri, R Kiefer, M
Schlechtweg ; IEEE EMC; 10/2003
S Bantas, Y Stratakos, N Kanakaris, Y Katsoulis, P Papadopoulos, M Margaras, V Korou, H Peyravi, Y
Koutsoyannopoulos ; IEEE VTC; 10/2003
BP Yan, ES Yang, YF Yang, XQ Wang, CC Hsu; IEEE TED; 10/2003
C Lee, P Saunier, JW Yang, M Asif Khan ; IEEE EDL; 10/2003
Y Okamoto, Y Ando, K Hataya, H Miyamoto, T Nakayama, T Inoue, M Kuzuhara ; IEEE Elect Letters;
10/2003
N Ceylan, JE Mueller, T Pittorino, R Weigel ; IEEE EMC; 10/2003
N Le Gallou, JF Villemazet, B Cogo, JL Cazaux, A Mallet, L Lapierre ; IEEE EMC; 10/2003
M Park, HK Ahn, DM Kang, HG Ji, JK Mun, HC Kim, KI Cho ; IEEE EMC; 10/2003
N Srirattana, A Raghavan, D Heo, PE Allen, J Laskar ; IEEE EMC; 10/2003
JB Johnson, AJ Joseph, D Sheridan, RM Malladi ; IEEE GaAs IC; 10/2003
M Rancanelli, PX Ma, P Kempf; IEEE GaAs IC; 10/2003
S Handa, E Suematsu, H Tanaka, Y motouchi, M Yagura, A Yamada, H Sato ; IEEE GaAs IC; 10/2003
YH Wang, HZ Liu, HK Huang, CC Wang, CH Chang, W Wu, CL Wu, CS Chang ; IEEE EDMO; 10/2003
GH Jessen, RC Fitch, JK Gillespie, GD Via, NA Moser, MJ Yannuzzi, A Crespo, JS Sewell, RW Dettmer,
TJ Jenkins, RF Davis, J Yang, M Asif Khan, SC Binari ; IEEE EDL; 10/2003
H Komizo, Y Arai, T Saito; IEEE MTT-S; 6/1977
JW Lee, LF Eastman, KJ Webb ; IEEE Trans MTT; 10/2003
PM Smith, D Dugas, K Chu, K Nichols, KG Duh, J Fisher, L MtPleasant, D Xu, L Gunter, A Vera, R
Lender, D Meharry ; IEEE GaAs IC; 10/2003
N Saka, M Nakamura, M Shimada, T Kimura, H Motoyama, I Hase ; IEEE GaAs IC; 10/2003
AR Behzad, ZM Shi, SB Anand, L Lin, KA Carter, MS Kappes, TS Lin, T Nguyen, D Yuan, S Wu, YC
Wong, V Fong, A Rofougaran ; IEEE J SS Circ; 12/2003
K Joshin, T Kikkawa, H Hayashi, T Maniwa, S Yokokawa, M Yokoyama, N Adachi, M takikawa ; IEEE
IEDM; 12/2003
M Ferndahl, HO Vickes, H Zirath, I Angelov, F Ingvarson, A Litwin ; IEEE MWWC Letters; 12/2003
X Jiang, AL Martin, A Mortazawi ; IEEE MWWC Letters; 12/2003
HC Chiu, SC Yang, YJ Chan, SH Chen, WS Liu, JI Chyi ; IEEE TED; 1/2004
JW Lee, KJ Webb ; IEEE Trans MTT; 1/2004
B Sahu, GA Rincon-Mora ; IEEE Trans MTT; 1/2004
P Colantonio, F Giannini, E Limiti, V Teppati ; IEEE Trans MTT; 1/2004
W Wang, YP Zhang ; IEEE MWWC Letters; 1/2004
X Jiang, SC Ortiz, A Mortazawi ; IEEE Trans MTT; 1/2004
T Shimizu, Y Nunogawa, T Furuya, S Yamada, I Yoshida, M Hotta; IEEE ISSCC; 1/2004
CM Wang, HT Hsu, HC Shu, YM Hsin ; IEEE EDL; 1/2004
B Toner, R Dharmalinggam, VF Fusco ; IEEE MWAntProp; 1/2004
L Samoska, A Peralta, M Hu, M Micovic, A Schmitz ; IEEE MWWC Letters; 1/2004
TY Yum, Q Xue, CH Chan ; IEEE Trans MTT; 3/2004
A Fukuda, H Okazaki, T Hirota, Y Yamao ; IEEE MWWC Letters; 3/2004
CW Park ; IEEE Sarnoff AWWC; 4/2004
M Ugajin, A Yamagishi, J Kodate, M Harada, T Tsukahara ; IEEE J SS Circ; 4/2004
S Forestier, P Bouysse, R Quere, A Mallet, JM Nebus, L Lapierre ; IEEE Trans MTT; 4/2004
CC Huang, HT Pai, KY Chen ; IEEE Trans MTT; 4/2004
R Behtash, H Tobler, FJ Berlec, V Ziegler, H Leier, RS Balmer, T Martin, M Neuburger, H Schumacher;
IEEE Elect Letters; 4/2004
YH Chee, J Rabaey, AM Niknejad; IEEE ISCAS; 4/2004
P Chen, HR Chang, X Li, B Luo; IEEE ISPSD; 4/2004
A Chini, D Buttari, R Coffie, L Shen, S Heikman, A Chakraborty, S Keller, UK Mishra ; IEEE EDL;
4/2004
MD Hampson, SC Shen, RS Schwindt, RK Price, U Chowdhury, MM Wong, TG Zhu, DW Yoo, RD
Dupuis, M Feng ; IEEE EDL; 4/2004
CM Snowden ; IEEE Proc CDS; 6/2004
UR Pfeiffer, SK Reynolds, BA Floyd ; IEEE MTT-S; 6/2004
139
JX Deng, P Gudem, LE Larson, PM Asbeck ; IEEE MTT-S; 6/2004
K Choi, DJ Allstot, V Krishnamurthy ; IEEE MTT-S; 6/2004
Y Zhang, P Heydari ; IEEE MTT-S; 6/2004
W Bakalski, K Kitlinski, G Doning, B Kapfelsperger, W Oesterreicher, W Auchter, R Weigel, AL Scholz ;
IEEE MTT-S; 6/2004
[1000] JG Fiorenza, J Scholvin, JA del Alamo ; IEEE EDL; 10/2003
[1001] ID Robertson, KKM Cheng, AH Aghvami ; IEEE ICC; 6/2004
[1002] HG Henry, G Augustine, GC DeSalvo, RC Brooks, RR Barron, JD Oliver, AW Morse, BW Veasel, PM
Esker, RC Clarke; IEEE TED; 6/2004
[1003] YS Noh, CS Park; IEEE J SS Circ; 6/2004
[1004] S Piotrowicz, E Chartier, JC Jacquet, D Floriot, JM Coupat, C Framery, P Eudeline, P Auxemery ; IEEE
MTT-S; 6/2004
[1005] YJ Jung, H Jeong, E Song, J Lee, SW Lee, DH Seo, IH Song, SH Jung, JB Park, DK Jeong, SI Chae, WC
Kim; IEEE J SS Circ; 7/2004
[1006] JB Johnson, AJ Joseph, DC Sheridan, RM Maladi, PO Brandt, J Persson, J Andersson, A Bjorneklett, U
petersson, F Abasi, L Tilly ; IEEE J SS Circ; 10/2004
[996]
[997]
[998]
[999]
140