Cell Modulated dc/dc Converter
by
James Raymond Warren III
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2005
© James Raymond Warren III, MMV. All rights reserved.
The author hereby grants to MIT permission to reproduce and
distribute publicly paper and electronic copies of this thesis document
H
in whole or in part.
AUG 14 2006
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August 1, 2005
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Cell Modulated dc/dc Converter
by
James Raymond Warren III
Submitted to the Department of Electrical Engineering and Computer Science
on August 1, 2005, in partial fulfillment of the
requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
Abstract
A very high frequncy converter roughly based on a class E topology is investigated for
replacing a conventional boost converter circuit. The loss mechanisms in class E inverters are characterized, and metrics are developed to aid in device selection for high
frequency converter. A (30 MHz) converter is developed based on a modified class
E inverter, single diode rectifier, and cell modulation control architecture based on
the Fairchild Semiconductor FDN361AN MOSFET identified by the device selection
metrics. In addition to meeting the output specification of 1 W to 2 W, the converter
has the ability to deliver up to 3W over its entire input voltage range of 3.6V to 7.2V.
Converter efficiencies were realized ranging from from 71% to 81%. Finally, converter
transient response to a 2:1 load step did not even exceed the transient ripple of the
converter, approximately 100mV. Higher frequency design allowed for decreasing the
magnitude of passive values, and in turn their corresponding physical size. Smaller
magnitude components reduced the energy storage in the circuit, allowing for the improved transient response. A potential application for this reseach include integration
of the circuit and/or passive components for further minitaurization. Potential applications that could take advantage of the significantly improved transient response
are circuits facing load transients, or applications designed to actively modulate their
supply voltage or power.
Thesis Supervisor: David J. Perreault
Title: Associate Professor
Thesis Supervisor: Timothy C. Neugebauer
Title: Sr. Member of the Technical Staff, C. S. Draper Laboratory
3
4
Acknowledgments
This thesis was prepared at The Charles Stark Draper Laboratory, Inc. under Contract No. CON05000-2, GB Draper Laboratory Fellow Support.
Publication of this thesis does not constitute approval by Draper or the sponsoring
agency of the findings or conclusions contained herein. It is published for the exchange
and stimulation of ideas.
James R. Warren III
I owe nothing more than to my wife Jes, who has been through this process by
side. Thank you for everything.
I would like to thank everyone at MIT that has helped me through this process.
My advisor, Prof. David J. Perreault, deserves accolades for the lengths lie went
to in supporting me. Thank you for your patience and your help. Juan Rivas and
David Jackson stood next in line for my questions when I headed to LEES. Thank
you for sharing your wisdom with me. Group meetings also introduced me to Olivia
Leitermann and Yehui Han who watched my thesis grow. To everyone else in LEES
who stopped by with kind words, my thanks.
I would like to reiterate my thanks to C.S. Draper Laboratory for supporting my
thesis. I also appreciate the broad freedom that my supervisor, Seth Davis, allowed
me in choosing a topic. Timothy Neugebauer, my thesis supervisor, was a great help
through the process. My cube farm/conference room/office mates, James Noonan
and Nick Nestle, helped keep the process light along the way. Best of luck guys.
Finally, Jay Bruso was an outstanding mentor. Thank you for everything.
Finally, I would like to thank my parents for their support throughout my education. You gave given me great tools to head into the world, and I will always
appreciate everything you do for me.
5
Assignment
Draper Laboratory Report Number T-1537
In consideration for the research opportunity and permission to prepare my thsis
by and at The Charles Stark Draper Research Laboratory, Inc., I hereby assign my
copyright of the thesis to The Charles Stark Draper Laboratory, Inc., Cambridge,
Massachusetts.
Date
es R. Warren III
6
Contents
1
2
Introduction
1.1
Research and Background
1.2
Thesis Objectives and Contributions
1.3
Organization of Thesis
. . . . . . . . . . . . . . . . . . . . . . . .
16
. . . . . . . . . . . . . . . . . .
18
. . . . . . . . . . . . . . . . . . . . . . . . . .
19
21
Losses in Class E Inverters
2.1
2.2
2.3
2.4
3
15
. . . . . . . . . . . . . . . . . . . . . . . .
21
2.1.1
Simplifying Assumptions . . . . . . . . . . . . . . . . . . . . .
21
2.1.2
QL
22
2.1.3
Output Power, P . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.1.4
Conduction Loss
. . . . . . . . . . . . . . . . . . . . . . . . .
23
2.1.5
Resonant Tank
. . . . . . . . . . . . . . . . . . . . . . . . . .
25
. . . . . . . . . . . . . . .
26
. . . . . . . . . . . . . . . . . . . .
26
. . . . . . . . . . . .
26
Gating Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
Class E Design Equations
. . . . .
.. . . . .. . . . . . . . . . . . . . . . . . . . . .
Insights from Simplified Design Equations
2.2.1
Output capacitance limits
2.2.2
Simplified Expression for Output Power
2.3.1
Traditional "Hard Switched" Gate Drive Losses
. . . . . . . .
27
2.3.2
Resonant Gate Drive . . . . . . . . . . . . . . . . . . . . . . .
28
Total Device Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
33
Switching Device Selection
.. .
3.1
Maximum RON . . . . .
3.2
Maximum Gating Loss . . . . . . . . . . . . . . . . . . . . . . . . . .
.....................
7
34
35
4
5
6
3.3
Device Characterization
3.4
Finalized Device Selection
35
. . . . . . . . . . . . . . . . . . . . . . . .
38
Class E Inverter Design
39
4.1
Loaded Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
4.2
Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
4.3
Resonant Tank Parameters . . . . . . . . . . . . . . . . . . . . . . . .
40
4.4
PSPICE Simulation of Class E Inverter . . . . . . . . . . . . . . . . .
41
From Inverter to Converter
43
5.1
Tank Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
5.2
Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
5.3
Prototype Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
Resonant Gate Drive
51
6.1
Multi-Stage Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . .
51
6.1.1
O scillator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
6.1.2
CMOS Inverter Drive Stage . . . . . . . . . . . . . . . . . . .
53
Resonant Gate Drive Circuit . . . . . . . . . . . . . . . . . . . . . . .
54
6.2.1
Basic Resonant Gate Drive Circuit
54
6.2.2
Improved Resonant Gate Drive Circuit
. . . . . . . . . . . . .
56
6.2.3
Effective Gate Capacitance . . . . . . . . . . . . . . . . . . . .
57
6.2.4
Effects of Reverse Capacitance . . . . . . . . . . . . . . . . . .
58
6.2
7
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .
Cell Modulation Control Architecture
59
7.1
General Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
7.2
Feedback Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
7.3
Enable/Disable Circuit for the RF Converter . . . . . . . . . . . . . .
61
7.4
Hysteresis Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
7.5
Cell Modulation Frequency . . . . . . . . . . . . . . . . . . . . . . . .
62
8
8
9
Experimental Results
65
8.1
Open Loop Converter Efficiency . . . . . . . . . . . . . . . . . . . . .
66
8.2
Cell Modulated Converter Efficiency
. . . . . . . . . . . . . . . . . .
66
8.3
Cell Modulation Operation . . . . . . . . . . . . . . . . . . . . . . . .
67
8.4
Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . .
68
8.5
Load Step Response
69
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusions
79
9.1
Research Developments . . . . . . . . . . . . . . . . . . . . . . . . . .
79
9.2
Converter Development . . . . . . . . . . . . . . . . . . . . . . . . . .
80
9.3
Potential Future Work . . . . . . . . . . . . . . . . . . . . . . . . . .
80
A PSPICE Code
A.1
Class E Inverter Simulation
A.2
Converter Cell Simulation
A.3
81
. . . . . . . . . . . . . . . . . . . . . . .
81
. . . . . . . . . . . . . . . . . . . . . . . .
82
Resonant Gate Drive Simulation . . . . . . . . . . . . . . . . . . . . .
84
A.3.1
Input to Gate AC Simulation
. . . . . . . . . . . . . . . . . .
84
A.3.2
Drain to Gate AC Simulation
. . . . . . . . . . . . . . . . . .
86
89
B Circuit Schematic
B.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
B.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
C PCB Layouts
93
C.1 Component Side Copper . . . . . . . . . . . . . . . . . . . . . . . . .
93
Silk Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
C.3 Solder Side Copper . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
C .4 D rills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
C .2
9
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10
List of Figures
2-1
Class E Inverter Topology [1].
. . . . . . . . . . . . . . . . . . . . . .
21
2-2
Totem Pole Gate Drive Circuit. . . . . . . . . . . . . . . . . . . . . .
27
2-3
Resonant Gate Drive Circuit . . . . . . . . . . . . . . . . . . . . . . .
28
2-4
Loss Mechanisms in FDN361AN vs. Frequency.
. . . . . . . . . . . .
30
2-5
Loss Mechanisms in FDN361AN vs. Pt
. . . . . . . . . . . . . . . .
31
3-1
MOSFET Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3-2
Normalized Device Losses vs. Frequency
. . . . . . . . . . . . . . . .
37
3-3
Loss Mechanisms in FDN361AN . . . . . . . . . . . . . . . . . . . . .
38
4-1
Class E Inverter Circuit for PSPICE Simulation . . . . . . . . . . . .
41
4-2
Class E Inverter Waveforms from PSPICE Simulation . . . . . . . . .
42
5-1
Tank Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
5-2
Converter Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
5-3
Converter Simulation Waveforms
. . . . . . . . . . . . . . . . . . . .
48
5-4
Unregulated Cell Waveforms . . . . . . . . . . . . . . . . . . . . . . .
49
5-5
Prototype cell power and drain efficiency (excluding gating loss power)
50
6-1
Multistage Resonant Gate Drive Circuit
. . . . . . . . . . . . . . . .
52
6-2
Relaxation Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . .
52
6-3
CMOS Inverter Structure
53
6-4
Basic Resonant Gate Drive Circuit
6-5
Improved Resonant Gate Drive Circuit
. . . . . . . . . . . . . . . . . . . . . . . .
11
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . .
55
57
7-1
Cell Modulation Architecture Block Diagram . . . . . . . . . . . . . .
60
7-2
Cell Modulation Control Schematic . . . . . . . . . . . . . . . . . . .
60
8-1
Prototype Converter Cell . . . . . . . . . . . . . . . . . . . . . . . . .
65
8-2
Converter Efficiency
68
8-3
Cell Modulation Behavior
8-4
Cell transient behavior, V,n = 5.0V and Rload = 24 Q
. . . . . . . . .
70
8-5
Output Ripple of LM7231Y Demonstration Board . . . . . . . . . . .
71
8-6
Converter Output Voltage Ripple . . . . . . . . . . . . . . . . . . . .
72
8-7
Converter Output Voltage Ripple, Meaurement Bandwidth = 20 MHz
73
8-8
Load Step Response of LM2731Y Demonstration Board . . . . . . . .
74
8-9
Load Step Response of LM2731Y Demonstration Board . . . . . . . .
75
. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
8-10 Load Step Response of Cell Modulated Converter
. . . . . . . . . . .
8-11 Ripple Resonse to Load of Cell Modulated Converter
69
76
. . . . . . . . .
77
B-i
Converter Schematic
. . . . . . . . . . . . . . . . . . . . . . . . . . .
90
C-1
Solder Side Copper, 2X Magnification . . . . . . . . . . . . . . . . . .
93
C-2
Component Side Silk Screen, 2X Magnification . . . . . . . . . . . . .
94
C-3 Solder Side Copper, 2X Magnification . . . . . . . . . . . . . . . . . .
95
C-4 PCB Drill File, 2X Magnification
95
12
. . . . . . . . . . . . . . . . . . . .
List of Tables
2.1
Class E Inverter Parameters . . . . . . . . . . . . . . . . . . . . . .
22
3.1
Characterized Devices
36
5.1
Tank Values from Transformation at
5.2
Unregulated dc-dc Cell Efficiency (Gating loss power not included)
47
8.1
Open Loop Converter Power and Efficiency . . . . . . . . . . . . . .
66
8.2
Prototype converter efficiency
. . . . . . . . . . . . . . . . . . . . .
67
8.3
Cell Modulation Frequencies . . . . . . . . . . . . . . . . . . . . . .
68
B.1
Bill of Materials for Converter . . . . . . . . . . . . . . . . . . . . .
91
. . . . . . . . . . . . . . . . . . . . . . . . .
13
f, =
30 MHz
. . . . . . . . .
45
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14
Chapter 1
Introduction
DC/DC power converter design encompasses tradeoffs between power density, defined as converter power relative to converter size, and efficiency. The problem of
power density translates to miniaturization when applied to lower power (< 10 W)
range switching converters.
The sizes of passive components in a low power reg-
ulator dominate over the size of the switching devices themselves.
Moreover, the
numberical values and stored energy in these passive components directly determine
achievable transient response; lower valued passive components lend themselves to
faser transient response. The switching frequency is the key to sizing the passives;
increasing frequency can lower the size of the devices and improve achievable transient performance. This is not without the challenge of mitigating switching, gating,
and magnetic core losses, which scale with frequency, and reduce overall converter
efficiency.
The primary application for this research is to reduce the size and improve the
transient response of a power supply currently implemented as a boost converter based
on a National Semiconductor LM2731. The application is to boost and regulate a
battery voltage supply over the discharge cycle of the cells. While the chip is efficient
and small, operating at a switching frequency of 1.6 MHz or 0.6MHz depending on the
version, it requires relatively large exterior passive elements, including the input and
output capacitors and the boost inductor. Moreover, its response speed and transient
output voltage variations (e.g. in response to load transients) is limited by the energy
15
stored in the passive components (especially the inductor) and its switching frequency.
The design objective is to increase the switching frequency significantly to the
vhf range (30-300MHz) in order to reduce the total size of the passive components
and to provide better dynamic performance (e.g. smaller and shorter output voltage
transients during load changes).
A cellular control architecture is investigated to
apply an optimized rf cell to the necessary load range [2, 3, 4, 5, 6, 1, 7, 8, 9, 10, 11,
12, 13, 14, 15].
1.1
Research and Background
A traditional direct converter is designed to meet wide load ranges by varying its
duty cycle. The load range, which can easily exceed an order of magnitude, limits
the extent to which the converter topology can be optimized. A recent approach is to
develop a control structure around optimized radio-frequency converter cells. While
an individual cell is designed for a narrow load range, the control structure adapts
to wider ranges by modulating the cell on and off over time, and/or by changing the
number of cells used to supply the load [2].
In this strategy, regulation of the output is provided by modulating the cells in
the time domain, with an output filter to smooth the resulting power pulsations and
provide the desired average output power. The benefit is that the sizes of the converter
magnetics are determined by the switching frequency, which can be extremely high
without sacrificing efficiency. There is thus the opportunity to reduce the size of the
largest passive component in the system. The output filter (e.g., a capacitor) still
needs to provide filtering at the lower modulation frequency, but often times it is sized
by other system requirements as well. Moreover, the high switching frequency and
low stored energy in the magnetics can yield exceptionally fast transient performance.
For low power converters, the cell modulated cellular architecture can be reduced
down to a single cell using on-off, or bang-bang, control. The general approach is that
an output filter is used to store and filter the energy which is regulated by modulating
an optimized cell with a varying on-off duty cycle to meet the load requirement.
16
While the output requirements of the entire architecture will size the output filter,
the intermediate passives can be sized to the optimized cell.
In this strategy, the power conversion is accomplished using a resonant cell operating at very high switching frequencies. As the switching frequency is increased,
the power losses associated with each switch transition accumulate. This has limited traditional direct converter switching frequencies in order to preserve efficiencies.
Switching loss occurs when a switch transitions from a high current state (on) to a
high voltage state (off). Neither the current or voltage changes instantaneously; the
switching loss comes from their product during the switching transition. In order to
increase switching frequency without sacrificing efficiency, a method of Zero Voltage
Switching (ZVS) should be implemented. By ensuring that the voltage across a switch
remains at or near zero during its switching transition, the power dissipation can be
minimized [3, 4].
High frequency analog design is an area with established design principles. As
switching frequencies rise, these RF principles are very applicable to power electronics
design. Moving towards a more sinusoidal gating signal and resonating charge on and
off the gate, as opposed to a square wave drive, lowers the gating power loss that can
limit high frequency operation [3, 2, 5, 6]. A resonant converter is a solution that takes
advantage of these RF design principles. Multi-stage self resonant amplifier circuits
that do not require a drive oscillator can be effectively employed in this context.
The implementation pursued in this thesis is the use of a converter based on a
resonant class E inverter [1, 7]. The class E inverter circuit is combined with a single
diode rectifier to create a full dc/dc converter with minimal part count and size. A
cell modulation architecture in the form of bang bang control is used to regulate the
output voltage.
The benefit of a cell-modulated control architecture is that an optimized conversion cell can allow for switching frequencies that are orders of magnitude higher than
a traditional direct converter. The tradeoff is in design complexity over a direct converter in both the topology of the converter cell and the architecture of the control
system. The benefits, however, are that resonant techniques can be applied to re17
duce switching losses, leading to higher frequencies, smaller passive components, and
improved converter transient response.
1.2
Thesis Objectives and Contributions
The objective of this thesis is to design a dc/dc converter that meets the following
specifications.
" Input voltage range: 3.6 to 7.2 volts
" Output power range: 1W - 2W
* Output current range: 150mA to 250mA
* Output voltage: 7V
The current solution of a National Semiconductor LM2731 Boost Converter operating at 0.6 MHz will serve as a point of reference for the contributions of this
thesis. The ojective is to decrease passive sizes and improve transient performance
by pursuing a topology that allows for a high frequency cell modulated converter.
A loss analysis of class E inverters is developed using design equations from [1].
The loss analysis encompasses both device conduction loss as well as gating losses
associated with driving the transistor. This loss analysis provides the basis of metrics
for device selection for high frequency power converters.
A device search is conducted to identify candidate devices for a low power, high
frequency resonant converter. Devices from 3 manufacturers were compared both on
the basis of published specifications as well as data from experimental characterization. This information allowed for a device to be selected for a converter design.
Based on the selected device, a converter topology is developed based on a modified
class E inverter combined with a single diode rectifier. PSPICE simulation is used
to analyze and develop the circuit. A prototype converter is implemented to confirm
the desired efficiency due to conduction loss in the power stage.
18
A multi-stage resonant gate drive circuit is developed to provide a sinusoidal drive
signal with dc offset at the gate of the selected device. The circuit includes a second
LC tank to reduce device stress on the switching devices providing the gate drive.
Finally, the circuit addresses the need to mitigate self oscillating behavior due to Crs
providing feedback from the drain to gate.
A cell modulation control architecture is implemented to control the high frequency converter cell. It also provides voltage regulation at the output. The control
architecture allows for near instantaneous transient response time.
Finally, the full converter cell is prototyped and characterized. Initial open loop
efficiency is measured to asses the maximum power capacity of the device at the
specified output voltage. Then, the closed loop system is characterized within the
specifications for efficiency, cell modulation characteristics, and transient response to
load steps.
1.3
Organization of Thesis
Chapters 2 and 3 develop the loss analysis of class E inverters and an approach
for evaluating candidate switching devices for high frequency resonant converters.
Chapters 4 and 5 develop the power stage of a dc/dc converter based on a class E
inverter.
Once the high power stage is designed and protoyped, Chapter 6 develops a multistage gate drive circuit. It is followed by a development of the cell modulation control
architecture in Chapter 7.
Experimental results from the full dc/dc converter comprise Chapter 8. Finally,
Chapter 9 summarizes the contributions of this thesis and expounds on directions the
work could be extended.
19
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20
Chapter 2
Losses in Class E Inverters
2.1
Class E Design Equations
In order to develop a tractable design for a class E inverter, design equations from
[1] are introduced. The classic class E inverter topology is presented in Figure 2-1.
Design equations have been documented for this topology to set up class E operation
[1]. Table 2.1 contains an explanation of the parameters for the class E inverter.
Li
VC
L 2C2
02
1
+
R
CCT
Figure 2-1: Class E Inverter Topology [1].
2.1.1
Simplifying Assumptions
Some simplifications clarify the design equations without sacrificing significant control of the parameters. The following assumptions are that parasitic resistances are
negligible, the choke inductance is large, QL is large, and the fall time of the switch
current at turn off tf is signinficantly shorter than the switching period. These results
21
Parameter
f
Vcc
VI
L,
L2
C1
C2
R
RON
Rioad
Description
Switching frequency
Supply voltage
Switch voltage drop
Choke inductor
Resonant tank inductor
Output capacitance across switch
Resonant tank capacitor
Load resistance attached to tank
Switch on-state resistance
Effective load resistance seen by converter
Table 2.1: Class E Inverter Parameters
of these assumptions are
ESRL2 = ESRC2 = ESRc
=
00
(2.2)
=
00
(2.3)
<< T
(2.4)
QL
tf
2.1.2
(2.1)
=0
QL
QL is the Q of the resonant tank in the class E inverter. The L subscript stands for
"loaded
Q".
QL =
27rf L 2
R
(2.5)
It is a free choice variable subject to the constraint
QL > 1.7879
(2.6)
Large QL coincides with a tank with a high purity sinusoidal output. A low
QL
is desirable for power converter designs utilizing the class E topology. A lower QL
reduces the magnitude of the energy resonated in the tank, which in turn reduces
conduction losses associated with the parasitic resistances of L 2 and C2 [2].
22
2.1.3
Output Power, P
Design equations are developed based on a least squares fit to tabulated values for
design parameters in terms of QL and supply voltage.
P =(c (VCC _ Vo
o
2
2
f(QL) is the fit equation.
(2.7)
f(Q L)
For a second order polynomial fit, the fit equation is [11
f(QL) =1.001245-
0.451759
0.402444
QL2(28
QL
(2.8)
QL
Therefore output power is
(CC _V)Vo)--2~~0415
2
2
R
_
+ 1.
1.001245 -0.451759
QL
-
.044
L5
(2.9)
The switching devices examined for this design were all MOSFETs, so Vo = 0.
Under the simplifying assumption of
QL = oo, all of the higher order terms of f(QL)
drop out. The simplified equation for output power is then
]Q
1
_(Vc)[
0.5775
(V)2
2
(2.10)
CC)2
R
Rearranging Equation 2.10 provides a calculation of the necessary load resistance
for the inverter in terms of desired output power and supply voltage.
R
2.1.4
=
0.5775. (V0C)
P
2
(2.11)
Conduction Loss
Drain efficiency, 'rD, is defined as the output power divided by the dc input power,
neglecting gate drive power losses. It is often used as a measure of performance in rf
power amplifiers. Existing expressions for calculating drain loss in [1] will be used to
23
compute conduction loss in the inverter switch.
In order to calculate the drain efficiency, two new parameters are introduced.
RLOAD
is an effective resistance term introduced in [1] for calculating drain efficiency.
RLOAD = R - ESRL2 - ESRC2 - 1.365 - RON - 0.2116. ESRc
(2.12)
A is a function of the fall time compared to the switching period, and is defined
as
A = (I +
0.82)
tI)
Using these new parameters, the drain efficiency
71 D =
(2.13)
TID
is calculated as
(27A
A) 2
RLOAD
RLOAD
[1]:
+ ESRL2 + ESRc 2 + 1.365. RON + 0.2116. ESRc1
12
12
-0.01
(2.14)
Combining Equation 2.14 with Equation 2.12 reduces to
(2irA) 2
12
RLOAD
R
7D
-
0.01
(2.15)
The constant 0.01 is designed to incorporate conduction losses associated with the
RF choke, L, [1]. In order to focus on losses associated directly with the switching
device, this loss will be dropped. Finally, by applying the simplifying assumptions of
Equations 2.1-2.4, the parameters used to calculate iD reduce to
RLOAD
A
=
R-1.365-RON
= t
A=
= 0
(2.16)
(2.17)
Combining these approximations leaves the drain efficiency assuming only conduction loss in the switch
RLOAD
D
R + 1.365- RON
R - 1.365- RON
R
24
=
1 - 1.365- RON
(2.18)
R
Combining Eqns. 2.11 and 2.18 gives
'D
1-
=
P
1.365.
O.5775 -(Vcc)
PRON
2
RON
O
1 - 2.363 - (VO)
=
(2.19)
(VCC)2
This is equivalent to saying that device conduction loss normalized to dc input
power is
P
Normalized ConductionLoss = 2.363 RON
(VCC) 2
(2.20)
For given system parameters of input voltage and output power, normalized conduction loss is independent of frequency.
2.1.5
Resonant Tank
Design equations are developed for the resonant tank parameters C1 and C 2 using
the same fit technique described in Section 2.1.3 [1]. The output capacitance across
the switch is
1
Cf
27rf R (i
)
) 2
_+
0.99866+
0.91424
1.03175)
QL
Q2
+
0.6
(27rf)2 L1
Incorporating Equation 2.11 into Equation 2.21 and simplifying it with QL
and L, = oc gives
1
27rf R
(.99866+
QL
+1)
1
27rf R
=
0.02918-
.02918
.5775
(0.99866)
+1)
1
fR
P
f(VC)
0.91424
2
25
1.03175)
0.6
(27rf) 2 Li
(2.21)
= o
= 0.05053 -f
c
(2.22)
f (VCC)2
The equation for C 2 does not easily simplify under these same assumptions. The
full equation should be used once the free choice variable QL has been chosen as
follows
C2=
20rf R
1(100121
QL~0.104823
+
1.01
L -1.
7 79
8
(27(2)22
0
(2.23)
Finally, the value for L 2 will follow from the choice for QL- Under the simplifying
assumption of
QL
= oc, L 2 does not have a significant value. Its calculation will also
be reserved until after design decision for a practical QL is chosen, and calculated as
L2 =
2.2
2.2.1
(2.24)
27rf
Insights from Simplified Design Equations
Output capacitance limits
Equation 2.22 offers an insight into the applicability of a given switching device to
a class E inverter.
It helps place an upper bound on what an acceptable output
capacitance is for a given application of power and frequency. If the device output
capacitance is lower than needed to achieve a desired power at a specified frequency,
external capacitance can be added to the specification.
C1 < 0.05053.
P
(2.25)
f (VoC)2
2.2.2
Simplified Expression for Output Power
Rearranging Eqn 2.22 also gives an insightful equation for output power. It breaks
down the class E capacity as a function of frequency, device capacitance, and input
power.
P
=
19.88.
fC(Vc)
26
2
(2.26)
This is a valuable equation because it immediately qualifies for a given frequency
and input voltage, what power a device can deliver. It is useful for a first approximation for design and for evaluating switching devices.
2.3
2.3.1
Gating Losses
Traditional "Hard Switched" Gate Drive Losses
Traditional "hard switched" gate drive circuits dissipate all of the energy stored on
the gate capacitor on each switching cycle. A traditional totem pole drive circuit
is illustrated in Figure 2-2. In each switching cycle, the circuit sources current to
charge the input capacitance of the switching device through Si. The MOSFET is
then turned off by sinking all of the charge on the gate capacitor to ground through
S 2 . This results in a total switching loss of [8]:
Pswitch =
f
Charging
Pswitch =
CGSV2
[ICGSV2+
CGSV
2
Discharging_
(2.27)
f
Vdd
gs
S
C
Figure 2-2: Totem Pole Gate Drive Circuit.
27
2.3.2
Resonant Gate Drive
A technique to reduce the dominance of traditional switching losses at high frequencies
is to employ a resonant gate drive circuit. In one possible implementation, an inductor
is added in series with the input capacitance, creating an LC tank, as shown in Figure
2-3. This allows charge to be stored in the tank and rung on and off of the input
capacitor. The tank is recharged using a push-pull output stage similar to the hard
switching design. However, the totem pole drives the equivalent of a second order LC
filter, instead of charging and discharging the capacitor on every cycle. The resultant
loss mechanism is dissipation in any ESR associated with the LC tank, including the
internal gate resistance.
V dd
L Ri
L3
|
Cgs
Figure 2-3: Resonant Gate Drive Circuit
The resultant voltage at the gate is the fundamental of the switch frequency as
filtered by the LC network, ideally a pure sinusoidal drive with a dc offset. Assuming
a sinusoidal gate drive allows the calculation of the loss associated with driving the
gate capacitance of a MOSFET. The approach is to calculate the current onto the
gate, and then calculate the loss associated with passing that current through Rg, the
ESR associated with C,.
(2.28)
Zc13
0tjw
Using Ohm's law and defining V as the peak ac component of the gate voltage,
28
the magnitude of the gate current may be calculated as:
|i| = 27rfCgsV sinwt
(2.29)
and the mean-square gate current is:
i2
(27TfCgsV)
2
2
= 27r 2 f 2 C2sV 2
2
RMS
(2.30)
g
The power dissipated in Rg is then
P
=
iRMSRg
=
27r2f 2 C2sRgV 2
(2.31)
Using Equation 2.10, the gating loss normalized to inverter power is:
Normalized Gating Loss =
2.4
27r2 f 2 C2
Ps
P
R V2
(2.32)
9
Total Device Losses
Eqns 2.20 and 2.32 can be summed to express the total normalized device loss in
terms of device parameters RON, Cgs, and Rg and as a function of frequency f:
P
Normalized Device Loss = 2.363. (V)
2
RON+
Conduction Loss
27r2
2
C2 R V 2
gs
g
(233)
Gating Loss
Figure 2-4 illustrates how the loss mechanisms in a single device vary versus frequency. The data for the plot comes from the device ultimately selected for the
converter design. At low frequencies, conduction loss is the dominant factor. However, as frequency increases, gating loss quickly becomes the limiting factor.
There is also an optimal output power for a given device at a fixed frequency
and input voltage. This is because the normalized conduction loss factor increases
linearly with output power for a fixed input voltage, while normalized gating loss
29
Loss Mechanisms in FDN361 AN, V_{cc}=3.6V, P=2W, and V_{g,max}=7V
0.2
-
-
- Conduction Loss
Loss
0.18-1 |Conduction + Gating
0.160.140.120
-j
0.1
-
E
0
Z
0.08 -
0.060.040.020
1
'.
,
10
Frequency (MHz)
100
Figure 2-4: Loss Mechanisms in FDN361AN vs. Frequency
factor decreases. The power consumed via gating loss is constant for a set frequency
and peak drive voltage, so as power output increases, the gating loss factor decreases.
Fig 2-5 illustrates this concept.
The output power variation is created by assuming that an arbitrary amount
of additional capacitance can be added in parallel with a device's Cds.
A device's
inherent Cd, will set the lower limit for how low the power can be chosen in Fig. 2-5.
30
Device Loss Mechanisms in FDN361 AN, V_{cc=3.6V, f=30MHz, and V_{g,max}=7V
I
I
I
II
Conduction Loss
- - - Gating Loss
.... Total Loss
0.25 F
0.21-
-.
0.15
z0
-
.
0.1
0.05F
0'
0
0.5
1
1.5
2
P_{out} (W)
2.5
3
Figure 2-5: Loss Mechanisms in FDN361AN vs. P,
31
3.5
4
THIS PAGE INTENTIONALLY LEFT BLANK
32
Chapter 3
Switching Device Selection
This chapter considers inverter device selection for the power converter.
The loss
models of Chapter 2 are used to make quantitative decisions regarding device seection
and converter switching frequency. The objective was to find commercially available
MOSFETs that could be employed in an unconventional manner at higher frequencies.
In order to develop a road map for the device search, the information commonly
available for devices was considered.
Equation 2.33 for device loss normalized to
input power is restated here for reference
Normalized Device Loss = 2.363
P
2 RON+
27r 2f 2C28 RgV2
-
(VCC)
P
ConductionLoss
Gating Loss
(3.1)
Four parameters primarily define the viability of a MOSFET for a high frequency
switching application. RON,
Cgs, Cds,
and R. are the parameters of interest. With
a fixed input voltage and output power requirement, RON dictates the conduction
loss in a device. Coss will next influence the switching frequency as determined by
Equation 2.10; with that, it will affect the size of the passive elements. Coss can also
serve as an indicator as to whether the device is oversized for the application. Finally,
the gating losses in a resonant drive circuit are determined by Cgs and Rg.
Unfortunately, of the four parameters, only three of them are commonly disclosed
on datasheets. Rg is the ESR associated with the gate terminal and a parasitic that
is not usually included. This is understandable, considering the difference in loss
33
mechanisms between the traditional drive of Section 2.3.1 and the resonant drive
structure of Section 2.3.2. Losses in traditional gate drives depend only on Cg, and
peak drive voltage V; they are independent of the parasitic gate resistance R., so it
is often left out of datasheets. Candidate devices must be selected without knowing
R9 and then tested to evaluate R. and determine switching performance.
3.1
Maximum RON
An initial polling of available devices was conducted.
The selection criteria were
looking for an RON that would allow for at most 5% conduction loss.
Recalling
Equation 2.20, the maximum RON must be evaluated at Vin,min and Pout,max for a
chosen normalized conduction loss Pc:
RON
0.423 (Vinmin ) 2 PC
(3.2)
Pout,max
Calculating this for Vcc,min = 3.6V and Pout,max = 2W, with an allowed loss
Pc ~ 5%, gave the first selection criteria of
RON
< 0.15Q
(3.3)
Any devices that exceeded this specification were disregarded. RON was initially
considered at the typical operating point for a rough search. It was then refined by
applying the temperature coefficient effect, which results in a larger RON as temperature increases.
For the devices that met the RON requirement of Equation 3.3, two metrics were
developed. One was the normalized conduction loss at a fixed frequency and output
power. The other was the maximum frequency the device could be operated at with
a conduction loss less than or equal to 5%. For this metric, the output power was
assumed to be set by the device's output capacitance and operating frequency. In the
case where the resultant frequency and output capacitance delivered power beyond
the output specificiation, it was assumed that cell modulation could be employed
34
to regulate the converter. The final requirement for selection was the availability of
devices for characterization.
3.2
Maximum Gating Loss
Within the available devices meeting the conduction loss requirement, the second
focus was to identify devices with the potential for low gating losses. Unfortunately,
the data sheets often do not contain the necessary information about device parasitics
such as R.. Reliable estimates can not be calculated solely from the data sheets as a
result.
While gating loss varies linearly with Rg, it has a quadratic dependence on Cg,.
This provides a guideline to search for devices with a low to moderate input capacitance. This decision was based on the assumption that gate resistance is approximately constant from device to device. With this assumption, the top two devices
in each product line of three different manufacturers were selected for measurement.
Package size was limited to requiring a surface mount package. Three manufacturers
were identified for the candidate devices. The devices acquired for characterization
are contained in Table 3.1.
The viable devices were acquired and characterized in order to effectively compare
the potential losses of each device. For the purposes of the loss calculations, Cg, and
R9 were determined experimentally while RON and C,,,
operating point, typical V,
(evaluated at the quoted
~ 20 V) were derived from the maximums on the data
sheets.
3.3
Device Characterization
The capacitances of the MOSFET structure are significant circuit elements in the
class E inverter topology. The parameters of interest are depicted in Figure 3-1. The
datasheet capacitance measurements are related to the model capacitances by
35
Manufacturer
Fairchild
ST
International
Rectifier
Part Number
FDN327N
FDN361AN
FDG311N
FDS4488
NDS331N
NDS8425
STS5DNF20V
STS7C4F30L
STS4DNFS30L
STD17NF03L
IRLML2502
IRLMS1902
IRLMS2002
IRF1902
IRF7601
Ciss (pF) R9 ()
479
3.5
233
1.2
315
14.8
1095
1.0
251
3.3
1249
2.7
569
4.4
1250
5.0
408
5.4
376
3.9
290
5.0
359
6.2
1179
4.2
383
0.8
1149
1.2
Table 3.1: Characterized Devices
D
Cgd
GR
GW
_
I
Cds
gs
S
Figure 3-1: MOSFET Capacitances
Ciss = Cgs + Cgd
(3.4)
Coss = Cds + Cgd
(3.5)
An HP 4395A in impedance analyzer mode was used to measure the input capacitance and its parasitic resistance. This device drives the device under test (DUT) with
a sweep of input input frequency, measuring magnitude and phase of the response as
a function of frequency. It then can extrapolate an individual measurement, such as
36
capacitance (based on the reactive component) or the series resistance (based on the
real component).
Measurements were performed between the gate and source of the device, with the
drain floating. As C,, is typically small compared to Cd,, their series combination
is approximately the same as if Cd, were shorted. An equivalent series RLC circuit
model was used to extract the parameters for gate resistance and any lead inductance.
Figure 3-2 contains loss data as computed by Equation 3.1 for four representative
devices. The best performing vertical devices from 3 manufacturers (ST, Fairchild
Semiconductor, and International Rectifier) are compared with a lateral device from
MACOM used for rf power amplifiers. The MACOM part is a significantly larger area
device and has a far larger package than the minitiaure packages focused on in the
device search. Moreover, this lateral device has special gate drive requirements (see
[9], [5]), making it impractical for use here. However, it helps illustrate how lower
gating loss allows for high frequency operation.
Device Losses, Vjcc}=3.6V, P=2W, and Vjg,max}=7V
0.2
MACOM LDMOS
0.18 --
--
-FDN361AN
... IRF1902
STD17NF03L
0.16 0.14S0.12-//
0.1
--
Z 0.08 0.060
0.04 -~
0.02
~
....
0
0
Frequency (MHz)
Figure 3-2: Normalized Device Losses vs. Frequency
37
100
Loss Mechanisms in FDN361 AN, \_{cc}=3.6V, P=2W, and V_.{g,max}=7V
0.2
-
0.18
-
-
- Conduction Loss
Conduction + Gating Loss
0.160.140.120.1 0
z 0.08 0.060.040.020
10
Frequency (MHz)
1
100
Figure 3-3: Loss Mechanisms in FDN361AN
3.4
Finalized Device Selection
Of the best performing miniature devices in Figure 3-2, the most efficient device at
very high frequencies was the Fairchild FDN361AN. While it has a higher conduction
loss than the STD17NF03L, it has a combination of acceptable input capacitance
and low gate resistance that allow for more efficient operation at higher switching
frequencies. It will be used as the primary switching device for the development of
the converter cell.
Figure 3-3 contains a closer look at the potential operating range of the FDN361AN.
Using this information, and a target device efficiency of 90%, the switching frequency
was selected to be
=
30 MHz
(3.6)
With a switching device and operating frequency determined, the development of
the converter cell could continue.
38
Chapter 4
Class E Inverter Design
This chapter addresses a first pass design of the inverter portion of the dc-dc converter.
The loss calculations from Chapter 2 and the design equations from [1] were used along
with the selected device of Chapter 3 to develop the following design. This inverter
design is used as the initial basis for a full converter design, as described in the next
chapter.
4.1
Loaded
Q
The simplifying assumptions of Equations 2.1-2.4 are too simple for a valid design.
Specifically, assuming QL = o0 is insufficient for calculating the tank values L 2 and
C 2 as denoted in Section 2.1.5. The design requirement for the equations from [1] is
QL
> 1.7879. Based on the discussion in Section 2.1.2 and [2], a low value of
QL is
desirable. The final design decision was to begin with
QL = 5
to form a first pass design.
39
(4.1)
4.2
Load Resistance
Using the choice of QL from Equation 4.1, the load resistance R can be calculated.
R is the load resistance that will deliver the maximum required power, 2.2 Watts
allowing for losses, at the minimum input voltage, 3.6 V. It is computed by rewriting
Equation 2.7 as
R
=
(VCC - V)2-2~
2
=3.6
(0.576801)
2
2
-f(QL)
1.001245 - 0.451759
2.2
= 3.04 Q
-
0.402444
J
QL
(4.2)
Resonant Tank Parameters
4.3
The resonant tank design equations of [1], previously enumerated in Section 2.1.5 as
Equations 2.21, 2.23, and 2.24 are restated here.
1
27rfR (2 +
C2
=
L2
=
27rf R
099866
0.91424
I
1)
QL
1
QL - 0.-104823
1.00121 +
1.03175
9
1.0168
QL - 1.7879
0.6
(27rf) 2 L
(27rf)2L,
(
(4.4)
QLR
27f(4.5)
One simplification that will be carred over from Section 2.1.5 is the assumption
that L= 00. The result of this is to disregard the second added term in the equations
for C1 and C 2 . Using these equations and the values for QL and R from above results
in the calculated values
Ci,calc
=
365 pF
(4.6)
C2,calc
=
470 pF
(4.7)
L 2 ,caic
=
81 nH
(4.8)
40
Noting that the output capacitance of the selected device (FDN361AN) is approximately 50 pF, and approximating the calculated values to standard values results in
the following tank values
4.4
C1
365 pF - 50 pF ~ 300 pF
C2
470 pF
(4.10)
L2
82 nH
(4.11)
(4.9)
PSPICE Simulation of Class E Inverter
Using the dsign values of Equations 4.2 and 4.9-4.11, a PSPICE simulation was designed to test the class E inverter, included in Appendix A.1.
The model used an
ideal switch in place of the FDN361AN, but its output capacitance was included in
the value C, = 350 pF. The circuit of Figure 2-1 is repeated here as Figure 4-1 to
illustrate the circuit and component values used for the simulation. Figure 4-2 shows
the resulting waveforms, demonstrating approximate class E operation for the circuit.
Note that effects of the MOSFET body diode are not included.
L
L2
240 nH
VIN
82 nH
-
1
350 pF
C
470 pF
R
3.04
Figure 4-1: Class E Inverter Circuit for PSPICE Simulation
41
Class E Inverter Drain Voltage, V =3.6 V - 7.2 V
30
---
25-
-
V.in=3.6 V
V.in=4.5 V
V =5.4V
V.in =6.3 V
-_V.
in=7.2 V
20 -
i
E510
15- -I
I
5-
0-
-5
II
0
20
40
60
Time (ns)
80
100
Figure 4-2: Class E Inverter Waveforms from PSPICE Simulation
42
120
Chapter 5
From Inverter to Converter
The previous chapter considers the design of a class E inverter having approximately
the correct power and operating frequency. This chapter considers the design of a full
dc-dc power converter that is roughly based on this first pass inverter design.
To construct a dc-dc converter based on a class E inverter, it is necessary to rectify
its AC output. An RF rectifier and matching network can provide this AC to DC
conversion [10,1 1, 6, 3, 12, 13, 14, 2, 5]. However, in an effort to minimize the number
of components, a simpler rectifier was investigated.
In a traditional class E dc/dc converter, the load resistor is replaced by an RF
rectifier network.
This network typically looks resistive to the LC tank, meaning
it has a minimal reactive component in its impedance, or its reactive component is
absorbed as part of the tank or matching network. Current gets delivered out of the
LC network into the "resistor" and then the tank is recharged from the input on the
next switching cycle. An output filter maintains a constant DC output with a low
AC ripple.
A new rectifier was designed that would allow energy to be drawn out of the tank
on each cycle, while also minimizing the number of components used. The topology
is roughly based on a class E converter with a transformed tank. A diode connecting
the tank to the dc output provides the means for energy removal. Analysis of the
circuit with this rectifier is complex due to the nonlinear asymmetric behavior of the
diode rectifier [11].
The system was refined using computer simulation to tune the
43
minimal number of components to meet the output requirements. The resultant tank
values for a series class E inverter are the first column of Table 5.1.
5.1
Tank Transformation
The class E inverter developed in Chapter 4 served as the starting point for the dcdc converter. Modifications to the topology allowed for the application of a simple
rectifier with a single diode. The tank must be transformed from a series LRC combination to a tank with an L in series with the parallel combination of R and C. L and
C create the resonant tank, and R is the dissipative element. The resistor is replaced
by a diode recitifier, which siphons energy and charge out of the tank. This section
develops the tank transformation.
Assuming that the tank current in a class E inverter is sinusoidal follows from
the assumptions the design equations in Chapter 2. For a fixed operating frequency,
the series LRC tank can be transformed to a tank with an inductor in series with
the parallel combination of an R and C. The inductor is still a series element, so its
value remains constant. What remains is a series to parallel transformation of the
RC network, illustrated in Figure 5-1. The impedance equations for each structure
are:
1j
ZSeries
=
+ Rs
=
Rs
Zparallel
=
.
1
jWC2,P
(5.1)
-
jU)C2,s
WC2,s
|Rp =
Rp
jwR 2C
,P
2
-P(5.2)
(wRpC 2 ,p) 2 + 1
(wRpC 2 ,p) + 1
2
To accomplish this transformation, equating the real and imaginary parts of the
two transfer functions results in the following two equations in two unkowns. These
can be evaluated at the operating frequency w = 27rf 8 . Table 5.1 contains the initial
series LRC tank values, and their transformed values for the new parallel RC inverter.
R
=
+
44
HRsC2,Sw2
(5.3)
ZE j
C
Z
2,S
C2,P
IRs
Series RC
Parallel RC
Figure 5-1: Tank Transformation
Element
L2
C2
Series
52 nH
Parallel
52nH
470 pF
438 pF
R
3.04 Q
45 Q
Table 5.1: Tank Values from Transformation at
1
C2,P
5.2
Re RsC2 ,sw2
f, =
30 MHz
(5.4)
Rectification
The result of the transformation described in the previous section allows for a simple
rectifier. The load resistor R is what removes energy from the tank, which is the
desired effect of the rectifier as well. The load resistor is replaced by a single diode
feeding into a capacitive dc output filter. It is assumed that the output of the converter
will be regulated to sit at a fixed voltage, enabling the capacitive output filter to be
treated as a constant voltage. This topology is illustrated in Figure 5-2. As the diode
capacitance is between the output of C2 and a constant dc node which serves as an
ac ground, its capacitance can be absorbed into C2.
The diode acts as an uncontrolled switch. When the voltage across C2 swings
above the output voltage, the diode will conduct and draw charge out of the tank and
into the output filter. The switch will continue to exhibit the zero voltage switching of
the class E inverter (measured across C1) as its ouptut rings down prior to transition.
45
L1
D
L2
VIN
C
C2
VOUT
Figure 5-2: Converter Cell
This comes from the LC tank that L 2 forms with the capacitance across the output
of the switch C 1 .
The result of replacing the load resistor R with a diode is illustrated by the waveforms in Figure 5-3. The drain waveform and the waveform across the tank capacitor
C2
are illustrated. The duty ratio of the diode is effected by C2 as it will determine
the slope of its output voltage during the time when the diode is off. Adjusted tank
values were determined using PSPICE to ensure zero voltage switching and to meet
the output power requirements. Standard values were chosen for all components so
that analysis could carry into prototyping directly. Manufacturer models were used
for the MOSFET (Fairchild FDN361AN) and diode (Fairchild MBR0520L). The tank
component values are
L,
=
240 nH
(5.5)
L2
=
56 nH
(5.6)
C1
=
220 pF
(5.7)
C2
=
220 pF
(5.8)
The waveforms in Figure 5-3 was generated using these values in the circuit of Figure
5-2. Appendix A.2 contains the PSPICE files used.
5.3
Prototype Cell
The circuit simulated in the previous section was prototyped to confirm its viability
for a final design.
The purpose of the prototype was to confirm the operation of
46
the topology, and measure the conduction losses associated with it. The gate drive
was provided by an external power amplifier driving the gate with a sinusoidal drive.
Gating losses are not included in this section.
One purpose of the prototype was to confirm that zero voltage switching could
be achieved to prevent excessive dissipation at switch transitions. Figure 5-4 shows
the drain voltage measured for operation across the input voltage range. Acceptable
switching behavior is achieved over the operating range.
For purposes of testing the power stage design, the prototype converter was loaded
with Zener diodes to maintain a constant output voltage. The converter was tested
with 7.5 V Zeners capable of handling the power expected based on the simulations
of the previous section. Loss associated with the conduction and switching loss was
the main measurement taken from the prototype. The gate was driven by an external
source, and power delivered to the gate is not accounted for here. Table 5.2 contains
the measured drain efficiency data, and it is graphed in Figure 5-5. As can be seen,
good drain efficiency (l7D =
Qi-)
is achieved over the input voltage range.
Vin
'in
Pin
Vout
Iout
Pout
3.60
4.51
5.38
6.31
7.18
0.84
0.91
0.96
0.99
1.04
3.02
4.10
5.16
6.25
7.47
7.24
7.12
7.21
7.32
7.42
0.370
0.493
0.614
0.747
0.879
2.68
3.51
4.43
5.47
6.52
7
7D
0.886
0.855
0.857
0.875
0.873
Table 5.2: Unregulated dc-dc Cell Efficiency (Gating loss power not included)
47
Converter Drain Voltage, V,=3.6 V - 7.2 V
30
V1n=3.6 V
S=4.5
25
-
-
V
V1=5.4 V
V =6.3 V
V, =7.2 V
20
-n
8
15
0
IIt
0
0
-5
0
40
20
60
Time (ns)
120
100
80
Rectifier Diode Voltage, Vn=3.6 V - 7.2 V
10
8
-
6
-
--- n =3.6
- -V =4.5
- .V =5.4
Vin=6.3
- -
4
\
- --
V
V
VV
V n=7.2 V
2
0)
0
0
ID)
-
-
-2
-4
-6
-8
-1
0
20
40
60
Time (ns)
80
100
Figure 5-3: Converter Simulation Waveforms
48
120
Vds Waveforms over Input Voltage Range, V
=
18.03V
Vin=3.6 V
. ---Vi=4.5 V
~---~Vin=5.4 V_
V
V=6.3
i
-
25
A--V
1n=7.2V
20
15
10
5
0
-50
-40
-30
-
I
-20
-10
I
I
0
Time (ns)
10
-ik
20
Figure 5-4: Unregulated Cell Waveforms
49
30
40
50
Output Power, V =3.6 V -7.2 V
10
8
6
0
4
4-.
4
5556-.
4.5
5
5.5
6
6.5
7
6.5
7
Vin (V)
Cell efficiency (excluding gating loss) Vi =3.6 V -7.2 V
I
I~
4
4.5
~
I
I
5.5
6
0.95
0.9
0
C
a, 0.85
w
0.8
0.75
0.7
5
Vi (V)
Figure 5-5: Prototype cell power and drain efficiency (excluding gating loss power)
50
Chapter 6
Resonant Gate Drive
6.1
Multi-Stage Gate Drive
A gate drive circuit must be able to deliver a minimum amount of power to the gate
of the main MOSFET in order to turn it on and off. Self oscillating structures may be
employed to resonantly drive the gate [2, 6], but loading of the main power circuit is a
consideration. Alternatively, a multi-stage amplifier approach may be used in which
a cascaded gate drive structure delivers the needed power (e.g. [5]).
A design was
developed that combines the features of a self oscillating resonant driver [2, 6, 5] and
the tapered hard-switched driver designs sometimes found in low-power integrated
converters [16, 15].
A multistage resonant gate drive circuit was designed to control the selected MOSFET, a Fairchild FDN361AN device. The circuit consists of an oscillator stage, a drive
stage, and a resonant tank to reduce the switching losses. The circuit is illustrated in
Figure 6-1. The following sections will develop each subunit of the gate drive circuit.
6.1.1
Oscillator
In maximizing the power density of a converter, fewer components used means less
space used. Here the first stage of a mult-stage driver is designed to self oscillate,
eliminating the need for a separate oscillator. The converter can be controlled by
51
Vdd
RR
INHIBIT 0-c
L4
X
Oscillator
v
v
'Drive Stage 'Resonant Tank MOSFET Gate
Figure 6-1: Multistage Resonant Gate Drive Circuit
103R
C3
Figure 6-2: Relaxation Oscillator Circuit
modulating the self oscillations on and off [2, 5].
Feedback combined with the hysteretic characteristics of an inverter can create
a simple relaxation oscillator as shown in Figure 6-2. A feedback resistor combines
with a capacitor, which absorbs the input capacitance of the inverter, to form an RC
network [17]. The time constant of this RC network sets the oscillation frequency of
the circuit.
When the oscillator output transitions to high, the input capacitor C3 begins
charging through the feedback resistor R 7 . Once the input voltage crosses the VIH
threshold of the inverter, the output will fall, and then discharge the cap down until
VIL is crossed [18].
In addition to an inverter, only 3 additional components are needed for a robust
oscillator.
C3
is a capacitor added in parallel with the input capacitance of the
52
inverter. When this value dominates the inverter input capacitance, it improves the
robustness of the design. R 7 is the feedback resistance. Combined with C3, this sets
the time constant of the circuit. Finally, R 8 is a pull up resistor. It is designed to
prevent the oscillator from entering a metastable state.
6.1.2
CMOS Inverter Drive Stage
A CMOS inverter is essentially a push-pull output stage, as illustrated in Figure 6-3.
This structure could be used for hard switching, or to drive a resonant gate drive
circuit.
Two design considerations are the current handling capability and losses
associated with the inverters. In practice, one could build the structure of Figure
6-3 with discrete MOSFETs (perhaps copackaged) or use a commercially designed
CMOS inverter stage.
Vdd
A
A
Figure 6-3: CMOS Inverter Structure
Complementary dual MOSFETs having large handling capability are available in
the same size packages as low power inverters. Simply tying the gates and sources
as in Figure 6-3 would create a custom inverter with large drive capability. A search
for possible gate drive devices identified multiple devices in the SC-70 package size.
The best dual package inverter found was the Fairchild Semiconductor NC7WZ04.
Fairchild also offers a complimentary MOSFET package, with one N channel and one
P channel device in the same SC-70 package.
The main concern with this discrete design approach is shoot through, when both
the n-channel and p-channel devices are on during the switching transition. In low
53
power devices, the threshold voltages are designed to be minimized. Operating these
devices from higher voltage rails can result in a scenario where both devices are
turned on as the input transitions from low to high or vice versa. This will sink
current directly from the supply to ground, causing an unacceptable loss at very high
frequencies [15].
Commercial inverters (e.g. Fairchild NC7WZ04) are designed to adapt to a range
of input voltages while minimizing this shoot through problem. This will eliminate
the need for any external level shifting circuitry that discrete MOSFETs would require
to mitigate shoot-through loss.. In addition, the inverters are designed to minimize
input and output capacitances to allow for high speed switching. As a result, multiple
inverters may be paralleled to meet the current requirements of the drive stage, while
not resulting in significant output capacitances before the LC tank. This is valuable
because any capacitance prior to the resonant tank will be hard switched, with losses
described by Equation 2.27. As a result, a design using parallel NC7WZ04 inverters
was selected for the converter.
The low power inverters such as the NC7WZ04 can operate over roughly half the
input voltage range, from 3.6 to 5 V. For the higher input voltage range, a low dropout
linear regulator was included in the design. It should follow the input voltage up to 5
volts, and then maintain a 5 volt supply for the gate drive when the input is between
5 and 7.2 volts. While there is some loss of efficiency due to the regulator when the
input voltage exceeds 5 volts, it will be at most
LDO Loss Factor =
6.2
6.2.1
5v
7.2V
(6.1)
Resonant Gate Drive Circuit
Basic Resonant Gate Drive Circuit
Figure 2-3 is repeated here as Figure 6-4 in order to illustrate a simplified resonant
gate drive circuit. This is essentially a series resonant inverter, where two switches
and an LRC filter convert a dc supply voltage to an ac voltage across the gate, plus
54
a dc offset.
Vd
L3
|R9
C
Figure 6-4: Basic Resonant Gate Drive Circuit
The ac sinusoidal voltage commutates the switch on and off. The dc offset across
the gate voltage is equal to half the inverter rail voltage. This is desirable because
it offsets the sinusoidal drive close to the threshold voltage of the device. This will
bring the duty ratio closer to the desired 50% [1].
Section 2.3.2 developed the benefits of a resonant drive as applied to gating loss. In
addition to these power savings, adding a reactive element L 3 to the circuit provides
another design parameter. This second order circuit can be utilized to achieve voltage
gain and set the desired power needed to drive the gate sufficiently by controlling the
resonant frequency fre relative to the switching frequency f,". Finally, if the circuit
is switched above resonance, ie f 8 ,
> fres, the resonant tank assists in charging
and discharging the output capacitance of the switching devices to reducing inverter
switching loss.
The simplified resonant gate drive circuit of Figure 6-4 is created by adding an
inductor in series with the gate of the MOSFET as discussed in Section 2.3.2. The
addition of an inductor creates a series LRC circuit. The C is the gate capacitance
of the MOSFET and R is a parasitic resistance associated with the circuit.
The
impedance looking into the LRC tank is
ZIN= Ls + R +
55
1
CS
(6.2)
The gate voltage is seen across the gate capacitor, Cgs. The transfer function from
tank input to the gate is
VG-
_
VT
=S
_
Ls+R+
LCs 2 +RCs + 1
(6.3)
Near the resonant frequency w0 , the magnitude of the transfer function is approximated by the
Q
of the circuit. These parameters are defined as
Wres
Q
=
(6.4)
=! ROC
(6.5)
where R is the sum of the gate resistance R9 and the effective inverter output resistance.
6.2.2
Improved Resonant Gate Drive Circuit
The primary disadvantage of the basic resonant gate drive circuit of the previous
section is that all of the reactive current flowing through the gate goes through the
inverter switches. This results in excessive dissipation in the switches, requiring them
to be overrated to compensate. To understand this, consider that when used to drive
a series resonant gate circuit, the on-state resistance of each switch will add in series
with the gate resistance Rg, and increase the power dissipation associated with the
resonant tank. There is a tradeoff between the hard switched output capacitance and
the loss due to the on state resistance.
capacitance scales by N - C,
As N inverters are parallelled, the output
and resistance scales by RON/N. This tradeoff can be
partially overcome, as described below.
A resonant tank circuit with an added shunt branch (Figure 6-5) solves this problem by creating a second LC tank for reactive current to oscillate in.
Figure 6-5
illustrates this added branch (comprising of L 4 and C 4 ) in a resonant circuit driven
by a square wave drive. L 4 acts to reduce the reactive current supplied by the driver,
while C4 acts as a dc blocking cap.
56
C,
L4
C4
Figure 6-5: Improved Resonant Gate Drive Circuit
One benefit arises from this added shunt circuit, with one offsetting disadvantage.
The current in the switches decreases as the second LC tank provides reactive power to
the gate. This allows for the switches to be sized smaller, with less output capacitance.
Less output capacitance is significant because any switch output capacitance is seen
before the resonant tank, and is therefore hard switched.
The disadvantage of the added shunt branch is the loss associated with the bypass
capacitor during cell modulation. When the gate drive starts driving, the blocking
capacitor C 4 becomes charged to half the peak inverter drive voltage Vdd. When the
gate drive is shut down (held low), C4 discharges to zero. Each time the gate drive
circuit is enabled and disabled, the bypass capacitor is hard switched. This results in
losses of
Psunt = C4
where Vdd is the inverter rail voltage, and
va
fmod
2
(6.6)
fmod
is the rate at which the converter is
modulated on and off to regulate the output.
6.2.3
Effective Gate Capacitance
The effect of the added shunt branch on the transfer function
E is equivalent to
vx
reducing the capacitance seen across the gate. The inductor value is chosen so that
the parallel L 4 C 3 has a higher impedance at the desired frequency than C,, which
corresponds to a lower equivalent capacitance. The resonance of L 4 and C,
be below
f,
should
so that it looks capacitive, although with a higher impedance than Cg,
alone.
57
The end resultant impedance looks like an equivalent capacitance that is smaller
than the original Cg. This will serve to increase the
Q
of the resonant gate drive
circuit as described by Equation 6.5. This increases the transfer function from input
to gate, providing a strong drive signal for the device.
6.2.4
Effects of Reverse Capacitance
Due to the reverse transfer capacitance Cdg of the MOSFET, there is a drive voltage
at the MOSFET gate due to the large ac drain-source voltage. The transfer function
from drain voltage to gate voltage is thus important.
At sufficiently high input
voltages, this reverse transfer can inject enough charge onto the gate to cause the
transistor to self oscillate even while the drive circuit holds its output low. In order
to prevent this, PSPICE simulation was used to sweep the inductor values to reduce
the drain to gate transfer function while still maintaining a large enough input to
gate transfer function to drive the transistor. These final values were used for the full
converter prototype.
Decreasing L 3 decreased L
faster than it decreased
Vd
V9.
V
While the gate waveform
amplitude decreases with v9, this will actually lower the gating loss (Equation 2.32).
So long as the switch device can still be fully activated while preventing self oscillation
while disabled, the resonant gate drive circuit will minimize the gating losses.
58
Chapter 7
Cell Modulation Control
Architecture
Cell modulation has previously been presented as a control architecture for rf power
converters [2].
In its simplest form for control of a single cell, the architecture re-
duces to on/off control of a converter, also known as bang-bang control [2, 19]. An
advantage of this approach is extremely fast and well behaved transient performance.
This section will develop the architecture used to regulate the output voltage of the
converter.
7.1
General Theory
Figure 7-1 contains a simplified block diagram for a cell modulated architecture. The
main components are the rf converter, an output filter, and a feedback network to
enable or disable the converter. The output filters averages the power delivered by
the converter, while the feedback network enables the converter with an appropriate
duty cycle to meet the load requirement.
A feedback network is needed to monitor the output voltage and provide the
control signals for the converter. For use in a cell modulation architecture, an rf power
converter must have the ability to be enabled or disabled by the control system. This
will be integrated via an addition to the multi stage gate drive previously developed
59
Voltage
Reference
._+
Controller
~
DC/DC
Converter
Cell
-~
o Load
Converter with Enable/Disable
Feedback Network
Figure 7-1: Cell Modulation Architecture Block Diagram
in Chapter 6.
The final control schematic is contained in Figure 7-2.
The following sections
describe the circuit elements that make up the functional blocks of figure 7-1.
Vdd
R4
R5
Vdd
R3
R6
oSCIN-HIBIT
Ail,
R
VOUT
C
R2
C5
Figure 7-2: Cell Modulation Control Schematic
7.2
Feedback Network
The voltage regulation is created by comparing a fraction of the output voltage to
a fixed reference voltage. The fixed reference voltage is provided by a shunt voltage
reference.
A resistive divider is used to sense the output voltage. A comparator
provides the control signals to the converter.
A shunt voltage reference was chosen with a reference voltage that is lower than the
minimum input voltage of the converter. This ensures that it is operating at its desired
reference value throughout the entire input voltage range. A 3V reference meets these
60
requirements. A reference ADR530 is selected, with a bias resistor R5 =1.0 kQ. This
element consumes at most ~ 1.8% of the output power at light load and max input
voltage.
PR
5 ,max
( nmax
Vre)
-
R5
18 mW
(7.1)
A resistive divider is used divide the output voltage down for comparison to the
reference voltage. The resistive values are chosen to control the power dissipation
across the total divider in addition to providing the correct division ratio. The resistor
values chosen were 12 kQ and 9 kM. The divider ratio and power dissipation are then
9 kQ
Divider Ratio
Pf
9 kQ
9 kQ + 12 kQ
=
2
9 kQ(7V)
+ 12 kQ
3
7
(7.2)
2.33 mW
(7.3)
Finally, the LMV7235, a high speed comparator (45 ns propagation delay) closes
the loop. The reference voltage is connected to the non inverting input and the divided
output voltage is seen at the inverting input. This results in the desired operation of
an enabling signal, or high output, when the divided output voltage drops beneath
the reference. When it rises above the reference, the comparator outputs low, which
is used to disable the RF converter, via the gate drive oscillator.
A hysteresis band provides noise rejection and is used to set the output ripple.
A capacitor is added in parallel with the resistive divider to filter out high frequency noise at the inverting input pin.
7.3
Enable/Disable Circuit for the RF Converter
In order to use the RF converter for a cell modulated architecture, it must be possible
to enable and disable the converter. This may be accomplished by causing the gate
drive circuit to hold the gate low, forcing the switch off.
A benefit of using 2 stages of standard inverters for the gate drive circuit as
described in Chapter 6 is the possibility for a logic level control signal. Holding the
61
input of the inverter used in the relaxation oscillator low will result in a low output
at the gate drive because of an inversion at each of the two drive stages. This helps
simplify the control logic.
The output of the comparator in the feedback network described above can provide
the low signal to the relaxation oscillator. A reverse biased diode is added between the
comparator and relaxation oscillator. When the output of the comparator goes high,
the diode will open circuit and allow the relaxation oscillator to operate. However,
when the comparator goes low, the diode will conduct and hold the input of the
relaxation oscillator at one diode drop above ground, preventing it from oscillating.
One consideration is that the diode adds some effective capacitance in parallel with
the input capacitance of the relaxation oscillator. This must be taken into account
when tuning the time constant of the oscillator.
7.4
Hysteresis Band
R 3 and R 4 create a voltage divider used to create a hysteresis band. The hysteresis
band reduces oscillation in the comparator. R 3 and R 4 divide the voltage between
Vref and Vt. For an open drain output comparator, the output will be pulled up to
approximately the rail voltage, Vdd. This creates a hysteresis band of
Vhyst
7.5
R3+ R4
(Vdd
~
Vref)
(7.4)
Cell Modulation Frequency
Along with the hysteresis band, the output capacitance and converter load will determine the cell modulation frequency and output ripple. Other contributing factors
are the propagation delay of the comparator and the turnon and turnoff speed of the
gate drive circuit.
When the output voltage drops below its minimum ripple, the comparator triggers.
After the propagation delay of the comparator, the multi-stage gate drive circuit
62
activates. The converter then charges the output capacitance. The output voltage
climbs until it crosses the maximum ripple, tripping the process in reverse. During
charging, the slope is set by the difference in converter current and load current
requirment. During discharge, the ripple slope is set by the load current.
The turn on transients of the components are small relative to the charging and
discharging periods of the output filter. These are illustrated in the experimental
results contained in the next chapter.
63
THIS PAGE INTENTIONALLY LEFT BLANK
64
Chapter 8
Experimental Results
Figure 8-1: Prototype Converter Cell
A full dc/dc converter was built using the converter cell of Chapter 5, the drive
circuits of Chapter 6, and the control techniques of Chapter 7. Appendix B contains
a schematic of the full converter, along with a table listing the bill of materials.
Appendix C contains details of the printed circuit board used for the converter cell.
The converter is pictured in Figure 8-1. The board is a complete converter, including input filter, power stage, gate drive, cell modulation control, and output filter.
65
A dime is included for relative scale. Active circuit board area for this prototype is
approximately 0.75 in.2 . The circuit heigh, including PCB, is approximately 0.25 in..
8.1
Open Loop Converter Efficiency
Before closing the control loop around the high frequency resonant converter, its
output power and efficiency were measured. The circuit was loaded with Zener diodes
to provide voltage regulation at the output. Table 8.1 contains the output power and
efficiency data.
Vin
3.65
4.00
4.50
5.00
5.40
6.00
6.30
7.00
7.20
Iin
1.00
1.09
1.17
1.23
1.27
1.30
1.33
1.40
1.42
Pin
3.639
4.344
5.265
6.150
6.858
7.800
8.379
9.800
10.224
Vout
7.03
7.08
7.17
7.25
7.30
7.37
7.42
7.51
7.56
lout
0.42
0.49
0.59
0.69
0.76
0.86
0.91
1.06
1.10
Pout
2.953
3.469
4.230
5.003
5.548
6.338
6.752
7.961
8.316
'q
0.811
0.799
0.803
0.813
0.809
0.813
0.806
0.812
0.813
Table 8.1: Open Loop Converter Power and Efficiency
At the minimum input voltage 3.6 V, it should be noted that the converter can
deliver just shy of 3 W. In a cell modulated architecture, this converter could meet
load requirements up to 3 W across its entire input voltage range.
8.2
Cell Modulated Converter Efficiency
Dc to dc converter efficiency was computed over the load and input voltage range. It
is calculated as
Pin
Pout
(8.1)
Data obtained from the full converter prototype is included in Table 8.2 and illustrated
in Figure 8-2. The circuit was measured over the full voltage range at three distinct
loads.
66
Vin
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
6.6
6.8
7.0
7.2
'in
1.0 W
0.365
0.348
0.334
0.321
0.309
0.298
0.288
0.278
0.266
0.256
0.245
0.236
0.226
0.217
0.212
0.199
0.192
0.187
0.171
1.5 W
0.563
0.535
0.512
0.494
0.475
0.459
0.442
0.428
0.410
0.395
0.379
0.364
0.350
0.336
0.323
0.309
0.294
0.277
0.260
2.0 W
0.741
0.706
0.677
0.650
0.627
0.604
0.585
0.565
0.541
0.521
0.499
0.480
0.462
0.443
0.427
0.409
0.389
0.365
0.342
ConverterEff iciency
1.0 W 1.5 W 2.0 W
0.761
0.740 0.750
0.756 0.738 0.745
0.749 0.732 0.739
0.742 0.723 0.733
0.736 0.718 0.725
0.730 0.710 0.720
0.723 0.707 0.712
0.708
0.719 0.701
0.723 0.704 0.711
0.723 0.703 0.711
0.729 0.707 0.716
0.718
0.710
0.731
0.722
0.737 0.714
0.728
0.743 0.720
0.726 0.732
0.737
0.736 0.741
0.761
0.766 0.750 0.756
0.764 0.774 0.783
0.812
0.812 0.801
Table 8.2: Prototype converter efficiency
8.3
Cell Modulation Operation
Figure 8-3 illustrates the cell modulation control behavior of the system at the four
corners of V, and load. The response shows how at the ends of the input range the
converter will modulate to meet both light and heavy load conditions. The bounds
on modulation frequency can be determined using these graphs. Table 8.3 contains
the cell modulation frequencies from the graph.
At the higher input voltages, some self oscillatory behavior is seen during turn off.
This decreases the modulation frequency somewhat, though it results in the ripple
voltage exceeding the hyseteresis bounds because the self oscillating turn off continues
charging the tank even after the gate drive is shut down.
The transient startup and shutdown response of converter at Vj" = 5.OV and
Rload =
24 Q is illustrated in Figure 8-4. The output of the comparator acts as an
enable signal; the gate begins oscillating shortly after the enable signal rises. The rise
67
Converter Efficiency Over Input Voltage and Load Range
Pout=1.0w
-
out=1.5W
PO=2.0W
0.8
F/
,
-
s- 0.75
E
*
4.5
5
0.71
0.65
4
5.5
VI (V)
6
6.5
7
Figure 8-2: Converter Efficiency
Tmod (As)
3.6
7.2
Pout = 2W
P0nt = 1W
Vin
4
5
(kHz)
250
200
fmod
Tmod (As)
(kHz)
91
200
frnd
11
5
Table 8.3: Cell Modulation Frequencies
time of the converter is approximately
0 25
.
ps and the fall time of the converter gate
drive is approximately 0.25ps.
8.4
Output Voltage Ripple
A sample output voltage ripple for the LM7231Y is illustrated in Figure 8-5. The
measurement is taken for V
= 5.0 V and presented with both a full bandwidth
measurement and as a bandlimited measurement.
The output voltage ripple was measured for the full converter cell across the input
voltage range. Again, measurements were taken at full measurement bandwidth,
68
VIN =3.6V
VIN =7V
POUT= 1W
15
POUT= 1W
15
-
105i
1
10
a)
5
-L
0
Ii
0
CO 0
0
-5
-10
-5
-5
5
0
Time (ps)
VIN3.6V
-10
10
5
0
Time (ps)
-5
VIN =7V
POUT =2W
15
15
10
10
5
10
POUT =2W
5
)
0
0
0
0
a)
0
-5
-5
-10
-5
5
0
Time (ps)
-10
10
-5
0
5
Time (ps)
10
Figure 8-3: Cell Modulation Behavior
illustrated in Figure 8-6. The bandlimited measurements are contained in Figure 8-7.
8.5
Load Step Response
The converter was tested in order to determine the transient response to a load step.
At the trigger time, the load was switched from a 50 Q load to a 25 Q. This changed
the output power requirement from approximately 1 W to approximately 2 W, the
maximum swing within specification.
For illustrative purposes, the experiment was first performed on a National Seminconductor LM2731Y prototype board configured for V0,
= 7 V.
Its load step
response is illustrated in Figure 8-8. The transient response deviates off of the speci69
1
10
1
1
11
1
1
1
8-
6-
0
2C
0
-
0.
E
0
-6-
-8 -1II
-1.5
-1
-0.5
1
0.5
0
1.5
2
Time (ss)
Figure 8-4: Cell transient behavior, V
=
5.OV and
RIoad =
24 Q
fled output voltage at the time of the loadstep by a peak value of +3.75V and -0.4V,
with the transient lasting approximately 1.5 ps. Figure 8-8 contains the LM7231Y's
ac response to a load step. It is bandwidth limited to 20 MHz.
Figure 8-10 contains the same experiment for the cell modulated converter. The
load step response is near instantaneous. The peak excursion does not exceed the
steady state ripple level, 100 mV.
The output voltage does not deviate with an
significant value outside of specification. The gate drive waveform is included to
demonstrate how the cell modulation duty cycle adjusts to the load requirements.
The load step response time is the strongest benefit of this converter. With
a comparable size to the LM7231Y demonstration board, the provides comparable
steady state voltage regulation. However, the prototype converter is clearly superior
to conventional design in dealing with load transients. This is because the energy
storage elements in the new converter are much smaller and can respond much faster
than the larger passive elements at in the conventional design. For applications
70
Output Voltage Ripple, V
=
5.0 V, Put 1 W
0.1
0.05
--
0
93
-7
>0-0.05
-0.
-4
-3
-2
1
0
-1
2
3
4
5
Time (pus)
Output Voltage Ripple, Vn= 5.0 V, P
1 W, Measurement Bandwidth =20 MHz
0.04
0.02-
0
>-0.02
-0.04
-4
-3
-2
-1
0
1
Time (gs)
2
3
4
5
Figure 8-5: Output Ripple of LM7231Y Demonstration Board
demanding reliable operation over load transients, the slightly less optimized efficiency
of the cell modulated converter could easily be outweighed by its agility.
71
Output Voltage Ripple, Vin= 3.6 V, Pout = 1 W
0.5
CL,
Cz
-0.5
0
2
4
6
8
10
Time (ps)
1
12
14
16
18
1
Output Voltage Ripple, Vin= 5.0 V, Pu=
out 1 W
0.5 1
ID
a
a
C.,
Cu
1I
1
1
1
1
1
12
14
16
18
80
90
0
- 0 .5u
0
2
4
6
8
10
Time (pCs)
Output Voltage Ripple, Vn= 7.2 V, Pu= 1 W
I~i
0.5
I
outI
a,
7a
0
-0.5
fS000N
0
10
20
30
40
50
Time (ps)
60
70
Figure 8-6: Converter Output Voltage Ripple
72
1
Output Voltage Ripple, Vi,= 3.6 V, P u=1 W, Measurement Bandwidth = 20 MHz
0.1
0.05
ca
0
0
-0.05
-0.1
-8
-6
-4
-2
0
2
Time (pts)
4
6
8
10
0L
Output Voltage Ripple, V = 5.0 V, P0u= 1 W, Measurement Bandwidth = 20 MHz
'
0.1
0.05
0
-
8
6
-
-
-8
-6
-4
-2
4
6
8
1 -
4
6
8
10
-0.05
-0.1
0
2
Time (us)
Output Voltage Ripple,
V = 7.2
V, P0 ut= 1 W, Measurement Bandwidth = 20 MHz
0.2
0.1
a
0~
0
0
Cu
-0.1
-40
-30
-20
-10
10
0
Time (ss)
20
30
40
50
Figure 8-7: Converter Output Voltage Ripple, Meaurement Bandwidth = 20 MHz
73
Load Step Response for National Semiconductor LM7231 Y Demonstration Board
15
10-
5Qi)
0 0-
0
-5-
-10
-15
-6
-5
-4
-3
-2
-1
Time ( is)
0
1
2
3
Figure 8-8: Load Step Response of LM2731Y Demonstration Board
74
Output Voltage Ripple Response to Load Step for LM7312Y Demonstration Board, Bandwidth = 20 MHz
4,
1
1
1
1
1
1
1
1
1
2
3
1
1
3.5 |
0.
0
-J
0
0
CL
0
3
2.5-
2-F
1.5l-
.
0)
0
0.5
-1
0
F,-
-0.5
-4
-3
-2
-1
0
4
5
Time (ps)
Figure 8-9: Load Step Response of LM2731Y Demonstration Board
75
K"iii
Load Step Response for Cell Modulated Converter
15
CL
S?
1
0
00 W-I *4P*w-M
4,
5
C,
CL
0
0.
ca
a)
0
-1
0
i..: .izzi:z.
-15
'
-6
I
I
I
I
-5
-4
-3
-2
I
-1
Time (gs)
I_
0
I
II
1
2
3
Figure 8-10: Load Step Response of Cell Modulated Converter
76
Output Voltage Ripple Response to Load Step for Cell Modulated Converter, Bandwidth = 20 MHz
0.1
I
~
0.08
0.06
0
a,
0.04
0
0
0.02
0
CL
0)
0
-0.02
-0.04
0
-0.06
-0.08
-n
1
I
I
-8
-6
I
-4
I
-2
I
0
I
I
I
I
I
2
4
6
8
10
Time (pts)
Figure 8-11: Ripple Resonse to Load of Cell Modulated Converter
77
THIS PAGE INTENTIONALLY LEFT BLANK
78
Chapter 9
Conclusions
This thesis developed a very high frequency power converter with cell modulated
control to compete with a National Semiconductor LM7231Y boost converter. It
achieved comparable bandwidth limited ripple to the reference part, with slightly less
efficiency. The major advantage came in converter response to load transients. The
cell modulation architecture achieved near instantaneous load response that did not
exceed the steady state ripple behavior.
Over the load range of V,t = 7V, P,t = 1W -2W, full converter efficiency ranged
from 71% to 81%, depending on load and input voltage. Cell modulation frequencies
were observed of 91-250kHz. Bandlimited output ripple was approximately 100mV.
9.1
Research Developments
Conduction loss and gating loss were the primary loss mechanisms considered in the
analysis of class E inverters. After examining the loss mechanisms at work in class
E inverters, metrics for devices selection were developed. These metrics helped to
identify devices based on both published device parameters as well as experimentally
characterizations of the gate parasitics. Based on these two sections, the Fairchild
Semiconductor FDN361AN was identified as a switching device for a converter topology operating at 30 MHz.
79
9.2
Converter Development
Following device selection, a converter topology was developed based on a class E
inverter with the objective of minimizing components. The classic series resonant tank
in a class E inverter was transformed to a parallel structure. A single diode rectifier
was then added to remove energy from the resonant tank. The diode capacitance of
the diode rectifier was absorbed into the resonant tank parameters.
A multi-stage gate drive network, including a self resonant stage, was developed
to drive the FDN361AN with a sinusoidal plus dc offset gate drive.
Commercial
inverters were applied as a push-pull stage to drive a series resonant circuit. The
reverse transfer capacitance of the FDN361AN required some development work to
prevent self oscillatory feedback during converter shutdown.
9.3
Potential Future Work
This thesis provides the groundwork for future efforts at minitaurization of dc/dc
converters. As a result of the high frequency operation, the air core magnetics could
be integrated into a circuit board, further decreasing the impact of magnetics sizing.
The active components of the circuit coud be integrated into a signal package, and
possibly copackaged with the passive elements. Finally, improved topologies over the
class E inverter that provide the basis for the converter could be pursued in order to
improve efficiency.
In addition to minimization, the thesis demonstrates methods for improving transient response of low power converters. These improvements in power converters can
improve the operation of circuits exhibiting load transients, such as power amplifiers.
The control architecture could also allow for dynamically regulating the output voltage of the circuit. Both of these improvements extend the capabilities of the power
supply, and could be utilized in circuits that actively regulate their power needs.
80
Appendix A,
PSPICE Code
A.1
Class E Inverter Simulation
1
*Class E Inverter Simulation
5
1
Vin
Vgate 5
+PULSE
1
Li
2
L2
2
C1
C2
3
X_Si 5
10
Ri
15
4
0
0
OV
2
3
0
4
0
0
{inputV}
1V 0 .ins .ins {D*Tsw} {Tsw}
{Livalue}
{L2value}
{C1value}
{C2value}
2 0 SCHEMATIC1_Si
{Rload}
.PARAM
+ D=.5
+ Tsw={1/30e6}
+ inputV=5.4V
+ Civalue=350pF
20
+ C2value=47OpF
+ Llvalue=240nH
+ L2value=82nH
+ Rload=3.04
25
.TRAN 1ns Sus 0 ins
81
.STEP Vin 3.6V 7.2V .9V
*.STEP param Civalue 105pf 110pf lpf
*.STEP param Civalue 50pf 150pf 25pf
*.STEP param Livalue .5uH 2uH .5uH
.PROBE
30
.OPTION NUMDGT=10
.PRINT TRAN V(2)
35
.subckt SCHEMATIC1_S1 1 2 3 4
3 4 1 2 _S1
SS1
1 2 1G
RSS1
.MODEL
_S1 VSWITCH Roff=1e6 Ron=.15 Voff=O.OV Von=i.OV
.ends SCHEMATIC1_S1
40
A.2
Converter Cell Simulation
The following code simulates the converter cell from Section 5.2 and generates the
waveforms of Figure 5-3. The library fairchild-parts. lib includes the manufac-
turer's models for the MOSFET (Fairchild FDN361AN) and rectifier diode (Fairchild
MBR0520L), are available online at http: //www. f airchildsemi. com/models/emailmodel-file.
j sp?f ile=FDN361AN.mod and http://www.fairchildsemi. com/models/
email-model-f ile . j sp?f ile=MBRO520L. lib, respectively. The MOSFET model was
modified to remove the temperature input pin; the circuit was simulated at a typical
operating temperature.
I
5
**** Class E Inverter + Rectifier *****
* v4.0 plays with the ideal diode some more
* v5.0 adds an ideal diode in parallel with the switch
* v5.0 replaces ideal diode in rectifier with MBRO520L
* v6.0 replaces ideal switch/diode with FDN361AN
82
***
LIST OF LIBRARIES
***
10
.LIB "fairchildmodels.lib"
*****
**********
****
************
*******
***
***
***
**** OPTIONS REQUIRED TO AVOID CONVERGENCE PROBLEMS
15
20
.OPTIONS ABSTOL=lnA
+
GMIN=10p
+
ITL1=5000
+
ITL2=2000
+
ITL4=400
+
RELTOL=0.002
+
VNTOL=O.OlmV
.OPTION STEPGMIN
*** OPTIONS TO KEEP A SMALL OUTPUT FILE ***
* ****
35
******
*******
* *****
****
** * *********
.OPTIONS
+ NOPAGE
+ NOBIAS
+ NOECHO
+ NOMOD
+ NUMDGT=8
*
*
40
45
50
***
***
*********************************************************
25
30
***
Circuit
*
1
Vin
Vgate 5
+PULSE
1
Li
C2
3
2
Cl
2
L2
2
XM
3
Dl
Vout 4
0
0
{inputV}
OV 10V 0 .lns .lns {D*Tsw} {Tsw}
2 {Llvalue}
0 {C2value}
0 {Clvalue}
3 {L2value}
5 0 FDN361AN
4 MBRO520L
0 7V
83
. PARAM
+ D=.5
+ freq=30e6
+ Tsw={1/freq}
+ inputV=7.2V
+ Clvalue=220pF;
+ C2value=22OpF;
+ Llvalue=240nH
+ L2value=56nH;
+ Rload=45
55
60
.STEP Vin 3.6V 7.2V .9V
65
.PRINT TRAN V(2) V(3)
.TRAN ins 5us 2us ins
.PROBE V(2) V(3)
70
A.3
Resonant Gate Drive Simulation
A.3.1
Input to Gate AC Simulation
1
* Oscillator Test
5
***************
***
***NOTES
** ***
10
***
*****
15
**
LIST OF LIBRARIES
* ** ****
****
***
****
*****
***
**********
OPTIONS REQUIRED TO AVOID CONVERGENCE PROBLEMS
***
*********************************************************
84
20
.OPTIONS ABSTOL=lnA
+
GMIN=10p
+
ITL1=6000
+
ITL2=4000
+
ITL4=500
+
RELTOL=0.002
+
VNTOL=O.OlmV
.OPTION STEPqMIN
25
*******
**********
***
30
** ***
***
***********
OPTIONS TO KEEP A SMALL OUTPUT FILE ***
.OPTIONS
+ NOPAGE
+ NOBIAS
+ NOECHO
+ NOMOD
35
+ NUMDGT=8
.WIDTH OUT=132
** ** ****
***
******
;TO PRINT MORE COLUMNS
*****
******
** ************
*
***
SPECIAL PARAMETERS AND CONSTANTS
*******************************************
.PARAM
;GUESS WHAT
+ PI=3.1416
+ FS=30MEG
***
40
***
45
***
****
**********
CIRCUIT DESCRIPTION
***
*** ** ****************
*Vin IN 0 PULSE(O {Vcc} 0 100P 100P {(1/(2*FS))-200P} {1/FS})
50
55
*Vin IN 0 SIN (0 5 {FS})
Vin IN 0 AC 5
Li IN Gext 50n
L2 Gext shuntint 150n
Cbyp shuntint 0 .022u
Rg G-ext Gint 1.5
Cgs G-int 0 250p
Cdg 0 Gint 15p
60
85
65
***
MEASURMENT CIRCUITS
* ***
*****
** ******
****
*ANALYSIS COMMANDS
***** ***
***
*
*** ** ***
.PARAM
+
Vcc=5
70
*.TRAN 0.05N 1U 0 0.05N UIC
.AC DEC 1000 1K 1G
.PROBE
A.3.2
Drain to Gate AC Simulation
1
* Oscillator Test
5
***************
***NOTES
10
***
***
LIST OF LIBRARIES
***
**** OPTIONS REQUIRED TO AVOID CONVERGENCE PROBLEMS
15
20
*********************************************************
.OPTIONS ABSTOL=1nA
+
GMIN=10p
+
ITL1=6000
+
ITL2=4000
+
ITL4=500
+
RELTOL=0.002
+
VNTOL=0.01mV
.OPTION STEPGMIN
25
86
***
*** OPTIONS TO KEEP A SMALL OUTPUT FILE ***
30
35
.OPTIONS
+ NOPAGE
+ NOBIAS
+ NOECHO
+ NOMOD
+ NUMDGT=8
.WIDTH OUT=132
***
*****
;TO PRINT MORE COLUMNS
* ******************************
***
SPECIAL PARAMETERS AND CONSTANTS
*******************************************
.PARAM
;GUESS WHAT
+ PI=3.1416
+ FS=30MEG
***
40
45
** *****
****
******* ** *******
CIRCUIT DESCRIPTION
***
***
*Vin IN 0 PULSE(O {Vcc} 0 100P 100P {(1/(2*FS))-200P} {l/FS})
50
55
*Vin IN 0 SIN (0 5 {FS})
Vin IN 0 AC 5
Li 0 Gext 50n
L2 Gext shuntint 150n
Cbyp shuntint 0 .022u
Rg G-ext G-int 1.5
Cgs G-int 0 250p
Cdg IN Gint 15p
60
*
this is for the transfer function from V-gate/V-drive
* ***
***
***
* ******
***
******
*** MEASURMENT CIRCUITS
65
****************************
***** ** ****
***
*****
*ANALYSIS COMMANDS
* ***
70
***
***
* ***
** ****
*
****
.PARAM
+ Vcc=5
87
*.TRAN 0.05N 1U 0 0.05N UIC
.AC DEC 1000 1K 1G
75
.PROBE
88
Appendix B
Circuit Schematic
B.1
Schematic
Figure B-1 contains the circuit schematic used to develop the prototype converter
PCB.
B.2
Bill of Materials
Table B.1 contains all circuit values, package information, and part information for
the prototype converter.
89
GND
GND
GND
US6
U
N
GN D
GND
Dl
MBR0520L
VIN-2 2
GATLIP
.T
M1
N1FDN361AN
VOUT-2
VIN-G
AND
(D
5V
5V
0
202k
VOUT
(0
CDt
3 5 8
510
D2
MA27D27ED
102BAN
IC2A
5..
.
LMV7210,
IC38
3 4
NC7WVZD
NC7WZC4
u
3
4GATE
L
C-1GND
GND
NC7WZ04
GND
REF1
VINV
R5
RM
G ND
GND
)
ADR530
IC4
V
'N
TPS7 6950
GND AND
V0T
2
GND GND
C2
j
GND
jC1
C,3
TITLE:
inverter_5.Oa
GND
Document Number:
GND
GND
REU:
GND
Date:
8/02/2005 02:43:44a
|Sheet:
i/1
Part
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C18
C19
D1
D2
IC1
IC2
IC3
IC4
Li
L2
L3
L4
L5
Ml
R1
R2
R3
R4
R5
R6
R7
R8
REF1
VIN
VOUT
Value
Package
220p
0805
220p
0805
15p
0402
0.022u
0805
0.022u
0805
lOu
1206
n/a
1206
lu
0805
lu
0805
lu
0805
lu
0805
0.1u
0805
0.lu
0805
0.lu
0805
lu
0805
lu
0805
lu
0805
MBR0520L
SOD-123
MA27D2700
SSS-MINI2
LMV7235
SOT-23-5
NC7WZ04
SC-70-6
SC-70-6
NC7WZ04
TPS76950
SOT-23-5
120n MIDI-SPRING
58n MIDI-SPRING
75n
0805
180n
0805
120n MIDI-SPRING
SUPERSOT-3
FDN361AN
0402
11.8k
8.87k
0402
510
0402
202k
0402
1k
0402
0402
10k
15.4k
0402
990k
0402
ADR530
SC-70-3
MPT2
PHOENIX
MPT2
PHOENIX
Device
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
Ceramic Cap
MBR0520L
MA27D2700
LMV7235
NC7WZO4
NC7WZO4
TPS76950
MIDI-INDUCTOR
MIDI-INDUCTOR
L0805
L0805
MIDI-INDUCTOR
FDN361AN
R
R
R
R
R
R
R
R
ADR530
2POL254
2POL254
COG
COG
COG
X7R
COG
X7R
X7R
X7R
X7R
X7R
X7R
COG
COG
COG
X7R
X7R
X7R
Table B. 1: Bill of Materials for Converter
91
THIS PAGE INTENTIONALLY LEFT BLANK
92
Appendix C
PCB Layouts
NOTE: All images in this Appendix are scaled UP by a factor of 2 from full size.
C.1
Component Side Copper
Figure C-1: Solder Side Copper, 2X Magnification
93
C.2
Silk Screen
Figure C-2: Component Side Silk Screen, 2X Magnification
C.3
Solder Side Copper
C.4
Drills
94
Figure C-3: Solder Side Copper, 2X Magnification
Figure C-4: PCB Drill File, 2X Magnification
95
THIS PAGE INTENTIONALLY LEFT BLANK
96
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[7] N.O. Sokal and A.D. Sokal.
Class E- A new class of high-efficiency tuned
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