Energy Efficient RF Communication System for Wireless
Microsensors
by
SeongHwan Cho
Bachelor of Science, Electrical Engineering,
Korea Advanced Institute of Science and Technology (1995)
Master of Science, Electrical Engineering and Computer Science,
Massachusetts Institute of Technology (1997)
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
aARKER
MA$SACHU S MS
ISTITUTE
OF TECHNOLOGY
Doctor of Philosophy in Electrical Engineering
at the
JUL 3 1 2002
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
LIBRARIES
June 2002
© Massachusetts Institute of Technology 2002. All rights reserved.
I/
......
Author.............................................................
Department of Electrical Engineering and Computer Science
May 24, 2002
C ertified by ...................
.. ...................
Anantha Chandrakasan
Associate Professor of Electrical Engineering
Thesis Supervisor
...........
............
Accepted by............. ..................I . . . . .. ......
.
. . .
.. .. . . .
Arthur C. Smith
Chairman, Department Committee on Graduate Students
Energy Efficient RF Communication System for Wireless Microsensors
by
SeongHwan Cho
Submitted to the Department of Electrical Engineering and Computer Science
on May 24, 2002, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy in Electrical Engineering
Abstract
Emerging distributed wireless microsensor networks will enable the reliable and fault tolerant monitoring of the environment. Microsensors are required to operate for years from a
small energy source while maintaining a reliable communication link to the base station. In
order to reduce the energy consumption of the sensor network, two aspects of the system
design hierarchy are explored: design of the communication protocol and implementation of
the RF transmitter. In the first part of the thesis, energy efficient communication protocols
for a coordinated static sensor network are proposed. A detailed communication energy
model, obtained from measurements, is introduced that incorporates the non-ideal behavior of the physical layer electronics. This includes the frequency errors and start-up energy
costs of the radio, which dominate energy consumption for short packet, low duty cycle
communication. Using this model, various communication protocols are proposed from an
energy perspective, such as MAC protocols, bandwidth allocation methods and modulation
schemes. In the second part of the thesis, design methodologies for an energy efficient transmitter are presented for a low power, fast start-up and high data rate radio. The transmitter
is based on a E-A fractional-N synthesizer that exploits trade-offs between the analog and
digital components to reduce the power consumption. The transmitter employs closed loop
direct VCO modulation for high data rate FSK modulation and a variable loop bandwidth
technique to achieve fast start-up time. A prototype transmitter that demonstrates these
techniques is implemented using 0.25pm CMOS. The test chip achieves 2 0ps start-up time
with an effective data rate of 2.5Mbps while consuming 22mW.
Thesis Supervisor: Anantha Chandrakasan
Title: Associate Professor of Electrical Engineering
Acknowledgments
I would express my sincere gratitude to those who have contributed to the completion of
this thesis. One valuable lesson I learned throughout these years is that nothing can be
done alone.
My foremost gratitude goes to Prof. Chandrakasan. He has guided me since 1995 when
I was a fresh blind graduate student. I truly appreciate his patience and support throughout
the long years at MIT. I would like to thank Prof. Sodini for numerous feedbacks he has
given me during RF meetings as well as in the thesis. His intuitive thoughts on many of
the thesis topics were invaluable and helped the completion of this thesis. I'd also like to
thank Prof. Chan for the constructive comments on the thesis. I am also grateful to Prof.
White, Prof. Lee and Prof. Lim for their advice.
I'd like to acknowledge the ABB Corporation Research in Norway for funding this
project.
I'm especially grateful to Snorre Kjesbu for guiding me on the wireless sensor
networks with the real world examples and experimental results.
I'd like to thank the members of technical staff at IBM T.J. Watson Research Center
for their support in fabricating the chip. I can't thank Herschel Ainspan enough for his
advice in layout. I would still be trying to get over DRC errors if it were not for him. He
has answered all my tedious questions with patience during the course of the chip design.
I'd like to thank Mehmet Soyuer for giving me an opportunity to work with him in the RF
area in 1999. Jungwook Yang was also helpful in numerous ways at IBM.
I am indebted to Dan McMahill and Don Hitko for their kind and patient answers to
various RF questions in the beginning of this work. I've also had many invaluable discussions
with Andy Wang on link budget analysis and modulation schemes. His intuitive ideas and
expertness in these fields have helped me on numerous occasions, including the writing and
proof reading of the thesis. Jung-hoon Lee was also helpful in optimization problems.
I'd like to thank the members of ananthagroupfor their support. Alice Wang has supported me since the beginning of my Ph.D study in various ways.
Rex Min has kindly
volunteered to go through the pain of reading the rough draft of this thesis and gave me
constructive feedbacks. Manish Bhadwarj gave me many intriguing ideas on the communi-
cation protocols and helped with license setups in various CAD tools. Eugene Shih helped
me with the first generation of pAMPS radio design. I'd like thank Fred Lee for taking
the lead role in the radio development of pAMPS project; he has done a wonderful job in
making the radio to work.
The OBs of ananthagroup, Duke Xanthopolous, Raj Amirtharaja, Jim Goodman and
Tom Simon have all helped me not only in cadence questions, but also in numerous academic
areas and in ways to survive at MIT. I'd also like to thank Margaret Flaherty and Beth
Chung for assisting me with numerous orders and reimbursements.
I'd like to thank Engim Inc. for providing me with an opportunity to experience the
unique life of a start-up company.
My friends have given me delightful memories in Boston that I could always cherish.
I'd like to thank Sungtae Kim for the cheerful talks. Sports conversation with SongJoon
Park was always great. The words of Park was another joy in Boston. SungJun Woo was
always ready when I needed a party for go-stop or any kind of gambling. I'd like to thank
Ki-hyuk Park for arranging the airline tickets to Korea. Their girlfriends also deserve some
credit for keeping them busy or I would have spent too much time with them, prolonging
my years as a graduate student.
I am grateful to EECS sunbaes, ChangDong Yoo, Won-Jong Kim, SaeYoung Chung,
Junehee Lee, DongHyun Kim, JeungYoon Choi, and Seokwon Kim for their support. In
addition, Choongyeun has been a great friend, Zhifuan's baseball and entertainment talks
were another pleasure at MIT. Seongmoo Heo has been a great hoobae in many ways and
Jin-chul had been a great roommate, until he got married =]. Junmo's inquisitiveness on
all fields of life is something I should learn from and I'm relieved that I graduated before
Gookwon (this kid's got something). I'm also also thankful to Sokwoo, Hyuksang, Sangjun
and Jinwoo hyung for being great big brothers.
My proud high school alumni at MIT and Harvard, too many names to write in one
page, have also given me cherishable memories to keep in Boston.
Lastly, my deepest love goes to my family, Appa, Umma, Nuna for raising me to the
person I am.
Contents
1
Introduction
17
1.1
Distributed Wireless Microsensor Network . . . . . . . . . . . . . . . . . . .
17
1.1.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Contribution and Scope of Thesis . . . . . . . . . . . . . . . . . . . . . . . .
20
1.2.1
Low power communication protocol
. . . . . . . . . . . . . . . . . .
22
1.2.2
Energy efficient transmitter . . . . . . . . . . . . . . . . . . . . . . .
22
Overview of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
1.2
1.3
2
3
Related work
Design Considerations of a Microsensor Node
25
2.1
Node Architecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.2
Transmitter Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
2.2.1
Link budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
2.2.2
Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.2.3
Start-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
2.2.4
Data rate
33
. . . . . . . ..
. . . . . . . . . . . . . . . . . . . . . . . .
2.3
Considerations on Receiver and Base Station Design
2.4
Sum mary
. . . . . . . . . . . . .
34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Low Power MAC Protocol
37
3.1
Previous Work
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
3.2
Radio Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
3.3
Low Power MAC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
3.3.1
40
Contention vs. scheduled MAC . . . . . . . . . . . . . . . . . . . . .
7
CONTENTS
8
3.4
3.5
4
6
Hybrid TDM-FDM .......
3.3.3
Effect of fading on MAC ......
............................
.........................
44
47
Variable Bandwidth Allocation Scheme .....................
49
3.4.1
Energy vs. bandwidth ..........................
49
3.4.2
Variable time-frequency slot allocation . . . . . . . . . . . . . . . . .
50
3.4.3
Energy efficient time-frequency slot allocation algorithm . . . . . . .
51
Sum m ary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
High Data Rate Low Power Transmitter
59
4.1
Binary vs. M-ary Modulation Scheme
. . . . . . . . . . . . . . . . . . . . .
60
4.2
High Data Rate Low Power FSK Modulator . . . . . . . . . . . . . . . . . .
63
4.2.1
Related work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4.2.2
Closed loop direct VCO modulation
. . . . . . . . . . . . . . . . . .
67
4.2.3
Modulation error and bit error rate . . . . . . . . . . . . . . . . . . .
70
4.2.4
Equalization at base station . . . . . . . . . . . . . . . . . . . . . . .
75
4.3
5
3.3.2
Sum mary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
Fast Start-up Transmitter
79
5.1
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
5.2
Loop Switching in Fractional-N Synthesizer . . . . . . . . . . . . . . . . . .
80
5.2.1
Variable loop bandwidth technique . . . . . . . . . . . . . . . . . . .
80
5.2.2
Effect of quantization noise . . . . . . . . . . . . . . . . . . . . . . .
82
5.2.3
Multiple stage loop switching . . . . . . . . . . . . . . . . . . . . . .
82
5.3
Digital Lock Detector
5.4
Sum mary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Implementation of Energy Efficient Transmitter
89
6.1
. . . . . . . . . . . . . . . . . . . . . . . . . .
89
Fractional-N synthesizer . . . . . . . . . . . . . . . . . . . . . . . . .
91
6.2
Low Power VCO: Architectural Approach . . . . . . . . . . . . . . . . . . .
93
6.3
Low Power Divider: Architectural Approach . . . . . . . . . . . . . . . . . .
97
Frequency Synthesizer Basics
6.1.1
9
CONTENTS
Divider vs. E-A .......
6.3.1
6.4
6.5
Low power VCO: Circuit Techniques ......
99
Low phase noise VCO . . . . . . . . . . . . . . . . . . . . . . . . . .
99
6.4.2
VCO with modulation input
. . . . . . . . . . . . . . . . . . . . . .
101
6.4.3
CMOS varactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
Low Power Divide-by-112/120: Circuit Techniques
. . . . . . . . . . . . . .
106
6.5.1
Divide-by-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
6.5.2
Divide-by-14/15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
6.6
E -A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
6.7
Phase Frequency Detector and Charge Pump . . . . . . . . . . . . . . . . .
109
6.7.1
110
Charge pump for variable loop filter . . . . . . . . . . . . . . . . . .
6.8
Loop Filter
6.9
Energy Efficient BFSK Modulator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
. . . . . . . . . . . . . . . . . . . . . . .
111
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
115
Prototype Test Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
7.1.1
VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
7.1.2
Fractional-N frequency synthesizer . . . . . . . . . . . . . . . . . . .
119
7.2
BFSK Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
7.3
Variable Loop Bandwidth Technique . . . . . . . . . . . . . . . . . . . . . .
122
7.4
Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
123
7.1
8
......................
97
6.4.1
6.10 Summary
7
.............................
Frequency Synthesizer
127
Conclusion
8.1
Conclusion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Critique and Future Works
. . . . . . . . . . . . . . . . . . . . . . . . . . .
A Prototype Chip Testing
127
129
139
A.1
Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
A.2
Serial Register Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
Program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
A.2.1
10
CONTENTS
A.2.2
A.3
Register value description . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Design
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B PLL model
142
142
145
B.1
Noise properties of 2nd order PLL
B.2
Maximum Quantization Noise on VCO Control Voltage
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .
145
146
List of Figures
1-1
Applications of distributed wireless microsensor network . . . . . . . . . . .
18
1-2
System design hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
1-3
Comparison of energy efficiency between a traditional radio and an ideal
radio for different packet sizes.
. . . . . . . . . . . . . . . . . . . . . . . . .
23
2-1
Microsensor node architecture.
. . . . . . . . . . . . . . . . . . . . . . . . .
26
2-2
Received power vs. transmit distance (Courtesy of ABB Corporation Research in Norway).
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
2-3
BER vs. output power in a slow Rayleigh fading channel.
. . . . . . . . . .
31
2-4
Degradation of SNR due to phase noise in adjacent channel. . . . . . . . . .
32
2-5
Start-up transient of a commercial low power transceiver (Tstart ~ 470ps). .
32
2-6
Effect of start-up transient on transmitter's energy consumption in a 100 bit
packet transm ission.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
. . . . . . . . . . . . . . . . . . . . . . . .
39
3-1
Block diagram of a sensor radio.
3-2
Comparison of energy consumption between scheduled and contention based
MAC.
. . . . . ........
.....
..
. . . . . ..
. . . . ....
. . . . . . .
43
3-3
Multiple access methods: TDM,FDM and hybrid TDM-FDM. . . . . . . . .
45
3-4
Drift in transmitted packets due to reference clock error. . . . . . . . . . . .
46
3-5
Energy consumption of a sensor network using hybrid TDM-FDM with different Tstart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6
47
Energy consumption of a sensor network using hybrid TDM-FDM with different Er.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
47
LIST OF FIGURES
12
3-7
Energy consumption of a sensor network with equaliztion. . . . . . . . . . .
48
3-8
Example of slot allocation in different available bandwidth.
50
3-9
Average energy consumption of a sensor radio vs. available bandwidth.
3-10 Bandwidth allocation schemes in a cellular network.
. . . . . . . . .
. .
51
. . . . . . . . . . . . .
52
3-11 Variable bandwidth allocation scheme with time-frequency slots.
. . . . . .
52
. . . . . . . . . .
53
3-13 Guard time of slots in the same frequency channel. . . . . . . . . . . . . . .
53
3-14 Number of sensors in joint macrocell network. . . . . . . . . . . . . . . . . .
55
3-12 Notations used in a cellular network (frequency reuse=7).
3-15 Power consumption of the sensor network for a variable bandwidth allocation
(VBA) and a fixed bandwidth allocation (FBA) scheme. . . . . . . . . . . .
58
4-1
Transmitter architecture of binary and M-ary modulation . . . . . . . . . .
61
4-2
The ratio of the energy consumed by M-ary modulation to the energy consumed by binary modulation versus a, the ratio of the modulation circuitry
power consumption.
4-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
Effect of start-up time on the energy consumption of different type of modulation schem es.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4-4
Indirect modulation architecture using Z-A fractional-N synthesizer. ....
4-5
High data rate modulator using pre-emphasis filter and automatic calibration. 65
4-6
Open loop direct VCO modulation architecture . . . . . . . . . . . . . . . .
66
4-7
Block digram of a closed loop direct VCO modulation architecture. . . . . .
67
4-8
Effect of closed loop PLL on direct VCO modulation.
. . . . . . . . . . . .
68
4-9
Simulated eye diagram of a raw data.
. . . . . . . . . . . . . . . . . . . . .
69
4-10 Simulated eye diagram of a Manchester encoded data.
65
. . . . . . . . . . . .
69
4-11 Coherent demodulator of the base station receiver. . . . . . . . . . . . . . .
71
4-12 SNR degradation (-y) from closed loop modulation. . . . . . . . . . . . . . .
73
4-13 BER vs. Eb/N of closed loop modulation scheme in AWGN channel.
. .
73
. . . . . . . .
74
4-15 BER degradation due to quantization noise in fractional-N synthesizer. . . .
76
4-16 Equalization of the transmitted data at the base station. . . . . . . . . . . .
76
4-14 BER of closed loop modulation in a Rayleigh fading channel.
.
LIST OF FIGURES
13
81
5-1
Variable loop bandwidth technique. ........................
5-2
Bode plot of a PLL with variable loop switching method.
. . . . . . . . . .
81
5-3
Effect of quantization noise in loop switching. . . . . . . . . . . . . . . . . .
82
5-4
VCO control voltage in multi-stage variable loop bandwidth technique. . . .
83
5-5
Settling time vs. number of variable loop stages.
. . . . . . . . . . . . . . .
85
5-6
Settling time vs. intermediate loop bandwidth in a two stage variable loop
technique. .........
..................
..
.. ...
.
.......
85
. . . . . . . . . . . . . . . . . . . . . . .
86
. . .
89
6-2
Direct frequency synthesizer using DAC and lookup table. . . . . . . . . . .
90
6-3
Indirect frequency synthesizer using PLL.
. . . . . . . . . . . . . . . . . . .
91
6-4
Noise sources in a fractional-N frequency synthesizer. . . . . . . . . . . . . .
94
6-5
Effect of loop bandwidth on VCO and E-A noise. . . . . . . . . . . . . . . .
95
6-6
Power consumption of VCO and E-A in different loop bandwidths. . . . . .
96
6-7
Multi-modulus divider architectures. . . . . . . . . . . . . . . . . . . . . . .
98
6-8
Output noise of the PLL for different divider architectures.
. . . . . . . . .
98
6-9
Power consumption of divider and E-A.
. . . . . . . . . . . . . . . . . . . .
98
. . . . . . . . . . . . . . . . . . . . . . . . .
100
6-11 Schematic of the 6.5GHz VCO. . . . . . . . . . . . . . . . . . . . . . . . . .
102
6-12 A CMOS varactor in high capacitance mode.
. . . . . . . . . . . . . . . . .
103
6-13 A CMOS varactor in low capacitance mode. . . . . . . . . . . . . . . . . . .
104
. . . . . . . . . . . . . . . . . . . .
104
6-15 Circuit schematic of the divide-by-8 prescaler. . . . . . . . . . . . . . . . . .
107
6-16 Schematic of the divide-by-14/15. . . . . . . . . . . . . . . . . . . . . . . . .
107
6-17 Quantization error and divider range of single loop E-A and MASH.
. . . .
109
. . . . . . . . . . . . . . . . . . . . . .
109
. . . . . . . . . . . . . .
110
5-7
Schematic of digital lock detector.
6-1
Direct frequency synthesizer using frequency multipliers and dividers.
6-10 Circuit schematic of the VCO.
6-14 Capacitance of two varactor structures.
6-18 Architecture of the single loop E-A.
6-19 Circuit schematic of the phase frequency detector.
6-20 Circuit schematic of the charge pump. . . . . . . . . . . . . . . . . . . . . . 111
6-21 Charge pump of the variable loop frequency synthesizer. . . . . . . . . . . .
112
6-22 Loop filter of the frequency synthesizer.
113
. . . . . . . . . . . . . . . . . . . .
LIST OF FIGURES
14
6-23 Variable loop bandwidth frequency synthesizer. . . . . . . .
113
7-1
Measured phase noise at 5.68GHz.
. . . . . . . . . . . . . . . . . . . . . . .
116
7-2
Die photo of the 5.3GHz VCO.
. . . . . . . . . . . . . . . . . . . . . . . . .
116
7-3
Tuning characteristic of the VCO on main control input......
. . . . . .
117
7-4
Tuning characteristic of the VCO on modulation input.
. . . . . . . . . . .
117
7-5
Phase noise plot of the VCO.
. . . . . . . . . . . . . . . . . . . . . . . . . .
118
7-6
Phase noise at different frequencies.
. . . . . . . . . . . . . . . . . . . . . .
118
7-7
Figure of merit for different VCOs. . . . . . . . . . . . . . . . . . . . . . . .
120
7-8
Output spectrum of the fractional-N synthesizer at 6.3800GHz.
. . . . . .
121
7-9
Output spectrum of the fractional-N synthesizer at 6.3813GHz.
. . . . . .
121
. . . . . .
121
7-10 Power consumption of different components in the modulator.
7-11 Eye diagram of 5Mbps Manchester encoded data with 100kHz PLL loop
bandwidth (h = 0.3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-12 Eye diagram of 5Mbps raw data with 100kHz PLL loop bandwidth (h
7-13 Eye diagram of the 5Mbps Manchester encoded data (h
=
122
0.3). 122
. . . . . . .
123
7-14 Spectrum of the 5Mbps Manchester coded data .. . . . . . . . . . . . . . . .
123
7-15 Start-up transient of frequency synthesizer with fixed loop bandwidth. . . .
124
7-16 Start-up transient of frequency synthesizer with variable loop bandwidth.
.
124
. . . .
124
. . . . . . . . . . . . . . . . . . .
125
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
=
0.5).
7-17 Energy efficiency comparison of different high data rate modulators.
7-18 Die photo of the 6.5GHz modulator chip.
7-19 PCB test setup of chip.
A-1
Pin out of the packaged chip.
. . . . . . . . . . . . . . . . . . . . . . . . . .
139
A-2
Timing diagram of the register value programming. . . . . . . . . . . . . . .
141
A-3 Test board schematic.
B-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
Linearized model of the PLL. . . . . . . . . . . . . . . . . . . . . . .
146
B-2 Maximum phase difference in a fractional-N synthesizer. . . . . . . .
147
List of Tables
1.1
Comparison of wireless sensor network and conventional wireless device.
1.2
Specification of a machine monitoring sensor network (Courtesy of ABB Cor-
.
18
porate Research in Norway). . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
7.1
Summary of VCO test results . . . . . . . . . . . . . . . . . . . . . . . . . .
116
7.2
Figure of merit of different VCOs.
. . . . . . . . . . . . . . . . . . . . . . .
120
A. 1
Pin descriptions of the packaged chip.
. . . . . . . . . . . . . . . . . . . . .
140
A.2
Description of function register. . . . . . . . . . . . . . . . . . . . . . . . . .
142
15
16
LIST OF TABLES
Chapter 1
Introduction
1.1
Distributed Wireless Microsensor Network
Recent advance in micro-fabrication technology has expanded the use of integrated devices
in a wide variety of applications for commercial and military use. The distributed wireless
microsensor network is one of the emerging technologies that will enable reliable monitoring
and control of various environments that span from home networking and medical sensing
to machine diagnosis and military surveillance as shown in Figure 1-1.
In a distributed
microsensor network, a large number of sensor nodes are scattered over an environment of
interest to collect and transmit data to a base station, where the end user can extract the
necessary information.
The microsensor network presents several advantages to a macrosensor system. Due
to the large number of nodes, the microsensor network offers high quality fault tolerant
monitoring capability. While a failure of a macrosensor results in an event miss or possibly
an entire system failure, a network of sensors provides redundant monitoring of events,
which can be exploited for collaboration to ensure a high quality, fault tolerant system. In
addition, the small form factor of a microsensor node will be followed by ease of deployment,
which will enable new applications that are inconceivable with macrosensors.
The constraints of a wireless microsensor network are quite different from those of conventional wireless hand-held devices, as listed in Table 1.1. First of all, sensors have small
packet size (~
hundreds of bits) and low average data rate (~
17
hundreds of bits/sec) due to
CHAPTER 1. INTRODUCTION
18
/1V
Home Networking
Patient Monitoring
1I
Military Vehicle Tracking
Factory Machine Monitoring
Figure 1-1: Applications of distributed wireless microsensor network.
low event rates. Second, the transmission distance is very short, typically on the order of ten
meters or less, and the communication link is highly asymmetric (i.e., traffic flow is mostly
up-link from the sensors to the base station). Third, sensors have low mobility and form a
quasi-static network. Last and most important, the battery lifetime of the sensor network
is crucial and must be maximized. Since the network may be deployed in inaccessible or
hostile environments, battery replacement of a sensor node is undesirable, if not impossible.
Sensors are typically required to operate for years from a small energy source and therefore,
minimizing the energy consumption of the sensor network is a key design challenge. An
example that shows these requirements of a sensor network is listed in Table 1.2, which is
used for a machine monitoring industrial environment.
Specs
Average data rate
Packet size
Communication range
Traffic
Network mobility
Battery lifetime
_Sensor network
WLANs/cellular phones
< kbps
~ Mbps
~100 bits
> kbits
~10 meters
up to kilometers
mostly up-link
mostly down-link/bidirectional
static
mobile
few years
few hours
Table 1.1: Comparison of wireless sensor network and conventional wireless device.
1.1.
DISTRIBUTED WIRELESS MICROSENSOR NETWORK
Cell Density
< up to 300 in 5m x
19
5m
< up to 3000 in 100m x 100m
Range of Link
Message rate
(message = 2bytes)
Error Rate and
Latency
Lifetime
Size
Frequency Band
<
average :
maximum:
minimum
10-6
10 m
20 msgs/sec
100 msgs/sec
: 2 msgs/sec
after 5ms
10-9 after 10ms
10-12 after 15ms
5 years
slightly larger than AA battery
2.400 - 2.4835GHz (ISM)
5.15 - 5.35GHz (U-NII)
5.725 - 5.875GHz (ISM)
Table 1.2: Specification of a machine monitoring sensor network (Courtesy of ABB Corporate Research in Norway).
Due to such unique characteristics of the sensor network, design methodologies for conventional wireless devices would result in inefficient use of energy if they are applied to
microsensor network. Hence, various levels of system design hierarchy, from software algorithms and communication protocols to circuit techniques, must be explored to maximize
the lifetime of the sensor network. At the communication protocol level, the sensor network
must be operated with a scheme that is optimized for low duty cycle, short packet size and
short transmission distance. At the physical layer, the sensor electronics must be designed
for low duty cycle activity. This implies that the sensors must have small overhead during
start-up.
1.1.1
Related work
The advantages of the wireless sensor network has spawned many interesting work in the
recent years. In industry, IEEE 802.15 Working Group has been formed for wireless personal area network (WPAN), which focuses on the development of consensus standards for
short distance low rate wireless networks [1]. In academia, there are several projects that
involve wireless sensor network on various topics. One of the leading research in this area
is the pAMPS (Micro Adaptive Multi-domain Power-aware Sensors) project that focuses
on developing a complete and flexible power-aware system for wireless sensor networks [2].
CHAPTER 1.
20
INTRODUCTION
The goal is no longer simply the development of low-power techniques in hardware and software, but rather to create and develop a flexible platform that can adapt computation in
order to trade-off quality and system lifetime. Other research in the field of wireless sensor
networks include PicoRadio [3] and WINS [4] that focus on radio communication aspect
of the sensor network and smartDust [5] that focuses on micro-electro-mechanical-system
(MEMS) technology.
Many papers have also been published in a wide range of technical areas from software,
signal processing algorithms, communication protocols to physical layer circuit implementations [6, 7, 8, 9, 10]. Research in network protocols includes scalable coordination of sensor
networks [11], multi-hop routing protocols [12], and adaptive clustering algorithms [13] that
aim to increase the network lifetime and aid the self-configuration of an autonomous network. In the signal processing area, efficient data aggregation methods such as data fusion
and beamforming techniques have been explored, which trade-off communication and computation energy [14]. Research has also been conducted in digital and RF circuits as well as
the MEMS area that explore low power systems and circuit techniques as well as miniature
implantable devices with energy harvesting techniques [15, 16, 17, 18].
1.2
Contribution and Scope of Thesis
This thesis primarily focuses on two aspects of energy efficient sensor network design: communication protocol and physical layer electronics. While there exists extensive research in
both of these areas, many have neglected the impact of one level of system hierarchy on
another. That is, the underlying electronics of the physical layer were not considered in
communication protocol design, but rather, treated as an ideal black box, resulting in suboptimal solutions. In this thesis, designs are based on multiple levels of system abstraction
as shown in Figure 1-2. Impact of physical layer electronics is considered in the protocol
design and protocols are taken into account in the radio design. Designing across different
levels of system abstraction raises many interesting issues that are not seen when each level
is treated exclusively. These include:
o What are the issues that arise from low duty cycle activity and how do they affect
1.2. CONTRIBUTION AND SCOPE OF THESIS
21
Network
Sensor coordination, clustering, routing, etc.
Algorithms
Beamforming, Energy scalable computation
Link layer
Error control, coding
Technology
CMOS, BiCMOS, GaAs, etc.
00
Communication
protocol
Physical layer
electronics
L
Figure 1-2: System design hierarchy.
communication protocol?
" How do the non-ideal characteristics of the radio electronics, such as start-up transient
and frequency errors affect communication protocol?
" How does the choice of modulation scheme affect the energy consumption of the
transceiver electronics?
" Can the specifications of the radio be relaxed in order to lower the energy consumption?
* How can an energy efficient radio, not a low power radio, be designed?
As will be seen throughout this thesis, these design strategies lead to a much more
efficient solution than that of the traditional approach where design is focused only on one
level of system abstraction.
CHAPTER 1.
22
1.2.1
INTRODUCTION
Low power communication protocol
In communication protocol design, media access control (MAC) protocol and modulation
schemes are explored from the standpoint of circuit energy consumption. A detailed communication energy model, obtained from measurements, is introduced that incorporates
the non-ideal behavior of the physical layer electronics. This includes frequency errors and
start-up energy costs of the radio, which dominates energy dissipation for short packet sizes.
Using this model, various levels of communication protocols are proposed from an energy
perspective, which include MAC protocols, bandwidth allocation methods and modulation
schemes.
These methods are applied to a coordinated sensor network used for machine
monitoring in an industrial environment. The main contribution is that the protocol design
incorporates the detailed model of the radio that includes the non-ideal behavior , rather
than treating the radio as an ideal component.
As will seen, this has a great impact on the energy consumption of the sensor network.
1.2.2
Energy efficient transmitter
In the second part of the thesis, design methodologies for an energy efficient transmitter are
presented. From the sensor network's perspective, energy efficient transmitter implies the
combination of the following parameters in a transmitter: fast start-up time, high data rate
and low power consumption. Fast start-up time is necessary in order to minimize the energy
consumption when a sensor node is turned on from an off state. High data rate reduces
the transmit time of a packet and hence reduces the active time of the radio. Low power
will reduce the energy consumption during active and start-up states. Today's commercial
radios do not meet all of these requirements and lead to an inefficient use of energy. This is
shown in Figure 1-3, where energy consumption per bit is plotted versus packet size. The
graph shows two plots, one for conventional radio and the other for an ideal radio that
only consumes RF output power of OdBm, which is enough for a 10 meter transmission,
with 100% efficiency.
It can be seen that there is a large separation between the two
curves, especially when the packet size is small. While the overall gap can be reduced by
employing low power, high data rate techniques, the difference for short packets can be
improved only by reducing the start-up time of the radio. In order to achieve fast start-up
1.3.
23
OVERVIEW OF THESIS
OdBm output power at
1Mbps
104
......
Conventional radio
Ideal radio
103-
102
................................................................
101
Fast sartp
Low power k High rate
100
10-.
102
10
3
10
4
10
5
106
Packet Size (bits)
Figure 1-3: Comparison of energy efficiency between a traditional radio and an ideal radio
for different packet sizes.
time, variable loop bandwidth technique is used in a fractional-N synthesizer.
For high
data rate, the transmitter employs closed loop direct VCO modulation. To reduce power
consumption, trade-offs between the analog and the digital components of a fractionalN frequency synthesizer are exploited. A prototype transmitter implemented in 0.25pm
CMOS that demonstrates these ideas will be presented.
1.3
Overview of Thesis
This thesis demonstrates how design methodologies across various levels of system abstraction can improve the performance of a system, which in the scope of this thesis, is minimizing
the energy consumption. Each of the chapter presented in this thesis covers a specific topic
associated with design of energy efficient microsensor network. First of all, design considerations of a sensor node is studied in Chapter 2 with emphasis on the radio specifications
such as link budget, noise and start-up time. This sets up basis for investigations on MAC
protocol analysis and radio implementation. The low power MAC protocols are examined
24
CHAPTER 1.
INTRODUCTION
based on a comprehensive radio model that includes the non-ideal characteristics of the
radio. Different MAC protocols are compared and an optimal MAC protocol for a coordinated sensor network is derived. Next, implementation of an energy efficient transmitter
for microsensors are studied. Techniques for high data rate, fast start-up and low power are
examined and the experimental results from prototype chip are presented. With contributions of all these techniques from MAC to circuits, more than an order magnitude energy
reduction is possible compared to existing solutions.
Chapter 2
Design Considerations of a
Microsensor Node
The characteristics of a wireless sensor network are quite different from those of conventional
wireless hand-held devices. In this chapter, requirements of the sensor node will be investigated from the standpoint of circuits and communication protocols design. In particular,
requirements of the sensor radio will be analyzed, such as link budget, noise specifications
and start-up time.
2.1
Node Architecture
The basic building blocks of a sensor node can be categorized into the sensor, analog-todigital converter (ADC), digital signal processing (DSP) unit and radio as shown in Figure 21.
The ADC extracts digital bits from external stimulus such as temperature, pressure,
mechanical or acoustic vibration. The DSP unit processes the digitized bits into necessary
information and codes the data for efficient communication. The DSP unit also handles
communication control protocols and manages the sensor components to their appropriate
modes of operation such as active, idle, or sleep mode [193. The processed data is then fed
to the radio and sent to the base station by means of high frequency electromagnetic wave.
The complexity and power consumption of these components are quite dependent on
the application of the sensor network. In the general scope of sensor applications, the
25
26
CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE
\0
cu/
DSP
AD
DSP
Sensor A/D
Transceiver
Radio
Figure 2-1: Microsensor node architecture.
requirements of each sensor component can be regarded as the following.
First, the requirements of the ADC are quite loose considering where ADC technologies
stand today. The sensor applications typically exhibit signals that are very low in frequency,
typically less than a few kiloHertz at a resolution of less than 12 bits per sample [20]. Since
commercially available ADCs with tens of kilo-samples per second(kSPS) consume about
a milliwatt (mW) of power [21], the sensor ADC does not exhibit a bottleneck in the low
power microsensor node design.
The complexity of a DSP unit depends on the role of a sensor node as well as the application. For example, sensors in a collaborative network are assigned to different roles such
as sensing, relaying or beamforming [12]. Hence the workloads of the DSP will vary from
as little as bit sequencing to complex algorithms, such as FFTs and Viterbi decoding [22].
While the recent technology advance in DSP has shown that dedicated solutions consume
orders of magnitude less power than a general programmable CPUs, which consume several
hundreds of mW [23, 24, 25], designing a low power DSP encompassing all the functions
necessary for a microsensor node will be a challenging task.
The radio module is the most critical bottleneck in the microsensor node design. Unlike
the DSP where complexity scales with functionality, the radio is required to operate under
a certain specification that cannot be scaled or compromised, such as output RF power and
noise. Considering that today's state-of-the-art low power transceivers [26, 27, 28] consume
hundreds of milliwatts of power with many off chip components, designing a radio for the
microsensor node will be a difficult task.
2.2. TRANSMITTER REQUIREMENTS
27
From the above discussions, the DSP unit and the radio unit are the critical components
in the microsensor node. While the DSP unit exhibits challenges of its own, the focus of this
thesis will be on reducing the energy consumption of the radio by improving the physical
layer electronics and communication protocols. In the following sections, specifications of
the radio components are developed. First, radio wave propagation is studied in order to
carry out the link budget analysis.
2.2
2.2.1
Transmitter Requirements
Link budget
Knowledge of channel characteristics is essential in a communication system design. In a
wireless network, radio wave propagation must be analyzed in order to determine various
specification of the system, such as output power and complexity of equalization.
Large scale path loss
In an ideal free space environment, the radio wave is attenuated along the transmit distance
(D) as D 2 . In reality however, the surrounding environments, especially indoors, often
cause reflections and scattering of the original signal that result in attenuation on the
order of D", where the path loss factor n varies from 3 to 4. Since the path loss depends
heavily on the surroundings of the radio wave's propagation path, it cannot be exactly
modeled for any arbitrary environment. However, for the general purpose of sensor network,
valid assumptions can be made about the channel based on various test results that have
already been reported [29, 30, 31, 32].
For sensor networks, short distance path losses
for indoor environments will be considered since they exhibit harsher conditions for radio
waves than outdoors. The reported measurement results [32] show that path loss at 10 meter
distance can vary from as little as 40dB to as large as 70dB depending on the surrounding
environment. The large path loss of 70dB is seen in environments that are likely to absorb
electromagnetic energy, such as office buildings with concrete walls, while small path loss
is seen in industrial surroundings with metallic objects that have good reflections of the
radio waves. In terms of path loss factor n, the indoor office environments show n of 3 to
28
CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE
Receiver power vs. distance
-20
-
-25-
Path3
Pathi n=1 .09
Path2 n=1 .03
Pa
n=1.37
Path2
-
O-45
Palhi
-50 -
-
-55 -
-60-
-65-70
10.
10
..
10
Distance(meters)
Figure 2-2: Received power vs. transmit distance (Courtesy of ABB Corporation Research
in Norway).
4, while factory environments with steel machinery show n of less than 2. An example of
path loss that is seen in an industrial factory is shown in Figure 2-2, where it can be seen
that the path loss factor is less than 2, which points out the vigor of reflected signals from
metallic objects. It also shows that the received power level does not drop monotonically
with distance, representing the effect of multi-path in non-line of sight (LOS) conditions.
Multi-path fading
While large-scale path loss describes the average signal attenuation as a function of spatial
separation, small-scale fading characterizes the statistics of the rapid variation of signal
amplitude over a short period of time [33].
For indoor environments that are prone to multi-path fading, the two main properties
of interest are the RMS delay spread and the probability distribution of the signal envelope.
The RMS delay spread measures the time dispersion of a signal. It gives an indication of
the time interval between the reception of the first and the last multi-path components.
In order to avoid equalization, the data symbol period must be kept longer than this time
interval since otherwise channel-induced inter-symbol interference will occur.
2.2.
TRANSMITTER REQUIREMENTS
29
In an office environment with typical length of 10 to 30 meters, measurement results
show that the RMS delay is around 10 to 100ns [34, 311, which translates to more than
10MHz of coherence bandwidth'. For industrial environments filled with metal equipment,
the RMS delay is greater since metals have good reflection coefficients and thus it takes
longer to attenuate the multi-path components. Measurement results show that the RMS
delay for a 30 meter factory room filled with metal machinery is about 80ns, for which the
coherence bandwidth is approximately 3MHz [32].
While the RMS delay spread limits the maximum data rate without equalization, the
probability distribution of the signal envelope determines the amount of transmit power
required to achieve a certain BER. In an obstructed environment, the probability density
function (PDF) of the signal envelope can be characterized by a parameter
KdB
10 log (Pedominant)
KdB
defined as
(2.1)
If KdB is large then the strength of multi-path components are small and the PDF of
the envelope is approximately Gaussian. If KdB is small, the multi-path components are
strong and the PDF approaches a Rayleigh distribution. In typical indoor environments,
KdB is measured to be around 1dB, for which the distribution is close to Rayleigh [331.
Link Budget
Based on the analysis given in the previous section, link budget of the sensor transmitter
can be calculated. The received signal to noise ratio (SNR) is
SNR = Preceived/W
(kT)Nf
(2.2)
where, Preceived is the signal power, Nf is the noise figure of the base station receiver,
W is the bandwidth of the transmitted signal and kT is the thermal noise constant. Taking
'The delay spread will roughly depend on the size of the room, since the arrival time of a reflected signal
is a function of radio wave's traveled distance [35].
CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE
30
path loss into account and taking the logarithms of each side, Eq. 2.2 at room temperature
becomes
SNR(dB)
-
p(dBm)
(dB)
-
N(dB)
-
10
log
(W)(Hz) _
7 4 (dBm/Hz)
(2.3)
where Pout is the output power of the transmitter, Poss is the average large scale path
loss and a is the variation of the path loss caused by fading. In order to calculate BER,
we must take into account the statistical variation of a, which is Rayleigh distributed. The
Raleigh fading conditions degrade the BER significantly more than an Additive White Gaussian Noise (AWGN) channel, resulting the BER to drop linearly with Eb/No rather than
exponentially, as shown in Figure 2-3. It can be seen that more than 20dBm output power
is needed to achieve BER as low as 10-6 for an uncoded transmission. This is obviously
an unacceptable amount for a sensor node. The BER can be improved by employing diversity and coding techniques. Diversity technique can be imposed on the high powered base
station, such as spatial diversity (multiple antennas) or time diversity (RAKE receiver).
The BER performance can also be improved at the transmitter side by employing forward
error correcting codes, which is effective in fading conditions as shown in Figure 2-3. In the
case of indoor environment, convolutional coding is appropriate due to the short packet size
and low circuit overhead at the transmitter [36]. Using these techniques, it is possible to
achieve less than 10-6 BER with 20dB of SNR in a 70dB path loss condition, which relates
to about -10dBm output power at the sensor transmitter with a data rate of 1Mbps. This
verifies the assumption that output power is negligible to power consumption of other radio
electronics.
2.2.2
Phase noise
Phase noise of the transmitter degrades the SNR of the signals in the adjacent channel. To
understand this problem, consider two sensors transmitting signals Si and S2 in adjacent
channels as shown in Figure 2-4. If the signal Si undergoes a larger attenuation (deeper
fade) than S2, the resulting degradation in SNR of Si at the base station can be expressed
2.2. TRANSMITTER REQUIREMENTS
loss=70dB,
Path
11
L :
31
Receiver NF=10dB, Rate=lMbps, Rayleigh flat fading
A
:: ::
-02
..........
10
......
......
..
.....
..
.
..
. .......
.
..
..
...
..
..
....
..
.I..
....
..
..
..
....
......
....
...
.
...
.
.....
.....
....
...
..
..
..
....
..
..
..
..
.I...
..
. .......
..
....
..
..
..
.;..
..
...
..
..
..
..
..
...
....
...
...........
............ F ... .... ......... ..........
..............
0-
.0
.........................
....................
.0
R
0
112,:
...............
R i'2/5:; K
R:: :1/2 1<4-. /
10-6
...
......
..
.............
... ................... ...........- ..................
..........
10-
.......
...
......
.... ...... ....
......... ..... .....
... .........
10-30
-10
-20
0
10
..........
30
20
Output Transmit Power (dBm)
Figure 2-3: BER vs. output power in a slow Rayleigh fading channel.
as
SNR
ff Si(f)df
f - >f
PsI
~S2(UO)(Ul - fO)
1
1
D(fo) (fl - fo)
DD(fo)W
ffl S2 (f )df
Psi
Ps2
2(ho)
(2.4)
(h - Ao)
(2.5)
where Si(f) is the power spectral density of the signal Si, P 2 is the total power of the
signal in the bandwidth W, from fo to fi, D is the excessive attenuation that Si undergoes,
and
(2(f)
is the phase noise of S 2 at f frequency from the carrier. Rearranging the terms
and taking logarithms, we achieve
-2(fo)
= -SNR(dB)
-
10 log D - 10 log R
(2.6)
To achieve 30dB fading margin and 20dB SNR when the signal bandwidth is 2MHz, the
required phase noise is -110dBc at 1MHz from the carrier.
CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE
32
S2 0f)
B.S.
D
S2
%
St
SNR
fo
f,
fch
Figure 2-4: Degradation of SNR due to phase noise in adjacent channel.
sample
Tek Run: 500kS/s
l
A: 466Jis
0: 448lis
t
....
. .. . . . .. . .....
t
. . . . ..
.. . . .
....
. . .. . .. .
. . . .. . .. .
.. .
T'
C1 HIgh
. .. . . ...
......... ..
i -4 F 1-'4 i- 1-4 .
..........
[....... ...
W
.......
................ ..
.... .... ...
... .. .......
L
S0mv
sam
l OOs
ni J-
Tos v
11 Jan 2001
15:4S:OS
Figure 2-5: Start-up transient of a commercial low power transceiver (Tstart r 470ps).
2.2.3
Start-up time
Start-up time is a critical parameter in short packet low duty cycle communication systems.
In a sensor network, the radio module needs to be turned on/off during the active/idle
periods (i.e. duty eycled) in order to save power. Unfortunately transceivers today require
initial start-up times on the order of hundreds of microseconds to go from the sleep state
to the active state as shown in Figure 2-5, where VCO control voltage is plotted against
time. This is achieved from a commercial low power transceiver [26] which is capable
of transmitting data up to 1Mbps while consuming 81mW. For short packet sizes, the
2.2. TRANSMITTER REQUIREMENTS
33
transient energy during the start-up can be significantly higher than the energy required by
the electronics during the actual transmission This effect of start-up transient is shown in
Figure 2-6, where energy consumption per bit is plotted versus packet size.
We see that as the packet size is reduced, the energy consumption is dominated by the
start-up transient and not by the transmit on-time.
R=1 Mbps, Tstartup=450p s, P =81mW, P =QdBm
::3O
10
Q.
CC
10~7
1
31
10,
10,
Packet size (bits)
104
105
Figure 2-6: Effect of start-up transient on transmitter's energy consumption in a 100 bit
packet transmission.
2.2.4
Data rate
As will be seen in the later part of this thesis, power consumption of the transmitter
in GHz frequencies is dominated by the frequency synthesizer and is not affected by the
data rate. Therefore, high data rate will allow lower transmitter energy consumption by
reducing the transmit time of a fixed sized packet. Unfortunately, this is true only from the
circuit's perspective. From the communication standpoint, increase in data rate will require
training sequence to overcome frequency selective fading as the occupying bandwidth of the
transmitted signal exceeds the coherence bandwidth of the channel. Hence, higher data rate
will not necessarily reduce the transmit time since packet length will increase from training
sequence. In such cases when equalization is necessary to overcome frequency selective
fading, the on-time of the transmitter when sending an L-bit packet with rate R bits/sec
CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE
34
can be represented as
Ton-tx =
Tpacket +
Ttraining-sequence --
L
(2.7)
+ atrainTdelay
where Tdelay is the effective excess delay of the channel which determines the coherence
bandwidth and atrain is a variable that depends on the the type of equalizer, characteristics
of delay spread, SNR, target accuracy, etc.
As the data rate increases, Eq. 2.7 will be
dominated by the length of training sequence and hence high data rate will no longer offer
significant energy reduction.
Therefore, it is important to take the effect of frequency
selective fading into account when the data rate approaches the coherence bandwidth of
the channel.
2.3
Considerations on Receiver and Base Station Design
Although the sensor's primary function is to transmit information to the base station,
receiver on the sensor node is also necessary in order to handle various control signals from
the base station. In typical wireless devices, the receiver circuitry consumes 2-
3 times
more power than that of the transmitter circuitry, resulting in hundreds of milliwatts of
power. While the receiver is not used as often as the transmitter in the sensor network,
it is important to consider how the receiver power consumption can be reduced.
For a
microsensor network, complexity of the sensor's receiver can be reduced by exploiting the
high-powered base station. That is, specifications on sensitivity and noise figure can be
reduced if the base station transmits at maximum power that the FCC allows. For example
at 2.4GHz ISM band, up to 30dBm output power can be transmitted, which would require
about -20dBm sensitivity with 50dB path loss. In addition, requirements on dynamic range
can be reduced if power control is employed at the base station. These can significantly
reduce the power consumption of the receiver components such as mixers LNA and IF
amplifiers.
2.4. SUMMARY
2.4
35
Summary
Design considerations of a microsensor node were studied with focus on the radio. The
important criteria of the transmitter are link budget, start-up time, data rate and noise.
The link budget analysis shows that RF output power of the transmitter is small compared
to the power consumption of the transmitter electronics. Start-up time is found to be a most
critical parameter for low duty cycle sensor communications as it may dominate the energy
consumption. While data rate reduces the on-time of the transmitter, training sequence
must be considered if the data rate exceeds the coherence bandwidth of the channel. Lastly,
the noise must be kept below a certain level to ensure enough SNR. A low power receiver
on the microsensor node can be implemented by exploiting the high-powered base station.
36
CHAPTER 2. DESIGN CONSIDERATIONS OF A MICROSENSOR NODE
Chapter 3
Low Power MAC Protocol
The need for medium access control (MAC) protocol arises from limited bandwidth. The
available bandwidth determines the capacity of a communication system with a given energy,
as described by the well known equation by Shannon. However, MAC protocols studied
in this chapter are viewed from a different perspective, from the standpoint of energy
efficiency of the entire system and not just the symbol energy that is typically considered in
conventional communication system design. Hence, bandwidth plays a different role from
its traditional role.
To develop low power MAC protocols, a radio model that includes
non-ideal behavior of the physical layer electronics, is introduced.
Based on the model,
low power MAC protocols for a single cell network and multiple cell network are explored.
These are applied to a coordinated sensor network used in an industrial environment. It
will be seen that bandwidth is indeed an important factor in power consumption, in that
larger available bandwidth leads to lower energy consumption of the network. However, it
will be seen that this is in a different sense than how it is traditionally perceived.
3.1
Previous Work
The study of communication protocols for wireless sensor network has mostly been concentrated on network level protocols such as scalable coordination of sensor networks [11],
multi-hop routing [12], and clustering algorithms [37] in an autonomous sensor network.
The design of MAC protocols for microsensor networks has not been considered by many
37
CHAPTER 3. LOW POWER MAC PROTOCOL
38
researchers and hence its impact on network's energy consumption has not been studied in
depth. In a broader range of wireless networks that include wireless LANs, there are some
published results on low power MAC protocols [38, 39]. In Kishore's work [38], an energy
efficient hybrid CDMA/TDMA is suggested, which schedules the network traffic based not
only on the priority of the user's information but also on the user's battery status. The
average lifetime of a user can be increased by granting transmission priorities based on the
user's energy status. In the paper by Chen [39], various standard MAC protocols such
as IEEE802.11 and Bluetooth are evaluated. The conclusion drawn is that protocols with
lower number of transceiver activity results in lower power and hence, collisions in transmitted packets should be avoided to lower the number of retransmissions. These papers
however, did not address the energy consumption of the radio in a detailed manner. The
MAC protocols studied in this chapter will be examined based on a detailed radio model,
which is described in the next section.
3.2
Radio Model
The sensor radio is composed of many modules; VCO, frequency synthesizer, mixers baseband DSP, filters, etc. To analyze the radio power consumption for a MAC protocol, these
modules are categorized into three components: transmitter, output power amplifier and
receiver, as shown in Figure 3-1. Note that transmitterwill be regarded as the modulator
part of the radio (i.e., mixer, frequency synthesizer) and excludes the output power amplifier stage. The output amplifier stage is decoupled from the transmitter because its power
consumption is primarily determined by the link budget, which the designer does not have
any control over.
The average power consumption of the radio can be described by the
following equation,
Pradio =
Ntx[Ptx(Ton-t + Tstart) + PoutTonritx]
+NrxPrx(Ton-rx + Tstart)
(3.1)
where Ntxlrx is the average number of times per second that the transmitter/receiver is
39
3.2. RADIO MODEL
Ptx
Baseband
DSP
-
Orx
Figure 3-1: Block diagram of a sensor radio.
used per unit time, Ptx/rx is the power consumption of the transmitter/receiver, Poat is the
output transmit power, Ton-x/rx is the transmit/receive on-time (actual data transmission/reception time), and Tstart is the start-up time of the transceiver. It is assumed that
transmitter and receiver shares the same frequency synthesizer and since the start-up time
is determined by the frequency synthesizer, start-up times of transmitter and receiver are
equal. For an environment monitoring application, Nt. depends on the event occurrence
rate of the application (i.e. how many times the sensor must report to the base station) and
Nrx depends on the media-access protocol used. Also note that T"'_t. = L/R, where L is
the length of a transmitted packet in bits and R is the data rate in bits per second. In this
radio model, the power amplifier needs to be on only when transmission occurs. During
the start-up time, data cannot be sent or received by the transceiver, because the internal
frequency synthesizer of the transceiver must be locked to the desired carrier frequency
before data can be modulated or demodulated.
It is important to highlight a few key points about this specific radio model. First,
it should be noted that power consumption of the transceiver dominates over the output
transmit power(Px/,.x
< Pot). As studied in Section 2.2.1, the required output power for 10
meter distance is less than OdBm (1mW), which results in less than 10mW even with a power
amplifier with 10% efficiency. Therefore the power consumption of the radio electronics
is dominated by the analog RF circuitry which typically consumes tens to hundreds of
milliwatts (mW) [9, 26]. In addition, the transmitter power (Px) does not vary much over
CHAPTER 3. LOW POWER MAC PROTOCOL
40
data rate to a first order approximation.
In GHz frequency bands, power consumption
of the transceiver is dominated by the frequency synthesizer which generates the carrier
frequency and it is not effected by the data rate to the first order [40]. Hence for low power
operation, it is desirable to send the data at maximum rate in order to reduce the transmit
on-time (T 0ntz). Second, the start-up time (Tstart) should receive special attention due
to the short packet size.
In order to save power, the radio module needs to be turned
on/off during the active/idle periods (i.e., duty cycled). Unfortunately transceivers today
require initial start-up times on the order of hundreds of microseconds to go from the sleep
state to the active state. For short packet sizes, the transient energy during the start-up
can be significantly higher than the energy required by the electronics during the actual
transmission (i.e. Tstart > Ton-tx).
Hence it is important to take this inefficiency into
account when designing energy efficient communication protocols.
Lastly, although the
data traffic is mostly up-link from the sensors to the base station, down-link may also be
necessary for certain protocols. That is, Ntx is governed by the application scenario and
Nrx is determined by the protocol. It should also be noted that Prx is usually 2 - 3 times
higher than Px in typical commercial radios and hence MAC protocol should try to avoid
receiver activity.
3.3
Low Power MAC Protocol
A media access protocol determines the activity of the transceivers, which directly impacts
the power consumption of a network. In this section, low power MAC will be developed for
a coordinated sensor network for the one shown in Table 1.2.
3.3.1
Contention vs. scheduled MAC
Multi-access schemes can be categorized into contention based or schedule based schemes.
The contention based MACs, such as Aloha, CSMA or slotted Aloha, are generally used for
networks that do not have a scheduled occurrence of events. Scheduled schemes on the other
hand, operate by means of strict scheduling of time, frequency or code as seen in TDMA,
FDMA or CDMA. The pros and cons of these two methods depend on the application.
3.3.
LOW POWER MAC PROTOCOL
41
For a sensor network, scheduled MAC protocols have the advantage that the latency of
a transmitted packet is guaranteed and that there is no collision of transmitted packets,
thereby eliminating the need for retransmission. The disadvantage is that bandwidth may be
wasted since the scheduling will be based on a worst case scenario, which is when the event
rate is at maximum and all the sensors try to transmit to the base station. Contention
based schemes on the other hand, have the advantage that the bandwidth can be used
more efficiently. If the average event rate is low and sensors seldom transmit to the base
station, then a sensor node can fully utilize the bandwidth when transmitting a packet.
The disadvantage is that the latency of a packet is not guaranteed due to retransmissions
caused by collision. The more severe problem of the contention based MAC arises from
the fact that it requires handshaking between the base station and the sensor every time a
packet is sent. This means that the receiver on the sensor side must be activated every time
a packet is sent. Therefore, sensors in contention scheme will always have more transceiver
activity than those in scheduled scheme. It should be noted that more transceiver activity
does not necessarily mean higher energy consumption, since the transceivers in contention
scheme will be able to use more bandwidth, which may be helpful in reducing the energy
consumption of the radio.
In order to compare the power consumption of the sensors in both schemes, let Ps, P,
denote the average power consumption of a sensor in scheduled scheme and contention based
scheme respectively. The transmitter's energy consumption is represented by Et, and Etz,,
for scheduled and contention based schemes respectively. The power consumption can be
described by the following equation,
Ps
=
Pc =
NtxEtx + NrxErx = REEtx + NrxErx
(3.2)
Ntx(1 + mc)(Etx,c ± Erx) = RE(1 + mc)(aEtx + Erx)
(3.3)
where RE is the average number of times that a sensor transmits a packet to the base
station (i.e., event rate), a is the ratio of transmitter's energy consumption between the
two schemes (a = E
) and m, is the the average number of retransmission trials before a
CHAPTER 3. LOW POWER MAC PROTOCOL
42
packet is successfully sent to the base station for a contention based scheme. In a scheduled
MAC, the number of receiver activity Nrx is determined by the protocol, while in a contention based scheme, it is equal to number of the transmitter activity due to handshaking.
Note that the energy consumption of the sensor receivers for both schemes are assumed
to be equal. The transmitters may consume different energy, since transmitter circuitry
in contention based scheme will benefit from the fact that it is given more bandwidth.
Comparing the above two equations by subtracting Eq 3.2 from Eq 3.3,
P, - P, =
R {(am, + a - 1)Et, + (1 + m,)EIx} - NrxEr.
(3.4)
In order for a scheduled MAC to achieve lower power than a contention based MAC, the
average receiver usage Nrx determined by the scheduled protocol must satisfy the following
inequality.
N,,
<
RE
1 + mc + (amc + a - 1)E
(3-5)
(3.6)
REKc
In other words, the scheduled protocol should make sure that the receiver usage is lower
than the event rate, RE, by a factor of Kc, to achieve lower energy than a contention
based scheme. It can be seen that K, is a function of average retransmission trials m, in a
contention based scheme. The factor K, is plotted against me in Figure 3-2 for different a.
me is regarded as a variable since it is a function of many parameters including available
bandwidth, event rate, etc. In the figure, scheduled scheme achieves lower power in the
region below the plotted line, which is where the Nrx is lower than the event rate by a
factor of Kc. a = 1 and a = 0 are the upper and lower limits for the transmitter energy
consumption of Etx,c.
In order to figure out how well a scheduled protocol must be designed to achieve lower
energy than the contention based schemes, N.
must be calculated. It will be seen in the
next section that the Nrx is given by the following equation,
3.3. LOW POWER MAC PROTOCOL
43
2. 5
-
-
=1
a=0.5
at=0
2-
eU
i .
S
0.5L
0
0.2
0.4
0.6
C
0.8
1
m : Average number of retransmissions
Figure 3-2: Comparison of energy consumption between scheduled and contention based
MAC.
Nrx
-
(3.7)
Tguard
where p is the frequency difference between sensors' reference clock and Tguard is the
guard time between two transmitted packets. Typical low cost crystal oscillators today have
p of about 50ppm. For a 100 sensor network that sends 100bit packet at 1Mbps with 10ms
latency, Nrx comes out to be two times per second. Therefore, if the average event rate
is more than one occurrence per second, then scheduled scheme will always achieve lower
energy than contention based scheme. If the average event rate is lower, than the designer
must consider other factors such as m, and a. In the example of the factory machine
monitoring, RE
MAC.
> Nrx, and therefore scheduled scheme is better than the contention based
CHAPTER 3. LOW POWER MAC PROTOCOL
44
3.3.2
Hybrid TDM-FDM
TDMA-FDMA
In this section we derive a low power MAC protocol based on the radio model from Eq. 3.1
for a single cell network where a high powered base station gathers data from the sensors.
It is assumed that the bandwidth is sufficiently enough such that network's maximum
possible aggregate data rate (i.e., when all sensor transmit to the base station) is less than
the available bandwidth. This is a valid assumption for for general low data rate sensors
that use ISM band with more than 80MHz of bandwidth at 2.4GHz and 5.8GHz. Assuming
we have control over data rate, whether by means of designing a custom transmitter or
choosing from an off-the-shelf component, T0 , is minimized in TDMA since the bandwidth
is at maximum, allowing the highest data rate. For FDMA, the available bandwidth is at
minimum, resulting in the longest on-time. A hybrid scheme of TDM-FDM is also possible,
where both time and frequency are divided into transmission slots. This is illustrated in
Figure 3-3 where shaded area indicates a valid transmit slot for sensor Si. In cases where
time division is employed, we should note that a down-link from the base station to the
sensors is required in order to maintain time synchronization among the sensors [41]. Due
to the finite error among each sensor's reference clock, the transmitted packets will drift
in time. For example, suppose two sensors have reference clocks that are p ppm apart.
After these two sensors are synchronized, the sensor with slightly higher frequency will
send the packet sooner than originally scheduled as shown in Figure 3-4. This will continue
in time and the sensor with faster clock will eventually smear into the other time slot. The
minimum time that take for these two sensor to collide is hence given by Tguard/PIn order to avoid collision, the base station must send out sync signals. Hence the sensor
receiver must be turned on every so often to receive these sync packets. The number of
receptions (N,,) depends on the guard time (Tgiard) which is the minimum time difference
between two time slots in the same frequency band, as shown in Figure 3-3. If two slots in
the same frequency band are separated by Tguard, it will take Tguard/p time for these two
packets to collide, where p is the difference between the two reference clocks. Hence the
sensor must be resynchronized at least p/Tuard number of times every second.
3.3. LOW POWER MAC PROTOCOL
45
Hybrid (h=3 )
FDMA (h=n)
A
U) T
U) I
I
Ton Tguard
ime
Tavail
4
H4..
FIIIH
TDMA (h=1)
Hybrid (h=2)
Tiat
Figure 3-3: Multiple access methods: TDM,FDM and hybrid TDM-FDM.
This is described in Eq. 3.8, where W is the total available bandwidth, L is the size
of the transmit packet in bits, Tiat is the latency requirement of the sensor data, h is the
number of channels in the given bandwidth W, Tavaii is the time difference between start of
two packets and M is the number of sensors. It is also assumed that the data rate is equal
to the occupying signal bandwidth and hence T 0, = L/(W/h).
N
=
_
Tguard
p
Tavail
-
p
Ton
(
-
(3.8)
-)h
From the above equation, we see that as the number of channels decreases, guard time
becomes larger and receiver activity is reduced. It is also apparent that the advantage of
pure FDMA is that it does not need a receiver (i.e. Tguard -+ 00, Nrx = 0).
Since (A + B) ;> 2vAiB, by plugging in Eq. 3.8 into Eq. 3.1, we can find an analytical
formula for the optimum number of channels which gives the minimum power. This is given
in Eq. 3.9, where in addition to the previous notations, h0 pt represents the optimum number
of channels to achieve lowest power consumption.
CHAPTER 3. LOW POWER MAC PROTOCOL
46
Frame I
Frame 2
Frame n
Frame 3
collision!
SI's ref clk
.-. .LF
S2 's ref clk
L
- -
Figure 3-4: Drift in transmitted packets due to reference clock error.
(T-
oc
6Prx(Ton-rx + Tstart)
Data)Nx(PX + pout)Da
Pr
Ntxt
(39
(3.9)
We see that hopt is determined by the power consumption ratios between the transmitter
and the receiver. As expected, receivers which consume less power favor TDMA with fewer
channels, while receivers with larger power prefer FDMA with more channels.
An example of the previous analysis is performed in a scenario where a sensor on average
sends twenty 100-bit packets/sec (Nt. = 20/sec, Data = 100bits) with 5ms latency require-
ment (Tat = 5ms). The bandwidth available to the cell is 10MHz (W = 10MHz), and
the number of sensors is 300. The resulting average power consumption is plotted in Figure 3-5 and 3-6, where average power consumption is plotted versus the number of channels
(i.e., h = 1: TDMA, h = 300: FDMA). The graph shows power consumption for different
Prx/Px and Tstart- It can be seen that h0 pt increases for higher receiver power, so that the
number of receptions is reduced. As the start-up time increases, the energy consumption is
dominated by the start-up time and choice of MAC does not effect the energy consumption
47
LOW POWER MAC PROTOCOL
3.3.
P =300mW, 100bit packet
10,
-
P =81mW, 100bit packet, T ,0=450p s
P =50mW
E
E
C
P =100mW
P =300mW
10'
0
0
E
0
0
0
a)
010
(3
0
0)
Tstn=100p s
0'
---~
--- ~
0100
1
~1
T start=1 Op S
101
number of channels(h)
60
L4
102
10,
number of channels(h)
102
Figure 3-5: Energy consumption of a sensor Figure 3-6: Energy consumption of a sensor
network using hybrid TDM-FDM with different network using hybrid TDM-FDM with different
Erx.
Tstart.
very much.
Again, the reason why TDMA with minimum on-time does not achieve the
lowest power is because of the receiver power consumption from network synchronization.
As the data rate increases, guard time becomes smaller and the receiver power starts to
become a significant portion of overall power consumption.
3.3.3
Effect of fading on MAC
The previous analysis demonstrates how appropriate MAC protocol can reduce the energy
consumption of a network.
It is under the assumptions that power consumption of the
radio is dominated by the transceiver electronics, which does not change over data rate.
However, it was seen in Chapter 2 that excessive data rate can increases the packet length for
equalization to overcome frequency selective fading. If the training sequence for equalization
is taken into account, the radio model now becomes,
I
P'adio
=
Ntx [Ptx + Pout] (
L
+ atrainTelay) + PtxTstart
+NrxPrx(Ton-rx + Tstart)
(3.10)
The result of optimum MAC scheme from the revised radio model is shown in Figure 3-7,
48
CHAPTER 3. LOW POWER MAC PROTOCOL
which assumes that excess delay of the channel is 10OOns. The graph shows that the energy
consumption of TDM is increased as due to equalization. However, the optimum number
of channel for MAC does not vary much since effect of equalization is small when the data
rate is below coherence bandwidth.
P -=81mW, PX=100mW, 100bit packet, T a=450p s
.
10'
. . . .....
.
. . . ....
.
I i i i i i iI
E
0
E
U)
0
0
a= 10
0)
a=2
100
Ca=0
0
UC
I
I i i I i . Ii
101
102
number of channels(h)
Figure 3-7: Energy consumption of a sensor network with equaliztion.
VARIABLE BANDWIDTH ALLOCATION SCHEME
3.4.
3.4
49
Variable Bandwidth Allocation Scheme
The previous section presented a low power design methodology for a single cell sensor
network with a fixed cell density. This section investigates how energy consumption can be
reduced in a multi-cellular network where each cell has a different cell density.
3.4.1
Energy vs. bandwidth
In the traditional perspective of communications, available bandwidth determines the required energy of a transmitted symbol. However, for short distance communications where
the symbol energy is small compared to the transceiver energy, bandwidth has a different
impact on energy consumption. To see this illustratively, consider an example where a cell
consists of 6 sensors and each sensor sends a 100bit packet every ims at 1Mbps. Using hybrid TDM-FDM, two schemes are shown in Figure 3-8, where the scheme in (a) has larger
available bandwidth than the scheme in (b). While the sensors in both scheme meet the
latency requirement of ims, the sensors in scheme (a) have larger guard time and hence less
receiver activity. Therefore, larger available bandwidth reduces the energy consumption
of the sensor network. This can be analytically shown by describing the average energy
consumption of a sensor radio with the following equation, which is derived from Eq 3.1
and Eq 3.8.
Eavg
=
Etx + Nr Erx
=
Etx +
Ntx
=
Etx +
T
Ni( -
L-)h
Erx
P
TguardNtx
Erx
(3.11)
If the specification of the radio is fixed (i.e., data rate, power consumption), then the
energy consumption of the sensor radio is a function of available bandwidth, W. This is
shown in Figure 3-9, where average energy consumption is plotted versus W. The energy
consumption reduces as the available bandwidth increases, due to the lower receiver activity.
CHAPTER 3. LOW POWER MAC PROTOCOL
50
__ __
_________=____
Ton=100us
r W=JMHz
Tguard,2
Tguard,j
(a) Available bandwidth = 3MHz
(b)Available bandwidth = 2MHz
Figure 3-8: Example of slot allocation in different available bandwidth.
3.4.2
Variable time-frequency slot allocation
One of the unique characteristics of the sensor network is that variation in cell density is
large, as shown in Table 1.2. Since the available bandwidth impacts the energy consumption
of the sensors, the bandwidth must be well managed in order to increase the battery lifetime
of the sensors. In a cellular network with frequency reuse, bandwidth is typically allocated
equally to all the cells regardless of its density. This scheme is wasteful in bandwidth if the
network has large variation in the cell density. A better way of bandwidth allocation is to
assign bandwidth according to the number of sensors in each cell, as shown in Figure 310(b).
Basically, cells with more sensors are assigned larger bandwidth than those with
fewer sensors. Unfortunately, the problem of this approach is that it is difficult to allocate
different amounts of bandwidth as the cellular network becomes large.
For example in
Figure 3-10(b), suppose we have allocated different amounts of bandwidth to cells A through
G and F ended up consuming dominant part of the total available bandwidth. If cells H,I
or K has more sensors than F, then the bandwidth allocation scheme on A ~ G must be
revised. As the cellular network becomes large, assigning bandwidth to the cells will resort
back to the fixed bandwidth allocation scheme.
This problem can be resolved if we allocate a time-frequency slot to each sensors instead
of allocating a band of frequency to a cell as shown in Figure 3-11. The requirement here
is that time synchronization must kept throughout the entire cellular network. This allows
sensors in different cells to use the same frequency at a different time. Hence cells with
more sensors can have more time-frequency slots, which is effectively same as having more
3.4. VARIABLE BANDWIDTH ALLOCATION SCHEME
51
Px~ P =300mW,p=100ppm,T =1ms,L=100bits,R=1Mbps,M=100
P -100mW,
5
4
-3
a)
2
1
1
2
3
4
7
8
9
10
Bandwidth (MHz)
Figure 3-9: Average energy consumption of a sensor radio vs. available bandwidth.
bandwidth. Furthermore, a time-frequency slot can be shared by two different sensors at
the same time if the sensors are placed far apart so as not to cause any interference to
one another.
This is similar to the conventional cellular network with frequency reuse,
where users in different region can communicate at the same frequency channel at the same
time without interference. While this reuse of time-frequency slot can reduce the energy
consumption of the network, it is difficult to optimally assign time-frequency slots to the all
the sensors in the entire network. This is because the slot assignment of one cell affects the
entire network through time-frequency slot reuse. In the following section, time-frequency
slot allocation algorithm is proposed to minimize the energy consumption of the entire
network.
3.4.3
Energy efficient time-frequency slot allocation algorithm
To approach this problem analytically, a set of notations is defined as the following. It is
assumed that the cellular network has the regular hexagonal structure shown in Figure 3-12.
Definition 1 (Neighbor) A cell is a neighbor to another cell if the boundaries of the
cells touch each other. A cell is also a neighbor to itself.
CHAPTER 3. LOW POWER MAC PROTOCOL
52
D
D
C
E
A
B
F ......
H
C0
E,
g
Fel
EK
906
cl
C
A
B
G
firme
G
A J
Ai
A
F
7
B
C
D
E
F
/KIRII
G
FI
R;N0
M
sesornunber
frequency
(b) variable bandwidth allocation
(a) fixed frequency bandwidth allocation
Figure 3-10: Bandwidth allocation schemes in a cellular network.
D
C
E
A
B
F
A
G
time
4
frequency
Figure 3-11: Variable bandwidth allocation scheme with time-frequency slots.
Definition 2 (Macrocell) A macrocell(e)
is a group of cells that are enclosed in a
closed space, in which the nodes are not allowed to use to same slot. Figure 3-12 shows an
example of macrocells that have frequency reuse of 7.
Definition 3 (Joint Macrocells)
Macrocells are called joint if there exists more than
one cell that are included in both macrocells. In Figure 3-12, 6
1
and 6
2
are joint macrocells.
Definition 4 (Disjoint Macrocell) Macrocells are called disjoint if there does not exist
any cell which is included in both macrocells. In Figure 3-12,
e2
and
03
are disjoint.
Definition 5 (Energy cost function) Energy cost function is defined as Ec(i)
=
53
3.4. VARIABLE BANDWIDTH ALLOCATION SCHEME
Macrocell
neighbors
E)2
E3
Figure 3-12: Notations used in a cellular network (frequency reuse=7).
di-
di
Figure 3-13: Guard time of slots in the same frequency channel.
1/min(di_1,di), where di_ 1 and di are the guard time between other slots as shown in
Figure 3-13.
The energy cost function directly follows from Eq. 3.11. Basically, min(di-1, di) is guard
time of ith sensor since ith slot can drift in either direction to slot i-1 or i + 1. With Et.,E,.x
and p being same for all the sensors, the energy cost function determines the number of
receiver activity and hence minimizing energy consumption is equivalent to minimizing the
energy cost function, E.
In order minimize the energy consumption of the entire network, slot allocation method
is approached from a network with a single macrocell and then generalized to a network
that has joint macrocells.
Single Macrocell optimization
A single macrocell can be treated as a single cell, since frequency reuse is not allowed.
Hence there is a unique slot that corresponds to each sensor. The energy consumption can
CHAPTER 3. LOW POWER MAC PROTOCOL
54
be minimized through following theorems.
Theorem 1 When assigning slots for the n sensors in the same frequency band, equi-distant
placement of the slots results in the lowest energy.
Proof. The statement can be rewritten as follows:
Ei Ec(i) is minimized when d, = d 2
S
=
E(i)~i=
E,
1I
mnin(di, d2)
subject to
- - = dn, where
+
+
1
.(3.12)
+ -.-. +
. 1
min (d2, d3)
min(dn, di)
_ d= constant
Proof. Since arithmetic mean is always greater than or equal to the geometric mean,
Eq. 3.12 is minimized when min(di, di+ 1 ) are same for all i. Also since E di = constant,
1/min(di, di+ 1 ) achieves minimum when di = di+1 and hence di must be same for all i in
order to achieve minimum energy.
Theorem 2 Energy consumption of a rnacrocell is minimized if the difference in the number
of nodes per frequency channel is minimized.
Proof. Suppose frequency channels i and j have nf(i) and nf(j) number of nodes respectively, where nf(i) + nf(j)
=
constant. In order for the nodes in each frequency channel to
achieve minimum energy the slots of the sensors must be equally spaced apart as explained
in Theorem 1. Hence the energy cost function of a sensor in the frequency channel i, E, is
E,
=
(1/nf(i))
1
and E, = (1/nf(j))~ 1 . The total energy cost function is then,
Ec,total =
nf(i)2 + nf(j)2
((nf(i) + nf (j))2 + (nf(i)
=
=
2
(k2 + nf (i) - nf (j)|2)
Hence, it is clear that Inf(i) - nf(j) must be minimized.
nf (j))2)
3.4. VARIABLE BANDWIDTH ALLOCATION SCHEME
55
Based on the above two theorems, an optimum slot assignment function, F(O), for a
single macrocell can be defined as the following.
F(E): Slot allocation function for sensors in macrocell E
1. Assign slots to sensors so that the difference in the number of sensors
in different frequency channel is minimized.
2. For each frequency channel, assign slots to sensors so that the guard
time between all the slots are equal.
Slot assignment in joint macrocells
For joint macrocells, the slot assignment function is extended to two macrocells: 0, and
E5. We define F(OIl0j) as a function that assigns slots to O; with subject to F(03 ). This
function is further explained below, where ni and n3 are the number of nodes that are
exclusively in O; and OE
and m is the number of nodes which are both in 04 and O5 as
shown in Fig. 3-14.
ESi
A
E)-
B
C
ugm
Figure 3-14: Number of sensors in joint macrocell network.
CHAPTER 3. LOW POWER MAC PROTOCOL
56
F(eiJj): Slot assignment function for two macrocells.
1. F(03 );
(i.e.,assign slots to sensors in Oj such that energy of 05 is
minimized.)
2. In order to assign slots to sensors in 02, empty the nj slots which are
exclusive to Oi
3. if ni < n, choose ni slots from the emptied nj slots such that the
distance between the slots are maximized.
4. if ni > nj, add ni - nj additional slots so as to accommodate for the
extra nodes. When adding extra slots, follow theorem 1& 2.
With the slot assignment function defined as above, we can minimize the energy consumption of a network consisting of joint macrocells based on the following theorem.
Theorem 3 When assigning slots to joint macrocells and ni
sensors whose slots are assigned by F(OiJE|)
< n, energy consumption of
is smaller than that by F(0jJ|0).
Proof. Since ni < nj, slots from F(OI0 3g) has smaller average guard time than slots
from F( 3 jl0i). Therefore, energy consumption of F(OiJE|)
is smaller.
Slot allocation for entire network
Based on the previous theorems, an energy efficient slot allocation algorithm is shown below.
Global network optimization
for (i = 1; i < Ntotai; i++;){
for (k = 1; k < Ntota; k++;){
F(0k1(OmaxI(i));
Calculate the energy cost function for the entire network.
}
}
3.5. SUMMARY
57
This is a full search of the entire network with slot optimization subject to F(Emaxli).
Following from Theorem 3, F(0;Imax) will achieve minimum energy for macrocells
E8
and
Omax, where emax denotes the macrocell with maximum number of sensors in the network.
Therefore, it may seem that the energy consumption of the entire network can be minimized
by allocating slots according to F(Oilemax). However, note that that F(EilEmax) achieves
minimum energy only when
E8
and emax are considered. For
E8
alone, F(E2 ) will achieve
minimum energy. If there are more macrocells that achieve lower energy with F(E8) than
F(emax), then the slots must be assigned subject to F(E8). For example, suppose the
network consists of 1 macrocell that has 10 nodes and 1000 other nodes that has 2 nodes. In
this case, assigning the slots to the macrocell that have 2 nodes will result in lower energy. In
the above algorithm, F(ek I(max|Ii)) accounts for scenario like these. The above algorithm
has been implemented in Matlab for a network that has 30 average number of sensors. The
simulation results are shown in Figure 3-15, where total average power consumption of the
sensors is plotted vs. standard deviation of the cell density. Two graphs are shown, one for
a conventional fixed bandwidth allocation (FBA) scheme and variable bandwidth allocation
(VBA) scheme. It can be seen that VBA approach consumes lower power than the FBA
scheme as the variation in the cell density is increased.
3.5
Summary
Low power MAC protocols were investigated based on the radio model that includes the
start-up time of the radio. The energy consumption of the network is minimized by employing a hybrid TDM-FDM system that trades-off energy consumption of the transmitter
and the receiver. The TDMA scheme reduces the energy consumption of transmitter by
decreasing the the on-time, while the FDMA scheme reduces the energy consumption of
the receiver by lowering the number of time synchronizations. For short distance communications, the available bandwidth has a different impact on energy consumption from the
traditional perspective of Eb/N,
in the sense that large available bandwidth allows less
synchronization and hence lower energy consumption in the receiver. This is exploited in
allocating bandwidth to the sensor network that has wide variation in the sensor distribu-
CHAPTER 3. LOW POWER MAC PROTOCOL
58
Fixed vs Variable Bandwidth Allocation Scheme
?
E
6-
55U>
500
040-
0
0-35-
FBA-
E 3s 0
25
0
CL
>
<
15
10
-
VBA
o20-
15
20
25
30
35
40
45
50
55
60
Standard deviation in number of sensors per cell
Figure 3-15: Power consumption of the sensor network for a variable bandwidth allocation
(VBA) and a fixed bandwidth allocation (FBA) scheme.
tion. By employing time-frequency slot allocation, bandwidth is used more effectively and
energy consumption of the network is reduced. Another interesting research area is to incorporate more detailed circuit models into protocol development. For example, allocating
larger bandwidth to a sensor can relax the specification of the transmitter's output noise
which in turn can reduce the power consumption of the transmitter circuitry significantly.
Chapter 4
High Data Rate Low Power
Transmitter
In the preceding chapters, multi-access protocols for a microsensor network were examined.
In the following chapters, a different aspect of the sensor network, implementation of the
sensor transmitter, will be investigated at the circuits and system level. Since the network
traffic of the sensor network is mostly up-link from the sensors to the base station, reducing
the energy consumption of the transmitter will have a dramatic impact on the network's
energy consumption.
Implementing an energy efficient transmitter is different from designing a low power
transmitter.
Since we are trying to maximize the sensor's battery lifetime, energy con-
sumption, rather than power dissipation, must be reduced.
As seen earlier, the energy
consumption of a transmitter when sending a packet can be represented by the following
equation,
EtX
=
(Pt + Pout)Ton-t + PtxTstart
=
L
(Ptx+ Pout) - +PtxTstart
R
(4.1)
where the parameters have been defined in Eq. 3.1. In order to reduce the energy consumption, it is important to reduce the transmit time and the start-up time as well as lowering the
59
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
60
power consumption of the transmitter. In other words, implementing an energy efficiency
transmitter means designing a high data rate, low power, and fast start-up transmitter. In
the following chapters, each of these tasks will be examined and accomplished by exploiting
architectural and circuit level trade-offs between various components of the transmitter.
As a first step, techniques for designing a low power high data rate transmitter will be
studied in this chapter. In the first section, modulation scheme that is appropriate for low
power high data rate transmitter will be chosen.
Different types of modulation scheme
will be viewed from the standpoint of circuits, rather than the traditional perspective of
Eb/No owing to the short transmit distance.
Based on this analysis, a low power high
data rate transmitter architectures will be explored. Specifically, a closed loop direct VCO
modulation architecture will be studied.
4.1
Binary vs. M-ary Modulation Scheme
The modulation scheme strongly impacts the energy consumption of a sensor node. As
evidenced by Eq.3.1, one way to increase the energy efficiency of communication is to reduce
the transmit on-time of the radio. This can be accomplished by sending multiple bits per
symbol, that is, by employing M-ary modulation. Using M-ary modulation, however, will
increase the circuit complexity and power consumption of the radio. In addition, when Mary modulation is used, the efficiency of the power amplifier is also reduced due to higher
linearity requirements. This implies that more power will be needed to obtain a certain
level of transmit output power.
The architecture of a generic binary modulation scheme is shown in Figure 4.1(a), where
the modulation circuitry is integrated together with the frequency synthesizer [26, 42]. To
transmit data using this architecture, the VCO can be either directly modulated or indirectly
modulated by using E-A modulator.
shown in Figure 4.1(b).
The radio architecture of an M-ary modulation is
Here, the data encoder parallelizes serially input bits and then
passes the result to a digital-to-analog converter (DAC). The analog values produced serve
as output levels for the in-phase (I) and quadrature (Q) components of the output signal.
The energy consumption for the binary modulation and the M-ary architecture can be
61
4.1. BINARY VS. M-ARY MODULATION SCHEME
data
P-
Data
EncodeW.
PFS-B, Pmod-B
da
PF
cos(o>R t
(b) M-ary Modulation
(a) Binary Modulation
Figure 4-1: Transmitter architecture of binary and M-ary modulation.
expressed as
Ebin
EM
=
=
(Pmod-B + PFS-B)Ton + PFS-BTstart + Pout-BTon
T0
(4.2)
T
(Pmod-M + PFS-M) Tn(TstartPout-M
n
n
± Pont-MTon(43)
log 2 M
(aPmod-B + 3PFS-B)Ton
log 2 M
In these equations, Pmod-B and Pmod-M represents the power consumption of the binary
and M-ary modulation circuitry such as mixers and DACs, PFS-B and PFS-M represent
the power consumed by the frequency synthesizer, Pout-B and Pout-M represent the output
transmit power for binary or M-ary modulation, Ton is the transmit on-time, and Tstart is
the start-up time. As mentioned, for a given packet size, Ton for M-ary modulation is less
than Ton for binary modulation by a factor of n, where n is the number of bits per symbol
(n = log 2 M). The factors a and 3 can be expressed as
Pmod-M
Pmod-B
PFS-M
PFS-B
(4.4)
where a represents the ratio of the modulation circuitry's power consumption between
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
62
M-ary and binary modulation, while 0 is the ratio of synthesizer power between the M-ary
and binary schemes. Basically these parameters represent the overhead that is added to the
modulation and frequency synthesizer circuitry when one switches from a binary modulation
scheme to an M-ary modulation scheme. For example, the frequency synthesizer in M-ary
modulation scheme must generate quadrature signals.
The quadrature components are
usually achieved by operating the VCO at twice the desired frequency and dividing it by
two. In addition M-ary modulation requires mixers and A/D that are not necessary in
binary modulation scheme. Hence these added components contribute significantly to the
power consumption of an M-ary scheme.
By comparing Eq. 4.2 and Eq. 4.3, it can be seen that M-ary modulation achieves a
lower energy consumption when the following condition is satisfied.
a
<
n 1+
PFS-B[(I -
)Ton
n+n
+
(1
+
-
Pmod-BTon
n 11 +
PFS-B[(1 - Pm)Ton
+ (
Po-on(4.6)
I
-
Pstart
out-B
Pout-M
Pmod-B
Pmod-B
(4.5)
/)Tstart
The last two terms of Eq. 4.5 are small since Pout-B and PoutM are negligible compared
to the power of the frequency synthesizer.
A comparison of the energy consumption of binary modulation and M-ary modulation
is shown in Figure 4-3. In this figure, the ratio of the energy consumption between M-ary
and binary modulation scheme is plotted versus the overhead a. It is assumed that 3 =
1.5, which is a reasonable assumption considering quadrature VCO is needed in the M-ary
scheme. It is plotted for the cases when start-up time is 20ps and 450ps. For each start-up
time, the graphs are plotted for M = 4,8 and 16. When the start-up time is 20ps, the
M-ary modulation achieves lower energy consumption as the power consumption of the
overhead circuitry is reduced. The saving increases as M gets higher, since transmit time
gets shorter.
However, when the start-up time is 450ps, the binary modulation always
achieves lower energy, independent of the overhead circuitry. This is because the start-up
time already dominates the transmit time of the packet and hence there is no savings in
energy consumption by going to the M-ary modulation scheme.
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
PFSB=
2
0mW,
Pmod-B=20mW, PoOdBm,
63
=
1.5
1.4
1.3
start=450-
-- ---_ _ .M;_4_
- -----------------------------
- -------
- -- -- -
1.2
WE
0.9
-M=
0.8
M=16
0.7
0.6
1.5
2
2.5
3
3.5
4
4.5
5
Figure 4-2: The ratio of the energy consumed by M-ary modulation to the energy consumed
by binary modulation versus a, the ratio of the modulation circuitry power consumption.
The effect of start-up time on modulation scheme is better seen in Figure 4-2, where
the energy consumption ratio between the two schemes are plotted against start-up time.
It can be seen that the M-ary modulation scheme achieves lower energy only if the startup time is small enough compared to the transmit time. Therefore, the radio designer as
well as the protocol designer must keep the effect of start-up time in mind when designing
a transmitter or a communication protocol. An in-depth analysis of various modulation
schemes for sensor network is studied in [43].
4.2
High Data Rate Low Power FSK Modulator
In the previous section modulation schemes were compared from the standpoint of transmitter's energy consumption. While M-ary modulation scheme can achieve lower energy
by reducing the on-time, it is true only if the start-up time is small compared to the
transmission time of the packet. Since the packet size is very short for sensor applications,
M-ary modulation scheme does not offer much advantages over binary modulation schemes.
Therefore, low power high data rate binary modulators will be investigated.
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
64
PFS-B=20mW, P mod-B=20mW,
P=1.5 a=1.5
1.5
1.4
1.3
1.2
*- .1
w
-.
E
M.
.
-..
-
0.9
0.8
-.-.-.M.1
....... -.
0.7
10
102
10
3
Tstart(p s)
Figure 4-3: Effect of start-up time on the energy consumption of different type of modulation
schemes.
4.2.1
Related work
Of the various binary modulation schemes, continuous phase modulation scheme has the
advantage that its modulation circuitry can be made simple with high output power amplifier efficiency. For continuous phase modulated signals, there are several architectures that
can be used. The most popular method is the heterodyne architecture that is used not only
in continuous phase modulators but also in non-continuous phase modulators as well. This
architecture can achieve very high data rate since the limitations on data rate come from
the linear range of the mixers and speed of DACs. However, the main drawback is that its
complexity is high, since mixers, DAC and low pass filters require power and area, both on
and off chip.
A better suited architecture for low power FSK modulation is based on a E-A fractionalN synthesizer [44]. The idea is that fine frequency contents of the modulation can be generated by proper dithering of the divider value with a high resolution E-A modulator. This
architecture removes majority of the modulator components in the heterodyne architecture
except the frequency synthesizer and hence consumes low power. The disadvantage is that
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
fref
PFD
65
-
fout
/N, /N+k
data
Figure 4-4: Indirect modulation architecture using E-A fractional-N synthesizer.
the data rate is limited by the PLL loop bandwidth, since the PLL shows a low pass transfer function from the E-A. Although the loop bandwidth can be increased, this leads to
higher power dissipation at the E-A in order to maintain low quantization noise. While
this architecture is very promising for low power continuous phase modulation, reducing
the power consumption of the divider and E-A is crucial for high data rate and low power
operation.
fref
-
PFD
--
fout
/N, /N+k+---data
Figure 4-5: High data rate modulator using pre-emphasis filter and automatic calibration.
To avoid the limitation of data rate from PLL loop bandwidth, a clever solution was
suggested by Perrott [40], by adding a transmit pre-emphasis filter to the E-A modulation
path as shown in Figure 4-5. The beauty of this technique is that the modulated data
and quantization noise each see different loop characteristics. While both the data and the
quantization noise goes through the low pass nature of the PLL, the data sees a much wider
loop bandwidth with the help from the pre-emphasis filter. Hence, high data rate can be
66
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
data
fref
..
..
PFD
fout
channel
select
Figure 4-6: Open loop direct VCO modulation architecture.
achieved even with a small loop bandwidth, which in turn enables low power consumption
at the E-A. A potential problem of this approach is the gain mismatch between the PLL
loop and the pre-emphasis filter. If the data does not see a flat band over its spectrum, the
modulated signal will be distorted. Since the PLL loop bandwidth depends on parameters
that cannot be controlled precisely (e.g.
VCO gain, charge pump current, etc), manual
calibration of the PLL loop bandwidth or the pre-emphasis filter is necessary. The solution
to this problem has been proposed by McMahill
[45], by adding an automatic calibration
circuitry. The basic idea is to compare the sampled output phase to the original data and
correct the loop response by adjusting the loop gain. While the above method is very
promising for low power high data rate continuous phase modulation schemes, a minor
drawback is that the power consumption of the calibration circuitry is quite high, since the
output sample must be produced from the high frequency RF output.
Another popular method that achieves high data rate low power modulation is the open
loop direct VCO modulation architecture. The underlying idea is to open the loop after the
PLL settles to a desired frequency and directly modulate the VCO. Since the loop is open
during modulation, the PLL does not affect the modulation in any way and hence the data
rate is not limited by the PLL. Furthermore, power consumption is dramatically reduced
since the VCO is the only component that needs to be turned on during transmission. A
critical drawback of this approach however, is the instability of the VCO when the loop is
open. The charge stored in the capacitor of the VCO control input will eventually leak away
and cause the carrier frequency to drift. In addition, great care must be taken as to avoid
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
67
data
Pulse shape
filter
vmod
kmod
kpnodvniod
H,(s)vmod
N
Figure 4-7: Block digram of a closed loop direct VCO modulation architecture.
any VCO pulling when the loop is opened. Efforts to reduce these effects often lead to high
quality off-chip resonant tanks of the VCO, which loses the merit of integration [26, 461.
4.2.2
Closed loop direct VCO modulation
Closed loop direct VCO modulation [47] on the other hand is robust to these problems and
still has the advantage that the upper bound on data rate is not affected by the PLL loop
bandwidth. Since the data is modulated in closed loop, any drifts that are seen in the open
loop architecture are no longer an issue. The disadvantage is that the modulated waveform
will be distorted from the negative feedback loop of the PLL. Since the PLL acts as a
high pass filter when viewed from the VCO, low frequency components of the modulated
data will be corrupted by the PLL. In other words, long strings of zeros or ones will not
be modulated correctly. The effect of PLL on modulation accuracy can be decreased by
reducing the loop bandwidth, which is also favored for low power frequency synthesizer as
will be seen in the following chapters.
For a detailed analysis of this architecture, a linear model of the closed loop direct VCO
modulator is shown in Figure 4-7. The output modulated waveform under locked condition
can be described as
68
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
Effect of PLL on direct VCO modulation (BT=0.5, h=0.5,
4030
loopBW=1 00kHz)
--
E2 20 -...-.
~-11 0 - - --
....
-..
-.
-..
....
..
- - -.. .. -.
..
...
.-.-
0 -0
> -20
C.-30
r -40
--
(D
-
-50
-60
2
Ideal Gaussian shaped
Closed loop modulated
Original bits
6
4
-
8
time (s)
10
12
14
x 10-
Figure 4-8: Effect of closed loop PLL on direct VCO modulation.
kmod-out
(Kmod
-
He(Wn)) 'mod
(47)
where Omod-out is the modulated output phase when the synthesizer is in lock, He(Wn)
is the error transfer function from the modulation input to the output, Kmod is the VCO
gain of the modulation input and Vmod is the input signal of the pulse-shaped data. For a
second order charge pump PLL, the frequency error e(s) from the ideally modulated signal
is,
e(s)
-He(S)Vmod
=
=
=
K
Kmod
W
(4.8)
2
(1 + sT-)
+
un2 Vmod
V2
where the parameters are those defined in Appendix B. It can be seen that the error shows
a low pass characteristics with a natural frequency of w.
Hence the error will decrease if
the loop bandwidth is reduced. Unfortunately, even for an arbitrary small loop bandwidth,
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
69
Manchester Coded GFSK @ 5Mbps o=100kHz, BT=0.5, h=0.5
GFSK @ 5Mbps woc=lO0kHz, BT=O.5,h=O0.5
5
N
I
o)
Ea
5
E
0.6
0
a
S
6
0
0.1
0.3
0.2
0.4
0.5
0.6
tiMe(As)
Figure 4-9: Simulated eye diagram of a raw
data.
o
0.1
0.2
0
timeQps)
04
05
0.6
Figure 4-10: Simulated eye diagram of a
Manchester encoded data.
the error will eventually show up if the transmitted data has a sequence of zeros or ones
that is longer than the time constant of H(w.). An example of the closed loop direct VCO
modulation is shown in Figure 4-8, which shows how the modulated data is corrupted by
the high pass nature of the PLL. The dotted line represents the original bit sequence of the
data, and the dashed line shows the pulse-shaped waveform of the data, which in this case
is a Gaussian shaped waveform with BT 1 of 0.5. The solid line shows the modulated output
in closed loop, where we can see the distorted waveform of the data by the PLL, especially
on the series of ones.
Simulation Results
The effect of closed loop modulation can be better seen in an eye diagram as shown in
Figure 4-9, which shows the eye diagram of a 5Mbps GFSK data when the loop bandwidth
is 100kHz. The effect of PLL is severe as the eye opening is reduced to about 50% of the
ideal value. Closed loop modulation is more effective if the DC component of the data is
removed. This can be done through Manchester encoding, which replaces O's and 1's with
transitions. The eye diagram of the Manchester encoded data is plotted in Figure 4-10,
which shows significant improvement as compared to the raw data. The drawback is that
the effective data rate is halved.
'BT is defined as filter bandwidth over data rate.
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
70
4.2.3
Modulation error and bit error rate
Modulation error from closed loop PLL
It is important to see how the modulation error of closed loop direct VCO modulation
scheme impacts the system performance.
It is assumed that the base station performs
coherent demodulation since the complexity of the base station receiver is not a critical
issue.
The transmitted waveform si(t) at the output of the modulator can be expressed by the
following equation,
si(t) =
-cos{w
- e(t)]t}
(4.9)
i E {0, 1}
where A is the transmitted energy of the bit with time duration T, wi is the frequency of the
modulated bit i, and e(t) is the error signal that results from the closed loop modulation.
Note that e(t) has memory and depends on the previous bits, thereby causing inter-symbol
interference.
Assuming white additive Gaussian noise is added to the transmitted signal, the signal
arriving at the baseband receiver, r(t), can be described as the following equation, where
is the received energy 2 of the bit.
Eb
r(t) = si(t) + n(t) =
2E
T cos{[wi - e(t)]t} + n(t)
(4.10)
The baseband receiver performs coherent demodulation as shown in Figure 4-11, where
it correlates the incoming signal to the orthonormal basis
#i(t),
which is defined by the
following equation.
0i(t) =
2;cos(wit)
(4.11)
The maximum likelihood detector compares the output of the correlator and makes a
decision based on the following:
2
The term energy is different from what we have discussed in the previous chapters. While Eb denoted
in this section indicates the RF energy, the energy that was described previously is the energy consumption
of the entire transmitter, which includes the RF energy as well as other transceiver circuitry.
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
71
)dt
Maximum
r(t)
10
Likelihood
Decision
-
)dt
Figure 4-11: Coherent demodulator of the base station receiver.
(r(t), 0(t)) < (r(t),01(t))
(r M),#0 M))
>
(r(t),01(t))
: s1 is sent
(4.12)
so is sent
where (a, b) represents the correlation between a and b. To calculate the BER, assume that
so is sent. The output of each correlator can be simplified as the following equation,
(r(t), o (t)) =
=
(r(t),
1
(t))
jT
cos(e(t)t)dt +
no
T 10
ao+no
=
T cos(AWt
T
0
+ e(t)t)dt + ni
(4.13)
(4.14)
ai 4ni
where
Q!o
and ai are the correlator output of the receiver, Aw is the frequency difference
between the two signals (i.e., |wi - wol) and no, ni are additive white Gaussian noise. Also
note that AwT = ir since 0 and q1 are orthogonal. Equations 4.13 and 4.14 cannot be
solved in closed analytical form due to the complexity of e(t). Therefore, an upper bound
on bit error rate must be calculated. Since no,
i1
are Gaussian random variables with zero
mean and variance !V,, no - n1 is also a Gaussian random variable with zero mean and
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
72
variance
.,
Therefore, the probability of error is,
Perror =
Prob[(r(t),0o(t)) - (r(t), # 1 (t)) < Ojso sent]
=
Prob[no - ni < ai - ao]
<
Prob[no - ni < (ai - ao)min]
(01-ao)min
,/2grNo
=
Q
(4.15)
e_ X 2 /(2N.)dx
-o
(4.16)
aO)min)
(a,
To calculate (ai - ao)min, the maximum value of error is denoted as
the error is not excessive
a1 -ao
emax.
Assuming
( emaxT < 7r) and that e(t) > 0, then
=
V
fT
T
cos(/Awt
-
e(t)t)
cos(e(t)t)dt
-
0
Art
=
-2sin
>
-2sin (Awt
sin(emaxT)
emaxT
{
r
sin Awt - e(t)t
sin (AWt-
emaxT
- emax T
I
dt
emaxt) dt
1ErE
v}
(4.17)
}
(4.18)
Substituting (O!1 - ao)min into Eq. 4.15, we achieve
Perror <
Q
7
where,
=
sin(emaxT)
emaxT
emaxT
7r
- emaxT
Assuming that 0 and 1 are equality likely, the overall probability of error is bounded by
Eq. 4.18.
The closed loop modulation impacts the SNR by the factor -Y.
The term -Y
depends on the data rate and the loop bandwidth of the PLL. A simulation has been done
for different data rates and loop bandwidths, and the results are shown in Figure 4-12
and 4-13. In Figure 4-12, -y is plotted against wcT. As the loop bandwidth,we, gets closer
to the data rate, the degradation in SNR becomes larger. In Figure 4-13, BER is plotted
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
modulation error due to closed loop modulation
73
BER vs E0 /N in closed loop modulation scheme
10,
I
0.8 -
10-
T=0.05
0.7 0.
CT=0.102
-6
- - ---
0.4 -
0.2
-- - ---- i-e--
- -- -l
Eb/N (dB)
a
10'
zo
--
0.01
0
m
peri
l
Lc~ bwidT
ha
0.09
SNR degradation (-y)
Figure 4-12:
closed loop modulation.
0.1
from
10
1
2
9
1
Figure 4-13: BER vs. Eb/N, of closed loop
modulation scheme in AWGN channel.
vs. Eb/N,. It can be seen that the wcT must be kept below 0.1 in order to achieve BER
without increasing Eb/N too much. An ocT of 0.05 results in less than 2dB degradation in
SNR. Considering the small output power that is required, this is certainly an acceptable
level of degradation.
Modulation error in Rayleigh fading
In the indoor environment, signals not only suffer from additive white Gaussian noise but
from multi-path fading as well. As mentioned in Chapter 2, the indoor channel in a sensor
network can be assumed as a slowly Rayleigh fading channel. This implies that the attenuation over one symbol period can be considered constant.
Hence the received signal in
Eq. 4.10 can be modified as
(4.19)
rf (t) = ae--osi(t) + n(t)
where a and
#
are amplitude and phase variations of the received signal due to fading.
Assuming that the fading is slow enough such that the phase deviation
#
can be estimated
without error, the receiver can still perform coherent detection. The BER in the fading
condition is simply,
Perror,fading -
PerrorProb(a)da=
Q (a-y r
) Prob(a)da
(4.20)
74
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
BER vs. Eb/No in Rayleigh fading
10
...........
...........d...... .........
.........
...........- .......................
...........
......................
.............
....... ........
...... ...............
10' ................... ...................
..
..
..
..
..
..
..
..
..I
....
...
..
..
..
..
..
............
.
....
..
..
..
..
.......
.
..
.
.-.....
..
.I.
..
..
...
....
...
..
..
..
..
..
..
..
..
..
...
...
.
....
..
..
..
..
..
..
..
..
...
.......
.
.
.
.
.
..
..
..
..
..
..
..
..
..
..
............
..
..
..
..
..
..........
..
..
..
..
..
..
..
..
..
.
..
....... .......
...
..... .......
....:................
..........
.... .............. 0) C'T 0*05'
............................
..
..........
.......... ...................
.........................
C1
to T=O. 1
.. ...........
. ............ ...
........
...
.
... ........
..
.................
..........
...
..
..
...............
.....
..........-..
: _...
..
....
..
..
..
......
.......
to C.T=0.02
10-20'
10-3
10-
.
..
...
...
...
........
................
..
..
.
.
.
.
..
.
....
...
.
.
.
..
..
..
............
..
..
...
...
...
...
.........; '...-...- .....
..
..
..
..
.
..
..
..
.I....
...
..
..
..
..
................ .................. .. .
..........
........I.................................................... .....
..
..................
........................................ .....
...............
..........I......................... ....
.......
......................... .........
s
10
(dB)20
1sEb/N
25
30
Figure 4-14: BER of closed loop modulation in a Rayleigh fading channel.
Since the channel is a Rayleigh fading channel, the probability density function, Prob(a)
has a Rayleigh distribution. The result of the integral [48] can be expressed as,
Perror,fading=
where
2
-
=
(4.21)
-yjE(a2)
No
The resulting BER is plotted in Figure 4-14. The required Eb/N to achieve a certain
BER increases as the loop bandwidth becomes larger compared to the data rate.
The
penalty in output power is small if wcT is kept below 0.05. For a 100kHz loop bandwidth,
this relates to data rate of 2Mbps.
Modulation error from quantization noise
As will be seen later in this thesis, fractional-N synthesizer provides the advantage that the
loop bandwidth can be increased without being limited by frequency resolution and stability
issue. The increased loop bandwidth allows fast start-up which is essential to minimizing
4.2. HIGH DATA RATE LOW POWER FSK MODULATOR
75
energy consumption. In a fractional-N synthesizer, the phase error at the PFD does not
become zero even in locked condition. This results in fluctuation of the VCO control voltage
under locked condition, which shows up as quantization noise and causes modulation error.
For the second order PLL described in Section 6.1.1, the maximum fluctuation on the VCO
voltage (AVmax) can be expressed as 3
27rNnom
Ie=
AV
=max
-
C
ax =
Kve0
2
T
WlTmax =
Nmax
27c Nnom
Kve0
2Kantw
n
Nnom
-
1) Tref (4.22)
(4.23)
where in addition to other parameters already defined, Nnom and Nmax are the nominal
and maximum values of the divider. Note that the fluctuation in the control voltage increases with loop bandwidth, which is consistent with the fact that more quantization error
shows up as the loop bandwidth is increased.
Carrying out a similar analysis to that shown in the previous sections, the bit error rate
from quantization error can be drawn. The resulting BER is plotted against loop bandwidth
in Figure 4-15, which shows that a loop bandwidth of less than 500kHz has little effect on
BER. It should be noted that effect of quantization noise on BER is smaller than that of
closed loop PLL.
4.2.4
Equalization at base station
From the receiver's perspective, the modulation error induced by the closed loop modulation
can be considered as fading from a communication channel. The received signal can be
represented as
R(s) = HPLL(S)Hchannel(s)X(s)
(4.24)
where HPLL(S), HChannei are the transfer function from the PLL and channel respectively
3
See Appendix B for derivation
76
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
10"
BER degradation from quantization noise in Rayleigh fading
.............
...............
.................... ................
...................
...............
...........
..
..
..
..
..
..
.7.
..
..
.......... ...
.
...
..
...
..
..
..
..
....
..
..
..
I.
...
....
..
..
..
..
..
..
..
..
..
..
..
..
...
....
..
..
..
..
..
..
..
.....
....
..
...
....
..........
..
..
..
..
..
..
..
.......................
.......
.............. I..:
m -75....
00...lkH. ...
z ....
'' ...
'',**... .'**'. ... ....
* ..
'"
... ... .... ..
.... .... .. ..
.. .... ... ... .... ..
10- ..
..
..
..
....
..
.....
....
..
..
..
..
..
..
..
..
..
..
..
..
..
...
..
..
.....
..
..
..
...
. ................
.
.......
..
... ... .. ..
..
..........
...................
.......
.....I..............
.................
..........
.... ideal:::::::::::::
.............
-.... . ..*... .
..
..
...... ......
....
..
......
.....
..
..
.......
...
.
.
.
.
.
..
..
...
..
...
...
.......
.... .................
...........................
..........
......................
............
..
....
..
.............. ............ .....
..... ..........................
..
............::..:.:.:.:.:.:.*.-..*....*...
.............
10
. ..... ... .... ... ... .... .. .... ..
to =1 MHz
..............
..................
...........
LI. i o-
10-3
F C
. .... .... ... ... .. . .... ....
10
15
E b/N (dB)
20
25
30
Figure 4-15: BER degradation due to quantization noise in fractional-N synthesizer.
and X(s) is the transmitted data. Since HPLL(s) results from the PLL, the base station can
employ equalization and cancel out the effect of PLL as shown in Figure 4-16. Moreover,
since
HPLL(S)
is a deterministic function, there is no need for a training sequence and
energy efficiency is not affected.
data
-
H PF
Front-end
data
HPLL(W)
Figure 4-16: Equalization of the transmitted data at the base station.
4.3
Summary
In this chapter, high data rate low power transmitter architecture was investigated. The
direct VCO modulation architecture achieves high data rate FSK modulation with minimal
overhead to the synthesizer. Basically, one CMOS varactor is the only component that is
added to the frequency synthesizer to perform FSK modulation. The modulation error from
4.3. SUMMARY
77
closed loop PLL is overcome by low loop bandwidth, Manchester encoding and equalization
at the base station. While the closed loop direct VCO modulation may not be suitable for
other applications which require precise modulation and large output power, it is certainly
applicable to sensors that require small output power.
78
CHAPTER 4. HIGH DATA RATE LOW POWER TRANSMITTER
Chapter 5
Fast Start-up Transmitter
The most critical issue in sensor communication is the start-up time of the transmitter,
which dominates energy consumption in short packet transmission. The start-up time is
usually dominated by the frequency synthesizer due to its inherent feedback loop. Other
components of the transmitter such as mixers or power amplifiers have negligible effect as
start-up time of these components are determined by their bias currents. 1 In the transmitter
architecture discussed in this thesis, the effect of start-up time is even more crucial, since
frequency synthesizer dominates the transmitter's energy consumption. Hence, fast start-up
techniques for the frequency synthesizer are investigated in this chapter.
5.1
Background
Start-up time of the frequency synthesizer is basically the lock time or the settling time 2
of the synthesizer, which is inversely proportional to the loop bandwidth of the PLL. Although reducing the settling time may seem trivial by increasing the loop bandwidth, there
are several obstacles that prevent the increase in loop bandwidth. First of all, the loop
bandwidth is limited by stability requirement that keeps the loop bandwidth below approx'Start-up time of the bias current depends on the amount of bias current. While the start-up time can
be made very small for large bias-currents, it can be large for small bias-currents, in which case the bias
current consumes negligible power in the overall system.
2
Strictly speaking, the term start-up time has the inherent notion of zero initial conditions and can be
distinguished from settling or lock time that may not have zero initial conditions. However, zero initial
conditions are assumed throughout the thesis and these terms will be used interchangeably.
79
CHAPTER 5. FAST START- UP TRANSMITTER
80
imately one-tenth of the reference frequency [49]. In an integer-N synthesizer architecture
with a prescaler value of 8, the stability requirement limits the loop bandwidth to below
12.5kHz if frequency resolution of 1MHz is to be achieved. This results in settling time on
the order of milliseconds, which is unacceptable for microsensors.
While the loop band-
width limitation due to stability can be improved by employing a fractional-N synthesizer,
power consumption is another factor that limits the loop bandwidth. As will be seen in
the next chapter, low loop bandwidth allows low power at E-A and divider. In addition, it
allows low power FSK modulator by closed loop direct VCO modulation. Hence, small loop
bandwidth is desirable for low power high data rate transmitter discussed in this thesis.
There have been numerous studies on fast locking PLLs for a variety of applications,
from frequency synthesizers to clock recovery circuits. The most popular approach is the
variable loop bandwidth method [49]. The main idea is to start the PLL with a wide loop
bandwidth and change it to a smaller loop bandwidth when the loop is close to being locked.
Variations of this architecture have also been published with different loop filter [50, 51]
and phase detector [52]. There are other fast settling techniques such as initial-value PLLs
and type-I PLLs. In the initial-value PLL, the desired VCO control voltage is stored in a
register so that the PLL can start near the final value. Unfortunately, this method requires
A/D and D/A in order to store the desired VCO control voltage. In a type-I PLL, phase
error does not need to be zero in lock and hence fast settling can be achieved. However, it
requires large phase acquisition range, requiring A/D and D/A in order to extend the phase
range of the PFD [53, 54]. This results in added power consumption and is not a suitable
solution for low power application. Therefore, loop switching method is used for the fast
start-up synthesizer.
5.2
5.2.1
Loop Switching in Fractional-N Synthesizer
Variable loop bandwidth technique
The basic architecture of a variable loop bandwidth method is shown in Figure 5-1.
To
allow minimal disturbance on the VCO control voltage during loop switching, the resistive
component of the loop is changed by opening the resistor path. In addition, the current
5.2. LOOP SWITCHING IN FRACTIONAL-N SYNTHESIZER
2
N 1
1
ref
R
U
div
D
D
81
T
o
N2
I
0-
IC
42N
R
R
N
ILoop switchI
Ndivider
Figure 5-1: Variable loop bandwidth technique.
Bode Diagrams of Variable Loop Switching
100
50
R
50-
(-50
-1001
-100
140
Q- -160-10
103
4
10
10,
10
6
1
108
10
Frequency (rad/sec)
Figure 5-2: Bode plot of a PLL with variable loop switching method.
source for the large loop bandwidth mode is turned off when the charge pump is in tri-state
mode. These keeps the same charge on the loop filter capacitors throughout the bandwidth
transition and hence seamless switching is achieved. Also, the values of the current source
and the resistors are chosen such that the phase margin is kept the same in both large and
small loop bandwidth modes. The bode plot of the PLL in the two bandwidth modes are
shown in Figure 5-2, where the phase margin is kept the same in both modes of operation.
CHAPTER 5. FAST START- UP TRANSMITTER
82
1st swtich
Loop switching occurrs
2nd swtich
desired
average
value
(a) Single stage loop switching
(b) Dual stage loop switching
Figure 5-3: Effect of quantization noise in loop switching.
5.2.2
Effect of quantization noise
The previous variable loop bandwidth technique has worked well in integer-N synthesizers
or clock recovery PLLs, where phase error is zero when the PLL is in lock [50, 52]. Unfortunately, the phase error does not become zero for a fractional-N synthesizer even in
locked condition, since the divider value is constantly changed. This non-zero phase error
results in quantization error on the VCO control voltage in locked conditions. As discussed
in Section 4.2.3, the magnitude of the quantization error is proportional to the loop bandwidth. The quantization noise on the VCO control voltage can be a serious problem when
loop switching is employed, especially when there is a large difference in loop bandwidths.
Suppose the loop switches from a large bandwidth to a small bandwidth after the PLL is
locked. Since the VCO control voltage fluctuates around a desired average value, the loop
switching may occur at an instant when the control voltage is far away from the desired
value as shown in Figure 5-3 (a). In such cases, the settling time is dominated by the small
signal settling time of the small loop bandwidth and the loop switching technique does not
help the fast settling of the synthesizer. This problem can be alleviated if the loop switching
is applied in multiple stages as shown in Figure 5-3 (b). By changing the loop bandwidth
to an intermediate value, the magnitude of the quantization noise can be reduced and the
settling time in the small loop bandwidth can be reduced.
5.2.3
Multiple stage loop switching
In order to obtain the optimum number of loop switching and the values of loop components
in each stage, the behavior of the VCO control voltage in multi-stage loop switching method
5.2. LOOP SWITCHING IN FRACTIONAL-N SYNTHESIZER
83
Average value of Vctrl
: Fluctuation
range of Vtr,
V--
Settling time
:T
-Final
Ts2
Ts3
Loop bandwidth: (01
(02
(03
Settling accuarcy : Pi
P2
P3
Vt
Figure 5-4: VCO control voltage in multi-stage variable loop bandwidth technique.
is modeled as shown in Figure 5-4. The shaded region indicates the fluctuation range of
VCO control voltage due to quantization noise. For a second order PLL with an underdamped response, the error of the average VCO control voltage from the final value can be
approximated by the following equation,
=
Verror(t)
AVe(W''nt
(5.1)
where AV is the difference between the final and the initial control voltage of the VCO.
Hence, the time it takes to settle to within p accuracy of the final value, Vf, is
1
(w
AV
pVf
(5.2)
For the multi-stage loop switching scheme, the initial voltage difference at the beginning
of the ith stage can be described as,
AV=
Kquant(W-1-o)+Pi-1Vf
ii>2
'> 2
CHAPTER 5. FAST START- UP TRANSMITTER
84
AV 1
=
Vf
i=
(5.3)
where Kquant is the parameter defined in Eq. 4.22, wi_ 1 and wi are the loop bandwidth
of stages i - 1 and i Hence the time it takes to settle to pi of the final value Vf can be
expressed as
Tsi =
1
-In
AVi
-n =
1
-
K(__
_
w?-___+_
The total settling time it takes for an M step variable loop switching is
M
Tsettie
=
l
Tsi
In the above equation, only the loop bandwidth and settling accuracy of the final stage are
fixed parameters (wf, pf) and those of previous stages are variables. In addition, the number
of loop stages (M) is also a variable. It is difficult to obtain a closed form expression for
the optimum number of stages that minimizes the settling time. Therefore, the variables
are swept across their possible values. The results are shown in Figure 5-5, where minimum
settling times are plotted against the number of variable loop stages for different initial loop
bandwidths. The graphs shows that the settling time decreases as the number of stages
increases, since each stage minimizes the effect of quantization noise. Ideally, settling time
will be minimized by maximizing the number of stages, M.
However, keeping M to a
minimum is desirable from the implementation standpoint since addition of a variable loop
stage requires increased complexity in charge pump and loop filter. Keeping this in mind,
M=2 with wi=1MHz is appropriate for the scenario when wf=OOkHz and pj=50ppm.
More number of stages provides little improvement in settling time while adding circuit
complexity. The graph also confirms that multi-stage switching is more effective when the
difference between initial and final loop bandwidth is large.
When the loop bandwidth
starts from 5MHz and jumps directly to 100kHz, the settling time is large due to the large
difference in the two loop bandwidths. However, addition of another variable loop stages
5.3. DIGITAL LOCK DETECTOR
85
W = 100kHz, p =50ppm
X 10'
1.75
K10
= 1MHz ,to
=100kHz
.,w.=500kHz
--
e =1MHz
1.7
.. MHz
1.65
2.2
1.6
E
Pi 1.55
E
1.5
04
1~
.2
1.45
.....--...-.-....
1.4
1.35
1.5
2
2.5
3
Number of variable loop stages
3.s
4
1
05
1o'
Intermediate loop bandwidth frequency(Hz)
Figure 5-5: Settling time vs. number of variable Figure 5-6: Settling time vs. intermediate loop
bandwidth in a two stage variable loop techloop stages.
nique.
immediately reduces the settling time. As the difference in two switching loop bandwidths
is small, the impact of adding variable loop stages becomes insignificant as shown in the
graph.
In Figure 5-6, settling time is plotted against the intermediate loop bandwidth
for the case when M=2 with wi=1MHz. It is seen from this graph that the settling time
can be reduced by employing two stage variable loop method, starting with 1MHz of loop
bandwidth and then to 280kHz before switching to final loop bandwidth of 100kHz.
5.3
Digital Lock Detector
In order to switch the loop bandwidth, a lock detector circuit is necessary. In a type-2
PLL system, the PLL is considered as locked if both phase difference and frequency change
over time is zero. In a fractional-N synthesizer the lock condition is different due to the
quantization error and can be defined as,
Lock:
d-tp
dt
A4D < AJmax-lock
(5.4)
where A1 represents the phase difference of the reference clock and the divided output of the synthesizer and A~max-1ock is the maximum phase difference in a fractional-N
CHAPTER 5. FAST START-UP TRANSMITTER
86
second switch for
variable loop filter
CP
PFD
LF
/14,15
dn
Onito
Delay
lock
---
----
~
dnv
16 bit serial register
up
f.t/8
-
ref/2 -
L
u
]U
4 bit counter
enable
fo . M8
21
Figure 5-7: Schematic of digital lock detector.
synthesizer under locked condition. In order to detect lock, the phase difference (A<D) is
monitored by a digital counter located at the output of the prescaler-by-8 as shown in
Figure 5-7.
The counter is enabled only when the up or down signal from the PFD is
high, i.e., when there is phase difference. Basically, the counter counts the number of high
frequency prescaled-by-8 pulses during the phase difference of the reference clock and the
divided output of the synthesizer. The output of the counter will represent the quantized
value of the phase difference and it will decrease as the loop approaches lock. Since the lock
condition also requires the frequency to settle, the lock detector must monitor the phase
difference for some amount of time before it decides that the loop is in lock. That is, the
output of the counter must stay below the phase-lock threshold for some amount of time.
The amount of time that the detector has to monitor depends on the loop bandwidth of
the PLL. As discussed in previous section, the frequency error, Af, and phase error, A4b,
can be approximated by the following equation,
Af = e-(W,"'
Af =e~nt
e<Wt
(5.5
(5.5)
87
5.4. SUMMARY
where ( is the damping factor and w, is the natural frequency of the system. Hence,
the time that the lock detector must monitor the phase difference after the occurrence of
first zero quantized phase error is,
Twait = Tock
-
To = In
where
-
(
In A4 max
<)max = 27 fref
(5.6)
(5.7)
fout/8
For the case when p=50ppm, (
=
1, fref=50MHz,fout=6GHz, and a 1MHz loop band-
width, Twait ~ 200ns which corresponds about 10 cycles of a 50MHz reference clock. The
lock detector circuit is implemented using a serial shift register at the output of the counter
and OR gates. The lock detector needs to produce two signals, one for the first loop filter
stage and the other for the second loop filter stage. The first signal comes directly from the
lock detect signal while the second signal comes from the delayed version of the first lock
detect signal. The amount of delay corresponds to the loop bandwidth of the second stage.
5.4
Summary
Fast start-up techniques for a fractional-N frequency synthesizer was investigated. The variable bandwidth technique provides simple form of aiding fast settling without adding much
overhead to the synthesizer. While this technique is successful for integer-N architectures,
quantization noise can be a problem for fractional-N synthesizers. To overcome this effect
of quantization noise, a multiple stage loop bandwidth technique is employed.
88
CHAPTER 5. FAST START-UP TRANSMITTER.
Chapter 6
Implementation of Energy Efficient
Transmitter
This chapter discusses the implementation details of the energy efficient transmitter. Minimizing the power consumption of the frequency synthesizer is explored by exploiting tradeoffs between digital and analog component of the synthesizer.
The building blocks for
continuous phase modulator and variable loop filter are also described.
6.1
Frequency Synthesizer Basics
A core component of a transceiver circuitry is the frequency synthesizer. The synthesizer
generates carrier frequencies for passband modulation schemes and often determines the
start-up time of a transmitter. Implementation of a frequency synthesizer can be categorized
into either direct synthesis or indirect synthesis.
frej
xK
-
BPF
-+fou=KMfref
/M
Figure 6-1: Direct frequency synthesizer using frequency multipliers and dividers.
89
90
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
input
word
'L
Phase
Accumulate
ROM
DAC
LPF
Figure 6-2: Direct frequency synthesizer using DAC and lookup table.
A direct synthesis method uses a reference clock as the source of sine waves and does
not have an oscillator of its own. A generic direct synthesis method based on frequency
multipliers is shown in Figure 6-1.
By using mixers and dividers, a rational multiple of
the reference frequency can be achieved. The advantage of this architecture for a sensor
network is that its start-up is fast, since it is determined by the settling time of the mixers.
The drawback however, is that its power consumption is high due to the mixers and that its
frequency resolution is limited. Another method of direct frequency synthesis is the direct
digital frequency synthesis (DDFS). This method implements sine waves from a digital
reference clock by using DACs and lookup tables as shown in Figure 6-2. While DDFS has
the advantage of fast settling time and high frequency resolution, the critical drawback is
that its power consumption is very high due to the high operating frequency. The DDFS
requires the reference clock frequency to be at least twice the output frequency [55] and
hence it is not practical to use DDFS at GHz frequencies due to high power consumption.
For example, DDFS at hundreds of MHz easily consumes watts of power due to the high
complexity of the digital circuitry. Hybrids of these two schemes are also possible but do
not solve the problem of high power dissipation.
While the direct synthesis method suffers from power dissipation, indirect synthesis using
a phase locked loop (PLL) is a simple approach that is agile and consumes low power. Due to
the ease of implementation in integrated circuits, it has gained great popularity in frequency
synthesizers and clock recovery circuits. A basic block digram of the PLL based frequency
synthesizer is shown in Figure 6-3. The voltage controlled oscillator (VCO) generates the
carrier frequency that is divided down to a lower frequency for phase comparison with the
reference clock. The charge pump phase frequency detector (CP-PFD) produces a phase
6.1.
91
FREQUENCY SYNTHESIZER BASICS
CP-PFD
Loop Filter
-
R
U
D
D
JFLJL~H
-
r
VCO
c
S
Lit
Figure 6-3: Indirect frequency synthesizer using PLL.
difference that is smoothed out by the loop filter. When the reference clock and the divided
output are phase aligned, the PLL is in lock and the VCO's output frequency is equal to N
times the reference frequency, where N is the divider value (i.e., fot = Nfref). The output
frequency can be changed in integer multiples of the reference frequency by changing the
divider value N and hence this architecture is called the integer-N frequency synthesizer.
6.1.1
Fractional-N synthesizer
Stability
An important aspect of a charge pump PLL is that it is a mixture of discrete and continuous
time systems. While the VCO output and its control input are continuous time signals,
charge pump PFD outputs are discrete time signals. This is due to the charge pump PFD
that essentially samples the phase difference every reference clock. Since the PLL is changed
from an s-domain to a z-domain from sampling, the issue of stability must be considered. In
order to maintain a stable system, the loop bandwidth must be kept low enough such that
the discrete time samples are averaged out to be seen as a smooth continuous time signal,
or else the feedback will force the loop out of stability. While the details of the stability
requirements can be found in Gardner's paper [56], a general rule of thumb for stability is
that the loop bandwidth of the PLL be kept below one tenth of the reference frequency.
Since the PLL is a negative feedback system, there is another stability issue that arises
if the loop gain is -1.
This can be solved by designing the loop filter such that enough phase
92
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
margin is achieved at the unity gain frequency.
Frequency resolution and lock time
In an integer-N frequency synthesizer architecture, a large loop bandwidth is desirable.
A large loop bandwidth results in a fast settling time and helps to reduce the contribution of the VCO phase noise to the output, which is often dominant in integrated circuits.
Unfortunately, the loop bandwidth cannot be increased indefinitely since it must be kept
below the reference frequency for stability reason. The reference frequency also cannot be
increased in integer-N frequency synthesizer architectures, because the frequency resolution
is determined by the reference frequency. For example, frequency resolution of 1MHz requires reference frequency to be less than 1MHz. This will limit the loop bandwidth to less
than 100kHz, resulting settling times as large as 100ps. Therefore, integer-N architectures
cannot be used for systems that require both high frequency resolution and fast start-up
time.
Fractional-N synthesizer
The frequency resolution and the reference frequency can be decoupled by using fractionalN synthesis.
The idea is to dither the divider value such that on average, the divider
value is equal to the desired value. The averaging is done through the low pass loop filter.
For example, if the divider value is 100 for nine reference clock cycles and 101 for one
reference clock cycle, the average divide value over 10 cycles will be 100.1.
Therefore,
frequency resolution that is independent of the reference frequency can be achieved. Hence,
the reference frequency can be increased without degrading the frequency resolution, which
implies that loop bandwidth can also be increased without being limited by stability issue,
helping to reduce the start-up time. However, there are some drawbacks of the fractional-N
synthesizer, namely the fractional spur and the quantization noise. Since the instantaneous
division value is not a fractional value but an integer value, quantization error is bound to
show up as undesired noise at the output spectrum. In addition, if any periodic contents
are found in the dithering pattern of the divider value, sideband called 'fractional spur'
will show up at the output as well. The fractional spur can be reduced by removing the
6.2. LOW POWER VCO: ARCHITECTURAL APPROACH
93
periodic pattern of the dithering value, by employing a digital E-A modulator. The E-A
modulator basically produces pseudo-random dithering patterns for the divider so that the
fractional spur is suppressed while the average value of the dithering pattern is unaffected.
In addition, E-A moves the quantization noise to a higher frequency, which is suppressed
by the PLL in closed loop.
In summary, the fraction-N synthesizer has the advantage over integer-N architecture in
that it allows higher reference frequency since frequency resolution is not limited to integer
multiples of the reference frequency. Consequently, a high loop bandwidth is realizable and
hence fast start-up time can be achieved. The challenge, however, is to reduce the quantization noise with low power consumption. In the following sections, low power techniques
for a E-A fractional-N synthesizer will be proposed from architecture and circuits.
6.2
Low Power VCO: Architectural Approach
A key component of the frequency synthesizer is the VCO. Needless to say, achieving low
phase noise, wide tuning range and low power consumption in a VCO are the key issues
in implementing an energy efficient transmitter. In this section, power consumption of the
VCO is reduced by exploiting the loop characteristics of the PLL.
The power consumption of a E-A fractional-N synthesizer is given by the following
equation, which is the summation of each component's power consumption.
Ptotal
=
S
VC + PDIV + PEA + PCP + PPFD
VCO
+ PDIV + PEA
(6.1)
In most cases, the power consumption is dominated by three components: VCO, divider,
and E-A. When reducing the power consumption of these components, great care must be
taken in order not to increase the output noise, since power often has a direct impact on
noise. In a fractional-N synthesizer, the output noise can be represented by the following
equation,
94
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
"r-
foul
PFD
vco
PLL
OZA
PLL
Figure 6-4: Noise sources in a fractional-N frequency synthesizer.
total
=
fvco(wc) vco + f A(we)A + fCP-PFD(Wc)
CP-PFD
+fDIV(UWC)'DIV + fLoop(Wc)hLoop + fref-clk(Wc)
ref-clk
(6.2)
fvco(Wc) vco + fEA(Wc)r"A
fx()
where 4, is the noise of the component x and
is the loop transfer function seen by
the component x when the loop bandwidth of the synthesizer is wc. The output noise is
usually dominated by the phase noise of the VCO (Dvco) and quantization noise (GDA)
from the E-A modulator. In detail, Dvco can be described by the following equation,
1VC0
=
2FkT
PVC0
(
)2}1
_L+1
2Qf
-
}
f
(6.3)
where PVC0 is the power consumption of the VCO, Q is the quality factor of the oscillator
tank, 2FkT is the thermal noise constant,
f3
is the flicker noise corner of the device and f
is the frequency of interest.
The quantization noise, DrA, can be described by
(2=rE)2
12fref
sin
7r
(
f
(6.4)
fref
where fref is the operating frequency of the E-A, E is the maximum quantization error,
and m is the order of the EA.
In the E-A, the power consumption is proportional to
6.2. LOW POWER VCO: ARCHITECTURAL APPROACH
its order and the reference frequency (i.e., PrA c mfref).
95
From these equations, it can
be seen that noise is inversely related to power consumption.
Therefore, any efforts in
trying to reduce power consumption of the VCO or the E-A will increase the noise of that
component. Fortunately, recall that the component noise is filtered by the PLL before it
appears at the output, as seen in Eq. 6.2 and Figure 6-4. For the VCO phase noise ('Dvco),
PLL exhibits a high pass characteristics. Hence the contribution of 4yco to the output can
be reduced if the loop bandwidth(wc) is increased. In other words, the power consumption
of the VCO (Pvco) can be reduced and yet, the same output noise can be achieved by
increasing w,. However, for the E-A, an increase in w, will increase the noise from E-A,
since the quantization noise (' 1 zA) goes through a low pass characteristics of the PLL. In
order to keep the same noise contribution from E-A to the output, power consumption of
the E-A (PEA) must be increased in order to lower GDA. Therefore, it can be seen that
there is a trade-off between the power consumption of the VCO and the E-A, as illustrated
in Figure 6-5. A large loop bandwidth reduces the contribution of VCO phase noise to the
output while increasing the contribution of quantization noise. Consequently, VCO power
consumption can be reduced at the cost of higher EA power consumption. On the other
hand, a small loop bandwidth reduces quantization noise and increases the VCO phase noise
at the output, which leads to higher VCO power and lower EA power consumption.
ME~
+ + =
PVC4
$XA j
Ototal =
constant
PLL
PEX A
Figure 6-5: Effect of loop bandwidth on VCO and E-A noise.
A circuit level simulation that shows this trade-off is shown in Figure 6-6.
In this
simulation, output noise level is kept constant in all conditions. It can be seen that higher
96
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
5
4
PTotal
3 - 0
o
eo
vco
P
1
0
>
0
2
4
6
8
Loop bandwidth (MHz)
10
Figure 6-6: Power consumption of VCO and E-A in different loop bandwidths.
loop bandwidth reduces the power consumption of the VCO. The total power consumption
is minimized when the loop bandwidth is kept to a minimum. It should be noted that this
result is highly dependent upon process and digital technology. Considering the previous
analysis between VCO and E-A as trade-offs between analog (VCO) and digital (E-A)
circuitries' power consumption, an analog-friendly process will favor a low loop bandwidth
while a state of the art digital technology with poor analog components will favor high
loop bandwidth. In the simulation above, the E-A is implemented in a 0.25pm CMOS
technology, while the VCO's is implemented using an inductor with a quality factor of 15.
Such a high
Q
inductor is a benefit of BiCMOS technology which is analog friendly, and
this results in phase noise of -113dBc at 1MHz with only 3mW of VCO power dissipation
at 5.8GHz. If a standard digital CMOS technology is used, it can be expected that the
inductor
Q
would be much lower and the power consumption of the VCO will increase in
a quadratic fashion to compensate for the lower
Q
as seen in Eq. 6.3. On the other hand,
better digital technology (i.e. shorter gate length) will reduce the power consumption of the
E-A. Therefore, wide loop bandwidth will be preferred in a pure digital CMOS technology
that lacks high
Q
passive components.
6.3. LOW POWER DIVIDER: ARCHITECTURAL APPROACH
6.3
6.3.1
97
Low Power Divider: Architectural Approach
Divider vs. E-A
In the GHz regime, the power consumption of the frequency synthesizer is often dominated
by the multi-modulus dividers, especially in the first few stages where operating frequency
is very high [40, 57]. Examples of multi-modulus divider architectures are shown in Fig. 671. From the standpoint of power consumption, fixed prescalers are more desirable than a
multi-modulus divider, since multi-modulus dividers require digital logic that operate near
the carrier frequency and consume much more power. Therefore power consumption can
be reduced if fixed prescalers are used at the first few stages of the divider chain and multimodulus divider are moved to later stages with a lower operating frequency. The penalty,
however, is that the quantization noise from E-A will increase by 6dB each time a divideby-two prescaler is inserted.
Moreover, the achievable frequency resolution is decreased
by a factor of two. In order to cancel out the increased quantization noise and keep the
same frequency resolution, complexity of the E-A must be increased, which results in a
larger E-A power consumption. Hence there is a trade-off between divider and E-A power
consumption.
As we try to decrease the divider power consumption by inserting fixed
prescalers at high frequency stages, we lose the frequency resolution and noise property
that need to be overcome by increasing the power consumption of the E-A. A circuit level
simulation which shows this trade-off has been conducted and the results are shown in
Figure 6-9.
In order to keep the same output noise and frequency resolution with more
number of prescalers, complexity of the E-A is increased accordingly. It can be seen that
the total power consumption reaches minimum when a fixed prescaler of divide-by-8 is used
before a dual modulus divider. The output noise of the synthesizer is shown in Figure 6-8,
for the cases when the number of divide-by-2 are 1, 2, 3 and 4. Quantization noise increases
as the number of divide-by-two stages is increased. However, the increased phase noise is
under the target specification.
Although other divider techniques exist such as pulse swallow architectures, cascade of divide-by-2/3
stages are shown here just for conceptual illustration.
98
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
6GHz 3GHz 1.5GHz 0.75GHz
/2,3
/2,3
/2,3
/2,3
... /N, /N+1, /N+2,..
+6dB
OEA
fo
/2
/2,3
/2,3
#0A
4
/2
/2
/2,3
Lower divider power
... /N, /N+2, /N+4,..
/2,3
Larger quantization noise
+6dB
... IN, /N+4, /N+8,..
/2,3
Figure 6-7: Multi-modulus divider architectures.
Second order PLL, loop BW = 100kHz, VCO noise=-1lOdBc/Hz @ 1 MHz
-An.
-90
--
-
-
-
-
Npre=3
-..-.-.-.-.-
-
-- 100
- ---
-0
-120
0-130
-140
-15C
-
100
1o
Frequency(Hz)
Figure 6-8: Output noise of the PLL for different divider architectures.
5
4
3
2
C4
- A
0
I
2
3
number of divide-by-2 prescalers
4
Figure 6-9: Power consumption of divider and E-A.
6.4. LOW POWER VCO: CIRCUIT TECHNIQUES
6.4
99
Low power VCO: Circuit Techniques
The performance of a stand-alone VCO is measured by its phase noise, power consumption
and tuning range. While low phase noise and power consumption are required for a high
performance, energy efficient communication, tuning range is necessary to switch the carrier
frequency over a wide frequency band.
More importantly, tuning range is essential to
overcome process variations in fabrication. In this section, design methodologies for a low
power VCO will be viewed from the circuit perspective. In particular, the CMOS varactor
will be focused in order to achieve high Q and wide tuning range.
6.4.1
Low phase noise VCO
Over the past years, various models have been proposed to analyze the phase noise of a
VCO. A fundamental theory was proposed by Leeson [58], which relates phase noise to
signal power, quality factor (Q) of the tank, and 1/f noise, as described below.
2FkT
1vco =1+1+-(6.5)
PVC
f(
(65
+f 2QfI
A recent linear time varying theory by Hajimiri [59] went a step further and suggested
that phase noise is related to the signal waveform. One key theory of this work was that 1/f
noise can be controlled by the waveform, and that 1/f noise is proportional to the DC value
of the impulse sensitivity function, which in most cases is similar to the time derivative of
the oscillating waveform. Hence, 1/f noise could be lowered if time integral of the waveform
is reduced. Therefore, if we are able to keep the waveform perfectly symmetric, 1/f noise
could ideally be eliminated.
Circuit topology
The circuits shown in Fig. 6-10 illustrate two types of VCO schematics. Basically, the L-C
tank generates the oscillation at a desired frequency and the transistor pair forms a negative
gm tank to account for the loss in the L-C tank. Following from the theory by Hajimiri,
the circuit in Fig. 6-10(b) achieves lower phase noise from the fact that the NMOS and
100
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
Noise from
VDD
M7
M8
out+
outM3
M4
M5
MI
M2
M6
Noise from
current mirror
Noise from
GND
(a)
(b)
Figure 6-10: Circuit schematic of the VCO.
PMOS pair provide a more symmetric waveform, thereby reducing 1/f noise [60]. However,
it should also be noted that this structure has advantages over the structure in (a) when
outside noise source is considered together with how it is coupled to the output. In Fig. 610(b), the sources of noise other than the negative gm transistor pair are the supply, ground,
and substrate noise. The ground and supply noise are coupled through the low gain common
gate amplifier formed by M5 through M8. In Fig. 6-10(a), there are additional noise sources
from the current mirror that contribute to the output noise. This noise is coupled through
the high gain common source amplifier at M2 and results in higher phase noise than the
circuit in (b). In addition, power is wasted by the bias current in MI. This bias current
cannot be made small compared to the current in M2, since current multiplication in the
mirror will increase the output noise [61].
The circuit in (b) does not suffer from these
issues and therefore it is chosen as the VCO for the frequency synthesizer.
Resonant tank optimization
The
Q
of the L-C tank is important as it has a quadratic effect on phase noise as seen in
Eq. 6.5. While many L-C combinations exist at the desired frequency, it is advantageous to
use a small inductor and a large capacitor, since it is easier to implement a high
with a small value than a large value.
Q inductor
Given a certain value of inductor, the required
capacitor to achieve the desired resonant frequency can be calculated by the following
6.4. LOW POWER VCO: CIRCUIT TECHNIQUES
101
equation,
1
fo
where
f,
2r
1
LC
2,r
L(Cvar + Cp)
1
2rVL(Cvar + kWLCox )
(66)
is the desired resonant frequency, L, Cvar are the value of the inductor and
varactor and C, is the capacitance of the -gm
transistor pairs, which can be expressed by
their width and length (kWLCx). The tuning range can be maximized if C, is minimized,
which requires the use of a minimum length devices for the transistor pair to achieve a
certain gm.
However, 1/f noise is inversely proportional to WL and minimum length
device will increase the 1/f noise. In order to reduce the 1/f noise, it is advantageous to
use a long length device and sacrifice the tuning range. The implemented VCO uses NMOS
devices that are twice the minimum size device to reduce the 1/f noise.
6.4.2
VCO with modulation input
The direct VCO modulation architecture requires two control inputs for the VCO, one for
the main control from the PLL and the other for modulation. These control inputs can be
implemented using CMOS varactors as shown in Figure 6-11. In addition to the varactor
design methodologies that will be explained in the next section, there are a couple of more
things to note for the modulation varactor.
First, the tuning range should be on the same order as the data rate. If the tuning
range of the varactor is too large, then the modulation input need to be adjusted to a
small level, resulting in high susceptibility to noise. For example, if the tuning range of the
modulation varactor is 100MHz over IV range, the voltage swing of the modulation input
need to be less than 10mV to achieve 1Mbps BFSK. This significantly reduces the SNR of
the modulation input. On the other hand, if the tuning range is too small then the desired
data rate cannot be achieved. Second, the modulation varactor must have a linear tuning
range over the modulation input. If the modulation input operates in the non-linear mode,
the spectrum will be distorted from the ideal spectrum. For example, if the voltage in the
'1' regime has lower gain than the voltage in the '0' region, side-lobes of '1' will be smaller
102
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
x
Ml
M2
M5
M6
8
M1,M2: .8u
x 12
M3,M4:
x 12
Vctrl
M7
-
M8
0.52u
M5,M6:
6u
X74
0.26u
Vmod
M5,M6:
M-4
M3
Nfinger
2u x 3
0.26u
Figure 6-11: Schematic of the 6.5GHz VCO.
in the output spectrum. Finally, the varactor must be designed for maximum
Q of the
Q
Q.
Since the
overall L-C tank is given by parallel connection of inductor and two varactors, the
of the modulation varactor must be maximized in order not to affect the original
Q
set
by the inductor and the high gain varactor. This can be easily achieved since the tuning
range of the modulation varactor is small.
6.4.3
CMOS varactor
Improving the quality factor of the oscillator tank has been an active area of research and
is critical to reducing phase noise and power consumption of the VCO. The effective
an LC tank is given by the following equation, where
QL
and
QC
are the
Q
Q
of
of the inductor
and capacitor respectively.
Q-1 = QLI + Qg
In most standard silicon processes,
Q
(6.7)
is dominated by the on chip inductors. How-
ever, recent improvements in process and design technologies, such as low resistance copper
metal [62] with circular structures [63] and substrate loss reduction techniques such as pattered ground shields [64] and deep trench [62], have made it possible to achieve high inductor
Qs of 15 to 20. Furthermore, inductor
Q will
tend to increase with frequency since high
Q
inductors are easier to achieve at higher frequencies since a smaller inductor size will have
less resistance in metal and have lower loss through substrate coupling [63]. Therefore the
6.4. LOW POWER VCO: CIRCUIT TECHNIQUES
103
R9
Req
a-
R
c- -:C
T Ce
Req
C
eq
Rch/ 4 + Rg
~= C
ox
Rsub
On : VGS > Vt (Inverted Channel)
Figure 6-12: A CMOS varactor in high capacitance mode.
Q
of the varactor has gained increased importance in addition to its ability to provide wide
tuning range.
Several approaches have been proposed to increase the tuning range of the varactor such
as the accumulation region varactor and gated varactor [65, 66]. These techniques provide
wide tuning range by reducing the parasitic junction capacitance in the off state of an MOS
device. However, these approaches do not follow common layout procedures, which often
leads to design rule violations in standard processes. A regular CMOS varactor on the other
hand, follows common layout procedures, offering ease of design. Moreover, recent study
shows that the tuning range of a regular CMOS varactor is comparable to that of other
sophisticated techniques [67].
In order to analyze the
Q
and the tuning range of a regular CMOS varactor, a detailed
model of an NMOS is shown in Fig. 6-12 and Fig. 6-13, each representing the state when
the NMOS is on and off. The MOS device is further simplified to a series of equivalent
resistance and capacitance.
Increasing the tuning range
In the on-state, the equivalent capacitance reaches maximum, which is dominated by the
gate oxide capacitance (C,). In the off-state, the capacitance is at minimum, which is
given by the parasitic capacitances of the junction and the overlap capacitances. Therefore,
the capacitance of a multi-finger device can be described by the following equation, where
N is the number of fingers and C,
,
C are the capacitance of the gate oxide, overlap
104
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
R9
completely off
depleted channel
C
d
d
Ti
TCd
Re=
Rg + Rsub
Ceq
2COv
Req ~= Rg
+ [CO-
1
+ (Cd'+Cd)~
Ceq
]1
2COv
+ 2ci
Rsub
Off : 0.5 VGS < Vt
Figure 6-13: A CMOS varactor in low capacitance mode.
and junction between the diffusion and substrate, respectively.
Con = NCOXWL
Coff = 2N(Cov + Cj)
(6.8)
For a given required capacitance, the tuning range can be maximized by using a single
finger device. For example, if the required capacitance in the on-state is 3COXWL, then it
can be implemented using a one-finger device or a three-finger device as shown in Fig. 6-14.
While both have same on capacitance, the single finger structure has a lower off capacitance,
due to the lower overlap capacitance.
D-*poly
Con =3Cox WL
Coff= 6Cv+6C
wt
Con = 3COx WL
Coff = 2COv+2C
diffusion
Figure 6-14: Capacitance of two varactor structures.
Increasing
Q
In order to maximize
Q,
the equivalent resistance (Req) must be minimized. In the on-
state, Req is approximately equal to the sum of the gate and channel resistances (Req
=
Rch/4 + R9 ). The gate resistance can be modeled as sheet resistance, and hence for a given
6.4. LOW POWER VCO: CIRCUIT TECHNIQUES
105
on capacitance (NWLCX), a long length, square shaped device lowers the gate resistance.
The channel resistance on the other hand, is inversely proportional to the gm of the device
and hence short length device will reduce the channel resistance.
Therefore, there is a
trade-off between the gate and the channel resistances. While low gate resistance requires
a long length device, low channel resistance needs a short length device. The equivalent
on-resistance can be described by the following equation,
Req
Rch
R- + -c=
_l
4
kW
-+
N L
-
W
k
L
k
equality:
k2__
>
2
-v/k 1 k 2
N(WL) - N
(6.9)
where k, and k2 represent constants from device parameters. It can be seen that the
Req can be reduced by increasing the number of fingers,N. For a given N, Req reaches
minimum when the WIL specified in the above equation is used.
In the off-state, the equivalent resistance is determined by the gate and substrate resistance (Req = Rsub + Rg). This can be minimized by placing many substrate contacts close
to the varactor and increasing the number of fingers of the device.
From the above discussion, it can be seen that the on and off resistance can both be
reduced by increasing the number of fingers. Recalling that the tuning range favors fewer of
fingers, a trade-off between the quality factor and the tuning range can be seen. While more
fingers will lower the resistance and raise
tuning range. In many cases, the
of fingers should be used.
Q
Q
of the varactor, fewer fingers will increase the
is a more important factor and hence a large number
106
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
6.5
6.5.1
Low Power Divide-by-112/120:
Circuit Techniques
Divide-by-8
The prescaler divide-by-8 is based on high speed divide-by-2 flip-flops as shown in Figure 615. The first divide-by-2 is based on the design by Wang [68]. The internal cross-coupled
NMOS pair with PMOS loads form a latching pair while the PMOS transistors outside
form a sensing pair. An important property of this circuit topology is that the PMOS loads
have low impedance in the transparent mode (clock=low) and high during latched mode
(clock=high).
RC time constant is therefore small, resulting in a very fast divider. The
next two divide-by-two stages are based on the design by Razavi [69]. This circuit has the
advantage of less input clock capacitance and larger output swing.
In order to operate these dividers at a low supply voltage of 1.6V with small input
amplitude, the input clocked transistors are biased separately from the input RF signals with
DC blocking capacitors. The blocking capacitors are implemented using MIM capacitors
and the bias is fed through a poly resistor. The values of the capacitor and the resistor are
set such that the input RF signal undergoes little attenuation. In the design, the capacitance
value is set to be 100fF, which results in about 5% attenuation of the input signal swing.
The resistor value is set large enough to be seen as a high impedance node from the input
signal and small enough as not to add significant thermal noise to the output. The thermal
noise due to the resistor goes through the PLL loop transfer function and shows up at the
output, which can be calculated using the following equation,
res
=
+Gopen
(I + Gopen)
4kTR
(6.10)
where Gopen is the open loop gain of the PLL. Assuming a maximum VCO gain of
500MHz/V and a loop bandwidth of 100kHz, resistors as large as 1OOkQs contribute about
-145dBc of noise at 100kHz offset, which is negligible compared to the VCO phase noise.
Resistor values used in the chip are 10kQ. Test measurement from the fabricated chip does
not show any degradation in output phase noise whether the divider is on or off, which
verifies the above analysis.
6.5. LOW POWER DIVIDE-BY-112/120: CIRCUIT TECHNIQUES
107
bias circuitry
clk
Q
cl
4brbp
n:
clk
ig
CLK
6.5GHz
bck
I
I
clk
.. _N-r
cIk
b
clk
kik
AA-
-1-
br
CLK
*
1
I
I
Q--
Dk
I
clk
-
Q
FIk
-
Figure 6-15: Circuit schematic of the divide-by-8 prescaler.
D
-
Q
D
Q
Div 3/4
D
Q
DV:S:~ 3/
Di 2
Div
fin
Out
Div 14/15
Figure 6-16: Schematic of the divide-by-14/15.
108
6.5.2
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
Divide-by-14/15
The divide-by-14/15 stage is shown in Figure 6-16.
It is composed of a divide-by-3/4
followed by a cascade of two divide-by-2 circuits. The divide-by-3/4 is formed using two
edge triggered flip-flops with differential control logic that divides the input by 4 when the
modulus control (mc) is high and by 3 when mc is low. The cascaded divided-by-2 forms
an asynchronous divide-by-4 circuit. The different skew path seen in the control logic of
divide-by-3/4 (nand vs nor gates) does not affect the performance of the divider, since it
is based on a synchronous positive edge triggered flip-flop. By employing a positive edge
triggered flip-flop in the asynchronous circuit, critical path has three clock cycles to work
with rather than one clock cycle seen in a negative edge triggered flip-flop. All the signal
paths are differential to increase power and ground noise rejection.
6.6
E-A
The E-A is based on a single loop architecture. Although the MASH architecture offers
several advantages that are favored in many E-A modulators, single loop architecture is
better suited for the frequency synthesizer shown in this chapter for the following reasons.
First of all, the single loop architecture produces less quantization noise than the MASH.
While an Mth order MASH produces an M bit output, an Mth order single loop EA provides a single bit output. Hence the quantization error for a MASH lies between
[0, 2M - 1] while that of a single loop lies between [0, 1].
Therefore, lower quantization
noise is produced from a single loop architecture. Second, the larger output bit width of a
MASH requires more complex divider and phase detector. Due to the larger division range,
a MASH needs a multi-modulus divider instead of a dual modulus divider. In addition,
the phase detector must have larger linear range than a single loop architecture, since the
instantaneous phase error is larger. With the prescaler value of 8 used in the frequency
synthesizer, the quantization error and phase error of the MASH becomes even larger,
as shown in Fig. 6-17. Finally, as will be seen in the Chapter 5, the large phase difference
produced by MASH is not well suited for variable loop bandwidth techniques. While MASH
presents some merits such as unconditional stability and easily pipelined architecture, the
109
6.7. PHASE FREQUENCY DETECTOR AND CHARGE PUMP
above reasons make the single loop architecture a more suitable choice.
Divide Value
8(Nd+2M-1)
Divide Value
Qerror
8(Nd+l)
-
8(Nd+l)
8(Nd+l)
-
8Nd
-
QerrorN
8Nd
Single loop
MASH
Figure 6-17: Quantization error and divider range of single loop E-A and MASH.
The single loop architecture used in the design is shown in Figure 6-18. The designed
MASH only requires three adders since the first adder always adds of +29, which can be
implemented using inverters.
IF
K+
_-Z
Figure 6-18: Architecture of the single loop E-A.
6.7
Phase Frequency Detector and Charge Pump
The PFD is based on a popular flip-flop structure used in many PLLs [50, 52]. The dead
zone is avoided by allowing enough delay through the OR gate so that current flows through
the charge pump even for small phase differences. The charge pump is based on a current
110
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
steering switch [70] as shown in Figure 6-20. The inherent mismatch between PMOS and
NMOS is avoided by using NMOS only switches.
An important thing to avoid in this
charge pump is the reverse current flow that result from finite output resistance of the
current source. As the output voltage varies, the current from M6 and M8 will change from
its ideal value due to the channel length modulation effect and therefore current mismatch
will occur. While some mismatches are acceptable as long as the output current increases
monotonically with of phase difference, it becomes a serious problem if the output current
reverses its direction. That is, even if the UP signal is asserted high for a longer duration
than the DN signal, the output voltage may be high enough to cause smaller current from
M8 than the current from M6.
Hence charge on the loop filter is taken away when it
should be added. Although this problem is often solved by increasing the output resistance
with cascoded transistors at the output, it cannot be applied when the supply voltage is
low. Therefore, long channel devices are used in order to increase the output resistance.
Moreover, it is important to not oversize the tail current source M1 and M2, since large
sized devices will increase the gm of these devices, which will increase the effect of channel
length modulation.
ref
R 4>-up
s
R
div
R
dn
Figure 6-19: Circuit schematic of the phase frequency detector.
6.7.1
Charge pump for variable loop filter
The schematic of the charge pump used in the variable loop bandwidth modes are shown in
Figure 6-21. The charge pumps for both large and intermediate loop values have the same
schematic and their only difference is the size of the transistors. In order to save power
6.8. LOOP FILTER
III
x2
M1,M2:
M8
M7
M3-M6:
2u
.24u
M7,M8:
2ux 2
M9:
2u.
out
off-chip:
"P
M3
M4
Fp
F
M5
M,
M9
M6
n
x2u
M2
Figure 6-20: Circuit schematic of the charge pump.
consumption in the final loop bandwidth mode, all the current paths are shut down by the
switch SHDN.
6.8
Loop Filter
The loop filters are implemented off chip as shown in Figure 6-22.
resistor paths are implemented using NMOS devices.
The switches in the
The parasitic capacitances of the
chip package and the PCB board form very high frequency poles and does not affect the
PLL performance. The low pass filter of R 3 and C3 aids the suppression of the reference
frequency leakage to the output spectrum.
6.9
Energy Efficient BFSK Modulator
The block diagram of the energy efficient BFSK modulator is shown in Figure 6-23. The
E-A provides 1MHz of frequency resolution with a reference frequency of 55MHz.
The
high reference frequency allows large loop bandwidth in the initial stage of the variable
loop bandwidth method. The power consumption of the divider is dramatically reduced by
using a low power prescaler divider-by-8. The BFSK modulation is achieved by directly
modulating the VCO.
112
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
Sp
up
up2
dn
dn2
2S
S
Figure 6-21: Charge pump of the variable loop frequency synthesizer.
6.10
Summary
Design methodologies for low power frequency synthesizer were investigated.
The high
frequency VCO and the digital E-A modulator has opposite effect on each other's power
consumption in conjunction with the loop bandwidth. While large loop bandwidth reduces
the power consumption of the VCO, it increases the power consumption of the E-A. In
that regards, the loop bandwidth can be considered as a measure of process technology
on whether it is analog-friendly or digital-friendly. The E-A modulator also reduces the
power consumption of the dual-modulus divider by allowing more prescaler stages at high
frequency. On the circuit side, the trade-off is also seen between the tuning range and the
phase noise of the VCO.
6.10.
113
SUMMARY
from
charge pump
Cl
R3
A
j
C
I
C2
control
I
~-
C3
R2-2
R2-1
-
VCO
off-chip
-
on-chip
from variable
loop control unit
Figure 6-22: Loop filter of the frequency synthesizer.
00
off-chip
ref
cik
fmu
R::D
F
I
C2
I2
T
C,
T C3
R2
lock detect
Pres caler /8
/14, 1
channelYE
select
Figure 6-23: Variable loop bandwidth frequency synthesizer.
114
CHAPTER 6. IMPLEMENTATION OF ENERGY EFFICIENT TRANSMITTER
Chapter 7
Prototype Test Results
The design methodologies discussed in the previous chapters are applied to a prototype chip
fabricated in IBM's 0.25pm SiGe BiCMOS technology. The implemented chip uses only the
CMOS part of the technology to test the capability of CMOS at high frequencies.
7.1
7.1.1
Frequency Synthesizer
VCO
Two VCOs have been fabricated for the RF transmitter. The first is a stand-alone VCO
fabricated in IBM's 0.35pm BiCMOS technology and the second one is a VCO that is
integrated together with the frequency synthesizer using 0.25pm BiCMOS technology. The
first stand-alone VCO achieves 15% tuning range around the center frequency of 5.3GHz and
the phase noise is -l20dBc/Hz at 1MHz offset from the 5.7GHz, while consuming 24mW
from a 3V power supply. The 1/f noise corner is around 500kHz and the phase noise
variation over the tuning range is less than 3dB. The measured phase noise plot, die photo
and the summary of chip test results are shown in Figure 7-1, 7-2 and Table 7.1, respectively.
The VCO also operates at 1.8V with 2.7mA, in which case the phase noise increases to 104.ldBc/Hz L 1MHz. This value of phase noise is very close to the theoretical value when
we account for the reduction in VCO's power consumption from 28mW to 4.8mW, which
causes 15dB increase in phase noise from Leeson's equation. The measured tuning range
at 1.8V is 14.6%. The tuning range is not effected much by the reduction of power supply
115
CHAPTER 7. PROTOTYPE TEST RESULTS
116
SPOT FRO
10 dB/
L-50 dBc/Hz
10
kHz
FROM
-
1.00 MHz
dBC/Hz
-120.00
FREQUENCY OFFSET
S.683 GHz CARRIER
10
MHz
Figure 7-1: Measured phase noise at 5.68GHz.
Figure 7-2: Die photo of the 5.3GHz VCO.
Frequency
Power
Phase Noise
Area
4.89 ~ 5.72GHz (15.6%)
8mA from 3V
-120dBc @ 1MHz
0.49mm2
Table 7.1: Summary of VCO test results.
7.1.
FREQUENCY SYNTHESIZER
117
VCO tuning range vs. modulation input
VCO tuning range vs. control voltage
6,192
90
-
6191
6500 -6l6
6100
i0
r
rt6.n
0
60
pl
LL
LL
0.4
0.6
0,8
1
1.2
1.4
1.6
1.6
2
6.162
0
-
0.2
Control Votage(V)
Figure 7-3: Tuning characteristic of the VCO on
main control input,
0.4
_________________________
068
068
1
12
1.4
Modulation input voltage(V)
Figure 7-4: Tuning characteristic of the VCO on
modulation input.
voltage, since the varactor can still change from on to off state.
The second VCO's center frequency is at 6.5GHz and the tuning range is 12%(6.1GHz
6.9GHz) as shown in Figure 7-3. The tuning curve shows linear characteristic when the
control voltages is near 1V. This is where the MOS varactor is in the linear region, changing
its state from an inverted mode to a depletion mode. As the control voltage reaches closer
to the supply voltage or the ground, the varactor enters completely on or off state and
the voltage gain is reduced. The tuning characteristics of the low gain varactor for the
modulation input is shown in Figure 7-4. It has similar curve as the large gain varactor,
except that its turning range is 8MHz. Ideally, this tuning range determines the maximum
data rate in a closed loop direct VCO modulation. However, in practice, the maximum
achievable data rate is smaller than the tuning range, due to the non-linearity of the tuning
curve. When the measured tuning curve is compared to the dashed line that represents the
ideal linear tuning curve, the graph is linear for 3.5MHz, which corresponds to 7Mbps of
BFSK data with a modulation index of 0.5.
The phase noise of the VCO is plotted in Figure 7-5, which shows -I12dBc/Hz of noise at
1MHz offset from the center frequency, while consuming 7.7mA from a 2.3V power supply.
The 1/f noise is approximately 120kHz, which is significantly lower than a single NFET's
1/f corner of couple of MHz. The phase noise over the tuning range is plotted in Figure 7-6.
It shows measured phase noise and the ideal phase noise with constant tank
Q.
The ideal
118
CHAPTER 7. PROTOTYPE TEST RESULTS
10
RL
dB/
-50
SPOT FRO
dBc/Hz
=
1.
00
-112._33
VCO phase noise vs frequency, @1 MHz from the center
MHz
dBC/Hz
-110-
I -110.5
U --
measured
-
0
I-111--
-111.5 -
-112constant tank Q
10
kHz
FROM
FREQUENCY OFFSET
6.099 GHz CARRIER
10
MHz
Figure 7-5: Phase noise plot of the VCO.
phase noise assumes that the the
Q
-112.L6
62
6.6
6.4
Frequency (GHz)
6.8
Figure 7-6: Phase noise at different frequ encies.
of the tank is constant throughout the tuning range
with the value at 6.1GHz and extrapolates phase noise at different frequencies from Eq. 6.5.
The measured phase noise increases with operating frequency more than the ideal value.
The difference between the two phase noise reaches maximum of 1.5dB when the operating
frequency is maximum. This is due to the degradation of
Q
Q
of the L-C tank. While the
degradation can be caused by both the varactor and inductor, it is more likely that it is
because of the inductor. The varactor
Q of the
off-state is determined by the substrate and
the gate resistance as discussed in Section 6.4.3 and this is often smaller than the Q in the
on-state. For the inductor, the
Q peaks
at only a particular frequency and rolls off at other
frequencies. From the measured plot, it can be estimated that the frequency at which the
inductor
Q
7
reaches maximum is below 6GHz.
While the results of 5GHz VCO is satisfactory, the performance of 6GHz is disappointing given that it uses better technology. The original target specification of the second
VCO was 5.8GHz of center frequency with -112dBc/Hz and 4.2mW of power consumption.
Unfortunately the target frequency and the power consumption was not met. The reason
for the poor VCO performance can be considered from the miscalculations of the resonant
tank. While slow process corners can explain the high power consumption, it does not justify the higher center frequency. If the resonant frequency of the L-C tank is miscalculated
(i.e., parasitic capacitance extraction), then it not only changes the VCO's center frequency
but also impacts the power consumption as well. This is due to the frequency dependent
7.1. FREQUENCY SYNTHESIZER
119
characteristics of the inductor, of which the
Q
peaks at a certain (in this case 5.8GHz)
frequency. As seen in Eq. 6.5, Q of the tank has a quadratic impact on power consumption
and hence the mismatched frequency of the tank results in poor performance.
As to fairly compare the result of these VCOs to other VCOs that have been published,
we employ figure of merit (FOM) defined as the following equation [71],
FOM = L(foffset) - 20log( fosc ) + 10log( PV")
1mW
fof fset
where L(foffset) is the phase noise at
(7.1)
fof fset from the VCO frequency of f 0 sc and PO is
the power consumption of the VCO. The figure of merit of recently published LC oscillators
around 5GHz are shown in Table 7.2 and plotted in Figure 7-7.
7.1.2
Fractional-N frequency synthesizer
The frequency synthesizer is a 4th order PLL with E-A for fractional channel selection of the
reference frequency. The frequency synthesizer is able to change its frequency in about 1MHz
steps with a 55MHz reference clock as shown in Figure 7-8 and 7-9. With the prescaler
value of 8 and a 10-bit E-A , an exact resolution of
5
MHz was not achieved due to the
non-linearities from the phase frequency detector and the charge pump. The resolution can
be easily increased by adding more bits to the accumulator of the E-A modulator. The
estimated increase in power consumption with additional 5 bits in the E-A modulator is
about 1mW. The total power consumption of the synthesizer is 22mW, where VCO draws
7.7mA of current from 2.3V power supply, while the rest of the synthesizer draws 2.7mA
from 1.6V. The detailed profile of synthesizer's power consumption is shown in Figure 7-10.
The divide-by-112/120 consumes 3.2mW with the input RF range of 6GHz to 6.9GHz. The
performance of this divider can be compared to other dividers by power efficiency, which
is defined as the ratio of divider's maximum operating frequency to its power consumption
expressed in GHz/mW. The dual modulus divider achieves 2.15GHz/mW, which is the
most power efficient dual-modulus divider yet reported above 5GHz. In the divider, about
2mW of power is consumed in the prescaler-by-8.
Hence it can be seen that the high
frequency components of the synthesizer accounts to more than 90% of the total power
120
CHAPTER 7. PROTOTYPE TEST RESULTS
Reference
freq
power
process
phase noise
tuning
FOM
Plou99 [71]
King98 [72]
Liu99 [73]
Nik99 [63]
Hung00 [74]
SamoriOl [75]
Hitko02 [61]
5GHz VCO
6GHz VCO
6GHz
4.7GHz
6.3GHz
4.4GHz
5.2GHz
4.6GHz
5.8GHz
5.3GHz
6.5GHz
22mW
10.8mW
18mW
12mW
7mW
13.8mW
6mW
24mW
17.7mW
Bipolar
.35 pm CMOS
.35pm CMOS
Bipolar
.25pm CMOS
.25pm CMOS
CMOS
.35pm CMOS
.25pm CMOS
-116@1MHz
-110A1MHz
-98.4©1MHz
-100©L00kHz
-117©1MHz
-114L1MHz
-107©1MHz
-120.1©1MHz
-112©1MHz
15%
4.3%
16.8%
6%
7%
18%
11%
15.6%
12%
-178.1 A 1MHz
-173.1 9 1MHz
-161.8 5 1MHz
-180.5 A 100kHz
-183.3@1MHz
-175.8©1MHz
-174.54 1MHz
-181.3 © 1MHz
-175.2 9 1MHz
Table 7.2: Figure of merit of different VCOs.
Figure of merit of different VCOs
-1An,
o
-165
Liu99
L
-170
0
o King98
o HitkoO2
.M-175
EL
o
0
-180-
o
VCO-2
SamoriOl
o Nik99
PIou99
o VC0o HungOO
4
4.5
5
5.5
6.5
Frequency (GHz)
Figure 7-7: Figure of merit for different VCOs.
121
7.2. BFSK MODULATOR
consumption. The PFD, charge pump and the lock detector consumes 400pW. The reference
spur is approximately 40dB below carrier.
ATTEN
6W
ATTEN 10dB
RL OdBm
MKR -23. 67dBm
10dB
RL OdBm
10dB/
6.380000GHz
10dB/
MKR -23. 83dBm
6.381317GHz
IT I F1
Imme,*.i II
CENTER 6. 380000GHz
VBW 30kHz
RBW 30kHz
SPAN 5.000MHz
SWP 50.0ms
Figure 7-8: Output spectrum of the fractional-N
synthesizer at 6.3800GHz.
CENTER 6. 380000GHz
VBW 30kHz
RBW 30kHz
5.000MHz
SWP 50.0ms
SPAN
Figure 7-9: Output spectrum of the fractional-N
synthesizer at 6.3813GHz.
MscI:0.4mW(2%)
Divider3.2mW(14%)
Lk
:0.9mW(4%)
VCO:17.7mW(80%)
Figure 7-10: Power consumption of different components in the modulator.
7.2
BFSK Modulator
The modulation performance of the closed loop direct VCO modulator is shown in Figure 712 and Figure 7-12, where eye diagram of raw and Manchester encoded data is plotted for
122
CHAPTER 7. PROTOTYPE TEST RESULTS
TRACE
R:
Chi 2FSK
A Har-ker
Meas
~
TRACE
Time
500.000
pnsyn
---
11.007.kHz
FOUND.
PULSE
IKT
R:
Chi 2FSK
A Mlarker
Meas
Tie
.
500.000
ns5Ys
-17.897
I-Eye
I-Eye
200
kHz:
Start: -1.5
-200f
kHz:
_______
syii
StOP: 1.5
Start:
syil
Figure 7-11: Eye diagram of 5Mbps Manchester
encoded data with 100kHz PLL loop bandwidth
(h = 0.3).
__
-1.5
syn
_
h
PULSE___
stop:
1.5
sym
Figure 7-12: Eye diagram of 5Mbps raw data
with 100kHz PLL loop bandwidth (h = 0.3).
synthesizer loop bandwidth of 100kHz. The eye is measured at the output of the prescalerby-8 using HP89440A vector signal analyzer. Hence the output modulated frequency is
scaled by 1/8. The data rate is 5Mbps and the modulation index is 0.3. The graphs are
very much similar to the simulation result shown in Chapter 4 and it is verified that the
Manchester encoded data indeed achieves higher modulation accuracy by removing the DC
component of the data. For the raw data, the modulated signal is severely corrupted by
the closed loop PLL and the eye opening is very small.
The eye diagram and the spectrum of 5Mbps Manchester encoded data for modulation
index of 0.5 is plotted in Figure 7-13 and Figure 7-14, respectively. The peak that occurs
every 2.5MHz in the output spectrum is from Manchester encoding.
7.3
kHz
Variable Loop Bandwidth Technique
The start-up time of the frequency synthesizer is shown in Figure 7-15 and 7-16 for fixed
and variable loop methods, respectively. While the start-up time of the fixed loop achieves
approximately 70ps, the variable loop method achieves 20p start-up time with the help of
multi-stage variable loop method, where the bandwidth is switched from 1MHz to 250kHz
before it is changed to final loop bandwidth of 100kHz.
123
7.4. SUMMARY
TRACE
A:
Chrk2FSK
Meas
Time
49.00000
sye
-124.42
kHz
1
1
ATTEN
RL
18dB
MKR
18dB/
AdBm
-38.
17dBm
6.38415GHz
I-Eye
/d0y
IOM
kHz
Start:
I
-300 ns
I
Stop:
300 ns
Figure 7-13: Eye diagram of the 5Mbps Manchester encoded data (h = 0.5).
7.4
CENTER 6.38415GHz
*VBW
388kHz
*RBW
18kHz
SPAN 20.OOMHz
SWP 58. Oms
Figure 7-14: Spectrum of the 5Mbps Manchester
coded data.
Summary
Test results of the prototype chip has been shown. To compare energy efficiencies of different
radios in sensor applications, we define Energy per bit as the energy it takes to transmit
a bit when sending a packet, which includes the start-up energy of the transmitter. The
comparison is shown in Figure 7-17, where energy efficiencies of low power high data rate
radios are plotted versus packet size. It is be seen that reducing the start-up time is crucial
in energy efficiency for short packet transmission. The die photo and the PCB test setup
of the chip are shown in Figure 7-18 and Figure 7-19, respectively.
CHAPTER 7. PROTOTYPE TEST RESULTS
124
Tek Run: 5.00MS/s
[
Sample
IM
--- - -
Tek Run: 25.OMS/s
_
---
Sample
UD0E
----
- ----
]
t
..... .
. . .
. . . . . . . ...
. . . . . .
. . . . . . .
...........
...
..........
. . . . . . . . . . . . . .
. . . . . . . . .
. . . . . . . . . . . . . . . . . . .
. . . ..
. . . .
. . . .
5.0u V
Ch4
lvi
1OOmV
V. U S
C. n
1
12 Dec 20
15:01:05
Figure 7-15: Start-up transient of frequency synthesizer with fixed loop bandwidth.
4
. .. . . . . . .
T
. . . . *
44
M
. ..
. . . . . . ...
... .... .... .......
4t ....
M
5.00
V
Ch4
100mV
M 2.uaps Ln I I
Energy efficiencies of different modulators
0)-7
0.10
[26 2.4GH-z 2Mbps
1.8GH, 2.8Mbps-
10
+
'..zv 12 Dec 2001
15:17:45
Figure 7-16: Start-up transient of frequency synthesizer with variable loop bandwidth.
10
10,
. . . ...
. . . . . . . . .. . . .. . . . . . .
......................
. . . . . . . . . .. . . . . . . . . .
. . . . . . . . . . . .
..
4-
. . . . . . . . .
. . . .
.. . . . . . . .
. .
.........................4 ... ...... . . .... ...
. . . . . . . . ...
. . . . . . . . . . . . . ....
. . . . . . . . . . .
.. .
4... ... ...............
....... ................. ..... ..
...................
.... .....................
.. .........
ir
. . . . . . . . ...
This work. 6.5GHz 2.5Mbas
10
10,
Ie
Packet size (bits)
Figure 7-17: Energy efficiency comparison of different high data rate modulators.
125
7.4. SUMMARY
Figure 7-18: Die photo of the 6.5GHz modulator chip.
Figure 7-19: PCB test setup of chip.
126
CHAPTER 7. PROTOTYPE TEST RESULTS
Chapter 8
Conclusion
8.1
Conclusion
Energy reduction techniques have been investigated for a wireless microsensor network.
Two aspects of system hierarchy, communication protocol and RF transmitter, were studied
based on multiple levels of system abstraction.
In the communication protocol design, the key aspect of this research is that protocols
are explored with the underlying physical layer electronics in mind. Rather than treating
the radio of the sensor node as ideal hardware, a model is derived that takes into account
the non-ideal characteristics of the radio.
The non-ideal behavior of the physical layer
electronics plays a crucial role in the design of energy efficient microsensor network. The
most critical parameter is the start-up time, which dominates the energy consumption
for a short packet transmission. The frequency errors in the reference oscillators are also
important as they cause time synchronization of the network, resulting in increased receiver
activity. Understanding these behaviors of the radio helps to minimize the network's energy
consumption at multiple levels of system abstraction.
The energy consumption of the network is further minimized by employing a hybrid
TDM-FDM protocol that trades-off energy consumption of the transmitter and the receiver. The TDMA approach exploits the fact that energy consumption of the transmitter
is dominated by the frequency synthesizer rather than the modulation circuitry and hence
transmits the data at maximum rate. However, this results in time synchronization of the
127
CHAPTER 8. CONCLUSION
128
network that requires receiver activity. The FDMA approach maximizes the number of
frequency channels so that the guard time can be maximized, thereby reducing the receiver
energy consumption. The available bandwidth has a different impact on energy consumption from the traditional perspective of Eb/N, in the sense that large available bandwidth
allows less time synchronization and hence lower energy consumption in the receiver. This
is exploited in utilizing the bandwidth of the sensor network that has wide variation in the
sensor distribution. By employing time-frequency slot allocation, bandwidth is used more
effectively and energy consumption of the network is reduced.
The choice of modulation scheme depends heavily on the start-up time.
Multi-level
modulation is more energy efficient than a binary modulation only if the start-up time of
the radio is small compared to the data transmission time. In addition, complexity of the
modulation circuitry for multi-level modulation must be minimized in order to achieve lower
energy than a binary modulation scheme.
In the second part of the thesis, design methodologies for a low power, high data rate
and fast start-up transmitter were explored. The key to achieving low energy consumption
is finding and optimizing the various design trade-offs that exist in the system.
To achieve a high data rate transmitter, the VCO is directly modulated in closed loop
PLL. This architecture provides the simplest form of modulation circuitry to perform BFSK
on the frequency synthesizer and hence achieves low power. The modulation error of the
closed loop PLL can be overcome by low loop bandwidth, Manchester encoding and equalization at the base station.
Fast start-up time is obtained by a employing variable loop bandwidth technique. The
PLL changes its bandwidth as the loop approaches lock and hence fast start-up time is
achieved.
To overcome the effect of quantization noise on loop switching, a two-stage
variable loop bandwidth method is used.
In the low power frequency synthesizer, trade-offs between analog and digital components are exploited. The high frequency VCO and the digital E-A modulator have opposite
effect on each others' power consumption in conjunction with the loop bandwidth. While
large loop bandwidth reduces the power consumption of the VCO, it increases the power
consumption of the E-A. In that regard, the loop bandwidth can be considered as a measure
8.2. CRITIQUE AND FUTURE WORKS
129
of whether the process technology is analog-friendly or digital-friendly. The E-A modulator
also reduces the power consumption of the dual-modulus divider by allowing more prescaler
stages at high frequency. On the circuit side, the trade-off between the tuning range and
the phase noise of the VCO was seen.
8.2
Critique and Future Works
While this thesis presents energy efficient design methodologies for both communication
protocols and transmitter for a microsensor node, there is still room for improvements.
Although the radio model includes the start-up time as a critical design parameter, it
does not incorporate some of the other parameters that impact power consumption. These
include phase noise of the VCO, efficiencies of the power amplifier and accuracy of the
modulator. Incorporating these into design will result in a more accurate optimization of
the system.
The MAC protocol developed in the thesis is primarily aimed at a coordinated static
sensor network. However, many of the sensor applications require ad-hoc autonomous and
sometimes even a mobile network.
The extension of low power MAC to mobile ad-hoc
network presents an interesting challenge as the network becomes more complicated. MAC
for multi-hop routing network is another area in which the MAC can have a significant
impact on the higher level protocol.
In the transmitter, high data rate is achieved through closed loop direct VCO modulation. The critical drawback is the modulation error from the closed loop PLL. Although
the error can be reduced by Manchester coding, this increases the bandwidth by a factor of
two. While this is acceptable for a low data rate sensor network, it may not be acceptable
for other applications. Therefore, ways to increase the modulation accuracy of the closed
loop direct VCO modulation must be found, in order for this architecture to be successful
in other applications. Calibration through digital E-A modulator or a dual PLL loop are
some of the methods that could reduce the modulation error.
The fundamental limit in achieving a low power frequency synthesizer is noise. While
fractional-N synthesizer helps to reduce the power consumption of the PLL, it introduces
130
CHAPTER 8. CONCLUSION
quantization noise. Therefore, implementation of fractional-N synthesizer architecture that
is free of quantization noise will greatly reduce the power consumption.
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BIBLIOGRAPHY
Appendix A
Prototype Chip Testing
A.1
Chip Description
The chip is packaged in a 32 micro-lead frame by Amkor Inc. The micro-lead frame has
pins underneath the package, which minimizes the bond wire inductance and capacitance.
The pin designations of the packaged chip are shown in Figure A-1 and its description is
shown in Table A.1.
31
32
30
29
28
27
26
25
01
24
02
23
03
22
04
21
05
20
19
06
07
18
08
17
09
10
11
12
13
14
15
16
Figure A-1: Pin out of the packaged chip.
139
APPENDIX A. PROTOTYPE CHIP TESTING
140
2
3
4
5
6
7
8
9
10
11
12
13
Pin Name [I/O [Description
GND
Ground
0
6.4GHz RF Output, open drain terminal.
VCOGround
GND
Vctrl
I
Control Voltage of the VCO.
RI
I/O Resistor connection of the high gain loop filter.
R2
I/O Resistor connection of the medium gain loop filter.
Loop Out I/O Charge pump output. For connection to a loop filter.
Ismall
I
Current source input of the small charge pump.
GND
Ground
Imedium
I
Current source input of the medium charge pump.
Ibig
I
Current source input of the large charge pump.
Ref Clk
I
Reference clock input for the PLL. High impedance CMOS input.
LE
I
Load Enable signal for the parallel register. High impedance CMOS
14
Data Clk
I
15
Data
I
16
17
18
19
20
GND
VE-A
Lock
E-A out
E-A in
I
0
0
I
21
Div8 Out
0
22
23
GND
VCO+
0
Ground
Power supply for the E-A .
Lock monitor detector output. Active low.
Output of the E-A .
E-A input for external control of division values. High impedance
CMOS input.
Output of the prescaled oscillator. 800MHz RF output with nonzero DC.
Ground
6.4GHz RF output with non-zero DC.
24
N/C
-
No Connection
25
26
27
28
29
30
31
GND
Vdiv
Mod In
Vvco
Vbuf
Ibias
Vmscl
I
I
I
I
I
I
Ground
Power supply for the dual-modulus divider.
Modulation input of the VCO.
Power supply for the VCO.
Power supply for the output buffers.
Current source to set up bias for the prescaler.
Power supply for the charge pump, PFD and variable loop bandwidth control unit.
32
N/C
-
No Connection
Pin No.
1
input.
Clock for the serial register programming. High impedance CMOS
input.
Data input for the program registers. High impedance CMOS input.
Table A.1: Pin descriptions of the packaged chip.
141
A.2. SERIAL REGISTER PROGRAM
A.2
Serial Register Program
A.2.1
Program timing
To reduce the number of pins, the 12 bit data needed for E-A and program register are
fed serially. The serial register and a parallel latch requires three signals (Data,Data Clk
and Load Enable) to load the data. The required timing for these signals are shown in
Figure A-2. Each signal drives a CMOS buffer on chip. Registers can be programmed using
the PLL CodeLoader from National Semiconductor Corp.
LSB
MSB
Data
77
F39y
j
Data Clk
Load
Enable
To
IA and program latch
P rallel Latch
Load
Enable
Data[11:0]
Data
Data Clk
)
Serial Shift Register
Figure A-2: Timing diagram of the register value programming.
APPENDIX A. PROTOTYPE CHIP TESTING
142
Control Bit
F15
Name
Control value description
connection.
-No
F14
Lock Select
F13
Return
F12
Stage
F11
Variable loop
able
E-A select
F10
en-
'1' enables lock detect for a window of 10 reference cycles. and '0'
enables lock detect for a window of 30 reference cycles.
'0' returns to high bandwidth mode if the PLL loses lock and '1'
remains in the low bandwidth mode even after the PLL loses lock
(works together with variable loop bandwidth).
'0' enable single stage loop switching and '1' enables dual stage
loop switching.
'1' enables variable loop bandwidth technique and '0' disables variable loop bandwidth.
'0' enables built-in E-A and '1' enables off-chip control of divider
value
F9
F8
F7
F6
F5
F4
F3
Zds
EA 8
F2
F1
EA2
EAi
Bit 2 of E-A
Bit 1 of E-A
FO
EA
Bit 0 of E-A (LSB)
EA7
EdA
EA5
EA4
EA3
0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
9
8
7
6
5
4
3
of E-A (MSB)
of E-A
of E-A
of E-A
of E-A
of E-A
of E-A
Table A.2: Description of function register.
A.2.2
Register value description
The 16 bit registers perform the functions described in Table A.2. These functions enable
testability of the chip in various modes. F15 is the first bit that goes into the register.
A.3
Test Board Design
The test board is implemented using a FR-4 material. The schematics of the board are
shown in Figure A-3. The thick line represents 50 Q matched impedance.
Low noise Voltage Regulator
in
out
LT1762
R22
(AM
gnd adj
Input Data
(from TEK HFS 9003)
JR1
'-1
Variable Curret Source
LM334Radj
C
vCo- out
I
IL
~
AAA
Div/8 out
IC
HO STA03
IL
'B
,vCO+ out
est Chip
Zi out
Lock
'M
ALVC125 (TI)
I3
i
YA in
-44<
is
-4
-
LE
Data Clk
I
50ohm matched impedence
Data
Ref OSC (55MHz) from HP8656B
144
APPENDIX A. PROTOTYPE CHIP TESTING
Appendix B
PLL model
B.1
Noise properties of 2nd order PLL
Noise properties of the PLL is important since it is directly affected by power consumption.
The PLL can be represented in a linear model as shown in Figure B-1.
The linearized
model helps to understand the properties of the PLL that will later be used to improve
the performance of the transmitter. Forn the VCO side, the PLL will act as a a high pass
filter. Intuitively, this can be seen since the negative feedback will only affect the signal that
are slow enough for the loop the respond. The high frequency components will show up at
the output without being affected by the loop since the feedback loop is not fast enough to
affect the fast signals. For a typical second order charge pump PLL shown in Figure B-1,
the transfer function from VCO noise to the output phase can be represented as
Oout
nvco
1
1 + Gopen
s2
s
2
+2~~s~w~(B.1)
where, for a second order charge pump PLL shown in Figure 6-3
n =
R
2
KvcoIch
2(rCN
145
K
0 IeC
27rN
(B2
(B.2)
APPENDIX B. PLL MODEL
146
nvco
#ref
+
-
GLF(S) -
Kc
--
O out
1/N
Figure B-1: Linearized model of the PLL.
For any input that lies outside of the loop filter, the PLL presents a low pass characteristic.
This is readily seen since the loop filter (which is a low pass filter in nature) suppresses
any high frequency component. The transfer function from reference to the output can be
represented as
Oout
Oref
_
GopeniN
1
+ Gopen
N
=
ST- 2
s2 +2(wns +
2
(B.3)
where -z is the zero location of the loop transfer function, which is RC.
From the above discussions, we see that it is helpful to increase the loop bandwidth when
VCO is the dominant source of noise and vice versa when noise from other components are
dominant.
B.2
Maximum Quantization Noise on VCO Control Voltage
The maximum fluctuation on the VCO control voltage due to modulus change in the divider
of a fractional-N synthesizer can be described as the following. The maximum change in
the VCO control voltage occurs when the phase difference between the reference and the
divided output frequency is maximum. For a second order PLL described in the previous
section, the maximum voltage change on the VCO control voltage, AVmax, can be expressed
B.2. MAXIMUM QUANTIZATION NOISE ON VCO CONTROL VOLTAGE
147
ref
div
4ATmW
Nmax-
+
Figure B-2: Maximum phase difference in a fractional-N synthesizer.
as
AVmax
=
(B.4)
ch ATmax
C
where Tmax is the maximum time difference the reference and the divided output frequency. This maximum time difference occurs when the divider value changes to a maximum
value, as shown in Figure B-2. Therefore,
ATmax
Tdiv - Tref = NmaxTo - Tref
=
=
(B.5)
(Nmaxl-)T
\Nnom
/
Combining the above two equations, we achieve
AVmax
=
ATmax = Ich (Nmax
C
max C \Nuo
nom
2
irNnom 2 Nmax1
I
Kve0
W
Nnom
- 1
Tref
(B.6)
148
APPENDIX B. PLL MODEL
=KquantWn
(B.7)