18-447
Computer Architecture
Lecture 5: Single-Cycle Microarchitectures
Prof. Onur Mutlu
Carnegie Mellon University
Spring 2012, 2/1/2012
Reminder: Homeworks for Next Two Weeks

Homework 1 solutions


Posted online
Homework 2



Already out
Due February 13
ISA concepts, ISA vs. microarchitecture, microcoded machines
2
Reminder: Lab Assignments 1 and 2

Lab Assignment 1


Lab Assignment 1.5



Due this Friday (Feb 3), at the end of Friday lab
Verilog practice
Not to be turned in
Lab Assignment 2


Will be out today
Due Friday, Feb 17, at the end of the lab
3
Readings for Next Lecture

P&P, Revised Appendix C



P&H, Appendix D


Microarchitecture of the LC-3b
Appendix A (LC-3b ISA) will be useful in following this
Mapping Control to Hardware
Optional

Maurice Wilkes, “The Best Way to Design an Automatic
Calculating Machine,” Manchester Univ. Computer Inaugural
Conf., 1951.
4
Answers to Some of Your Questions

Can you do the labs in System Verilog?




Unfortunately, no, you cannot do the Labs in System Verilog.
Fortunately, Verilog is easy after you know System Verilog
Yes, this class will hopefully fulfill your desire to understand
how a processor truly works
Yes, this course will be time consuming 

But, it will also be fun and “easy” (that is if you understand all)

Yes, I do have your pictures already, but …

Yes, you got the MIPS acronym, correct. And, thanks!
5
Review of Last Lecture: ISA Tradeoffs






Complex vs. simple instructions: concept of semantic gap
Use of translation to change the tradeoffs
Fixed vs. variable length, uniform vs. non-uniform decode
Number of registers, addressing modes
Unaligned memory access
What is the benefit of translating complex instructions to
“simple instructions” before executing them?




In hardware (a la Intel, AMD)?
In software (a la Transmeta)?
Which ISA is easier to extend: fixed length or variable length?
How can you have a variable length, uniform decode ISA?
6
A Note on Length and Uniformity


Uniform decode usually goes with fixed length
In a variable length ISA, uniform decode can be a property
of instructions of the same length

It is hard to think of it as a property of instructions of different
lengths
7
A Note on RISC vs. CISC

Usually, …

RISC





Simple instructions
Fixed length
Uniform decode
Few addressing modes
CISC




Complex instructions
Variable length
Non-uniform decode
Many addressing modes
8
A Note on Small Semantic Gap

With a small semantic gap


Software’s job is harder is the HLL constructs do not map
to ISA constructs easily


Software’s job to translate from HLL to ISA is easy if the HLL
constructs map to ISA instructions easily
Semantic mismatch
The semantic gap is small if the semantic level of HLL and
ISA are close and the semantics match
9
Implementing the ISA:
Microarchitecture Basics
10
How Does a Machine Process Instructions?


What does processing an instruction mean?
Remember the von Neumann model
AS = Architectural (programmer visible) state before an
instruction is processed
Process instruction
AS’ = Architectural (programmer visible) state after an
instruction is processed

Processing an instruction: Transforming A to A’ according to
the ISA specification of the instruction
11
The “Process instruction” Step

ISA specifies abstractly what A’ should be, given an
instruction and A

It defines an abstract finite state machine where



From ISA point of view, there are no “intermediate states”
between A and A’ during instruction execution


State = programmer-visible state
Next-state logic = instruction execution specification
One state transition per instruction
Microarchitecture implements how A is transformed to A’


There are many choices in implementation
We can have programmer-invisible state to optimize the speed of
instruction execution: multiple state transitions per instruction


Choice 1: AS  AS’ (transform A to A’ in a single clock cycle)
Choice 2: AS  AS+MS1  AS+MS2  AS+MS3  AS’ (take multiple
clock cycles to transform AS to AS’)
12
A Very Basic Instruction Processing Engine


Each instruction takes a single clock cycle to execute
Only combinational logic is used to implement instruction
execution
 No intermediate, programmer-invisible state updates
AS = Architectural (programmer visible) state
at the beginning of a clock cycle
Process instruction in one clock cycle
AS’ = Architectural (programmer visible) state
at the end of a clock cycle
13
A Very Basic Instruction Processing Engine

Single-cycle machine
ASNext
Combinational
Logic


Sequential
Logic
(State)
AS
What is the clock cycle time determined by?
What is the critical path of the combinational logic
determined by?
14
Remember: Programmer Visible (Architectural) State
M[0]
M[1]
M[2]
M[3]
M[4]
Registers
- given special names in the ISA
(as opposed to addresses)
- general vs. special purpose
M[N-1]
Memory
Program Counter
array of storage locations
indexed by an address
memory address
of the current instruction
Instructions (and programs) specify how to transform
the values of programmer visible state
15
Single-cycle vs. Multi-cycle Machines

Single-cycle machines




Each instruction takes a single clock cycle
All state updates made at the end of an instruction’s execution
Big disadvantage: The slowest instruction determines cycle time 
long clock cycle time
Multi-cycle machines





Instruction processing broken into multiple cycles/stages
State updates can be made during an instruction’s execution
Architectural state updates made only at the end of an instruction’s
execution
Advantage over single-cycle: The slowest “stage” determines cycle time
Both single-cycle and multi-cycle machines literally follow the
von Neumann model at the microarchitecture level
16
Instruction Processing “Cycle”



Instructions are processed under the direction of a “control
unit” step by step.
Instruction cycle: Sequence of steps to process an instruction
Fundamentally, there are six phases:

Fetch
Decode
Evaluate Address
Fetch Operands
Execute
Store Result

Not all instructions require all six stages (see P&P Ch. 4)





17
Instruction Processing “Cycle” vs. Machine Clock Cycle

Single-cycle machine:


All six phases of the instruction processing cycle take a single
machine clock cycle to complete
Multi-cycle machine:


All six phases of the instruction processing cycle can take
multiple machine clock cycles to complete
In fact, each phase can take multiple clock cycles to complete
18
Instruction Processing Viewed Another Way


Instructions transform Data (AS) to Data’ (AS’)
This transformation is done by functional units

Units that “operate” on data

These units need to be told what to do to the data

An instruction processing engine consists of two components

Datapath: Consists of hardware elements that deal with and
transform data signals




functional units that operate on data
hardware structures (e.g. wires and muxes) that enable the flow of
data into the functional units and registers
storage units that store data (e.g., registers)
Control logic: Consists of hardware elements that determine
control signals, i.e., signals that specify what the datapath
elements should do to the data
19
Single-cycle vs. Multi-cycle: Control & Data

Single-cycle machine:



Multi-cycle machine:



Control signals are generated in the same clock cycle as data
signals are operated on
Everything related to an instruction happens in one clock cycle
Control signals needed in the next cycle can be generated in
the previous cycle
Latency of control processing can be overlapped with latency
of datapath operation
We will see the difference clearly in microprogrammed
multi-cycle microarchitecture
20
Many Ways of Datapath and Control Design



There are many ways of designing the data path and
control logic
Single-cycle, multi-cycle, pipelined datapath and control
Single-bus vs. multi-bus datapaths


Hardwired/combinational vs. microcoded/microprogrammed
control



See your homework 2 question
Control signals generated by combinational logic versus
Control signals stored in a memory structure
Control signals and structure depend on the datapath
design
21
A Single-Cycle Microarchitecture
A Closer Look
22
Remember…

Single-cycle machine
ASNext
Combinational
Logic
Sequential
Logic
(State)
AS
23
Let’s Start with the State Elements

Data and control inputs
on
5
Register
numbers
3
Read
register 1
5
Read
register 2
Registers
5 Write
Add Sum register
PC
Instruction
ion
ory
Data
Write
data
Read
data 1
Data
AL
Read
data 2
RegWrite
uction memory
b. Program counter
c. Adder
a. Registers
b
MemWrite
Instruction
address
Address
PC
Read
data
Instruction
Instruction
memory
a. Instruction memory
Add Sum
Write
data
b. Program counter
Data
memory
MemRead
a. Data memory unit
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
16
Sign
extend
c. Adder
b. Sign-exten
24
For Now, We Will Assume

“Magic” memory and register file

Combinational read


output of the read data port is a combinational function of the
register file contents and the corresponding read select port
Synchronous write

the selected register is updated on the positive edge clock
transition when write enable is asserted



Cannot affect read output in between clock edges
Can affect read output at clock edges (but who cares?)
Single-cycle, synchronous memory


Contrast this with memory that tells when the data is ready
i.e., Ready bit: indicating the read or write is done
25
Instruction Processing

5 generic steps (P&H)





Instruction fetch (IF)
Instruction decode and register operand fetch (ID/RF)
Execute/Evaluate memory address (EX/AG)
Memory operand fetch (MEM)
Store/writeback result (WB)
WB
IF
Data
Register #
PC
Address
Instruction
memory
Instruction
Registers
ALU
Address
Register #
ID/RF
Register #
Data
memory
EX/AG
Data
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
MEM
26
What Is To Come: The Full Datapath
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Instruction [15– 11]
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
Address
Write
data
Instruction [15– 0]
1
M
u
x
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
0
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
ALU operation
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier.
ALL RIGHTS RESERVED.]
27
JAL, JR, JALR omitted
Single-Cycle Datapath for
Arithmetic and Logical Instructions
28
R-Type ALU Instructions



Assembly (e.g., register-register signed addition)
ADD rdreg rsreg rtreg
Machine encoding
0
rs
rt
rd
0
ADD
6-bit
5-bit
5-bit
5-bit
5-bit
6-bit
R-type
Semantics
if MEM[PC] == ADD rd rs rt
GPR[rd]  GPR[rs] + GPR[rt]
PC  PC + 4
29
ALU Datapath
Add
4
25:21
PC
Read
address
20:16
Instruction
Instruction
15:11
Instruction
memory
3
Read
register 1
Read
register 2
Registers
Write
register
Write
data
ALU operation
Read
data 1
Zero
ALU ALU
result
Read
data 2
RegWrite
1
IF
if MEM[PC] == ADD rd rs rt
GPR[rd]  GPR[rs] + GPR[rt]
PCfrom
+ 4 2004 Elsevier. ALL RIGHTS RESERVED.]
**Based on original figure
[P&HPC
CO&D, COPYRIGHT
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
ID
EX
MEM WB
Combinational
state update logic
30
I-Type ALU Instructions



Assembly (e.g., register-immediate signed additions)
ADDI rtreg rsreg immediate16
Machine encoding
ADDI
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
I-type
Semantics
if MEM[PC] == ADDI rt rs immediate
GPR[rt]  GPR[rs] + sign-extend (immediate)
PC  PC + 4
31
Datapath for R and I-Type ALU Insts.
Add
4
PC
25:21
Read
address
20:16
Instruction
Instruction
Instruction
memory
15:11
RegDest
isItype
3
Read
register 1
Read
register 2
Registers
Write
register
Write
data
Zero
ALU ALU
result
GPR[rt]  GPR[rs] + sign-extend (immediate)
PC  PC + 4
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
Address
Read
data 2
Write
data
ALUSrc
Sign
extend
IF
if MEM[PC] == ADDI rt rs immediate
Mem
Read
data 1
RegWrite
116
ALU operation
32
Data
memo
isItype
ID
Mem
EX
MEM WB
Combinational
state update logic 32
Single-Cycle Datapath for
Data Movement Instructions
33
Load Instructions



Assembly (e.g., load 4-byte word)
LW rtreg offset16 (basereg)
Machine encoding
LW
base
rt
offset
6-bit
5-bit
5-bit
16-bit
I-type
Semantics
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
GPR[rt]  MEM[ translate(EA) ]
PC  PC + 4
34
LW Datapath
Add
add
4
PC
Read
register 1
Read
address
Instruction
Instruction
Instruction
memory
Read
register 2
Registers
Write
register
Write
data
RegDest
isItype
3
MemWrite
Read
data 1
Zero
ALU ALU
result
Address
Address
Read
data 2
RegWrite
116
MemWrite
ALU operation
Write
data
ALUSrc
Sign
extend
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
GPR[rt]  MEM[ translate(EA) ]
PC  PC + 4
32
Read
data
Read
data
16
Data
Write
data Data memory
memory
MemRead
isItype
MemRead
a. Data memory unit
IF
ID
EX
MEM WB
Combinational
state update logic 35
b. Si
Store Instructions



Assembly (e.g., store 4-byte word)
SW rtreg offset16 (basereg)
Machine encoding
SW
base
rt
offset
6-bit
5-bit
5-bit
16-bit
I-type
Semantics
if MEM[PC]==SW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
MEM[ translate(EA) ]  GPR[rt]
PC  PC + 4
36
SW Datapath
Add
add
4
PC
Read
register 1
Read
address
Instruction
Instruction
Instruction
memory
Read
register 2
Registers
Write
register
Write
data
RegDest
isItype
3
MemWrite
Read
data 1
Zero
ALU ALU
result
Address
Address
Read
data 2
Write
data
RegWrite
016
MemWrite
ALU operation
ALUSrc
Sign
extend
if MEM[PC]==SW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
MEM[ translate(EA) ]  GPR[rt]
PC  PC + 4
32
Read
data
Read
data
16
Data
Write
data Data memory
memory
MemRead
isItype
MemRead
a. Data memory unit
IF
ID
EX
MEM WB
Combinational
state update logic 37
b. Si
Load-Store Datapath
Add
4
PC
add
Read
register 1
Read
address
Instruction
Instruction
Instruction
memory
Read
register 2
Registers
Write
register
Write
data
RegDest
isItype
3
MemWrite
Read
data 1
Zero
ALU ALU
result
Read
data
Address
Read
data 2
RegWrite
!isStore
16
isStore
ALU operation
Sign
extend
32
ALUSrc
isItype
Write
data
Data
memory
MemRead
isLoad
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
38
Datapath for Non-Control-Flow Insts.
Add
4
PC
Read
register 1
Read
address
Instruction
Instruction
Instruction
memory
Read
register 2
Registers
Write
register
Write
data
RegDest
isItype
3
MemWrite
Read
data 1
Zero
ALU ALU
result
Read
data
Address
Read
data 2
RegWrite
!isStore
16
isStore
ALU operation
Sign
extend
32
ALUSrc
isItype
Write
data
Data
memory
MemRead
isLoad
MemtoReg
isLoad
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
39
Single-Cycle Datapath for
Control Flow Instructions
40
Unconditional Jump Instructions



Assembly
J immediate26
Machine encoding
J
immediate
6-bit
26-bit
J-type
Semantics
if MEM[PC]==J immediate26
target = { PC[31:28], immediate26, 2’b00 }
PC  target
41
Unconditional Jump Datapath
isJ
Add
PCSrc
4
PC
Read
register 1
Read
address
Instruction
concat
Read
register 2
Registers
Write
register
Instruction
Instruction
memory
?
Write
data
3
XALU operation
MemWrite
Read
data 1
Zero
ALU ALU
result
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
if MEM[PC]==J immediate26
PC = { PC[31:28], immediate26, 2’b00 }
Read
data
Address
Read
data 2
RegWrite
0 16
0
Sign
extend
32
ALUSrc
X
Write
data
Data
memory
MemRead
0
42
What about JR, JAL, JALR?
We did not cover the following slides in lecture.
These are for your preparation for the next lecture.
Conditional Branch Instructions



Assembly (e.g., branch if equal)
BEQ rsreg rtreg immediate16
Machine encoding
BEQ
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
I-type
Semantics (assuming no branch delay slot)
if MEM[PC]==BEQ rs rt immediate16
target = PC + 4 + sign-extend(immediate) x 4
if GPR[rs]==GPR[rt] then PC  target
else
PC  PC + 4
44
Conditional Branch Datapath (For You to Fix)
watch out
PC + 4 from instruction datapath
Add
PCSrc
Add Sum
4
PC
Shift
left 2
Read
address
Instruction
concat
Instruction
memory
Instruction
Branch target
sub
ALU operation
3
Read
register 1
Read
register 2
Registers
Write
register
Write
data
Read
data 1
ALU bcond
Zero
To branch
control logic
Read
data 2
RegWrite
0
16
Sign
extend
32
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
45
How to uphold the delayed branch semantics?
Putting It All Together
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Instruction [15– 11]
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
Address
Write
data
Instruction [15– 0]
1
M
u
x
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
0
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
ALU operation
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier.
ALL RIGHTS RESERVED.]
46
JAL, JR, JALR omitted
Single-Cycle Control Logic
47
Single-Cycle Hardwired Control

As combinational function of Inst=MEM[PC]
31
21
16
11
6
0
0
rs
rt
rd
shamt
funct
6-bit
5-bit
5-bit
5-bit
5-bit
6-bit
31
26
21
16
0
opcode
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
31

26
26
0
opcode
immediate
6-bit
26-bit
R-type
I-type
J-type
Consider
 All R-type and I-type ALU instructions
 LW and SW
 BEQ, BNE, BLEZ, BGTZ
 J, JR, JAL, JALR
48
Single-Bit Control Signals
When De-asserted
RegDest
ALUSrc
MemtoReg
RegWrite
When asserted
Equation
GPR write select
according to rt, i.e.,
inst[20:16]
GPR write select
according to rd, i.e.,
inst[15:11]
opcode==0
2nd ALU input from 2nd
GPR read port
2nd ALU input from sign- (opcode!=0) &&
extended 16-bit
(opcode!=BEQ) &&
immediate
(opcode!=BNE)
Steer ALU result to GPR
write port
steer memory load to
GPR wr. port
opcode==LW
GPR write disabled
GPR write enabled
(opcode!=SW) &&
(opcode!=Bxx) &&
(opcode!=J) &&
(opcode!=JR))
49
JAL and JALR require additional RegDest and MemtoReg options
Single-Bit Control Signals
When De-asserted
MemRead
MemWrite
Equation
Memory read disabled
Memory read port
return load value
opcode==LW
Memory write disabled
Memory write enabled
opcode==SW
According to PCSrc2
next PC is based on 26bit immediate jump
target
(opcode==J) ||
next PC is based on 16bit immediate branch
target
(opcode==Bxx) &&
PCSrc1
next PC = PC + 4
PCSrc2
When asserted
(opcode==JAL)
“bcond is satisfied”
50
JR and JALR require additional PCSrc options
ALU Control

case opcode
‘0’  select operation according to funct
‘ALUi’  selection operation according to opcode
‘LW’  select addition
‘SW’  select addition
‘Bxx’  select bcond generation function
__  don’t care

Example ALU operations


ADD, SUB, AND, OR, XOR, NOR, etc.
bcond on equal, not equal, LE zero, GT zero, etc.
51
R-Type ALU
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction
memory
Instruction [15– 11]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
1
0
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
16
Sign
extend
Read
data
Address
Write
data
Instruction [15– 0]
0
Data
memory
1
M
u
x
0
32
funct ALU operation
ALU
control
0
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
52
I-Type ALU
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction [15– 11]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
1
0
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
16
Sign
extend
Read
data
Address
Write
data
Instruction [15– 0]
0
Data
memory
1
M
u
x
0
32
opcodeALU operation
ALU
control
0
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
53
LW
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction [15– 11]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
1
0
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
16
Sign
extend
Read
data
Address
Write
data
Instruction [15– 0]
0
Data
memory
1
M
u
x
0
32
Add
ALU
control
ALU operation
1
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
54
SW
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction [15– 11]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
*
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
0
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
16
Sign
extend
Read
data
Address
Write
data
Instruction [15– 0]
0
Data
memory
1
M
u
x
0
*
32
Add
ALU
control
ALU operation
0
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
55
Branch Not Taken
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction [15– 11]
Instruction [15– 0]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
*
0
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
0
0
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
Write
data
16
Sign
extend
Read
data
Address
Data
memory
1
M
u
x
0
*
32
bcondALU operation
ALU
control
0
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
56
Branch Taken
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
ALU
Add result
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction
memory
Instruction [15– 11]
Instruction [15– 0]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
*
0
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
0
0
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
bcond
ALU ALU
result
Write
data
16
Sign
extend
Read
data
Address
Data
memory
1
M
u
x
0
*
32
bcondALU operation
ALU
control
0
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
57
Jump
Instruction [25– 0]
26
Shift
left 2
PCSrc1=Jump
Jump address [31– 0]
28
PC+4 [31– 28]
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
Instruction
memory
Instruction [15– 11]
Instruction [15– 0]
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
*
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
Shift
left 2
0
0
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
*
Write
data
16
Instruction [5– 0]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
1
*
ALU
Add result
Add
0
Sign
extend
Zero
bcond
ALU ALU
result
Read
data
Address
Write
data
Data
memory
1
M
u
x
0
*
32
*
ALU
control
ALU operation
0
58