A Miniaturized Single Crystal Silicon Solar Cell Array for a
MEMS Power Source
by
Nicole D. Gerrish
B.S. Materials Science and Engineering
Massachusetts Institute of Technology, 1998
SUBMITTED TO THE DEPARTMENT OF MATERIALS SCIENCE AND ENGINEERING IN
PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF SCIENCE IN MATERIALS SCIENCE AND ENGINEERING
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June, 1999
© 1999 Nicole Gerrish. All rights reserved.
The author hereby grants to M.I.T. and The Charles Stark Draper Laboratory, Inc. permission to reproduce
and to distribute publicly paper and electronic copies of this thesis document in whole or in part.
Signature of Author
Departwe t of Materials 9'nce and Engineering
May 7, 1999
Approved by
Dr. Jeffrey T. Borenstein
Tehnical!uperyiser, Draper.J aboratory
Certified by
Prof. Eugene A. Fitzgerald
Associa'te Professor of Materials Science and Engineering
Thesis Supervisor
/i
Accepted by
MASSACHUSETTS INSTITUTE
LIBRARIES
Prof. Linn W. Hobbs
John F. Elliot Professor of Materials
Chairman, Departmental Committee on Graduate Students
2
A Miniaturized Single Crystal Silicon Solar Cell Array for a
MEMS Power Source
by
Nicole D. Gerrish
Submitted to the Department of Materials Science and Engineering
on May 7, 1999 in Partial Fulfillment of the Requirements for the Degree of
Master of Science of Materials Science and Engineering
ABSTRACT
For the first time, a single crystal silicon solar cell array is investigated as a power source for MEMS. A
hybrid approach is designed and fabricated. The design is a modified version of the V-Groove MultiJunction (VGMJ) cell developed at Berkeley, where V-grooves are etched in (100) silicon and junctions are
implanted on the (111) sidewalls. Novel developments include replacing the glass substrate with silicon
using silicon on insulator (SOI) technology, using commercial, screen printed "fired through" technology
for the metallization, and incorporating corner compensation to produce a miniature array of square cells.
One device and four test lots are fabricated to investigate potential problems with the modified VGMJ
design. These lots examine the implantation performance, the contact resistance, the trench filling of screen
prints, and the compensation of convex corners. Results demonstrate that the implant and anneal are not
optimized, the contact resistance is below 50 mQ-cm 2, adequate trench filling can be obtained, and <010>
compensation produces corners with no undercut.
A 40 pm thick, screen printed, modified VGMJ cell is designed and built. A 300 pm x 300 gm cell has an
open circuit voltage between 0.48-0.56 V and a short circuit current between 15-30 pA. The variation
among devices is due to high leakage currents caused by metal on the junction edge. A seven series array
yields an open circuit voltage of 3.61 V, proving that high voltage arrays can be obtained by connecting the
cells in series.
The current design is capable of producing a voltage 80 V/cm2 and a current of 15-20 pA. Modifications
are suggested to produce an integrated, 6 gm thick array. The integrated approach replaces screen printing
2
with a sputter and lift-off technique. Preliminary analysis reveals that this design is capable of 2020 V/cm
and a current of 1 pA.
Thesis Supervisor: Eugene A. Fitzgerald
Title: Associate Professor of Materials Science and Engineering
3
4
Table of Contents
Page
Abstract
3
Table of Contents
5
List of Figures
9
List of Tables
13
Acknowledgements
15
1
Introduction
17
2
Background
18
2.1
2.2
2.3
2.4
2.5
3
18
20
20
21
22
Solar Cell Principles of Operation
Design Criteria
Materials Issues
Single Crystal Silicon Cells
Design Options
24
Design
3.1 V-groove Multi-junction Cells
3.2 The Modified V-groove Multi-junction Cell
3.3 Design and Fabrication Selection
4
29
Procedure
4.1 Planar Cell
4.1.1
Design and Metallization
4.1.2
Implantation
4.1.3
Fabrication
4.2 Test Lots
4.2.1
SCELLI-P and SCELL1-B: Contact Resistance
4.2.2
SCELL2: Trench Filling of Screen Prints
4.2.3
SCELL3: Corner Compensation
4.3 Electrical Characterization
5
24
25
29
Results and Discussion
30
30
31
32
33
33
34
35
37
38
5.1 Planar Cell
5.2 Test Lots
5.2.1
SCELL1-P and SCELL1-B: Contact Resistance
5.2.2
SCELL2: Trench Filling of Screen Prints
5.2.3
SCELL3: Corner Compensation
5
38
42
42
44
47
6
Table of Contents (continued)
6
Page
50
The Modified VGMJ Cell
6.1 Design
6.2 Fabrication
6.2.1
SOI Substrates
6.2.2
Modified VGMJ Processing
6.3 Results
6.3.1
SOI Substrates
6.3.2
Metallization
6.3.3
Cell Performance
6.3.4
Array Performance
6.4 Future Design and Integration
7
50
52
52
52
54
54
55
56
59
61
Conclusion
7.1 Planar Cell and Test Lots
7.2 The Modified VGMJ Cell
64
64
64
Appendix A: Corner Compensation
66
Appendix B: Contact Resistance Calculations
71
Appendix C: Corner Compensation Etch Evolution
72
References
76
7
8
List of Fi2ures
Page
19
Figure 1:
I-V characteristic for a p-n junction under dark and illuminated conditions.
Figure 2:
A schematic of the Lee et al. a-Si series connected solar cell.
21
Figure 3:
The relationship between (a) short circuit current density and cell thickness
and (b) open circuit voltage and cell thickness.
22
Figure 4:
The layout for (a) a planar configuration and a vertical configuration for a
thin film single crystal Si solar cell.
23
Figure 5:
Major fabrication steps of the Chappell et al. VGMJ silicon solar cell.
25
Figure 6:
The layout of the Chappell VGMJ cell (a) compared to the layout of the
modified VGMJ cell (b).
26
Figure 7:
The major fabrication steps for a thin modified VGMJ cell.
27
Figure 8:
A schematic of the screen printing process.
28
Figure 9:
A schematic of the planar cell design.
31
Figure 10:
A schematic of lots SCELL1-P and SCELL1-B.
33
Figure 11:
The layout of a unit cell of test lot SCELL2.
35
Figure 12:
Planes occurring at convex corners during KOH etching.
36
Figure 13:
The various convex corner compensation methods investigated in test lot
SCELL3.
37
Figure 14:
A schematic of the contact resistance measurement and test structures.
38
Figure 15:
The planar cell performance with an incident power of 80 mW/cm2 for (a)
silver/silver metallized cells and (b) silver/aluminum metallized cells.
39
Figure 16:
The reflectance of the designed and actual ARCs versus wavelength.
41
Figure 17:
A schematic of the contact resistance measurement for the planar Ag/Al
cell.
42
Figure 18:
The contact resistivity of silver ink on heavily doped n-type silicon versus
the firing time.
43
Figure 19:
The contact resistivity of silver and aluminum ink on heavily doped p-type
silicon versus the firing time.
44
9
10
List of Fi2ures (continued)
Page
45
Figure 20:
The difference between the measured line width and the designed line
width for the trenches in lot SCELL2.
Figure 21:
The trench filling if a 350 gm wide and 50 pm deep trench with silver
ink using a screen print mask width of (a) 350 gm and (b) 250 pm.
46
Figure 22:
The difference between the measured line width and designed line width
in lot SCELL2.
47
Figure 23:
(a) A top view of a 250 x 250 jm square mesa with no convex corner
compensation etched in 36 % KOH to a depth of 50 pm. (b) A close
up of a convex corner of the structure shown in (a).
48
Figure 24:
A top view of a 250 pm x 250 jm mesa compensated with (a) <110>
beams and (c) <110> squares etched in 36 %KOH. A close up of the
(b) <110> beam compensated corner and the (d) <110> square
compensated corner.
49
Figure 25:
(a) A top view of a 250 jm x 250 pm mesa with <010> convex corner
compensation etched in 36% KOH to a depth of 50 pm. (b) A close up
of the convex corner of the structure shown in (a).
49
Figure 26:
The evolution of the etch profile for a <0 10>/<110> band compensation
structure in 36% KOH at 80 0 C.
51
Figure 27:
A schematic of the mask layouts in the vertical cell.
52
Figure 28:
The major processing steps in the modified VGMJ fabrication.
53
Figure 29:
The trench filling of a 350 jm wide trench with prints of metal mask
widths (a) 300 jm (b) 280 jm (c) 270 jm and (d) 250 jm.
55
Figure 30:
A close up of the sidewall coverage of a metal line printed with a 250 pm
metal mask width.
56
Figure 31:
The dark (a) and light (b) I-V curves for selected cells in lot VERTL.
57
Figure 32:
The relationship between leakage current and open circuit voltage in lot
VERTI.
58
Figure 33:
A plot of the fill factor versus leakage current in lot VERTI.
59
Figure 34:
3x1 arrays of the modified VGMJ silicon solar cell.
60
Figure 35:
The measured I-V curve for an array of three series connected 300 jm x
300 jm cells as well as the I-V curve for each cell in the array.
60
11
12
List of Fi2ures (continued)
Page
61
Figure 36:
The measured I-V curve for seven series connected 300 gm x 300
pm cells.
Figure 37:
A schematic of a modified VGMJ array using the current 40 gm thick
cells. The junctions are implanted and the interconnects are screen
printed.
62
Figure 38:
A schematic of an array of modified VGMJ cells with a thickness of
6 gm. The interconnects are deposited with a sputter and lift-off
technique and the junctions are diffused.
63
List of Tables
Table 1:
Implant and anneal conditions for the planar cell.
32
Table 2:
The etch time and estimated etch depth for the SCELL3 corner
compensation test lot.
37
Table 3:
Solar cell parameters for the Ag/Ag and Ag.Al planar cells compared
to typical screen printed cells at an incident power of 80 mW/cm2.
40
Table 4:
Performance parameters for various cell areas in lot VERTi.
57
13
14
Acknowledgement
This thesis would not have been possible without the help of the amazing people that I have been working
with at Draper. In the micromechanical lab I would like to thank Brenda Hugh, James Cousens, Brian
Orrick, and Mert Prince for your input and work along the way. A particular note of thanks goes out to
Connie Cardoso. I appreciate your hard work and diligence more than you will ever know. In engineering,
thanks to Dom Fulginiti for the countless screen prints, to Lance Niles for the struggle with file formatting,
and to James Campbell for the ride to Evergreen. Upstairs, I would like to thank Joe Ricker and Linda
Habib for processing the endless number of SEM photos. Outside of Draper, thanks to Evergreen Solar,
Inc. and ASE Americas, Inc. for the use of your processing facilities and expertise.
I extend my gratitude to my MIT advisor, Gene Fitzgerald, and my Draper advisor, Jeff Borenstein. A
special note of thanks goes out to Jeff, for not only his advice and optimism, but also for calling in favors so
I could complete fabrication. I look forward to continued work with both of you in the future.
Finally, I want to recognize the people who kept me sane during this experience. Thanks to Chris, for
always listening and supporting me, to my Mom, for believing in and praying for me, and to my Dad, for
making me laugh and keeping me grounded. I love you guys and I couldn't have made it through five years
of MIT without you.
This thesis was prepared at The Charles Stark Draper Laboratory, Inc., with funding provided by Draper
Independent Research and Development.
Publication of this thesis does not constitute approval by Draper or the sponsoring agency of the findings or
conclusions contained herein. It is published for the exchange and stimulation of ideas.
I hereby grant permission to the Massachusetts Institute of Technology to reproduce this thesis in whole or
in part.
I
/
I277~7
15
IA7
Nicole Gerrish
May 7, 1999
16
1
Introduction
Key projects in both space and military research are moving toward developing autonomous devices." 2
These self-contained, self-powered devices can be used to explore areas where it is unsafe for human travel.
In space applications, they allow us to obtain new information about the atmospheres of uninhabitable
planets; and in military applications, they can save lives by alerting troops to the presence of chemical or
biological agents. An autonomous system requires devices that can sense and actuate a response to a
changing environment; and a power supply, which allows the system to operate independently. Because
there is a constant push for smaller, lighter, and cheaper systems, the sensors and actuators of choice are
usually microelectromechanical systems or MEMS. However, the power requirements of MEM devices are
very different from those of general electrical circuitry, and usually external voltage/current conversion
circuitry is required. Since this requirement becomes a problem for autonomous systems where size and
weight are important issues, there is a need for a self-contained, on-board power supply method that is
suitable for MEMS.
Other researchers have investigated this problem and developed power supply techniques. These
techniques include a rechargeable lithium microbattery 3 and a transformer using a magnetic field to
remotely induce currents and voltages on-chip. 4 Although these methods provide the power required, they
involve discrete components that must be aligned and joined. Solar cells are an appealing option because
they can be built using essentially the same materials system as MEM devices; thus the two can be
integrated. Solar cells are also well developed and characterized for both space and terrestrial applications.
However, traditional solar cell design is not useful for MEMS since the cells are usually very large and have
low voltage capabilities. A typical electrostatic MEM device requires a driving voltage on the order of 10100 V, while a typical solar cell only provides 0.5-3 V. 5 In order to obtain the voltages necessary for
MEMS operation, many cells must be aligned in series in an array. If the cell area is small enough, high
voltages can be achieved without consuming a significant area. Reducing the cell area does not effect the
voltage, but it does cause a significant drop in cell current. This current drop is not a problem for a MEMS
power supply because electrostatic MEM devices have driving currents in the nA-pA range.5 Since these
currents can be achieved with cell sizes less than
1 mm2 , it is possible to design high voltage, miniature
solar cell arrays that can provide power sources for MEMS.
Lee et al. have succeeded in designing and fabricating miniature solar cell arrays out of amorphous silicon
(a-Si:H). 5 Although this a-Si design is easy to fabricate, a-Si has two key disadvantages. First, there is
instability in cell performance during the PV operation. Exposure of a-Si cells to light causes degradation
17
of cell performance due what is known as the Staebler-Wronski effect. 6 Second, there is a temperature
limitation for a-Si cells. The a-Si film loses hydrogen at temperatures over 400'C, and thus irreversibly
damages the PV performance. As a result, the processing steps that can be performed after the a-Si
deposition are severely limited.
In this work, we introduce a method of fabricating miniature solar cell arrays using single crystal silicon.
First, a hybrid approach is designed and demonstrated and then an integrated approach is proposed. To the
author's knowledge, this is the first miniaturized, single crystal silicon solar cell array fabricated directly on
a silicon substrate. The design builds upon a V-groove multi-junction cell previously developed at
Berkeley, to produce an array capable of providing an integrated power source for MEMS. The hybrid
approach utilizes a screen printing "fired-though" process developed at Mobil Solar, Inc., while the
proposed integrated approach can be fabricated entirely with silicon microfabrication technology. The
integrated approach is predicted to output 2020 V/cm 2. This voltage is over an order of magnitude higher
than the 150 V produced by the Lee a-Si cell, and does not exhibit the same degradation or temperature
limitations.
2
Background
2.1
Solar Cell Principles of Operation
Solar cells convert light energy into electrical energy. The basic element of a solar cell is a p-n junction,
usually a thin, heavily doped, n-type emitter region over a thick, lightly doped, p-type base region. When
light energy impinges on the device, photons penetrate into the thick p-type region and are absorbed when
the photon energy exceeds the band gap. This absorption creates electron-hole pairs in the p-type material.
If the extra carriers are created within a diffusion length of the junction, the minority carriers (usually
electrons) are "swept" across the junction, giving rise to a photocurrent and a photovoltage. If the cell is
connected to a load, current will flow from one terminal of the cell, through the load, and to the other cell
terminal. In this manner, power is supplied to the load.
Figure
1 shows an I-V characteristic curve for a p-n junction solar cell in dark and illuminated conditions.
This I-V curve describes the solar cell behavior and can be examined through three main parameters: the
open circuit voltage, the short circuit current, and the fill factor. The open circuit voltage, Vc, is the
voltage output when the load impedance is much larger than the device impedance, and the short circuit
18
IA
(Reverse)
(Forward)
I
uminated
D k
......... VVo
A
' scPower
V
Rectangle
Figure 1:1I-V characteristic curve for a p-n junction under dark and illuminated conditions.
current, Isc, is the current output when the load impedance is much smaller than the device impedance. The
fill factor, FF, is defined as
Iv
where Im and Vm are the current and voltage at maximum power output. Once the fill factor is calculated,
the solar cell efficiency, rj, can be found by
FF.I-IV
0 -V
Pn
P(.2
Pn
where Pi,, is the input power to the solar cell.
The solar cell efficiency can be measured at a variety of sun conditions. For space and satellite
applications, the relevant spectrum is AMO, the zero air mass condition. The peak spectral irradiance for
AMO is 1353 W/m2. The AMi condition represents the sunlight at the earth's surface when the sun is at its
zenith and corresponds to an incident power of 925 W/m 2. For terrestrial applications, the AM
19
1.5 condition
is usually assumed, with a peak irradiance of 844 W/m2. This condition represents the sun at a 450 angle
above the horizon and thus is a satisfactory energy-weighted average.7
2.2
Design Criteria
The integration of solar cells with MEM devices imposes notable restrictions on the solar cell design and
fabrication method. First, the solar cells must be electrically isolated from the substrate in order to prevent
interaction between the solar and MEM devices. Second, the solar cell and MEMS processing must be at
least partially compatible, i.e. there must be a fabrication path that allows both structures to be built without
sacrificing the performance of either device. Third, in order to minimize the size of the final system, the
solar cell array should consume as small an area as possible. In addition to these restrictions, the cells must
supply the current and voltage necessary for MEMS operation. Electrostatic MEM devices typically
operate at voltages between 10-100 V and at currents in the nA-pA range. Since solar cells provide
voltages between 0.5-3 V, the cells must series connected in an array to obtain the necessary operating
voltages. The individual cells should also have a high V,, so fewer cells are required. Note that the low
driving currents make it unnecessary to maximize the current output of the cell or array.
Since most MEM devices are Si based, Si solar cells would provide the best process compatibility.
However, with conventional Si solar cell technology, connecting cells in an integrated circuit fashion is not
a simple task. Si is an indirect gap material and thus the absorptivity,
a, is relatively low. To compensate
for this low a, Si solar cells are typically 200-400 gm thick. This thickness ensures that most of the
incident solar energy is absorbed. The cells are constructed in a bulk wafer, with the emitter contact on one
wafer surface and the base contact on the other. Therefore, connecting the cells in series requires a contact
to travel through or around the wafer. Thin film solar cells are preferred because interconnects can be
defined on one side of the wafer, allowing for the use of conventional micromachining techniques. Thin
film cells are also easier to isolate than bulk wafer cells due to the availability of dielectric films.
2.3
Materials Issues
For thin film cell technology there are several materials options. Direct gap materials such as gallium
arsenide (GaAs) have high absorptivities and can absorb nearly 100% of the incident power in less than
1
gm. GaAs also has a high V., of 0.94 V due to its large band gap. However, GaAs is difficult to integrate
with Si based MEMS technologies. Polycrystalline Si can be easily and cheaply made into a thin film solar
cell, but poly-Si cells have low Vc's due to high leakage currents across the conductive grain boundaries.
20
.G
iimaarn li I'iG
Ie
3liili
Iifllia
1lo
1iifl~ f M
ll' I~l~lali
ini fill
illlll lt ~~'
aIlifli
M
il'i |E
:
"
l
'~
"i
l
.
.
-
..
. 'J
--
.Y '~a ' h
~.--l
I 1a
lllIIF
IM
M
lil iloloni nnl............in il ilH
-
'
'
--
.
-
5
-
-
--
'
.
-
-
-
-
IT
ZnO.
a-Si
Cr or Ti
Figure 2: A schematic of the Lee et al. a-Si series interconnected solar cell.
Hydrogenated amorphous Si (a-Si:H) is cheap, easy to fabricate, has a high absorptivity. It also has a larger
band gap than single crystal Si (1.55 eV compared to 1.12 eV) and thus has a higher Voc (0.9 V versus 0.7
V). Because of these attractive qualities, Lee et al. have developed an a-Si solar cell array for MEMS
applications. Figure 2 shows this a-Si cell design.
For a
1cm x 1cm array, Lee et aL reported a total voltage of 150 V and a current of 2.8 FA under AM1.5
conditions.5 Although this design satisfies the power requirements for MEMS, there are several problems
with a-Si which make it an undesirable choice for a solar cell material. First, a-Si cells degrade in
performance after exposure to light. This degradation is due to a phenomenon known as the StaeblerWronski effect, that describes optically induced decreases in both photoconductivity and dark conductivity
in a-Si. Second, a-Si:H begins to lose hydrogen at temperatures over 400*C and thus irreversibly damages
cell performance. This hydrogen loss severely limits the fabrication capabilities after cell growth; thus the
MEMS processing must either be low temperature or completed before a-Si deposition.
2.4
Single Crystal Silicon Cells
Single crystal Si does not have the degradation problems or the temperature limitations of a-Si.
Historically, single crystal Si was not considered as a thin cell material for two reasons. First, the
absorptivity of Si is low, and thus thick cells have higher efficiencies. Second, single crystal Si is difficult
to isolate because single crystal material cannot be grown on an insulator such as an oxide. However,
reexamining these issues reveals that single crystal Si may be a candidate for thin film solar cells for
MEMS. Traditional cells seek to maximize the cell voltage and current capacity in order to maximize the
21
7
-
.
.
' '
t
. -
-
''
'
Z
-
46
800
45
790
780
X" 44
770
760
S43
750
>
S42
41
40
0
50 100 150 200 250 300 350 400
Thickness (gm)
740
730
720
710
0
50 100 150 200 250 300 350 400
Thickness (gm)
(a)
(b)
Figure 3: The relationship between (a) short circuit current density and cell thickness and (b) open
circuit voltage and cell thickness. 8
output power of the cell. Figure 3 shows the relationship between J,4 , Ve, and thickness for back surface
field solar cells. Figure 3a demonstrates that as the thickness of the cell decreases, the current decreases.
This trend prevents thin cell use for traditional applications, but it does not eliminate use for MEMS
applications since the current required is 4 to 6 orders of magnitude lower. Figure 3b shows that the voltage
increases as the cell thickness decreases. This voltage increase occurs because the carriers generated have
shorter distances to collection and thus less of the potential is lost. In summary, thin single crystal Si cells
have lower currents and higher voltages; exactly what is required for MEM devices.
The isolation issue can be solved with the recent development of silicon on insulator (SOI) wafers. By
placing two silicon wafers in intimate contact and annealing for several hours, a physical bond is formed
between the two wafers. This process is known as silicon fusion bonding. If one or both of the wafers are
oxidized, then a silicon-oxide-silicon structure is formed. One of the wafers can then be thinned to the
desired thickness to obtain a single crystal Si layer that is isolated from the substrate by an oxide layer.
Using this SOI technology, individual, isolated solar cells can be defined and etched from the device layer.
2.5
Design Options
Starting with an SOI substrate, there are two configurations for a series-connected, single-crystal Si solar
cell: a planar configuration and a vertical configuration (Fig. 4). Both configurations require a thin n+ layer
22
to establish the p-n junction, and a thin p+ layer to reduce the resistance of the back contact. In the planar
configuration, the junction is parallel to the substrate and the incident light travels through the emitter layer
and into the base. This configuration is sufficient for traditional cells, but for thin film cells this design has
some key disadvantages. First, to get a p+-p-n+ configuration, the base p-Si must be epitaxially grown on a
heavily doped p+ layer. Due to the presence of the smaller boron atom, the p+ layer has a smaller lattice
constant than the p-Si layer. This lattice mismatch leads to dislocations in the p-Si if the layer is above the
critical thickness. For a boron doping of 2x0 cMn3 , the change in the lattice constant between p+ and p-Si
is about 0.005
A.
This lattice change results in a strain level of approximately 9.4x10-4 and a critical
thickness of about 0.16 pm.9 Since the base layer would be much thicker than 0.16 pm, it would contain a
high concentration of threading and misfit dislocations. These dislocations assist recombination in the
material and thus reduce the solar cell performance. The dislocation concentration increases with
increasing film thickness; therefore, the thickness of the base layer is limited.
A second disadvantage of the planar configuration is that the p+ region (usually about 0.5-1 gm thick) is a
substantial fraction of the cell volume for thin cells (<10pm). Heavily doped regions have low minority
carrier lifetimes, thus a large percentage of the generated carriers recombine before the junction collects
them. As the cell thickness decreases, the volume percentage of heavily doped material increases. This
results in a decrease in the internal collection efficiency and limits the performance of thin cells. Finally, a
planar configuration limits the metallization method. Traditionally, thin fingers are used to contact the top
of the cell and only a small percentage of the cell area is shadowed from the incident light. For a
miniaturized cell, the finger width would have to be on the order of a few microns to prevent significant
shadowing. These thin fingers would have a small cross sectional area and a high resistance, resulting in
power loss from the cell. Materials such as indium tin oxide, ITO, can be used to avoid this problem since
ARC
(a)
metallization
(b)
Figure 4: The layout for (a) a planar configuration and (b) a vertical configuration for a thin film
single crystal Si solar cell.
23
it is conductive as well as transparent to visible light. However, even though ITO offers a lower resistance
than fingers for miniature cells, it can still dissipate significant power. ITO has a resistivity of about 240
gQ-cm, two orders of magnitude higher than most metals. At maximum current operation, this resistance
can reduce the cell power by as much as 12%.
The vertical configuration does not share these disadvantages. Since the junctions are on the sides of the
device, there is no need to grow an epitaxial layer and thus the SOI device layer determines the base quality.
As the cell thickness decreases, the volume percentage of heavily doped material remains the same;
therefore, the internal collection efficiency is unaffected. Lastly, since the metal does not cover the top
surface of the cell, traditional metals can be used and resistive losses can be prevented. One disadvantage
of the vertical configuration is that the carriers have a longer distance to travel to be collected than in the
planar configuration. For a miniaturized cell, the cell thickness is much less than the cell width. A carrier
generated in the planar configuration may only have tens of microns to travel to the junction while a carrier
in the vertical configuration may have to travel hundreds of microns. The increased collection distance will
reduce both the current and voltage output of the cell. Designing rectangular cells where the width of the
cell is smaller than the length reduces this effect significantly without compromising the cell area. If the
quality of the base material is high and the cell area is small, reasonable internal collection efficiencies can
be achieved. Since it has fewer disadvantages than the planar configuration, the vertical configuration was
chosen for the thin film solar cell design.
3
Design
3.1
V-groove Multi-junction Cells
In the late 70's and early 80's, vertical junction cells received a lot of attention due to the ease in series
connection and low series resistance. The interest gradually dwindled as researchers realized how difficult
the cells were to fabricate. Silicon fabrication methods favor planar technologies, and micromachining
thick, isolated structures with deep p+ and n+ regions was not a simple task. Chappell et al. overcame this
problem by developing what they called a V-groove Multi-junction (VGMJ) cell. Figure 5 outlines the
fabrication of VGMJ cells. Fabrication begins by anodic bonding a thin, oxidized silicon wafer to a
thermally-matched, Corning 7070 glass wafer. Anodic bonding is a procedure which uses moderate
temperatures (-300'C) and high voltages (-1000 V) to form a physical bond between silicon and glass
wafers. Once the wafers are bonded, the oxide on the exposed side of the Si wafer is patterned to define the
position of the cells (Fig. 5a). This oxide pattern is the only masking step; thus there are no complicated
24
alignments required. The wafer is then etched in KOH to isolate the cells. In an anisotropic etchant like
KOH, the silicon crystal etches at a higher rate along the <100> direction than along the <111> direction.
The { 1111 planes, inclined 350 from the surface normal, define the sidewalls and form "V-grooves." By
ion implantation at +/- 35*, the heavily doped p+ and n+ regions can be easily fabricated. The cells are then
annealed to repair implant damage, and an aluminum layer is deposited and alloyed to connect the cells in
series. The final cell is illuminated on the glass side of the wafer. Light transmits through the glass and into
the silicon solar cell allowing for PV operation.
Although the VGMJ cell achieved favorable results, it never made it past the research stage. The silicon
layer shown in Figure 5a is approximately 50 pm thick and was bonded to the glass at this thickness.
Because the wafer was so thin, it often broke during handling, making the VGMJ cell difficult to fabricate.
3.2 The Modified V-groove Multi-junction Cell
Due to the advent of high quality SOI material, it is no longer necessary to bond such a thin wafer to glass.
An SOI wafer with a 50 gm device layer on top of a thicker handle wafer can be used to fabricate the
SiO2
Silicon
7070 Glass
a) Grow silicon dioxide layer, bond silicon to glass, etch
oxide to form V-groove pattern windows.
n
....
p+ n
p+ n
p+
metal
Si
~Si
i
7070 Glass
b) KOH etch V-grooves down to glass substrate, ion
implant and anneal n+ and p+ junction regions.
Si
Si
Si
7070 Glass
c) Deposit aluminum using evaporation and alloy.
Figure 5: Major fabrication steps of the Chappell et aL VGMJ silicon solar cell.
25
Chappell cell. The SOI wafer and the glass wafer can be bonded in the same manner as in the Chappell
design, but with SOI, the silicon wafer is thick, making wafer handling easier. After bonding, the handle
wafer can be etched away, using the oxide of the SOI wafer as an etch stop. The result is an oxidized 50
gm device layer bonded to glass, the same structure achieved in the Chappell cell. Although the Chappell
VGMJ cell is now easy to fabricate, it is not easy to integrate. Complications arise if the solar cell and
MEM device require controlling CMOS circuitry. The substrate is glass and cannot be processed at the
high temperatures used in silicon CMOS processing due to thermal expansion mismatch and low softening
temperatures. If CMOS processing is completed before solar cell fabrication, the high voltage bonding step
would most likely cause permanent damage to the electronics. In addition, glass contains contaminants such
as sodium that adversely effect CMOS performance. To avoid the complications of glass processing, it is
desirable to have a solar cell fabricated on a silicon substrate.
A modified version of the Chappell design is shown in Figure 6b. In the modified design, there is no glass
wafer and processing proceeds directly on an SOI substrate. Since the substrate is now silicon and not
transparent glass, the cell must be illuminated from the top. Due to the V-groove etch, there is a smaller
area at the top of the cell than at the bottom. As a result, the modified cells have to be slightly larger to
obtain the same illumination area. Top illumination also requires that the top surface is free of metals and
has a good anti-reflection coating. This requirement makes patterning steps after the KOH etch necessary, a
difficult task for thick cells. Conventional photolithography cannot reliably print patterns in trenches much
deeper than 6 gm.10 If the cells are thicker than 6 gm, patterning the metallization layer may be difficult,
Incident
.. SiS
..
Si~~
. .. .... ....
.....
.....
.A
7070 Glass.Si..........
7070 Glass
light
C
..................
SO
iio
Incident light
a) Chappell VGMJ Design
a) Modified VGMJ Design
Figure 6: The layout of the Chappell VGMJ cell (a) compared to the layout of the modified VGMJ
cell (b).
26
depending on the lithography technique. Due to this problem with photolithography, the modified VGMJ
fabrication can be split into two categories: thin cell fabrication and thick cell fabrication.
For cells 6 pm or less, standard micromachining processes can be used. Figure 7 shows the major
fabrication steps for a thin cell. Beginning with an SOI substrate, the first step is to deposit a nitride for an
etch and implantation mask. Similar to the Chappell cell, the substrate is etched in KOH to define the Vgrooves and the junctions are implanted and annealed. The nitride mask is then removed and a thin nitride
Si 3N4
a)
SiO2
Silicon
Silicon
Silicon
Silicon
b) Pattern nitride to define V-groove windows.
Begin with SOI wafer, deposit nitride masking
Si 3 N4
n
p+ n
Si
22
+
Si
Silicon
Silicon
d) Remove masking nitride and deposit and pattern thin
nitride ARC.
c) KOH etch V-grooves down to buried oxide, ion
and anneal n+ and p+ junction
.metal
...
Silco
e) Deposit and pattern metal contacts.
Figure 7: The major fabrication steps for a thin modified VGMJ cell.
27
ARC is deposited and patterned. Finally the metal contacts are deposited and patterned using a lift-off
technique.
For thick cells, the processing is slightly more difficult. Unlike thin cell fabrication, the nitride ARC cannot
be patterned after the KOH etch. As a result, the ARC must be deposited before the etch and implantation
mask and must be left behind when the mask is etched away. To achieve this requirement, the mask must
be an oxide and not a nitride. However, when the oxide mask is stripped, the etch must be highly controlled
in order to ensure that the buried oxide, that is now exposed, is not completely removed. Although
possible, this fabrication method requires more stringent process control.
Another problem for thick cells is that the final metallization has to provide conformal coverage of deep
trenches. A similar problem occurs in buried contact solar cells, where the top metallization layers are
deposited in grooves in the substrate to improve the aspect ratio of the metal pattern and the collection
efficiency of the cell. In buried contact cells, there are two major metallization methods: electroless plating
and screen printing. In electroless plating, metal is deposited through controlled chemical reduction. Metal
salts and a reducing agent react in the presence of a suitable catalyst, usually the surface being plated or a
catalyst deposited on it. No external power supply is required and plating occurs by immersing the
substrate in a carefully designed plating solution. Screen printing is a process where metal ink is pushed
through a patterned screen with a squeegee. The ink is conductive and consists of a viscous fluid containing
very fine metal particles. The squeegee is drawn across the screen at a certain angle (Fig. 8). This squeegee
motion produces a strong shear field on the metal ink at the squeegee tip, and results in a localized decrease
in the ink viscosity." The decrease in viscosity allows the ink to be pushed through openings in the screen
to the substrate. Once on the substrate, the shear rate is decreased and the viscosity of the ink is increased,
allowing the printed line to maintain its shape. The substrate is then fired at 700-800*C for 1-2 minutes.
During firing, the liquid component of the ink evaporates and the metal particles undergo liquid-assisted,
solid-phase sintering, forming a durable, printed pattern.
queegee
Squeegee
motion
M
Screen
Figure 8: A schematic of the screen printing process.
28
3.3
Design and Fabrication Selection
For the first prototype, a thickness of 50 pm was chosen. At this thickness, the cell can be directly
compared to both planar cells and the Chappell VGMJ cell, making cell performance easy to evaluate.
Draper also has extensive experience with 50 gm SOI fabrication from other projects. Since the cell is
thick, the metallization must be either electroless plated or screen printed. Although electroless plating
offers better linewidth resolution and process control, the plating capabilities at Draper are currently
inadequate for micromachining. In the limited time scale of this project, fabricating an electroless plated
cell was not a feasible option. However, Draper does have screen printing capabilities available, making
screen printing a more viable option for a proof of concept device. Screen printing also holds some
inherent advantages. First, it is a simple two step procedure. This can be compared to the plating
procedure that usually requires a three step metallization: a thin nickel layer, a thick copper layer, and a thin
silver layer. Each plating step requires careful concentration and temperature control in the plating solution
to assure proper deposition and uniformity. Second, certain inks can "fire through" Si3N4 anti-reflection
coatings. Inks can contain fine glass particles as well as metal particles. When the ink is fired, the glass
particles melt and quickly etch the nitride layer, bringing the metal particles in direct contact with the
silicon. In this manner, a low resistance contact can be made between the ink and the cell without the need
to pattern the ARC. This allows the ARC to be deposited right before the final metallization step, providing
better surface passivation at the Si/Si3N4 interface. 12
Screen printing provides a quick and easy way to verify the solar cell design, but it is not an integratable
technique. The resistance of a screen printed contact is extremely sensitive to high temperature processing
due to the presence of glass in the ink. . This sensitivity severely limits the wafer processing capabilities
after the ink has been printed. The prints are typically 10-30 pm thick, therefore, it is difficult to use
photolithography after printing to connect a printed line to a sputtered or evaporated line. Also, printing
cannot be the final step in an integrated system since the 700-800'C firing temperature is well above the
450*C melting point of aluminum. The 50 jm, screen printed cell is presented as a hybrid technique which
will be used to verify the solar cell I-V capabilities and to collect data that will be essential for the
development of an integrated technique.
4
Procedure
Before the vertical cell design could be finalized and fabrication could begin, there were parameters and
processes that needed investigation. Examples include the implantation parameters and performance, the
29
metallization scheme and line width capabilities, and the underetching of convex corners in KOH. In order
to resolve these and other issues before vertical cell fabrication, one device and four test lots were built.
Each lot investigated a potential problem with the vertical cell fabrication or design. The results from each
lot were analyzed and the information obtained was incorporated into the vertical cell.
4.1
Planar Cell
A traditional planar configuration solar cell was fabricated for two reasons. First, the metallization scheme
necessary for the vertical cell had to be verified. Conventional screen printed cells use an aluminum ink for
the back contact and a "fritted" silver ink for the emitter contact, where the term "fritted" refers to the
presence of glass frit in the ink. Aluminum contamination of the silver ink has been shown to lead to a
sharp increase in the contact resistance of the Ag-Si contact.12 This increased resistance results in a decrease
in the fill factor of the cell and thus drastically reduces cell performance. In the modified VGMJ design,
both junctions are on the same side of the wafer and are very closely spaced (Fig. 7d). Since the junctions
must be connected in series, cross contamination will occur if both Ag and Al are used. Consequently, one
ink must be chosen as the contact for both junctions. Because the condition of the emitter junction is more
crucial to solar cell performance, Ag was selected as the metallization material. Planar cells with both
silver and aluminum back contacts were fabricated to compare the effects on cell performance.
The second reason for building the planar cell was to verify the implant and anneal conditions of the emitter
and base contacts. Typically, diffusion is used for heavily doped regions in solar cells. In the 50 pm
modified VGMJ cell, diffusion cannot be used since it is difficult to define a diffusion mask on the thick
mesas. Ion implantation can define the doped regions by implanting at an angle of 350, the angle of
inclination of the
{1111 planes. However, ion implantation creates a great deal of damage in the implanted
region. If this damage is not properly annealed, the doped regions exhibit low lifetimes and high sheet
resistances. The overall result is a reduction in the open circuit voltage and fill factor in ion implanted cells.
The planar cell was fabricated using ion implantation in order to compare the implanted cell to typical
diffused cells.
4.1.1
Design and Metallization
The structure of the planar cell is shown in Figure 9. The cell is
1 cm x 1 cm and is wafer thick. Both the
n+ and p+ regions were implanted externally, and subsequently annealed at Draper. The front metal is
conductive, fritted silver ink made by the Ferro Corporation (ink #3349). The pattern consists of two 250
30
Front contact (Ag)
ARC
n+ emitter
p-type base
Rear contact (Ag or Al)
Figure 9: A schematic of the planar cell design.
gm wide fingers connected by a 1000 grm wide busbar. These dimensions were chosen using a FORTRAN
solar modeling program that minimizes the series resistance of metallization layers. The silver ink is
printed on top of the Si 3N 4 ARC coating. When the cell is fired, the frit etches though the nitride, allowing
the metal to come into intimate contact with the emitter. This firing process is crucial. If the cell is under
fired, the ink will not etch through the nitride and a high resistance contact will result. In contrast, if the cell
is over fired, the glass frit will etch the emitter and possibly short the junction. Firing must be optimized to
produce maximum cell performance.
Half of the planar cells were fabricated with an aluminum back contact and the other half were fabricated
with a silver back contact. For the silver cells, the back contact was fabricated in the same manner as the
front contact: a nitride film was deposited, the silver ink was printed, and the cells were fired. In order to
make the process for the aluminum back contact as similar to this process as possible, a fritted aluminum
ink was used (#53-038 from the Ferro Corp.). The "fired through" aluminum contact has demonstrated
similar performance to aluminum printed directly on silicon, and is designed to be used in a co-fire process
with the fritted silver ink.13
4.1.2
Implantation
It has been shown that the most critical variable for low contact resistance in screen printed cells is the
active dopant concentration at the Si surface.14 High doping levels at the surface cause significant band
31
bending at the metal-silicon interface. This band bending enables carrier tunneling through the Schottky
barrier, resulting in low resistance, ohmic contacts. The implant and anneal in the planar cell were designed
to provide a maximum surface concentration while still maintaining a small junction depth. Assuming a coanneal process, SUPREM modeling was used to investigate various implant and anneal parameters.
Limitations on the annealing step included a maximum temperature ramp up of 10 0/min and ramp down of
50/min. The parameters chosen are shown in Table 1. Implants were angled at a 70 tilt to prevent
channeling.
Table 1: Implant and anneal conditions for the planar cell.
Implant
Anneal
Profile
Dose (cm2)
Energy (keV)
Temp ©
Dwell Time (min)
Junction Depth (pm)
Nsurf (active) (cnf 3)
3
Nsurf (chemical) (cni )
4.1.3
N+ emitter
5.30E+15
10
p+ back contact
2.00E+15
15
900
10
0.69
900
10
N/A
1.88E+20
9.50E+19
3.7 1E+20
1.001E+20
Fabrication
The substrates used for planar cell fabrication were 4 inch, double-side polished, p-type, silicon wafers that
were 525 pm thick and 1-10 0-cm in resistivity. The substrates were cleaned and 0.25 pm of thermal oxide
was grown at 1000'C on both sides of the wafers. The front and back oxides were patterned with
photolithography and a buffered HF (BHF) oxide etch, using the wafer flat as a reference to align the two
patterns. The patterns defined
1 cm x 1 cm oxide windows separated by 0.5 cm of oxide on all sides.
These oxide windows determined the position of the solar cells. The wafers were then sent to IICO custom
services for ion implantation. The front and back sides of the wafer were implanted with phosphorus and
boron, respectively, using the parameters specified in Table 1. The wafers were then annealed at 900'C for
10 min in a 6% 02 and 94% N2 ambient; and a
1 min, 50:1 HF etch at room temperature was used to
remove any oxide grown during the anneal. A 900 A, Si 3N 4 anti-reflection coating was deposited in a
PECVD, pancake reactor on the front and back sides of the wafer. The depositions were done at 300*C for
9 min, with a plasma power of 17 W, and a gas flow of 100 sccm N2, 80 sccm NH 3, and 25 sccm SiH 4. The
wafers were sawed into quarters in order to aid in screen printing and to provide more samples to test the
firing conditions. A total of 16 quarters were produced, each with six
32
1 cm x 1 cm solar cells. The back Al
ink was printed with a 200 wire mesh screen, and the back Ag ink was printed with a 325 wire mesh screen.
Both prints were dried at 100*C for 10 min. Subsequently, the front Ag pattern was printed with a 325
mesh screen and dried at 100*C for 10 min. The cells were fired at Evergreen Solar Inc., in Waltham MA.,
using a 5 zone, commercial, infrared belt furnace. The temperature profile is proprietary to Evergreen
Solar. The firing was optimized by varying the dwell time in the high temperature zone of the furnace from
14-18 sec.
4.2
Test Lots
Four test lots were fabricated to prepare for the design and fabrication of the vertical cell. SCELL 1-P and
SCELL 1-B were contact resistance test lots used to measure the emitter and base contact resistivities.
SCELL2 was a metallization test lot that investigated the trench filling capabilities of screen printing.
Finally, SCELL3 was a corner compensation test lot that sought to minimize the undercut of convex corners
in KOH etching.
4.2.1
SCELL1-P and SCELL1-B: Contact Resistance
In order to measure the contact resistance of the silver ink on n-type Si and the silver and aluminum inks on
p-type Si, test lots SCELL1-P and SCELL1-B were fabricated. These lots employ the "Shockley Ladder"
method,' 5 where contact resistance is measured through thin, parallel metal lines on top of a conductive
layer. The specifics of the measurement technique are described in section 4.3. A schematic of the
structure is shown in Figure 10. The conductive layer is phosphorous doped Si in lot SCELL1-P and boron
doped Si in lot SCELL1-B. The metal pattern in both lots consists of 250 pm x 4500 gm, Ag or Al lines
spaced at even intervals of 5000 pm.
Ag
ARC
Doped layer
Si
Figure 10: A schematic of lots SCELL1-P and SCELL1-B.
33
SCELL1-P and SCELL1-B were both fabricated on 20 mil, 4 inch, p-type silicon wafers. In lot SCELL1-P,
the wafers were cleaned and sent out for implantation at IICO. Implant conditions were the same as the
emitter contact in the planar cell: phosphorus implant, 5.3x1015 ions/cm 2 dose, 10 keV energy, and 7* tilt.
The wafers were annealed at 900 0C for 10 min in a 6% 02, 94% N2 ambient, and etched for
1 min in 50:1
HF at room temperature to remove any oxide grown during the anneal. Lot SCELL1-B was cleaned and
doped with a shallow boron diffusion. Diffusion was chosen over implantation due to process availability.
The wafers were diffused at 1125'C for 60 min in a 3%
02
ambient, followed by a dilution oxidation at
875'C for a total of 50 min. The dilution oxide was removed with a 2 min, 1:1 HF etch. After doping, both
SCELL I-P and SCELL 1-B were coated with 900 A of plasma nitride under the same conditions as the
planar cell. Both lots were then sawed into quarters and screen printed. Lot SCELL1-P was printed with
fritted silver ink using a 325 mesh screen, and lot SCELL1-B was printed with either fritted silver or
aluminum ink using a 325 mesh and a 200 mesh screen, respectively. The substrates were dried at 100 C
for 10 min, and fired at Evergreen. The dwell time in the high temperature, firing zone of the furnace was
varied from 13-19 sec for lot SCELL1-B, and from 9-29 sec for lot SCELL1-P.
4.2.2
SCELL2: Trench Filling of Screen Prints
Although screen printing can be used to fill trenches, it cannot be used to fill very deep trenches. The
viscosity of the ink increases exponentially with decreasing shear rate." Deep inside a trench, the ink is
separated from the shear force of the squeegee; thus the viscosity is not low enough to provide conformal
trench coverage. SCELL2 was designed to test the filling capabilities of 50 gm trenches. Figure 11 shows
a unit cell of the SCELL2 layout. The test lot examines trenches of 200-450 gm in width, where the trench
width refers to the distance between Si mesas at the top of the trench. Lines of 100-450 gm were also
printed directly on the substrate to monitor the line width capabilities of the print. The pattern shown in
Figure 11 was oriented both parallel and perpendicular to squeegee motion in order to determine if
orientation had an appreciable effect on printing quality.
For SCELL2, fabrication began with 20 mil, 4 inch, p-type, silicon wafers. The wafers were cleaned and
oxidized at 1 100'C to an oxide thickness of 0.6 jm. The substrates were patterned using photolithography
and oxide windows were opened using a BHF etch. A 36% KOH solution at 80'C was used to etch the 50
gm trenches. Strandman et al. have demonstrated that this KOH concentration and temperature provides
smooth
{1111 groove walls without the formation of pyramidal hillocks on the bottom <100> surface.16
The KOH solution exhibited an average etch rate of 1.1 jm/min, resulting in a total etch time of 46 min.
34
etal
I
I
IMor,
I'll
Figure 11: The layout of a unit cell of test lot SCELL2. Structure is not shown to scale.
The oxide mask was stripped in a 3:1 HF solution, and a plasma nitride was deposited using the same
parameters as the planar cell and SCELLI lots. The substrates were then sawed into quarters and screen
printed with silver ink. For this print, a 290 mesh screen was used. A 290 screen has 45% more open area
than the recommended 325 screen. The higher percentage of open area results in a thicker print and thus
better trench filling capabilities. The metal was dried at 100*C for 10 min and fired at Evergreen Solar.
After processing, the substrates were cleaved to expose a cross-sections of the trenches and SEM photos
were taken. The width of the printed lines were measured with a WYKO interferometer.
4.2.3
SCELL3: Corner Compensation
In the anisotropic KOH etching of (100) silicon, the {411} planes etch faster than the (100} planes. As a
result, severe undercutting occurs at convex corners where these planes are open to the etching solution.
The undercutting exposes the (4111 planes as well as a rugged surface that the (4111 etch leaves behind
(Fig. 12). This undercut is a problem for the modified VGMJ cell because it consumes cell volume that can
be used for generation, and also because it forms complex surfaces that will be doped during implantation.
In order to build reliable cells, perfect square convex corners are necessary. These corners can be
fabricated by adding compensation structures to the convex corners on the etching mask. If the
compensation structure is designed correctly, the structure etches away gradually during the KOH etch,
35
(001)
(110
(110)
Figure 12: Planes occurring at convex corners during KOH etching.
protecting the convex corner. When the final etch depth is reached, the compensation structure is
completely etched away, leaving behind a corner with little or no undercut.
Four different compensation methods were investigated in the SCELL3 test lot: <110> strips, <110>
squares, <010> bands, and <010> bands with <110> compensation. The added structures, shown in Figure
13, protect the convex corner during the KOH etch. As the etch proceeds, the compensation structures are
undercut, causing them to slowly etch away. A well-designed structure is completely underetched just as
the desired etch depth is reached. The dimensions of each compensation structure depend on the final etch
depth and the etch ratio of the (4111 and (100) planes. The (411)/(100} etch ratio does not depend on
temperature in the range of 600 to 100*C, but it does depend on KOH concentration.17 As a result, different
compensation dimensions are necessary for different etch solutions. For specifics on the compensation
structure dimensions, refer to Appendix A.
The substrates for lot SCELL3 were 20 mil, 4 inch, p-type, silicon wafers. The wafers were cleaned and 0.6
gm of thermal oxide was grown at 1 100*C. The oxide was patterned to define the mesas and compensation
structures and was etched in BHF. The wafers were sawed into quarters and the quarters were etched in
36% KOH at 80*C for various times. The etch time for each quarter is shown in Table 2. Quarters A I-A4
were used to monitor etch profiles of the compensation structures over time. Quarters B 1-C2 were used to
find the first point where each compensation structure was completely removed. At this point, the undercut
is at a minimum and thus the maximum compensation capability is demonstrated. SEM photos were taken
of the samples to show compensation performance.
36
<110> strips
<110> squares
<010:- bands
<010> bands with
<110> compensation
Figure 13: The various convex corner compensation methods investigated in test lot SCELL3.
Table 2: The etch time and estimated etch depth for the SCELL3 corner compensation test lot.
Quarter ID
Al
A4
A3
A2
Cl
B2
B3
B1
-B4
C2
Etch Time
(min)
11.5
23
34.5
46
40
42
44
46
48
50
Estimated
Depth (sm)
12.5
25
37.5
50
43.5
45.7
47.8
50
52.2
54.3
4.3 Electrical Characterization
After planar cell fabrication was completed, the cells were tested for electrical performance. The test
apparatus consisted of a Keithley Model 2400 Sourcemeter and four needle probes. By varying the voltage
and measuring the corresponding current, light and dark I-V curves were generated. The front of the cell
was contacted directly with the probes, while the back was contacted by placing the probes on the
conductive stainless steel chuck. The cells were tested with a four-point probe technique, where two probes
supply the voltage to the cell and two separate probes measure the current. The four-point probe technique
is necessary to eliminate the series resistance of the test setup.
37
Lots SCELL1-P and SCELL1-B were measured for contact resistance using the Shockley Ladder method.
The test setup is shown in Figure 14. Using two probes, a constant current was supplied between the two
outermost lines with the Keithley Sourcemeter. The voltage drop between one of the two current probes
(referred to as the lead probe) and an adjacent line was measured using a third probe and a Fluke Voltmeter.
The third probe was then moved in a stepwise fashion down the series of lines, and the corresponding
voltage drop was recorded. A linear plot of voltage drop vs. distance from the lead probe was produced.
The intercept of this line was used to calculate the resistivity of the contact under the lead probe. The
details of this calculation can be found in Appendix B.
(lead probe)
Figure 14: A schematic of the contact resistance measurement and test structures.
5
Results and Discussion
5.1
Planar Cell
The planar cell photoresponse was measured outside with an incident solar radiation of 80 mW/cm 2. Figure
15 shows the results for the Ag/Ag and Ag/Al cells for various peak firing times. In the Ag/Al cells, there is
little variation in performance for the different firing conditions. However, in the Ag/Ag cells, the
performance is drastically reduced with decreased firing time. This decreased performance is most likely
due to inadequate firing of the back silver contact. The furnace that was used for firing has infrared heating
elements on the top side of the belt. The cells were fired with the emitter side up; thus the back contact was
38
Silver/Aluminum Cell Performance
Silver/Silver Cell Performance
3..
3-
a-
r..)
Voltage (V)
Voltage (V)
(a)
(b)
Figure 15: The planar cell performance with an incident power of 80 mW/cm 2, for (a) silver/silver
metallized cells and (b) silver/aluminum metallized cells. Performance is shown for various times at
peak temperature.
indirectly exposed to the heat. Since silicon is an excellent thermal conductor, in the firing of traditional
cells there is not much temperature difference between the front and back contacts. However, the planar
cell had a thick oxide layer and a thin nitride layer on each side of the wafer. The thermal conductivity of
these layers is two orders of magnitude lower than silicon. Because the etch rate of the glass frit is
exponentially dependent on temperature, even a small temperature fluctuation can significantly change the
contact quality. The Al ink has slightly lower firing requirements than the Ag ink; therefore, in the Ag/Al
cells the back contact was sufficiently fired. In the Ag/Ag cells, both contacts require the same firing
conditions. As a result, the indirect heating of the back Ag contact was inadequate, resulting in high
resistance contacts. For long firing times, the cell was exposed to high temperatures for longer periods of
time, allowing the back contact condition and cell performance to improve. The Ag/Ag cell photoresponse
might be improved further by increasing the firing time above 18 sec. However, a longer firing time may
result in over-firing of the front contact. Over-firing occurs when the frit etches through the junction,
causing either a short of the junction or a low shunt (parallel) resistance. The balance between the front and
back contact conditions makes the Ag/Ag planar cell difficult to optimize. In the modified VGMJ cell, both
contacts are on the front surface of the wafer and thus are exposed to the same firing conditions. Therefore,
the under-firing of the base contact should not be an issuefor the vertical cell.
39
Table 3 compares the performance of the maximum power Ag/Ag and Ag/Al cells to typical screen printed
cells. In both cases the open circuit voltage about 0.5 V, 0.1 V lower than typical cells. There are three
possible reasons for this low V,: a high shunt resistance, a low base doping, or an insufficient anneal after
implant. The shunt resistance is determined by the slope of the dark reverse current. For the Ag/Ag cells
and the Ag/Al cells, the shunt resistances were 31 kQ and 9 kQ, respectively. These resistances are too
high to cause any significant effect on the open circuit voltage.18 The second possibility for the low Vc is a
high base resistivity. Typical screen printed cells have 1 fl-cm bases. Spreading resistance data revealed
that the base resistivity of the Ag/Ag and Ag/Al cells was 9 92-cm, corresponding to a base doping of
1.5x10 cm 3 . At this doping level, the V, of the cell should be about 0.54 V, accounting for more than
half of the decrease in V.
17
Finally, an insufficient implant anneal can reduce the open circuit voltage.
Ion implantation causes a great deal of lattice damage in the implanted region. If this damage is not
properly annealed, it will result in a low carrier lifetime and high sheet resistance. The sheet resistivities of
the doped layers after anneal were measured with a Vecco resistivity probe. The emitter layer averaged a
sheet resistivity of 29 L2/sq, while the boron doped back contact averaged a sheet resistivity of 50 L/sq.
Although these resistivities are comparable to diffused cells, it is possible that the implantation damage was
not completely annealed, resulting in a reduction of V,.
Table 3: Solar cell parameters for the Ag/Ag and Ag/Al planar cells compared to typical screen
printed solar cells at an incident power of 80 mW/cm 2.'8 The Ag/Ag cell was fired for 18 sec while the
Ag/Al cell was fired at 16 sec.
A A
Ag/Al
Typical
V
(V)
0.51
0.49
0.6
Isc
(mA)
16.0
19.2
24.0
VM
(V)
0.3
0.35
0.5
In
(mA)
14.2
17.8
21.6
Po
(mW)
4.26
6.23
10.8
Pi
(mW)
80
80
80
FF
Efficiency
0.52
0.66
0.75
5.33%
7.79%
13.5%
The solar cells also displayed low efficiencies, fill factors, and short circuit currents. One reason for the
low solar efficiency is a poor anti-reflection coating. The nitride ARC was designed to have an index of 2.0
and a thickness of 900 A. Figure 16 shows the reflectance characteristics of the designed ARC versus
wavelength. At these designed parameters, the average reflectance is 10.8%. Due to an overpressure of
silane during the nitride deposition, the actual ARC was silicon rich and had an index of 2.5-2.6. This high
index raises the average reflectance to 19.4%, thus reducing the external collection efficiency of the cell.
40
ARC Performance
60
50
des
40
30
act
20
10
0
0.4
0.5
0.6
0.7
0.8
0.9
1
.
1.1
Wawlength (mm)
Figure 16: The reflectance of the designed and actual ARCs versus wavelength.
Although the ARC is not optimized, it is not responsible for the large drop in cell efficiency. A comparison
between cells with the designed and actual coatings demonstrates that the ARC results in less than a 1%
drop in efficiency and has no effect on the fill factor.
The primary reason for the poor cell performance is a high series resistance. Dark I-V curves reveal series
resistances of 9.1 Q and 4.4 9 in the Ag/Ag and Ag/Al cells, respectively. The high series resistance in the
Ag/Ag cell can be explained by the under firing of the back contact. The Ag/Al cell does not appear to be
under fired because there is no variation in cell performance with firing time. There are five possible
sources of series resistance in the Ag/Al cell: the metallization layers, the heavily doped regions, the lightly
doped base, the contacts, and the testing apparatus. The resistances of the metallization and doped layers
has been shown to be negligible for screen printed cells. 8 The base resistance can be calculated from the
resistivity and was found to be 0.47 92. Using a
1 a-cm base will reduce this resistance to 0.05 Q.
Figure 17 demonstrates the method used to determine the contact resistance of the emitter. The cell was
scribed and cleaved to separate the fingers from the busbar, and needle probes and a sourcemeter were used
to measure the resistance between the two fingers. The resistance value measured includes the resistance of
the test setup, the fingers, the emitter layer, and the two metal/Si contacts. The resistance of the test setup
was measured to be 2.5 9, and the resistance of the fingers and the emitter layer were calculated to be
1.5x10-5 Q and 37.5
Q, respectively. Adding these resistances and subtracting from the total value of 54 Q,
reveals a contact resistance of 14 91. This resistance corresponds to a contact resistivity of 336 mQ-cm2
and a total resistance of 2.32
Q for the planar cell. The surface concentration of the emitter was 1.9x102
41
ARC
n+
Si-base
Figure 17: A schematic of the contact resistance measurement for the planar Ag/Al cell.
cm 3 . At this concentration, the contact resistivity should be 30-40 mf -cm 2, much lower than the observed
value. The high contact resistivity in the planar cell is most likely due to Al contamination in the Ag ink.
The base resistivity and the emitter contact resistivity accounts for 2.8 Q of the total series resistance. The
remaining resistance could be due to either the base contact or the test apparatus. The base contact is a
solid square; therefore its resistance cannot be measured in the same manner as the emitter contact.
Because the base contact has a
1 cm 2 area, the contact resistivity would have to be on the order of ohms to
cause a significant resistance. A contact resistivity of this order is unlikely with a fully fired, heavily doped
contact. The four-point probe method used to generate the I-V curves eliminates the series resistance of the
testing apparatus. However, if the probes are not in good contact with the cell, a reduced current will be
read for a given input voltage. This decreased current results in an "effective" resistance that reduces the
measured performance. Since the cells were tested outdoors, no microscopes were available to ensure that
the probes were in good contact with the cell. More controlled testing conditions are necessary to get an
accurate reading of the cell output.
5.2
Test Lots
5.2.1
SCELL1-P and SCELL1-B: Contact Resistance
Borenstein et. al. demonstrated that the fill factor drops off sharply when the contact resistance rises above
100 m9-cm2 ' 9 In order to characterize the contact resistance for the emitter and base contacts in detail, lots
SCELL1-P and SCELL1-B were fabricated. Lot SCELL1-P examined the resistance of the emitter contact
for peak firing times. Results are shown in Figure 18. For firing times between 12 and 20 sec, the contact
42
Emnitter Contact Resistivity
25
2 00
2 50
5
10
15
20
25
30
Peak firing time(sec)
Figure 18: The contact resistivity of silver ink on heavily doped n-type silicon versus the firing time.
resistance is essentially unchanged and has an average value of 50 mQ-cm 2 . This value is much lower than
the 336 m:Q-cm 2 measured in the planar cell. The doping, nitride coating, printing, and firing of SCELL1-P
were identical to the conditions of the planar cell, yet no samples fired for the same amount of time exhibit
high contact resistances. This disparity confirms the theory that the emitter contact in the planar cell was
contaminated with aluminum. Below a firing time of 12 sec, the contact resistivity increases rapidly with
decreasing time. This trend is due to inadequate firing of the contact. As the firing time decreases, the
glass frit has less time to etch through the nitride and contact the underlying silicon. Eventually, the ink will
not be able to make good contact to the silicon causing the contact resistivity to increase rapidly. A small
increase in contact resistivity also occurs at long firing times. Once the glass frit in the ink has etched
through the nitride, it will continue to etch the silicon at a finite rate. If the sample is fired too long, the ink
will etch through the heavily doped Si at the surface and make contact with the underlying lightly doped Si.
Since metal-Si contact resistance increases with decreasing doping levels, the contact resistivity will
increase as the firing time increases. This resistivity will eventually plateau when the ink contacts the
lightly doped base. However, at this point the emitter junction has been shorted and the cell is destroyed.
The results for lot SCELL1-B are shown in Figure 19. This test lot examines the base contact resistivity for
silver and aluminum metallizations. The firing time was varied from 12-2 1 sec, within the optimal firing
range of the emitter. Both the silver and aluminum exhibit contact resistivities below 15 m:Q-cm 2 on the p' Si. The Al contacts have an average resistivity of 10 md2-cm 2 and a standard deviation of 0.76
43
rrLQ-cm
2
,
Base Contact Resistivity
20
Eqg
15
10
U
5
11
13
15
17
19
21
Peak firing time (sec)
Figure 19: The contact resistivity of silver and aluminum ink on heavily doped p-type silicon versus
the firing time.
and the Ag contacts have an average resistivity of 12.4
mr2-cm 2 and a standard deviation of 1.7 m(2-cm 2.
Although the Al contacts show slightly lower and more reliable resistivities, the Ag contacts are well within
the 100 mQ-cm2 requirement and can be used to contact the p-type base.
5.2.2
SCELL2: Trench Filling of Screen Prints
In lot SCELL2, the line width of the metal prints in the trenches and the metal prints on the substrate were
measured with an optical interferometer. In both cases the printed width was much larger than the mask
width. Figure 20 plots the difference between the printed width and mask width versus mask width for the
trenches. The metal mask width was designed to be the same as the width of the top of the trench. Since
the actual printed width was larger than this, there was metal on the top of the silicon mesas. In the
modified VGMJ cell, this will short the emitter-base junction and destroy the cell. In order to avoid this
failure in the vertical cell, the metal mask lines must be smaller than the trench width. However, it is
difficult to determine exactly how much smaller the mask width should be. The difference between the
printed width and the mask width varied from 43-75 gm, and did not have a clear dependence on mask
width. The trenches that were aligned parallel to squeegee motion averaged a difference of 48 pm while the
perpendicular trenches averaged a difference of 61 gm. The parallel trenches also had a slightly lower
deviation in width for the same mask dimensions (5
sm compared to 8 gm).
44
This data suggests that for the
SCEL12 Trenches
80
70
V
60
E50
40
2
-.-
30
Paralle
I
-ePerpendicular
20
150
200
250
300
350
400
450
500
Mask Width (gm)
Figure 20: The difference between the measured line width and the designed line width for the
trenches in lot SCELL2. Data is shown for trenches aligned parallel and perpendicular to squeegee
motion.
best line width in vertical cell, the trenches should be aligned parallel to squeegee motion and the metal
mask width must be at least 48gm smaller than the trench width.
In Figure 21a, SEM photos are shown of the trench filling capabilities for a 350 pm wide trench printed
with a 350 pm metal mask line. The metal is in good contact with both the bottom and sidewalls of the
trench, demonstrating that at a depth of 50 gm, screen printing can provide conformal coverage. However,
for the same trench width, the coverage capability decreases as the width of the metal mask line decreases.
The alignment structures of the test lot were designed with a metal mask width 100 pm smaller than the
trench width so the mask could be easily aligned in the center of the trench. A cross-section of the
alignment structure (Figure 21b) demonstrates that at these dimensions, there is no metal on the top of the
mesa but the ink does not make good contact with the sidewalls. Therefore, the difference between the
trench width and the metal mask width must be at least 48 pm to prevent the ink from depositing on top of
the mesa, but it must be less than 100 pm to provide conformal trench coverage. If both requirements
cannot be met at the same time, then screen printing will not be a viable method of metallization.
Figure 22 shows the difference between the measured and designed width of the lines printed directly on the
substrate. For narrow lines, the printed width was significantly larger than the mask width. As the width of
45
(a)
(b)
Figure 21: The trench filling of a 350 pm wide and 50 gm deep trench with silver ink using a screen
print mask width of (a) 350 im and (b) 250 im.
the lines increased, this difference gradually decreased. The narrow prints also displayed a high standard
deviation in width, and the 100 gm line width varied by as much as 50 pm. This deviation decreased with
increasing line width and for prints thicker than 250 jm, the deviation was below 10 pm. The size of the
woven mesh and the diameter of the wire determine the fineness of detail that can be achieved with screen
printing. The screen used had a wire diameter of 20 jm and a mesh count of 290 lines per square
centimeter. If the dimensions were perfectly regular, it would be possible to print lines of about 75 jm in
width. However, the wire spacing in the mesh is not regular nor are the wires perfectly straight. Also, the
edges of the emulsion that define the pattern to be printed are in random orientation with the mesh. As a
result, openings in the mesh near the line edge may be partially or completely covered. This blockage
restricts the flow of ink in certain positions along the line edge, causing uneven printing and line width.
The effect is greater for finer lines because there are only a few screen apertures over the width of the line. 20
SCELL2 demonstrates that for reliable screen prints, the width of the lines should be at least 250 pm. A
screen with a smaller diameter wire and a higher mesh could be used to reduce the minimum line width;
however, this would decrease the thickness of the print and reduce the trench filling capabilities.
46
SCELL2 Lines
9-Paralel
100
- - 0 - -Parallel StDev
.5
80
-
Perpend.
60
40
S
20
0
50
100
150
200
250
300
350
400
450
500
Mask Width (pm)
Figure 22: The difference between the measured line width and the designed line width in lot
SCELL2. Data is shown for lines aligned parallel and perpendicular to squeegee motion.
5.2.3
SCELL3: Corner Compensation
Figure 23a shows a 250 x 250 gm square mesa with no convex corner compensation that has been etched to
a depth of 50 pm. Approximately 55% of the cell area was removed due to undercutting. There are no
<Ill> sidewalls present, and thus it is impossible to obtain a well-defined junction. A close-up of the
corner undercut is shown in Figure 23b. As expected, the corner is defined by the
{4111 planes and a
rugged surface where only fractions of the main planes are evident.
The <110> beam and <110> square compensation methods significantly reduce the amount of undercut
present in the final structure. Figure 24a and c represent 250 x 250 gm square mesas with <110> beam and
<110> square convex corner compensation, respectively. In both techniques, there is still a moderate level
of undercut. For the <110> beam technique, the least amount of undercut occurred in the structure with the
thinnest beams (15 pm) and the longest end branch length (30 pm, see Appendix C). Figure 24b and d
show close-ups of the beam and square compensated corners when the compensation structures are
completely underetched. The <110> compensation structures are undercut by the (4111 planes; thus, the
(411 } planes and the rugged surfaces they produce define the final corner structure. As a result, it is
impossible to obtain complete convex corners defined by the intersection of the (111} planes. The complex
47
(a)
(b)
Figure 23: (a) A top view of a 250 x 250 pm square mesa with no convex corner compensation etched
in 36% KOH to a depth of 50 pm. (b) A close up of a convex corner of the structure shown in (a).
surfaces at the corner will be exposed during ion implantation of the modified VGMJ cell. The complex
geometry of the junction formed will decrease the performance and reliability of the solar cells.
Both the <110> beam and square compensation structures were completely underetched at an etch depth of
44.4 pm, 5.6 pm short of the desired etch depth. The dimensions of the structures were determined by
assuming a (411 }/( 100} etch ratio of 1.35, as reported by Bean.' Since the compensation structures were
removed before the designed depth, the etch ratio in the solution was slightly higher. Using the design
criteria described in Appendix A, the etch ratio was back calculated from the maximum depth of corner
protection. The observed etch ratio was found to be 1.52. This value corresponds well to data reported by
Enoksson for 36% KOH.22
In the <010> compensation method, the (100) planes undercut the band from the sides and the (4111
planes undercut from the end. If the band is long enough, the (1001 planes reach the corner before
the
(4111 planes, forming a perfect square convex corner defined by the (1111 planes. Assuming a
{411)/(1001 etch ratio of 1.35, the band length must be at least 1.6 times the width to achieve perfect
corners. The width of the band is twice the etch depth; therefore, the length of the band should be 160
pm
for a 50 pm depth. For the observed etch ratio of 1.52, the required band length increases to 180
pm. A
250 x 250 pm square mesa with <010> convex corner compensation is shown in Figure 25a. The
compensation band was 175 pm long. A close-up of a corner demonstrates near perfect compensation
48
(a)
(b)
(c)
(d)
Figure 24: A top view of a 250 x 250 sm mesa compensated with (a) <110> beams and (c) <110>
squares etched in 36% KOH to a depth of 44.4 gm. A close up of the (b) <110> beam compensated
corner and the (d) <110> square compensated corner.
250x
50
(a)
(b)
Figure 25: (a) A top view of a 250 x 250 pm mesa with <010> convex corner compensation etched in
36% KOH to a depth of 50 pm. (b) A close up of a convex corner of the structure shown in (a).
49
(Figure 25b) at a depth of 50 gm. The slight underetch at the bottom of the corner can be eliminated by
extending the band length to 180 gm.
The <010> band with <110> compensation was designed to provide the same convex corner compensation
as the <010> band but with lower spatial requirements. In the compensated bands, the <110> beams protect
the band from both {100) and {411) undercut in the initial stages of etching. By delaying the etch of the
<010> band, the total length of the band can be reduced. Figure 26 shows the evolution of the etch profile
for a <010>/<110> compensated corner. As in the <010> band, near perfect compensation is achieved but
in this case the initial structure is only 95.5 jm long. The slight undercut in the final structure is again due
to the low approximation of the (411}/{100} etch rate. This undercut can be avoided by increasing the
length of either the <010> band or the <110> beams. The etch profile evolution of the other compensation
techniques is presented in Appendix C.
6
The Modified VGMJ Cell
6.1
Design
Using the information obtained from the test lots, the modified VGMJ cell was designed. The lot, named
VERTI, investigated two issues: the optimum metal mask width for trench filling, and the relationship
between cell area and performance. A schematic of the VERTI layout is shown in Figure 27. SCELL2
demonstrated that the metal mask width must be between 48 and 100 jm less than the trench width, and that
lines narrower than 250 pm cannot be printed with good thickness control. In lot VERTI, the width
between cells was designed to be 350 pm. At this trench width, different metal mask widths can be used
without pushing the line width capability of the screen print. Metal mask widths of 250 jim, 270 jm, 280
jm, and 300 pm were examined in order to determine which dimension provided the best trench filling.
The length of the metal line was 100 jm smaller than the length of the cell to prevent the metal from
extending around the corner of the cell and shorting the junction. The side length was varied from 300 to
450 pm in 50 pm intervals to demonstrate the effects of area on cell performance. Since there was ample
space between cells, the <010> band compensation method was used. In accordance to the results from lot
SCELL3, the bands were designed to be 180 jm long.
50
(a)
(b)
(c)
(d)
(e)
Figure 26: The evolution of the etch profile for a <010>/<110> band compensation structure in 36%
KOH at 80*C. Etch times are (a) 0 min, (b) 11.5 min, (c) 23 min, (d) 34.5 min, and (e) 44 min.
51
Figure 27: A schematic of the mask layouts in the vertical cell. The light gray represents the oxide
mask while the dark gray represents the metal mask openings.
6.2
Fabrication
6.2.1
SOI Substrates
The SOI substrates were fabricated by bonding an oxidized device wafer to a handle wafer. The device
wafers were 525 gm thick, 1-5 91-cm, double-side polished, p-type wafers, and the handle wafers were 525
pm thick, 0.1-0.5 a-cm, single-side polished, p-type wafers. The wafers were cleaned and 1 pm of thermal
oxide was grown on the device wafer at 1 100*C. The wafers were fusion bonded at MIT and the exposed
oxide on the device layer was removed using BHF. At Valley Design, Inc., the device wafers were lapped
to the desired thickness of 50 pm and optically polished. The thickness of the device layer was measured
using Fourier Transform Infrared Spectroscopy (FTIR).
6.2.2
Modified VGMJ Processing
A schematic of the modified VGMJ processing is shown in Figure 28. The substrates were cleaned and
0.65 gm of thermal oxide was grown at 1000*C. The oxide was patterned with the KOH mask using
photoresist and a BHF oxide etch, and the wafers were etched in 36% KOH at 80 0C. The KOH etch rate
was 0.91 pm/min resulting in a total etch time of 55 min. The p+ and n+ regions were implanted externally
at IICO. The implants were designed to provide the same dopant profile as the planar cell. Since the
implantation of the vertical cell is on the (111) plane and not the (100) plane, the phosphorus dose was
increased from 5.3x10 15 to 5.5x1015 cm 2 to generate the same surface concentration.
52
The other implant
Sil D
Silicon
Siliczi
Silicon
Silicon
a) Begin with SOI wafer, grow thermal nitride
b) Pattern oxide layer to define V-groove windows
n
... . ....
. .
U / P+
p+ n- ...............
pj77
Silicon
Silicon
d) Implant and anneal n+ and p+ regions
c) KOH etch to the buried oxide
Si 3 N4
SiSi
Sc
Silicon
Silicon
c) Carefully strip oxide on top of cells
d) Deposit plasma nitride
Ag
.
.......
Silicon .
...
Silii
.-MM
e) Screen print Ag ink and dry
f) Fire cells to create contacts
Figure 28: The major processing steps in the modified VGMJ fabrication.
53
conditions were the same as used in the planar cell: phosphorus energy = 10 keV, boron energy = 15 keV,
and boron dose = 2.0x10
cm-2 . After implant, the wafers were annealed at 9001C in a 6% 02 and 94% N 2
ambient for 10 min to repair damage.
The oxide mask was stripped in BHF. In the original fabrication plan, the KOH and implantation mask was
a plasma nitride layer. A nitride mask can be stripped without etching the buried oxide, using a phosphoric
acid etch. However, due to problems with the plasma deposition system, an oxide mask was necessary. As
a result, the mask etch had to be carefully controlled so that the buried oxide was not completely removed.
This removal was avoided by careful thickness selection of the oxide mask. The selectivity of silicon to
oxide in the 36% KOH solution at 80'C was measured to be 140:1. Therefore, with an original oxide
thickness of 0.65 pm, 0.3 gm remained after the KOH etch for an implantation mask. The buried oxide was
1 pm thick and was not exposed to the KOH solution. By using a controlled BHF etch, the top oxide was
removed leaving approximately 0.65-0.7 gm of the buried oxide behind to isolate the cells from the
substrate. Although these process steps produced the desired results, a nitride process would be more
robust.
Due to problems with the plasma nitride system at Draper, the silicon nitride ARC was processed off site at
ASE Americas Inc., in Billerica MA. An 800
A, double layer nitride was deposited using proprietary
parameters. The substrates were sawed into quarters and screen printed with fritted silver ink using a 290
mesh screen. The quarters were fired in an infrared belt furnace at Evergreen Solar, and the peak firing
time was varied from 13-21 sec to find the optimal firing conditions.
After processing was complete, I-V curves were generated using the four-point probe technique described
in section 4.3. Testing was performed on a Wentworth probe station to ensure that all probes were in good
contact with the metal. The cells were illuminated with a 300 W tungsten halogen bulb with infrared
reflectors. A Newport optical power meter was used to verify a power density of 100 mW/cm 2.
6.3
Results
6.3.1
SOI Substrates
FTIR measurements of the SOI material revealed an average device layer thickness of 41.4 pm, 8.6 pm less
than the desired value. The average from wafer to wafer ranged from 38.9 pm to 43.7 gm, and the
thickness across each wafer varied by as much as 6.8 gm. This result demonstrates the difficulty in
54
obtaining good SOI thickness control with a bond and lap process. SOI wafers of the desired thickness can
be fabricated externally once a reliable vendor is identified. An etch pit density measurement was
performed to determine the number of defects induced during SOI processing. The etch pit density was
found to be less than 25 /cm 2. With this dislocation density, less than 1% of the cells will be effected by the
presence of defects.
6.3.2
Metallization
SEM analysis was used to determine which metal mask width produced the best trench filling capabilities.
Figure 29 shows the filling of 350 pm trenches printed with mask widths of 300, 280, 270, and 250 pm. All
of the prints left metal on top of the silicon mesa except the line printed with the 250 gm mask width.
However, as in lot SCELL2, this print does not exhibit conformal sidewall coverage (Fig. 30); thus, there is
poor electrical contact to the cell. The cells printed with the 270 gm mask width do have good sidewall
coverage. These cells were chosen for electrical testing because there was good electrical contact and the
metal on top of the cell was at a minimum.
(a)
(b)
(b)
(d)
Figure 29: The trench filling of a 350 pm wide trench with prints with metal mask widths of (a) 300
gm (b) 280 pm, (c) 270 pm and (d) 250 pm.
55
750x
Figure 30: A close up of the sidewall coverage of a metal line printed with a 250 gim metal mask
width. Note the gap between the sidewall and the metal ink.
The metal particles present on top of the cell provide an alternate path across the junction and result in a
large leakage current. Leakage currents for several cells were measured and normalized by the cell area.
The leakage current density varied between 2-140 mA/cm 2. There was a direct correspondence between the
amount of metal at the edge of the silicon mesa and the leakage current.
6.3.3
Cell Performance
Cells that exhibited lower leakage currents (<15 mA/cm 2) were selected for I-V analysis. Dark and light
curves for the cells are shown in Figure 31 and are summarized in Table 4. Unlike the planar cells, the
vertical cells do not exhibit high series resistances. The average resistance value of the three cells was 373
Q. This value may appear high, but it corresponds to a value of 0.54 f/cm2 when normalized by the cell
area. For a 1 92-cm base, the series resistance is approximately 250 Q. This base resistanceaccountsfora
substantialportion of the series resistancefor the modified VGMJ cell. When the cells are aligned in
series, this resistance is additive and becomes significant for large arrays. If the array is used to power a
voltage driven device such as a switch, the resistance is not a problem because it does not effect the open
circuit voltage. However, if the MEM device has strict current requirements, a lower resistivity base should
be used to lower the total series resistance. The remaining series resistance is due to the contacts.
Dimensional analysis using an optical interferometer demonstrates that approximately 50% of the junction
area is contacted by the metal ink. Multiplying the remaining series resistance by the contact area revealed
contact resistivities between 7-20 mQ-cm 2. These contact resistivities are significantly lower than the
values measured in lot SCELL1. The difference in contact resistivity is because the (111) surface is
56
0
S..
S..
I-
0
I
Voltage (V)
Voltage (V)
(a)
(b)
Figure 31: The dark (a) and light (b) I-V curves for selected cells in lot VERT1. The key refers to the
dimensions of the cells in pm.
Table 4: Performance parameters for various cell areas in lot VERT1.
Cell
Dimensions
Vc
R,,i.
Ic
2
(gm)
(V)
(mA/cm )
(.)
300x300
350x350
400x400
450x450
0.54
0.49
0.56
0.51
28.50
26.94
25.19
24.44
405
330
333
424
Leakage
Current
Pout
Pin
FF
Efficiency
0.576
0.508
0.587
0.502
8.87%
6.71%
8.28%
6.26%
(mA/cm2 ) (mW/cm 2) (mW/cm 2 )
2.44
7.44
1.69
6.72
8.87
6.71
8.28
6.26
100
100
100
100
contacted rather than the (100). The densely packed 1111 } planes are more resistant to etching. When the
glass frit reaches the (111) surface, it will not be able to etch the silicon as easily as on the (100) surface.
Therefore, the silver contacts the silicon closer to the surface where the doping concentration is higher,
resulting in a lower contact resistivity.
57
As expected, the short circuit current of the cell increased with increasing cell area. However, as shown in
Table 4, the short circuit current density increases with decreasing cell area. In the vertical junction
configuration, as the area of the cell decreases, the distance to carrier collection also decreases. As a result,
the internal collection efficiency of the device is increased, causing a higher current for the same area. The
current density will reach a maximum when the cell dimensions are less than the minority carrier diffusion
length. The 300 pm x 300 gm cell has a short circuit current of 25.6 pA. Since electrostatic MEM devices
have driving currents in the nA-pA range, the cell size can be reduced and still provide the required current.
The exact cell dimensions depend on the MEM device to be powered.Although an effort was made to find
cells with low leakage currents, the leakage still dominated the cell performance. Leakage is a serious
problem for a MEMS solar array because it reduces the open circuit voltage of the cells; thus more cells are
required for the same voltage. The effect of the leakage current on the open circuit voltage is shown in
Figure 32. With increasing leakage, the V. decreases linearly with a slope of 10.3 mV/mA/cm2.
Extrapolating the trend line to zero leakage current yields a Vc of 0.572 V. Therefore, if the leakage
current can be reduced to normal levels, the open circuitvoltage of each cell would be 0.57 V. This
voltage can be increased to the desired value of 0.6 V by optimizing the implantation and anneal
parameters.
A plot of fill factor versus leakage current is shown in Figure 33. The fill factor decreases with increasing
leakage current; however, leakage is not the only cause of the low fill factors. An extrapolation of the trend
line to zero leakage yields a fill factor of about 0.6. This value can be compared to the fill factors of 0.750.8 for 50 pm planar cells. The low fill factor is due to the large distance to carrier collection. The
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0
8
4
12
16
Leakage Current (mA/cm2)
Figure 32: The relationship between leakage current and open circuit voltage in lot VERT1.
58
0.60
0.55
1
0.50
0.45
0
4
8
12
16
Iakage Current (mA/cm)
Figure 33: A plot of the fill factor versus leakage current in lot VERT1.
minority carrier lifetime for production grade silicon is approximately 100 gm. In the vertical cell, the
carriers may have to travel 300-400 gm before collection by the junction. As a result, a high level of
recombination occurs in the base and thus the fill factor is reduced. Surface traps at the Si/SiO 2 and
Si/Si 3N 4 interfaces will also enhance the recombination rate. Although low, this fill factor is still
comparable to the Chappell cell (0.63) and higher than the Lee a-Si cell (0.495).
6.3.4
Array Performance
Figure 34 shows an SEM photo of the modified VGMJ cells. The cells were series connected in sets of
three to gather preliminary data on array performance. The I-V curve of three series connected 300 pm x
300 pm cells is shown in Figure 35. The voltage of the array is determined by summing the voltages of the
individual cells at a constant current. Since the open circuit voltage of each cell is about 0.55 V, the open
circuit voltage for the array is 1.65 V. The series resistance is also additive. Dark I-V analysis reveals an
average series resistance of 330 Q for the cells, and a total resistance of 850 92 for the array. The array
resistance is slightly less than the sum of the three cells due to minor alterations in the I-V characteristics
due to string assembly.23 Since the current in the array has to be constant, the cell with the lowest current
output limits the current of the array. This effect can be seen in Figure 35. Cell #3 is the limiting diode and
the short circuit current for this cell corresponds almost exactly with the short circuit current of the array. A
benefit of this current limiting is that the leakage current is reduced. The leakage current for the 3 cell array
was 0.27 pA, an order of magnitude lower than the leakage of the individual cells. This low leakage is due
59
Figure 34: 3x1 arrays of the modified VGMJ silicon solar cell. Cell dimensions are 300x300 gm 2,
350x350 gm 2, and 400x400 gm2 .
UU-
Voltage (V)
Figure 35: The measured I-V curve for an array of three series connected 300 pm x 300 pm cells as
well as the I-V curve for each cell in the array.
60
to current limiting as well as the increased voltage for the same current. Therefore, the total leakage current
for a large array will not be a significant factor. However, the leakage across each cell will still result in a
reduction of the VO, of the cell and thus reduce the output voltage of the array.
The performance of a 7 cell array is shown in Figure 36. The open circuit voltage for this array was 3.61 V,
demonstrating that the open circuit voltage for larger arrays will continue to be additive. The I-V curve has
two plateaus in the regime of power operation. This effect occurs when cells of unequal output are aligned
in series, because the low current cells limit the current of the array. Since two plateaus are evident, there
were two current limiting cells, one with a current of 18.5 pA and the other with a current of 15.5 pA. A
similar effect is witnessed when cells in the array are shadowed from the incident light.2
i.i
I-
Voltage (V)
Figure 36: The measured I-V curve for an array of seven series connected 300 pm x 300 pm cells.
6.4
Future Design
The current design is capable of providing 80 V and 15-20 pA in a
1 cm x 1 cm array. It is important to
note that the voltage output for the array is limited by the screen printing and not the device. In order to
align the cells in a large array, the end of one row of cells must be connected to the opposite end of the next
row as shown in Figure 37. This configuration is necessary because the angular implant of the doped
regions requires that the emitter and base contacts always be on the same side of the cell. As shown in
SCELL2, the interconnects must have 250 gim lines and spaces for reliable printing. As a result, there must
be at least 750 pm between cell rows. The 350 pm width between cells also consumes a significant portion
61
r
n+
p+
350 pm
Figure 37: A schematic of a modified VGMJ array using the current 40 pm thick cells. The junctions
are implanted and the interconnects are screen printed.
of the substrate area. A more advanced screen printing system can be used to reduce both the width
between rows and the width between cells. State of the art technology can provide reliable printing with
125 pm lines and spaces. With this technology, the voltage per cubic centimeter can be increased to over
300 V. However, this technology still can not be integrated. As discussed in Section 3.3, the high
temperature firing step and the height of the print makes it nearly impossible to integrate with MEMS and
CMOS technologies.
The current provided by the 40 pm x 300 pm x 300 pm cell is an order of magnitude higher than the
maximum current required for electrostatic MEMS. As a result, the thickness of the cell can be reduced and
still provide the necessary operating currents. If the cell thickness is reduced to 6 gm, then
photolithography can be used in solar cell processing after the KOH V-groove etch. This ability to pattern
has three key advantages. First, the interconnects can be deposited with a sputter and lift-off technique and
thus the width between cells can be dramatically reduced. The cell spacing will be limited be the area
needed for corner compensation. Using a <010> compensation method, the minimum cell spacing for 6 pm
cells is 35 pm. This spacing can be reduced to approximately 20 pm if a <010>/<1 10> compensation
method is used. Second, since masks can be deposited and patterned, the heavily doped regions can be
diffused rather than implanted. With diffusion, there is no damage incurred during the doping process and
thus open circuit voltages of 0.6 V can be easily obtained. Third, the ability to pattern eliminates the need
62
to run long interconnects from one row of cells to the other as in the thick cells. Since masks can be used,
the emitter region can be on any side of the square mesa. As a result, the junction can be switched from one
side of the cell to the other and there is no need for long interconnects (Fig. 38). Cells can also be arranged
in a square around the MEM device to further minimize the area. With a thickness of 6 pm, the design
flexibility allows the cells to be very densely packed, allowing much highervoltages for the same area.
Assuming the same volume generation rate as the 40 pm cell, the 6 pm cell should produce
1 gA of current
when the cell dimensions are 150 pm x 150 gm. Using these dimensions and a cell spacing of 20 pm, the 6
pm cell has the potential to produce 2020 Vfor a 1 cm2 area. This array has a voltage over an order of
magnitude higher than the 150 V reported for a
1 cm 2 array of a-Si cells, and is not effected by the same
performance degradation or temperature limitations. To the author'sknowledge, this arrayhas the highest
voltage/areacapabilitiesof any MEMS power source reported. The fabrication of the array is also
compatible with both MEMS and CMOS processing. This process compatibility allows for the fabrication
of a power source, MEMS sensors and actuators, and controlling CMOS circuitry all on the same chip. As
a result, low cost, high functionality, autonomous systems can be designed and fabricated.
20 gm
n+
n+
p+
Figure 38: A schematic of an array of modified VGMJ cells with a thickness of 6 pm. The
interconnects are deposited with a sputter and lift-off technique and the junctions are diffused.
63
7
Conclusions
7.1
Planar Cell and Test Lots
Valuable information was obtained from the fabrication and testing of the planar cell and the four test lots.
First, the implantation and anneal used in the planar cell and subsequently in the modified VGMJ cell was
not optimized. Approximately a 0.03-0.04 V drop in V,, was attributed to damage in the heavily doped
regions. The damage can be qualified directly using a minority carrier lifetime measurement. This type of
analysis will be necessary if the implant and anneal are to be optimized. Second, the contact resistivity of
silver to the base and emitter regions on a (100) surface is 12 rmQ-cm 2 and 50 mK2-cm 2, respectively, when
the contact is fully fired. These contact resistivities are well below the critical value of 100 Mn
-cm 2 where
the fill factor begins to degrade. Third, with a screen printed metal scheme, accurate metal lines are
difficult to achieve. For interconnect lines, 250 pm is the minimum line width that can be printed with a
thickness deviation less than 10 gm. For trench filling, there is a balance between conformal sidewall
coverage and printing quality that has to be optimized. The mask width on the screen has to be less than the
trench width to prevent the ink from depositing on top of the silicon mesa, but must be large enough to
provide conformal coverage. Finally, perfect convex corners can be obtained using either <010> or
<010>/<110> compensation methods. These techniques rely on the (100) planes to undercut the
compensation structure; thus, they produce corners defined by the intersection of the { 1111 planes. If the
spacing between cells is low then the <0 10>/<1
7.2
10> method is preferred.
The Modified VGMJ Cell
A 40 pm, screen printed, modified VGMJ cell was designed and built as a hybrid power source for MEM
devices. With the dimensions used, there were no interconnects that exhibited conformal trench coverage
and left the top of the silicon cell free of metal. The best results occurred in the 350 gm trenches printed
with a metal mask line of 270 gm. The presence of metal on top of the cell led to high leakage currents, and
this leakage dominated the solar cell performance. If this leakage could be eliminated, the open circuit
voltage of each device would approximately 0.57 V. Removing all of the implantation damage with a rapid
thermal anneal would increase this voltage to 0.6 V.
The current design is capable of producing 80 V/cm 2 and a current of 15-20 pA. The voltage output for the
array is limited by the line width capabilities of screen printing and the position of the junctions due to the
angular implant. The line width can be reduced by a factor of two by using a state of the art printing
64
system; however, the design would still not be easily integrated. Since the current requirements for MEMS
operation are on the order of FA-nA, the cell thickness and area can be reduced. If the cell thickness is
reduced to 6 Rm, then photolithography can be used in device fabrication and the design flexibility is
greatly improved. For the 6 gm cell, the cell spacing can be reduced to 20 gm and thus the cell density can
be dramatically increased. Preliminary calculations reveal that a 6 gm x 150 pm x 150 gm cell would
produce a current of
1 gA. With these cell dimensions, a 1 cm x 1 cm array can produce a total voltage of
over 2020 V. This voltage is over an order of magnitude higher than any other solar arrays reported.
Furthermore, the 6 gm cell fabrication is compatible with MEMS and CMOS technologies. As a result, the
6 pm modified VGMJ cell can be used to develop small and lightweight autonomous devices capable of
performing very complex tasks.
65
Appendix A: Corner Compensation
1.
<110> Beams
A simple method to reduce convex corner undercut is to add <110> oriented beams to the edges of all
convex corners. With the beam addition, the convex corner has been made concave and thus (4111
undercutting is prevented. However, the end of the <110> beam has two convex corners that will be
laterally undercut, causing the beam to slowly etch away. The best quality of the convex corner is obtained
when the <110> beam is completely underetched at the desired etch depth. Figure Ala shows the evolution
of the etch profile for a <110> beam. When the beam is completely underetched, there is a bevel of length
L2 at the face of the corner. This effect can be reduced by using "folded" <110> strips as shown in Figure
Alb. In the folded structure the etch front is controlled by the device dimensions and the undercutting is
significantly reduced.
LLI
L2
L2
a) <110> beam
b) <110> "folded" beam
Figure Al: The structure and etch profile evolution of <110> beams (a) and folded <110> beams (b)
for convex corner compensation.
The amount of protection that a <110> strip provides can be determined by calculating the effective length
of the structure, Lff. This corresponds to the straight moving distance of an etching front along the <110>
direction when the compensation structure is completely removed. For a <110> beam, the effective length
is
66
-
1-1-1-1-7, 1,M 0151MMIRIM-1 I1M
11
P I M M IN 11"
1 - , '11 - -.,. - IMF -
-1-11-p-1 I
I,;,-.
Leff= Li +
B
(A.1)
1.2
where L, and B are the length and width of the strip respectively, and the factor of 1.2 corresponds to the
projected length of a <410> etching front in the <110> direction. For a <110> folded beam, the effective
length is
Leff = Li +1.867 * B
(A.2)
where 1.867 is geometrical term related to the effects of the end branch on the evolution of the etch.
The effective length can be related to the <100> etch depth by the following equation
Leff= H *V *1.998
(A.3)
with H = the etch depth and V = the etch ratio of the {411} and {1001 planes. The factor of 1.998 is a
result of the geometry between the <411> and <110> directions. For a 36% KOH solution, V is
approximately 1.35. To protect a convex corner to an etch depth of 50 gm in a 36% solution, the effective
length of the beam must be about 135 gm. Using equation A.2, various folded beam geometries were
designed and tested in lot SCELL3. Beam widths of 15, 20, and 25 pm were tested each with end branches
with lengths of 1*B, 4/3*B, 5/3*B, and 2*B.
2.
<110> Squares
In the <110> square compensation method, squares are added to each convex corner as shown in Figure A2.
This compensation method is very similar to the <110> beam method because it relies upon the {4111
planes to underetch the additional structure leaving the convex corner of the device relatively unattacked.
The dimensions of the square can be calculated with the same equations as the unfolded beam. Using
equation B. 1, L, and B are converted to s/2 and s respectively, where s represents the side length of the
square. With an effective length of 135 gm, s must be 101 pm for maximum compensation.
67
s
s/2
Figure A2: The structure and etch profile evolution of <110> squares for convex corner
compensation.
3.
<010> Bands
A third compensation method involves the addition of <010> bands to convex corners as shown in Figure
A3. The <010> method is particularly attractive because the structure is undercut by the (100} planes
rather than the (411} planes. This has two important advantages. First, in the temperature and
concentration range of interest there are no undefined, rough surfaces formed by (100) undercutting. As a
result, it is possible to produce sharp edges defined by the (111} planes down the entire depth of the corner.
Second, since the undercut is controlled by the same etch planes that control the etch depth, the corner
quality does not have a concentration dependence. A <010> compensation structure with a width of twice
the etch depth will produce sharp and reproducible corners defined by the (1111 planes. However, the
band must be long enough that the (100) planes reach the corner faster than the {411) planes undercutting
the band from the tip. For a KOH solution of 36%, the length of the band, L, must be at least 1.6 times
the
width, B. Therefore, the <010> structure for a 50 pm etch depth in a 36% solution must have B=100 gm
and L=160 pm.
68
.11 Im "Iml I.PPI"PI'lF W.qIRIIII0p'
B
Figure A3: The structure and etch profile evolution of <010> bands for convex corner compensation.
4.
<010> Bands with <110> Compensation
The <010> band method produces high quality convex corners, but the structure has high spatial
requirements and is not useful for situations where small device spacing is necessary. In order to reduce
this spatial requirement, Mayer et al. developed a compensation method that combines the <010> and
<110> techniques. The new structure, shown in Figure A4, relies on the idea that the { 100} etch planes that
form the convex corner do not have to be present at the beginning of the etch process. By protecting these
planes with <110> beams, the { 100) etching is delayed and thus the total length of the device reduced. The
length of the <110> beams, L2, can be calculated with the equation
L2 =
(H
B
2
)*V *1.998
(A.4)
where B refers to the width of the <010> band. The equation above is very similar to equation A.3, except
that in this case the <110> beam only has to protect to a depth of H-B/2, since the <010> beam will protect
for the remainder of the etch. In lot SCELL3, the <010>/<1 10> compensation structure had a <010> band
with a length and width of 95.5 gm and 59.7 pm respectively, and a <110> beam with a length and width of
54.4 pm and 16.8 gm respectively.
69
..
.....
............
. . . . . . ......
.
...................
..................
..
.........
....................
. . .......... .. ..
............
. . . . . . ..-
.
.
Figure A4: The structure of a <010> band with <110> beams for convex corner compensation. The
mass in the upper right hand corner represents either an outer waH or another device.
70
Appendix B: Contact Resistance Calculations
Using the Shockley Ladder technique described in Section 4.2.1, important contact resistance data can be
obtained. In a plot of voltage drop vs. line spacing, the slope can be used to determine the sheet resistivity
with the equation
RS =
Slope * Z
I(B.1)
where Z is the length of the contact sections and I is the current flowing between the two end probes. The
intercept determines the contact resistivity via the "transfer length," LT, or the characteristic distance over
which the current transfer takes place.
1/2
LT =
Intercept * LZ
IR,
(B.2)
In this equation, L refers to the width of the contact sections. Once the transfer length is calculated, the
contact resistivity can be found using the following equation:
Pc = (R, * LT2 )
(B.3)
Contact resistivity is a geometry-independent parameter and has the units of Q-cm 2.
71
Appendix C: Corner Compensation Etch Evolution
(a)
(b)
(c)
(d)
(e)
Figure Cl: The evolution of the etch profile for a <010> band compensation structure in
36% KOH
at 80*C. Etch times are (a) 0 min, (b) 11.5 min, (c) 23 min, (d) 34.5 min, and (e) 46 min.
72
(a)
(b)
(c)
(d)
(e)
Figure C2: The evolution of the etch prorfle for a <110> beam compensation structure in 36% KOH
at 80*C. Etch times are (a) 0 min, (b) 11.5 min, (c) 23 min, (d) 34.5 min, and (e) 42 min.
73
(a)
(b)
(c)
Figure C3: Convex corners compensated with the <110> beam method. (a) 15 pm beam (b) 20 pm
beam (c) 25 pm beam.
74
(a)
(b)
(c)
(d)
(e)
Figure C4: The evolution of the etch profile for a <110> square compensation structure in 36% KOH
at 80*C. Etch times are (a) 0 min, (b) 11.5 min, (c) 23 min, (d) 34.5 min, and (e) 42 min.
75
References
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Freeman J. Dyson, "21st-Century spacecraft," Scientific American, September 1995, pp. 114-117.
http://swissnet.al.mit.edu/-'switz/arpa-info/memsisat/sldO02.html
J.B. Bates, G.R. Gruzalski, and C.F. Luck, "Rechargeable solid state lithium microbatteries," in
Proc. 6th IEEE Workshop on Micro Electro Mechanical Systems, Fort Lauderdale, FL, Feb. 1993,
pp. 82-86.
H. Matsuki et al., "Implantable transformer for an artificial heart utilizing amorphous magnetic
fibers," J. Appl. Phys., vol. 64, 1988, pp. 5859-5861.
J. Lee et al. "A miniaturized high-voltage solar cell array as an electrostatic MEMS power supply,"
J. of Micro Electro Mechanical Systems, vol. 4, no. 3, Sep. 1995, pp. 102-108.
D.L. Staebler and C.R. Wronski, "Reversible conductivity changes in discharge-produced
amorphous silicon," Appl. Phys. Lett., vol. 28, no. 4, Aug. 1977, pp. 292-294.
S.M. Sze, Physics of Semiconductor Devices, John Wiley and Sons, New York, 1981.
M.A. Green, Silicon Solar Cells: Advanced Principles and Practice, Bridge Printery, Rosebury
N.S.W. Australia, 1995.
K. Wu, "Novel Etch-Stop Materials for Silicon Micromachining", Master of Science Thesis, MIT,
1997.
J.H. Smith, S. Montague, and Sniegowski, "Material and processing issues for the monolitic
integration of microelectronics with surface-micromachined polysilicon sensors and actuators,"
SPIE Vol. 2639, 1995, pp. 64-73.
J. Kawabata, H. Shi-igai, K. Yabuno, and T. Saito, "An analysis of highly viscous flow using
Imai's complex function method with application to screen printing," Fluid Dynamics Research,
vol 10, 1992, pp. 11-23.
J.T. Borenstein, "Influence of process parameters on open circuit voltage of silver fired cells,"
Mobil Solar Energy Corporation Technical Memorandum, 1988.
Ferro Electronic Materials data sheets.
J.T. Borenstein, "The silver fired-through contact: Recent discoveries and the opportunity for highefficiency cell", Mobil Solar Energy Corporation Technical Memorandum, 1989.
H. H. Berger, "Contact resistance and contact resistivity," J. Electrochem. Soc., vol 119, 1972.
C. Strandman, L. Rosengren, G Hakan, A. Elderstig, and Y. Backlund, "Fabrication of 450 mirrors
together with well-defined V-grooves using wet anisotropic etching of silicon," Jour. of
Microelectromech. Systems, vol 4, no. 4, 1995.
G. Mayer, H. Offereins, H. Sandmaier, and K. Kuhl, "Fabrication of non-underetched convex
corners in anisotropic etching of (100)-silicon in aqueous KOH with respect to novel
micromechanic elements," J. Electrochem. Soc., vol. 137, no. 12, 1990.
H. Hovel, Semiconductors and Semimetals: Solar Cells, Academic Press, New York, 1975.
J.T. Borenstein and F.C. Wilson, "Contact resistance: A simple, powerful tool for electrical
characterization and diagnostics of silver fired-through cells," Mobil Solar Energy Corporation
Technical Memorandum, 1989.
G. Shorthouse, B. Walton, "Precision printing for high density interconnections," 6 h European
Microelec. Conf. Proceedings, Bournemouth, U.K., 1987, pp. 82-6.
K. Bean, " Anisotropic etching of silicon," IEEE Trans. Electron Dev., vol25, no. 10, 1978.
P. Enoksson, " New structure for corner compensation in anisotropic KOH," Jour. of
Micromechanics and Microengineering, vol. 7, no. 3, 1997.
H. Rauschenbach, Solar Cell Array Design Handbook, Van Nostrand Reinhold Company, New
York, 1980.
76