New Architecture for USB Powered Battery
Charger
by
Hao (Steven) Zhou
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electric Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Jan 2008
@ Massachusetts Institute of Technology 2008. All rights reserved.
MASSACHUSETTS INSTITUTE'
OF TECHNOLOGY
L___
-,NOV 13 2008
........................................
Author..
rU i RA R IE S
Department of Electrical Engineering and Computer Science
e
A
January 05, 2008
Certified by.
.
.
.
...................
..
David J. Perreault
Associate Professor
Thesis Supervisor
Certified by............
...........
.........
Steve Martin
Design Engineer
Jhesis Supervisor
A ccepted by.........................
Arthur C. Smith
Chairman, Department Committee on Graduate Students
BARKER
New Architecture for USB Powered Battery Charger
by
Hao (Steven) Zhou
Submitted to the Department of Electrical Engineering and Computer Science
on January 05, 2008, in partial fulfillment of the
requirements for the degree of
Master of Engineering in Electric Engineering
Abstract
The goal of this project is to design and simulate a new architecture for a USBpowered battery charger chip. The chip is designed to be able to deliver constantcurrent/constant-voltage charge regulation to the battery when ample power is avaliable. The total power to the chip must also meet the specification of the USB port.
The chip is also required to operate at an output voltage greater than 3.6V no matter
how low the battery voltage discharges to, unless the load is so large such that the
battery is required to supply additional current to the load. Furthermore, this new
architecture is designed with improvements in both the charging efficiency as well as
USB current limit violation time.
Thesis Supervisor: David J. Perreault
Title: Associate Professor
Thesis Supervisor: Steve Martin
Title: Design Engineer
3
4
Acknowledgments
First and foremost, I would like to thank Linear Technology and Sam Nork in conjunction with MIT's VI-A program to provide me with the opportunity to work on
an extremely interesting and practical Masters of Engineering project. Furthermore,
I would like to thank Dave Simmons and my manager, Steve Martin, for providing
me with the outlines and architecture of my project and especially thank Sauparna
Das for helping me progress through the project.
I would also like to thank professor Dave Perreault for being my thesis adviser for
this project and his helpful comments during the writing of the thesis as well as his
advice at the beginning of project.
Finally, I would like to thank my parents for their support throughout my life and
my friends for shaping an enjoyable and fulfilling M.I.T. experience.
6
Contents
1
2
3
Introduction
17
1.1
Motivation For Project . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.2
O ld A rchitecture
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
1.3
New Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
1.4
O rganization
22
Gate Drive Design
23
2.1
G ate D rive Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.2
Sizing the Switching Transistors . . . . . . . . . . .. . . . . . . . . . .
24
2.2.1
Case 1: Conduction Stage
25
2.2.2
Case 2: PMOS turn off stage
. . . . . . . . . . . . . . . . . .
25
2.2.3
Case 3: PMOS turn on stage
. . . . . . . . . . . . . . . . . .
26
2.2.4
Power Loss Analysis
. . . . . . . . . . . . . . . . . . . . . . .
26
. . . . . . . . . . . . . . . . . . . ..
Dynamic Behavior of Buck Converter
3.1
4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analysis of Average Current Control
29
. . . . . . . . . . . . . . . . . .
32
3.1.1
Reason for Average Current Control
. . . . . . . . . . . . . .
32
3.1.2
Stabilizing Average Current Control . . . . . . . . . . . . . . .
33
Analysis of Integrate and Hold Technique
35
4.1
M otivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.2
Implementation of Sample and Integrate
. . . . . . . . . . . . . . . .
36
. . . . . . . . . . . . . . . . . . .
36
4.2.1
Input Current Measurement
7
. . . . . . . . . . . .
37
Error A nalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Implementation of Average Inductor Current Control . . . . .
39
4.2.2
4.3
4.3.1
5
5.1
O verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
5.2
Stabilizing Input Current Limit Control. . . . . . . . . . . . . . . . .
45
5.2.1
Analysis of Blocks of Input Current Limit Control . . . . . . .
45
5.2.2
Choosing the CLPROG Network
. . . . . . . . . . . . . . . .
48
Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . .
49
6.1
O verview : . . . .... . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
6.2
Stabilizing Constant Battery Current Loop without Lower Deck . . .
52
6.2.2
6.3
8
9
51
Constant Battery Current Control
6.2.1
7
45
Input Current Limit Control
5.3
6
Average Inductor Current Measurement
Analysis of different blocks of the constant battery current control loop without the Lower Deck . . . . . . . . . . . . . . . .
52
Analysis of Constant Battery Current Error Amplifier . . . . .
55
Stabilizing Constant Battery Current Loop with Lower Deck Regulation 56
6.3.1
Analysis of Blocks in Control Loop . . . . . . . . . . . . . . .
57
6.3.2
Analysis of the Lower Deck Regulator Circuitry . . . . . . . .
58
61
Constant Battery Voltage Control
7.1
O verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
7.2
Stabilizing Constant Battery Voltage Control Loop
. . . . . . . . . .
61
Interaction between Control Loops
63
8.1
M inim izer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
8.2
Improvement on Input Current Violation . . . . . . . . . . . . . . . .
65
67
Conclusion
A Schematics and Behaviors
69
8
B Simulation Results
83
9
10
List of Figures
1-1
Power path of the LTC4061 charger . . . . . . . . . . . . . . . . . . .
18
1-2
Block diagram for the LTC4088 . . . . . . . . . . . . . . . . . . . . .
19
1-3
Block diagram for new architecture
. . . . . . . . . . . . . . . . . . .
21
2-1
Model for the power stage . . . . . . . . . . . . . . . . . . . . . . . .
23
2-2
Logic for gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
2-3
Behavior of the switcher when the PMOS switch is fully on . . . . . .
25
2-4
Transition for PMOS switch turning off . . . . . . . . . . . . . . . . .
27
3-1
Model for a synchronous switch buck converter . . . . . . . . . . . . .
29
3-2
Block diagram for the dynamic behavior of the buck converter
. . . .
32
3-3
Block diagram for average current control
. . . . . . . . . . . . . . .
33
4-1
Sample and integrate circuit for calculating average high-side SW node
voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
4-2
Implementation for input current measurement
36
4-3
Implementation for average inductor current measurement
4-4
Matlab simulation for average input current measurement for duty ra-
. . . . . . . . . . . .
. . . . . .
tio of 0.72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5
37
41
Matlab simulation for average input current measurement for duty ra-
tio of 0.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4-6
Circuit implementation for average inductor current control . . . . . .
43
5-1
Block diagram for input current limit loop
. . . . . . . . . . . . . . .
47
5-2
Frequency response of error amplifier for input current limit loop . . .
48
11
5-3
Circuit implementation for input current measurement
. . . . . . . .4
49
6-1
Circuit representation for battery current measurement
. . . . . . . .
53
6-2
Block diagram for constant battery current loop . . . . . . . . . . . .
53
6-3
Circuit topology of bBattery current measurement with lower deck
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
6-4
Block Diagram for Constant Battery Loop with Lower Deck Amplifier
57
6-5
Circuit Implementation of the Ideal Diode Functionality
. . . . . . .
59
7-1
Block diagram form constant voltage control loop
. . . . . . . . . . .
62
8-1
Circuit implementation for minimizer circuit . . . . . . . . . . . . . .
64
A-1
Circuit for error amplifier of average current control loop . . . . . . .
69
A-2
Frequency response for the error amplifier of average current control
lo o p
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
A-3
Circuit implementation of ilinopamp . . . . . . . . . . . . . . . . . .
71
A-4
Frequency response of ilimopamp
72
A-5
Circuit implementation of PWM coniparator . . . . . . . . . . . . . . .
73
A-6
Frequency response of PWM comparator . . . . . . . . . . . . . . . .
74
. . . . . . . . . . . . . . . . . . . .
A-7 Transient response of PWI comparator
. . . . . . . . . . . . . . . .
74
. . .
75
A-8 Circuit implementation of error amplifier for input current limit
A-9 Circuit implementation of error amplifier for constant battery current
lo o p
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
A-10 Frequency response for error amplifier for constant battery current loop 77
A-11 Implementation for lower deck amplifier . . . . . . . . . . . . . . . . .
78
A-12 Frequency response for Idiode(s) . . . . . . . . . . . . . . . . . . . . .
78
A-13 Circuit implementation for battery voltage error amplifier . . . . . . .
79
A-14 Frequency response for battery voltage error amplifier . . . . . . . . .
79
A-15 Circuitry for the complete error amplifier for all three loops with minim izer circuitry
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-16 Complete high level schematic of battery charger
12
. . . . . . . ....
80
81
B-1
Response to a IA load step increase at the output w/ battery voltage
at 3.2V. Constant current charging and input current limit both set to
500m A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
B-2 Response to a IA load step decrease at the output w/ battery voltage
at 3.2V. Constant current charging and input current limit both set to
500m A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-3
85
Response to a IA load step increase at the output w/ battery voltage
at 3.2V. Constant current charging and input current limit both set to
IA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-4
86
Response to a IA load step decrease at the output w/ battery voltage
at 3.2V. Constant current charging and input current limit both set to
IA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-5
87
Response to a IA load step increase at the output w/ battery voltage
at 4.15V. Input current limit both set to 500mA . . . . . . . . . . . .
88
B-6 Response to a IA load step decrease at the output w/ battery voltage
at 4.15V. Input current limit both set to 500mA . . . . . . . . . . . .
89
B-7 Response to a IA load step increase at the output w/ battery voltage
at 3.8V. Constant current charging and input current limit both set to
lA ..........
.....................................
90
B-8 Response to a IA load step decrease at the output w/ battery voltage
at 3.8V. Constant current charging and input current limit both set to
IA ..........
B-9
.....................................
91
Response to a IA load step decrease at the output w/ battery charging
to float voltage. Constant current charging set to 500mA . . . . . . .
13
92
14
List of Tables
1.1
Percent input power loss through charge FET with 0.5A charge current
20
4.1
Percent error for average input current measurement
39
15
. . . . . . . . .
16
Chapter 1
Introduction
The goal of this Master of Engineering thesis is to design, model, and simulate a new
architecture for a battery charger powered by a Universal Serial Bus (USB).
1.1
Motivation For Project
Over the past decade, there has been a drastic increase in the number of portable devices ranging from cell phones to palm pilots to portable media players. These devices
are often powered by a rechargeable battery cell that is required to be recharged on a
regular basis. In the past, most of the charging has been done via wall outlets; however
over the past few years, more and more of these portable devices have transitioned
to using USB ports as a means to recharge their batteries. The most notable of these
devices are the portable media players that often need to be connected to a computer
in order for media files to be transferred. However, unlike drawing current from a wall
outlet, there is a specification that limits the amount of average current that can be
drawn from a USB port. In addition, in order to safely charge these batteries without
the risk of damaging the cells, it is usually common practice to employ a constant
current-charging algorithm while charging along with a constant voltage algorithm
once the battery voltage reaches a specified voltage level. Thus, a power management
integrated circuit (PMIC) is required to ensure the proper charging without violating
the USB specifications.
17
1.2
Old Architecture
PMICs that regulate battery charging via the USB port are not a novel idea in the
analog industry. One way such PMICs are designed is through the use of a linear
regulator. In this topology, the battery is connected to a source voltage through a
power MOSFET. The gate of that transistor is then controlled through error amplifiers that insure the accurate constant current and constant voltage charging behavior
of the charger. Figure 1-1 depicts a part of the block diagram of the LTC 4061 that
demonstrates the power path of the charger of the 4061.[1]
GND
PR
G
IRPROG
Figure 1-1: Power path of the LTC4061 charger
The
RPROG
resistor can be used to set the level of the constant current into the
battery, and the gate voltage of the transistors is adjusted depending on the
RPROG
resistor and the battery voltage. When the battery voltage goes up, the gate voltage
goes down, so that the FET drain-source voltage decreases such that the same current
flows through the battery. Similarly on the constant voltage side, as the battery
voltage approaches the float voltage, the gate voltage of the FET increases such that
18
constant voltage is maintained across the battery.
The main disadvantage of this topology is efficiency. When the battery voltage is
low, the charge transistor has a large voltage drop and a lot of power is dissipated
in it. Suppose the user wants to charge the battery at 500mA, Vcc is at 5V, and the
battery voltage is at 3V, then essentially 40 percent of the power is lost in the power
FET. Furthermore, the previous architecture acted solely as a charger as input power
is transferred to the battery, and since the battery could be at any voltage during the
charging cycle it could not be used to power external loads. In the new topology, the
output and battery nodes are separated by a transistor, and thus the output node
can be controlled independently to regulate at a certain voltage and supply power to
the external load.
Although there are various different architectures that employ the idea of linear
chargers., all of them share the same problems of lack of efficiency.
Due to this,
architectures for switching regulators were designed. One example of such architecture
is the LTC4088, whose block diagram is shown in figure 1-2.[2]
(
VBUS
11
SW
US
ISWITCH/N
VOUT
PWMIK AKnD
GATE DRI V E-
I
---- --
I
IDEAL
DIODE
CONSTANT CURRENT
CONSTANT VOLTAGEBATTERY CHARGER
OV
+
GATE
8
15mV
2
CL PR OG
1.188V
4
+
AVERAGE INPUT
CURRENT LIMIT
CONTROLLER
A
0.3V
-
366BAT
+ 3.6V
-
__ _
_ _
--------_
9
AVERAGE OUTPUT
VOLTAGE LIMIT
CONTROLLER
4'
Figure 1-2: Block diagram for the LTC4088
The LTC4088 has two main blocks. The first block is essentially a buck converter
that regulates output voltage, Vt,
at 300mV above the battery voltage. The reason
19
why it is 300mV is somewhat arbitrary, but it's more or less due to the on resistance of
the charge FET connecting V 0st and BAT pins, as well as the maximum programmable
current through that FET. The second block of the charger is the constant-current,
constant-voltage regulator, which essentially acts the same way as it did before in
the linear charger.
As noted, one of the main advantages of this architecture is
the fact that the voltage across the charge FET is now fixed at 300mV, which is a
huge improvement over the linear charger, and the efficiency is drastically improved.
However, one point to note with this architecture is that the output voltage can not
drop below a threshold voltage, in this case 3.6V, no matter what the battery voltage
falls to. The reason for this lower-bound (deck) threshold voltage is so that the system
load, which is powered by V 0st, will still be operational regardless of what the battery
voltage is. Thus, in the case that the battery is discharged to extremely low voltages,
there is again a significant percentage of power that is dissipated through the charge
FET; however it is still a lot more efficient than in the case of the linear charger.
Table 1-1 demonstrates the percent input power loss through the charge FET with
varying battery voltages with a 500miA programmed current.
Battery
Voltage (V)
Linear Charger
Percent Input Power
Switching Charger
Percent Input Power
2.5
3.0
2.3
2.6
2.9
Loss in Charge FET
50%
40%
34%
26%
22%
Loss in Charge FET
31%
17%
8%
8%
7%
Table 1.1: Percent input power loss through charge FET with 0.5A charge current
Even though this topology significantly improves the efficiency of the charger,
there is still some room for improvement, especially since the 300mV difference between V 0,t and BAT pins is more than what is nowhere near necessary if the programmed charge current is set at relatively low values. This issue concerning efficiency
is one of the improvements in the new architecture.
20
-
1.3
-~
-
~---.-
-
----
~---.
-
=
~
-~
=
New Architecture
The new architecture, whose block diagram is shown in figure 1-3, incorporates in
its design two significant improvements over its predecessors. As mentioned before,
one area of improvement in the new architecture is in its charging efficiency. The
way such a task can be accomplished is by connecting the gate of the charge FET to
ground thus connecting the V0st and BAT pins so that the power dissipated through
that FET is at a minimum, no matter what the level of charge current the charger
17
is programmed for. However, by doing so, the V ot and BAT pins are essentially tied
to each other via the small on-resistance of the charge FET. However, as the battery
voltage drops below the threshold voltage, the gate voltage of the charge FET can no
longer be grounded, and must be set such that the voltage at the V0st pin is set to the
threshold voltage. Essentially, the major improvement here is that when the Battery
voltage is above 3.6 Volts, the 300mV differential that was present in the LTC 4088
is no longer required.
pswitchD
VOUT
+
VREF
2R
Gate Drive
n
CLPROG
RPROG VA
RCLPCL
0
VBCOMP
+-
1.2R
IR2
Figure 1-3: Block diagram for new architecture
The second major improvement in the new architecture is the lowering of USB
current limit violation time during a transient step on the load.
21
When the user
~
-~--.4
pulls a transient step, it takes a while before the input current limit loop servos into
regulation. In that period of time, the current being pulled from the USB port may
exceed the 500mA limit that is specified by the USB port. During this transient, the
excess current that the charger demands is pulled from a 120uF capacitor inside the
USB port. Due to this, the longer the violation time, the lower the voltage at the
output of the USB port becomes. Thus, that violation time needs to be as low as
possible. Significant improvement was made in the design of the new architecture to
decrease the USB current limit violation time.
1.4
Organization
Chapter 2 describes the gate drive design for the switchers in order to size the switch
transistors. Chapter 3 delves into the analysis of the dynamic behavior of a buck
regulator and also discusses the circuitry required to stabilize average inductor current
control, Chapter 4 depicts an error analysis for the average input current and average
inductor current.
Furthermore, after the analysis for average current control along
with the error analysis, chapters 5 through 7 will analyze the design of circuitry to
stabilize the three loops of constant input current limit, constant battery current
control, and constant battery voltage control.
Lastly, chapter 9 will tie the three
control loops together and demonstrate how the loops interact with each other to
achieve the proper behavior of the battery charger.
22
Chapter 2
Gate Drive Design
2.1
Gate Drive Logic
V w
+
+
Vin
Vout
Q2
Figure 2-1: Model for the power stage
Figure 2-1 depicts the model for the power stage. Q1 is the gate voltage of the
PMOS, and Q2 is the gate voltage of the NMOS. The diodes depicted represent the
body diodes of the two switches. A non-overlapping gate control topology was used
in this architecture. Essentially, in this topology the PMOS and NMOS are never on
at the same time. Thus, logic is required to ensure that when the Q1 goes low, Q2 is
already low, and also when Q2 goes high, Q1 is also already high.
The logic of the gate drive circuitry is depicted in Figure 2-2. The SWON signal
goes high to set the PMOS switch on, and goes low to turn the PMOS switch off. As
can be noted, when the SWON signal goes high, the NGATE voltage goes low, thus
shutting off the NMOS, and only when the NMOS is completely shut off does the
23
PGATE voltage start too fall, thus turning on the PMOS. When the SWON signal
goes low, the PGATE voltage goes high first, thus shutting off the PMOS. Once the
PMOS is completely shut off, the NGATE voltage starts to rise, which turns on the
NMOS. Conversely, when the SWON node goes low, the PGATE node goes high first,
thus shutting off the PMOS; and only when the PMOS shuts off does the NGATE
voltage start to go high, thus turning on the NMOS switch.
SWON)+
PGATE
NGATE)
Figure 2-2: Logic for gate drive
2.2
Sizing the Switching Transistors
In order to correctly size the switching transistors, an analysis of power loss of these
transistors needs to be completed. There are three main sources of power loss: conduction loss, switching loss, and capacitance loss. Conduction loss is lower with a
higher W/L ratio of the transistor due to the lowering of the transistor's on-resistance.
Capacitive loss is a result of charging and discharging of transistor capacitances, thus
the smaller the devices, the less capacitance is present. In order to use the smallest possible size of the transistors, a minimum value for the length should be used.
Thus, given the available 0.6um CMOS process, the length of the switching transistors should be set to 0.6um. However, taking electrostatic discharge (ESD) into
consideration, the NMOS switcher needs to be doped with an ESD layer which is
roughly 0.3um in width. Thus, the length of the NMOS switcher needs to be 0.9um.
The power loss in the switches is analyzed through one switch cycle. Since the
switcher is typically programmed to run from 500mA to 1.5A of current through
24
the inductor, we will assume for analysis sake that an average current of .75A is
being used and that the current does not vary significantly within a switching cycle.
Furthermore, since the buck converter intends to step down 5V at Vin to anywhere
between 3.6V to 4.2V at V0s, we will assume a duty ratio, D, of 0.8 for this analysis.
f,,,
In addition, the switching frequency,
2.2.1
for this application is 2.25MHz.
Case 1: Conduction Stage
During this stage, one of the switches is fully on while the other is fully off. All of
the inductor current flows through the on switch, which essentially behaves like a
resistive device with some small on-resistance. Thus, the power loss in this stage is
dominated by conduction loss through the on switch. Figure 2-3 depicts the behavior
of the switch when the PMOS is fully on, and the NMOS is shut off.
Vsw_
..
+
Vin
Rdsp
Q2 [
Vout
Figure 2-3: Behavior of the switcher when the PMOS switch is fully on
In this case the total energy lost in one cycle in this stage is equal to:
U4i,, = D * T,.* I2 * Rdp= 2 * 10-7 * R,
2.2.2
(2.1)
Case 2: PMOS turn off stage
When the gate of the PMOS switch goes high, the switch pin voltage starts to fall
rapidly through the discharge of capacitor, C,, shown in figure 2-4. Once the voltage
at the V,,, node falls to a diode drop below ground, the body diode of the NM4OS
turns on and the current through the PMOS, Ip, goes to zero. However, during that
25
transition, there is switching loss through the PMOS due to the non-zero lp*(Ma -V,,)
product.
Once the body diode of the PMOS turns on, there is conduction loss through the
diode. However, since the diode is really on for a really small percentage of one cycle,
that loss can be ignored. Lastly, the NMOS switch turn on to complete the switching
period. Figure 2-4 demonstrates the different steps in the switching transition when
the PMOS turns off, neglecting overlap time
Even though this switching loss can be significant, the dominant power loss of this
stage can be attributed to the gate drive capacitive loss of the two switches. Thus, the
power dissipated in one of these switches in one transition is equal to what's shown
in equation 2.2 under the assumption that the gate capacitance is linear and is being
charged to 1/,.
UdssQ*gt
2.2.3
zCj
p
* V2
(2.2)
Case 3: PMOS turn on stage
When the PMOS switch is turning on, the NMOS needs to be turned off first, the
inductor current again flows through the body diode of the NMOS. Once the gate of
the PMOS goes low, current begins to flow through the PMOS, and the voltage at
the switch node rises. Again, there is switching loss due to the nonzero I * V product
across the switches but this loss is dominated by the power loss in the charging and
discharging of the gate capacitors.
2.2.4
Power Loss Analysis
The goal in sizing the transistors is to minimize the power dissipated in a cycle. The
bigger the devices, the larger the gate capacitances and smaller the on-resistance,
which increases capacitive loss but lowers conduction loss.
The total per cycle power loss in a PMOS is equal to, given L = 0.6um:
26
Ip
Cp
VW
+
Vout
In
Q2
Vin
Vinn
V§w
++
Vin
Vout
In
Vw
++
Vin
Vout
In
Rdsn
Figure 2-4: Transition for PMOS switch turning off
Uis
12Rsp+
= D * T*I*
C
*
v2
(2.3)
= 2* 10-7 *Rdp +17.5 * C
= 2
10-7
W
+ 17.5 * Cp * W * L
5.17 * 14* 6.6
+ 17.5 * 2.5 *10
W
1.55 * i0-3
- + 2.625 * 10- 4 * W
= 2
(2.4)
10-7
W
(2.5)
15 *
W *0.6
(2.6)
(2.7)
For maximum efficiency, by setting the derivative to be equal to zero, W =
27
240, OOOum
Due to the on-chip size constraints for both switches as well as the other sources
of power loss such as the power loss through the body diodes of the transistors during
switching, which increases with size and was not accounted for in my first-order analysis, I decided to size my PMOS to be 160,000/0.6, and my NMOS to be 60,000/0.9.
28
Chapter 3
Dynamic Behavior of Buck
Converter
Before designing the control system, a dynamic model of the buck converter must be
formulated. This can be done by analyzing the average model of the buck converter. [3]
This model essentially analyzes the average behavior over one cycle of the converter,
and is used to determine the transfer function relating small signal perturbations
between state variables such as duty cycle, d, output voltage,
, inductor current,
i1 , etc. The simplified circuit formulation of a synchronous buck regulator is shown
in figure 3-1.
iL
T
+
=Vout
-q(t)
Cou~t
--
Rout
Vin
Figure 3-1: Model for a synchronous switch buck converter
Assuming that q(t) is 1 when the PMOS switch is closed, and a 0 when the switch
is open, the time domain equations that represent the behavior of the buck converter
are formulated in equations 3.1 and 3.2.
29
Cout*
L *
=
at
.
&VOUT
= I
at
VOUT
L--ZR =L
(3-1)
Rout
(3.2)
(VIN - vOUT) * q(t) - vOUT * (1 - q(t))
Assuming that the local average of a variable is defined as 2(t) =-T
x('r dT,
and duty ratio as d(t). The state equation of the average output voltage and inductor
current simplifies to:
VOUT
?(-L~t
Cout * *BOfr
L
*
'uIN(t) *
L=
dI(t)
q(t)
-
vouT(0)
-
VOUT(t)
(3.3)
Rout
VIN M
OUT)
-
(3.4)
* VN(t) - VOUT(t)
The approximation can be made due to the fact that
'UIN(t)
and1 iL(t) have small
ripples and their average values do not vary rapidly. Given equations 3.3 and 3.4, we
can now analyze the small signal behavior of the buck converter by substituting the
variables with its DC and small signal components, i.e. VIN () = VIN(t)-f-hin(t), d(t)
D(t) + d(t), IL (t)
CoU *
(
aoOUT (t)
L* (aIL(t) +
(f a
L (t
at
(t)
at
+
+
=
)
L(t),
VOUT
at
and
VOUT(t)
IL
VOuT(t)
+ l(t) -
(D(t) + d(t)) (VIN(t) + i
+iout (t). Doing so, we get,
VOuT(t) + i) 0o(t
in(t)) -
(
RO(3.5)
(VOUT(t)
+
ou
0 t(t))
(3-6)
Due to the small perturbations in the small signal terms, we can ignore their
second order effects, thus equations 3.5 and 3.6 can be simplified to: [3]
30
Cout
L*
*
aVOUTt
+ Co
at
VaoUT(t)
IL (t)
-
at
t
+
-
VouT(t)
R
fCout (t)
Rout
+ILL* (t)
at
at
=D(t) * VIN (t)
(3-7)
(3.8)
+ D(t) * iCin (t) + d(t) * VIN (t) -- VOUT (t) -- iout (t)
We can then subtract out the DC portions of the signal from equations 3.7 and
3.8 to get the small signal response of the buck converter. Doing this, and assuming
that there is sufficient filtering at the input such that fsi,(t) = 0, we get:
_
Cout * aVOUT (t)
-
at
L*
ait)
- dtt)
)ut
oVut (t)
R(t
(3.9)
' out (t)
(3-10)
_~
* VIN
Taking the first derivative of equation 3.9 and substituting it into equation 3.10,
we get:
LCt
2
a
*1 OiOUT
2
Lt
L
(t)
R
*
aVOUT (t)
at+
_
out (t) = d(t)
* VIN(t)
(3-11)
Taking the Laplace transform of equation 3.11 and simplifying, we get a frequency
domain response of the output voltage to the duty ratio, shown in equation 3.12.
LCots2 y()
LiR
vo
N+
(s)
D(s)
_
*
0
+V
0
(V
St(s)=(s)
D(s)* VIN
(3.12)
LCoat-s2+L Rout8+1
Using equations 3.9 and 3.10, we can also formulate a block diagram for the
dynamic behavior of the buck converter shown in figure 3-2.
Given the block diagram. the transfer function from D(s) to It(s) can be easily
derived, and is shown in equation 3.13.
31
Figure 3-2: Block diagram for the dynamic behavior of the buck converter
I (s)
D (s)
±
VIN *
1 + sL1 *
VIN *
sRoutout
s LRoutCout + sL + Rout
2
1--
1+sR 0 ,j.jtC,
Equation 3.12 shows that the transfer function from duty ratio to output voltage
has a double pole due to the LC tank, and given variable values of load resistance
and capacitance, it becomes difficult to compensate. Thus, it is not a great idea to
use voltage control to stabilize the behavior of the buck converter. However, from
equation 3.13, we can conclude that there is a double pole and single zero in the
transfer function from duty ratio to inductor current. This makes compensating the
system a lot more manageable. This equation becomes extremely useful in determining the compensation required to stabilize the average current control loop described
in section 3.1, as well as the compensation re(Iuired to stabilize the three outer loops
as described in chapters 5 through 7.
3.1
3.1.1
Analysis of Average Current Control
Reason for Average Current Control
Due to the dynamic behavior of the buck converter shown in equations 3.9 and 3.10,
current mode control was selected instead of voltage mode control.[4] Current control
has the benefit of the extra zero it adds to the transfer function from duty ratio to the
control signal. Furthermore, in order to eliminate slope compensation problems that
arise with peak current mode control, average current mode control was selected.
32
~
±~ GU~s
1/N
H(s)
U
Figure 3-3: Block diagram for average current control
3.1.2
Stabilizing Average Current Control
Figure 3-3 depicts the block diagram for the average current control loop. f, is defined
as the command inductor current, and i0 t be the actual inductor current.
is defined to be
'*s
(equation 3.13).
Gacc(s)
H(s)
represents the transfer
function from the error signal (between the command inductor current and the actual
inductor current) to the voltage signal controlling the duty cycle of the buck converter.
Dividing that signal by the peak voltage, Vm, of the ramp signal determines the duty
cycle.
Gacc(s)
can be implemented using some amplification stage to minimize error
along with the correct internal compensation network to ensure loop stability. The
actual circuit implenentation of this stage will be discussed later in this section, but
before doing so, analysis of the poles and zeros of the H(s) function must be carried
out.
The frequency response of the average current control loop needs to cross over
with reasonable phase margin at a frequency below a quarter the switching frequency
in order for the average circuit model calculations to remain valid. With the switching
frequency of this application being 2.25Mhz, the frequency response of the loop gain
needs to crossover before roughly 600KHz for all modes of operation and all load
conditions.
Analysis of H(s)
H(s) = gtRicCOUo'
VI N 1
+R"o
geometric mean of
, and it has a zero at
1C~t
33
and two poles that have a
u
twoepolesnt hatfave.
This means that at high frequencies, there is a fixed level of attenuation, with
20dB/dec roll-off. Thus., at the desired crossover frequency of 600 KHz, the gain from
the zero will be roughly 600Khz * 27 * Rst * C0st and the attenuation from the two
poles will be roughly (600Khz * 27 * VL *Cost.
Thus, the total gain at 600 KHz due to H(s) is approximately equal to
K.
Ro
t
600Khz*2*R,,t*Cnt
(60OKhz*2r*v L*eCout)
_
V7,
Rout*
Rot
600Khz*2-i*L
(3.14)
600Khz*2n*L
Since the battery charger is powered by the USB port, Vi, is equal to 5 volts,
and typical battery chargers in industry use an inductor size of 3.3uH. With these
numbers, it can be calculated that
H(s)|s=2,*600KRad
0.4
Analysis of Gacc(s)
In order to cross over at 600 KI~z,
Gacc(s)
needs to have a gain of approximately 6 at
600 K1Iz for V = 2.5V. Vm, was chosen to be 2.5V because it allows for 100% duty
ratio and it is high enough so that the Vdaty value has a sifficient dynamic range.
Gacc(s)
also cant contribute too much negative phase around the crossover frequency
due to the fact that there is already a pole in the system from H(s) that contributes -90
degrees of phase. Thus, a feasible implementation for Gacc(s) would be to use pole-zero
compensation at the output of a high gain GM-Amp. Implementing this technique
will allow for a constant gain around the crossover frequency without the addition of
too much negative phase. As seen in appendix A, the amplifier was designed using
the principles of a current mirror amplifier with a pole-zero-pole compensation at
the output.
The resistor RI sets the high frequency gain of the amplifier around
the crossover frequency of the average current control loop. In appendix A, Figure
A-1 shows the circuit implementation, and figure A-2 demonstrates the frequency
response of the amplifier. It can be seen that at the frequency around crossover, the
gain of the amplifier is roughly 12dBs with very little negative phase, which is the
desired behavior.
The means for measuring the current and for implementing the
current control are described in the next chapter.
34
Chapter 4
Analysis of Integrate and Hold
Technique
4.1
Motivation
A integrate and hold circuit is useful in tracking the average of the input voltage when
the input is connected and holding that average when the input is disconnected. [5]
Such a technique is extremely useful in measuring the input current as well as the
inductor current.
In measuring both the input current and inductor current, the
average SW node voltage when the PMOS switch is on needs to be first determined.
Once found, the inductor current is equal to the supply voltage minus the average
high-side SW node voltage divided by the on-resistance of the PMOS switch. The
input current is then equal to the inductor current multiplied by the duty ratio. The
sample and integrate circuit shown in figure 4-1 demonstrates how the average highside SW node voltage can be calculated. When the PMOS switch is on, transistor
MP2 is turned on and the voltage on the SWAVG node is integrating to the correct
value through the RC network. When the PMOS switch is off. MP2 is turned off and
the voltage at the SWAVG node is held. Transistor MP4 is added to reduce the error
of the sample and integrate circuit by sinking the gate charge from MP2 as MP2 shuts
off. thus reducing the parasitic charge flow into the capacitor during transitions.
35
-
MAXDRV
20P-
T
C2
Figure 4-1: Sample and integrate circuit for calculating average high-side SW node
voltage
4.2
Implementation of Sample and Integrate
Even though the sample and integrate technique is used in both measuring the input
current and inductor current, there is a significant difference between the two. The
reason for this is because the input current switches to zero as the PMOS switch is
turned off, thus making the current discontinuous, whereas the current through the
inductor remains continuous.
4.2.1
Input Current Measurement
VBUS
ONEAMP
8
PGATE:_
ONEAMP
TENTHAMP
'ENTHAMP, TENTHAM
,G5
4MW
VSAMPLE
SAMPLE
zH
0
VCLPROG
Figure 4-2: Implementation for input current measurement
Figure 4-2 demonstrates the implementation for input current measurement. MP1
and MN1 are the power switches for the buck converter. The SW node is a pulsing
signal that goes roughly between ground and VBUS every switching cycle. VGSH
is the control signal for the switch that connects the SW node to the RC network
36
when MP1 is on. The reason for the input current measurement circuit is to extract
out the average voltage on the SW node when the SW node is high, and hold that
average value when the SW node is low. That average voltage then servos the drain
voltage of MP2 through a high gain amplifier. Furthermore, MP2 is sized to be a
ratio, a, times smaller than MP1, thus the current flowing through the sense FET
(MP2) is approximately a times smaller than the average current flowing through
MP1, when the SW node is high. The value for a is set depending on whether or
not the input current regulation is .1 amp, .5 amp, or 1 amp. In .1 amp mode, the
input signal TENTHAMP is high and ONEAMP is low and a is set to be 200; in .5
amp mode, both the input signals are low and a is set to be 1000; and lastly, in the
1 amp mode, the signal TENTHAMP is low and ONEAMP is high, and a is set to
be 2000. The reason for the variable ratio in the three different mode of operation
is because the voltage at the VCLPROG node will be servoed to be 1.2V while the
loop is in regulation with a fixed RC network at the VCLPROG node. Lastly, the
VSAMPLE signal controls the switch between the drain of MP3 and the RC network,
and only connects the two when IP1 is high. This modulates the measured current
by the duty ratio, d. thus the input to the negative terminal of the OPAMP does
not fluctuate rapidly. Doing so ensures a fairly accurate measurement of the input
current.
4.2.2
Average Inductor Current Measurement
Figure 4-3 depicts the circuit representation of the average inductor current measurement.
This circuitry is somewhat similar to the average input current circuitry in
that it still attempts to find the average voltage of the SW node when the SW node
is high. It also servos that average voltage onto the drain of MP2. However, in this
case, MP2 is sized to be exactly one thousand times smaller than MP1.
Thus, the
current through MP2 is roughly one thousand times smaller than the current flowing
through the inductor. That sense current is then amplified through a 1KQ resistor
in order to extract out the average inductor current in terms of a voltage, which can
then be used in stabilizing the average current loop.
37
PGATE
440/0.9
1500
MP2
S
MP3
1K
Figure 4-3: Implementation for average inductor current measurement
4.3
Error Analysis
The bigger the RC time constant in the sample and integrate circuit, the more precisely the input signal can be tracked. However, the RC product can't be too large
because it adds an extra pole in the frequency response. Thus, R was picked to be
11667Q and C to be 20pF, which results in a pole beyond the crossover frequency of
the loop. Unfortunately, this leads to significant error in tracking the average input
current. Ideally, the exact average voltage of the SW node when the SW node is high
can be extracted. However, as the RC product decreases, the averaging node, between
the resistor and the capacitor actually tries to track the slope of the SW node more
and more. Thus even though there is no cumulative error during the sampling phase,
the error during the hold phase is drastically increased as the RC product decreases.
This behavior is demonstrated in MATLAB simulations shown in figures 4-4 and 4-5.
The error is analyzed under varying RC products, average inductor currents, and
duty ratios, and is depicted in table 4-1. The percent error is calculated to be equal
to 100
,,t.a-SWAVGiesr.ed.
* SWAVGSWAVG~i-de
The reason for picking duty ratios of .72 as the
lower bound is because when the battery voltage is low, the output node needs to be
at 3.6V which is .72 of VBUS.
As expected, the lower the average inductor current, the worse the error gets due
Percent Error
Inductor
Duty
Current (A)
Ratio
0.20
0.72
0.50
0.72
1.00
0.72
0.20
0.84
0.50
0.84
1.00
0.84
C=l0OpF
C==20pF
C=1pF
1.59
0.64
0.32
1.27
0.51
0.25
7.72
3.09
1.54
6.10
2.44
1.22
32.3
12.9
6.46
22.4
8.95
4.48
Table 4.1: Percent error for average input current measurement
to the fact that the average SW high voltage is closer to the VBUS voltage thus a
smaller deviation due to error causes a higher percentage error. A lower duty ratio
also leads to higher error because the hold period of the sample and integrate is
increased, where a constant error is present. However, looking at the numbers in the
case of using a 20pF capacitor, the worst case error present is roughly 8%. This 8%
error can be more or less eliminated by trimming the sense FET MP2 to an optimal
size.
4.3.1
Implementation of Average Inductor Current Control
Figure 4-6 depicts the circuit implementation of the average inductor current control.
As described in section 4.2.2, the VGSH signal is used to control the connection
between the switch pin and the RC circuit. MP2 acts as the switch transistor and
MP4 is sized to be half the size of MP2 to alleviate error due to the charge dump
when MP2 turns off. The ilimopamp is a high gain amplifier with a DC gain of 10000
and a unity gain crossover frequency of roughly 12 MHz. The circuit implementation
of this amplifier is shown in figure A-3, and its frequency response is shown in figure
A-4 of appendix A. Given the proper behavior of the ilimopamp and the sample and
integrate circuitry, the voltage at node VAOC is equal to 1Q multiplied by the inductor
current. That voltage then gets compared to a command current, represented as an
input node, Vc, to generate an amplified signal that determines the duty voltage.
That voltage is then compared to a PWM waveform to generate the duty ratio of
39
the converter. The circuit implementation of the comparator is shown in figure A-5
of appendix A. The frequency response of the comparator, figure A-6 of appendix
A, shows the high gain feature of the comparator and figure A-7 shows that the
comparator has an approximate delay of 13ns, which is sufficiently fast.
40
Average of SW Node, R=1 1667, lo=0.2, D=.72
0
5.01
Actual Voltage
-- C=100pf
C=20pf
5
~-
0
> 4.99
-
-
-
-
C=lpf
--------
-
c4.97
<> 4.96
0.5
0
1
1.5
2
2.5
3
time (sec)
3. 5
X 10-7
Average of SW Node, R=11667, 1o=0.5, D=.72
5
Actual Voltage
- - - -- ---------C=100pf
C=20pf
C=lpf
.
CO4.99
0
4.98
.
-
.
.........
.....
...
...
...
... .
0
4.97
'
Ca
(D
4.96
0
0.5
1
1.5
2
2.5
3
time (sec)
3. 5
X 10-7
Average of SW Node, R=1 1667, 10=1, D=.72
. 4.97
Actual Voltage
0
4.96
4.
-----
...........
> 4.95
.....
.
C=10p
..........--.C =2 0pf
--C=1pf
------
............
0
.~4.94
<~ 4.92
U
0.5
1
1.5
2
time (sec)
2.5
3
3.5
X 10-7
Figure 4-4: Matlab simulation for average input current measurement for duty ratio
of 0.72
41
Average of SW Node, R=1 1667, lo=0.2, D=.84
0
o
5.02
Actual Voltage
C=100pf
----
C=2Opf
-C=1pf
55
7
a 4.98 F
.
------- ----
......
...
.
............
cc
4.96
0
0.5
2
1.5
1
3.5
3
2.5
time (sec)
4
x 10'
Average of SW Node, R=1 1667, Io=0.5, D=.84
> 5.02
Actual Voltage
-------- C=100pf
- -..............
C =20pf_
------C=1pf
cc
o
5
C/)
o) 4.98
T 4.96
0
0.5
2
1.5
1
3.5
3
2.5
time (sec)
4
x 10-
Average of SW Node, R=1 1667, 1o=1, D=.84
0 4.98
I
II
I
' 7
0)
CD
0
4.96
..
~~~ ~~
...
......
_
Actual Voltage
--------- C=100pf
C=20pf
- C=1P
-
.. ...............
4.94
4.92
0
0.5
1
1.5
2
time (sec)
2.5
3
3.5
4
X 10-7
Figure 4-5: Matlab simulation for average input current measurement for duty ratio
of 0.84
42
MAXDRV
(n
6
MP1
40/0.6
+
MP2
21.6
20P
C2
SWAH2
1
>
-MP4
c ilimopamp
VG
1220.6
12099
VGSB
1.
+
SWA
/VTEST
0
250U
MAXDRV
c_gmamp
-7
R3
VPWMVDUTY
+IWM
OMP
C-pwmcoM
MAXDRV
C1
SGacc
Figure 4-6: Circuit implementation for average inductor current control
43
44
Chapter 5
Input Current Limit Control
5.1
Overview
Since the chip is powered by the USB port, there must exist some circuitry to control
the amount of current the chip draws from the USB port. Thus one of the major loops
that control the command inductor current is the input current limit control loop.
In a typical application, the USB port is able to supply a DC current of 100mA or
500mA due to the USB specifications. However, it is possible that in some situations
the chip might want to be programmed to pull as much as IA or more from the power
source; thus, all modes of operation is also supported by this chip.
5.2
Stabilizing Input Current Limit Control
5.2.1
Analysis of Blocks of Input Current Limit Control
Given that the average current loop has a cross over frequency of 600 KHz, the
frequency response from the command current node, V, to the actual inductor current
has a DC gain of roughly 1-
with a pole at 600KHz. Thus, in order for that pole
to have a minimal effect on input current limit loop, the loop should cross over
at a frequency below 200 KHz under all operating and load conditions. In a buck
converter,
45
iIN
d*
(5.1)
iOUT
Substituting the signals with its nominal and small signal components and eliminating the product of small signal components, we get:
IIN +
= D * IOUT +
in
(5.2)
* IOUT + D * out
Subtracting out the nominal portions from equation 5.2, we can get an expression
for the small signal response for the input current, shown in equation 5.3.
t
in =OUT *
d + D * tout
(5.3)
The input current then gets scaled down by a depending on the mode of operation
and passed through the RC network of the sample and integrate circuit, which is
modeled by the transfer function of SI2 i(s). Given our method of sizing the resistors
and capacitors of the RC network, we can approximate SIic (s) to be unity gain for
frequencies below the cross over frequency, and thus can be ignored.
Since there
are three different modes of operation, lOOmA, 500mA, and IA input current limit
criteria, a can vary between 200, 1000, and 2000.
The scaled down input current then needs to be passed through another RC
network, CLP(s), in order to convert the sense current back to a voltage in order for
it to be regulated. The difference between that voltage and a fixed bandgap voltage
(1.2V) then gets amplified to produce the command signal v,. The RC network is
thus designed to have a resistor in parallel with a capacitor. The resistor size is set
to be 2.4K due to the sense current of 500uA and the reference voltage of 1.2 volts.
The complete block diagram for the input current limit loop is shown in figure
5-1.
Before the analysis of the entire loop can be made, we must first formulate the
transfer function from i~c to d. Applying black's formula on the block diagram we get
the result in equation 5.4.
46
V
3-:Gapogs)G.,,(s)
Vyg
1No,
CLP(s)
- H(S)-
S lid(s) (""
/
Figure 5-1: Block diagram for input current limit loop
_
5c
/V m*Gacc(s)
1+
/Vm*Gacc(s)*H(s)
1*
-
H(s)
Since e
(5.4)
/V*Gacc(s)*H(s)
1+ /Vr*Gacc(s)*H(s)
H(s)
fc
is essentially 1 for frequencies less than the cross over frequency of the
input current loop, we can simplify equation 5.4 to:
d
1
s 2 LRoutCou + sL + Ro(t
H(s) ~ -Vi, (sRoutCout + 1)
Thus, at high frequencies,
f, the
transfer function will have a 20dB/dec gain, and
the gain will be equal to what's shown in equation 5.6.
Rot
V,,
Rout *f *27*L
f * 27r* VT * Cout)
f * 2-F * Rout * Cot
V,
f *2*L
Rout
(5
Given the inductor size of 3.3uH, and an input voltage of 5 volts, the transfer
function has a unity gain at roughly 200 KHz, and +20dB/dec
gain.
Thus, we
can simplify the transfer function from the duty ratio to the input current to be
approximately that shown in equation 5.7 at frequencies around the desired cross
over frequency of the input current loop.
= D * out+
yec
VC
Iout *
vc
47
D + Iout * 8 * 10- 7 s
(5.7)
We would like the DC gain from iin to ic to be at least 200 in order to reduce
the error between the command input current and the actual input current. Since
there are three different modes of operation, we want to design the error amplifier,
Gcprog(s), to have variable gm, so the gain around the cross over frequency is different
for each mode of operation given the same RC compensation network at the output.
The error amplifier, whose schematic is shown in figure A-8 of appendix A, was thus
designed to have the frequency response characteristics shown in figure 5-2.
5.2.2
Choosing the CLPROG Network
32M8
-40*
OdB
-120*
-so,
-1dB
-32dS
100mHz
1Hz
10Hz
11)0Hz
1KHz
10KHz
00KHz
-100'
-200-
IMHz
10MHz
54dB
-20*
18dB
-8O'
0d0
-18dB
100mHz
-110
.440'
1*
10Hz
100Hz
1KHz
10KHz
lOOKHz
1ONIz
1IM*
60da
IA
0,I
4$48
.30*
24dB
-7W
12690
OdB
-12dB
10,MHz
1Hz
10Hz
100Hz
IKHz
10KHz
100KHz
IMHz
110'
-130'
10MHz
Figure 5-2: Frequency response of error amplifier for input current limit loop in all
three modes
Given this, we have a fixed gain of roughly 5.9 * 10-
* CLP(s) from ii, to ic
through the feedback branch and the amplifier stage. The upper limit for the gain
from , to zi, in the forward loop at 200 KHz is D + Iout *8* i0- * 27r * 200KHz < 2.
48
Thus, we want the CLPROG network to have a pole at roughly 7 KHz with its DC
gain of 2400, such that the loop will cross over at the desired 200 KHz. Thus the
capacitor size is required to be at least 1OnF. To be on the safe side, the capacitors
were sized to be 20nF to ensure a loop cross over frequency below 200 KHz.
Note that the zero in the transfer function from
c
to zi, varies, but in the worst
case, when its zero is at its lowest frequency, the entire loop still crosses over at 200
KHz. Also, if the zero of the transfer function from i9c to Zi
actually occurs at a high
frequency beyond 200 KHz, the zero at roughly 30 KHz in the Gciprog(s) network
improves the phase margin of the loop transfer function.
5.3
Circuit Implementation
1A
ICL
100mA
ICL
2
20
MP3
MP2
40/0.6
40/0.6
500mA
ICL
MAXDRV
4
'MP1£
40/0.6
MP
+
VGSR
2/0.5
SWAH4_2__
20P
1
+
C1T
-
VG
MP4
120/0.6
c-limopamp
+
-
MN2
30/0.6
1
MP5
474.4/.6
SWA
MP7
1/0.6
V
EST
_____
1
CCLPROG
25N
RLPROG
24
Figure 5-3: Circuit implementation for input current measurement
The circuit implementation of the input current measurement is shown in figure
5-3. As described in section 4.2.1, the voltage at the SWAH3 node is averaging the
49
on voltage of the SW node when the PMOS switch is on, and holding the value when
the PMOS switch is off. That voltage is servoed to the SWAH4 node through the
high gain amplifier cilimopamp.
Depending on the modes of operation, MP1, MP2, and MP3 are controlled to set
the ratio, a, between the PMOS switch and the sense transistors. This is done so
that the nominal current flowing through MP4 in all three modes of operation is the
same. The VSAMPLE input is then used to control the switches MN1, MN2, and
MN3, such that the current flowing down MP4 is shunt to ground when the PMOS
switch is off. Thus, the current flowing through MN3 is equal to the current flowing
through MP4 multiplied by the duty ratio of the converter. This current is therefore
the input current divided by alpha.
Since a is proportionally set in the three diffirent modes of operation, the noniinal current flowing through RCLPROG is equal to 500uA independent of mode of
operation, thus making the nominal voltage at the VCLPROG node 1.2 volts when
the control loop is in regulation.
50
Chapter 6
Constant Battery Current Control
6.1
Overview:
The batteries used in the application of the chip are typically made of Lithium Ion
cells. Even though battery charging can be done by simply feeding current into the
battery, the life of the battery is drastically shortened if there is no regulation on the
amount of current being fed into the battery or of the final float voltage. For Lithium
Ion batteries, a typical charging system is considered to be CCCV (constant current
constant voltage) charging. In such a system, the battery is charged with a fixed
current, usually determined by the battery size, until its reaches a float voltage, at
which point the charger enters its constant voltage phase where the current flowing
into the battery tapers off in order to maintain a constant voltage at the battery
node.
In addition to maintaining a constant charging current into the battery until the
float voltage is reached, it is also required for this application that the system output
voltage be maintained above 3.6V regardless of how low the battery voltage is. The 3.6
volts is considered to be the lower deck voltage, and circuitry is required to maintain
the output voltage to be a minimum of 3.6 volts regardless of the battery voltage.
The first part of the constant battery current control analysis will focus on maintaining constant current assuming that the battery voltage is above the lower deck
voltage. The second part of the analysis will demonstrate the effect the lower deck
51
circuitry will have on stabilizing the constant battery current control.
6.2
Stabilizing Constant Battery Current Loop without Lower Deck
6.2.1
Analysis of different blocks of the constant battery current control loop without the Lower Deck
The current through the inductor gets split into two branches, part of the current
flows into the battery to charge it, while the rest flows through the output node to
power the load device. For simplicity, the external load at the output is modeled to
be a resistor in parallel with a capacitor. Typically, the load capacitance of the device
is at least 1OuF due to the capacitance of an external device that is being powered by
the charger as well as any additional capacitance the user adds for output filtering.
In the battery branch, the output node is connected to the battery through an
internal power transistor. This transistor is sized to be 120K/.6 in order for it to have
a sufficiently low on resistance while not taking up too much space on chip. In the
case when the battery voltage is above the lower deck voltage of 3.6 volts, the gate of
the transistor is grounded to ensure minimum power dissipation through the device.
Furthermore, the Lithium Ion battery is modeled as a small resistor in series with a
huge capacitor.
The amount of current flowing through the battery then gets measured by a sense
transistor that delivers one thousandth of the battery current. That current is then
converted into a voltage by a resistor the user sets at the VPROG node. Thus, when
the servo loop is complete, the programmed constant battery current is equal to the
reference voltage (1.2V) divided by the RPROG resistor multiplied by 1000. The user
may choose to charge the battery at anywhere between 500mA and 1.5A, thus the
resistors they use will range from 2.4KQ to 0.8KQ respectively.
The outlining schematic for the output load as well as battery current measurement is shown in figure 6-1. The IBCGMAMP node is used to better compensate the
52
entire loop gain, and will be discussed later in this section.
MAXDRV
RLOAD
>
1
3000
11000
CLOAD
0IU
VGATE
BATGATE
RBAT
1
RPROG
2K
CBAT
100
Figure 6-1: Circuit representation for battery current measurement
The difference between VPROG node voltage and the reference voltage is then
amplified through an error amplifier which outputs the voltage for the command
current. The transfer function of the error amplifier is represented by Gprog(s). The
complete block diagram for the constant battery-current loop without LD regulation
is shown in figure 6-2.
VfG,
.isi
H1s
J
Load(s3)
Figure 6-2: Block diagram for constant battery current loop
Once again, we would like the constant battery current loop to have a cross-over
frequency lower than 200 KHz. Thus, in the frequencies of interest,
the high frequency cross-over of the minor loop.
53
= 1, due to
Load(s) =
sRoutCload + 1
*
Rioad
Rioad + Ronmp2 + Rbat
(6.1)
where,
Rout = Rload// (Ronmp 2 + Rbat)
and 1/
(6.2)
is fixed to be 1/1000 in this loop.
What makes this loop slightly difficult to compensate variations in the load resistance, load capacitance, battery resistance, and PROG resistor. We must first
analyze the range of variation in these variables before designing the error amplifier,
GPROG(s) and its compensation network.
In order for the battery current loop to be in regulation, there can not be a huge
load at the output. If such a load existed, then the constant input current limitation
loop will be in charge of current regulation. The extreme case is where the input can
supply 5 watts of power (1A input current limit conditions) and the user programs
for 500mA of battery charge current, while the battery is at 3.6V. Thus, there can
be a maximum of 3.2W of power into the load while still having the constant battery
current loop be in regulation. 3.2W of power at 3.6 volts translates to a minimum
load resistance of 4Q. Since it's possible for the external load to draw no power from
the output node of the charger chip, the load resistance at the output node could
be infinitely large. The equivalent load capacitance can also vary quite a bit, but in
general it is between lOuF to 1OuF.
The internal battery resistance varies with each individual battery, but is typically
around .05 to 0.2 ohms.
Ronmp 2 is typically equal to .07Q given the size of the
transistor, thus making the resistance looking down the battery branch approximately
.12 Q to .27 Q. Lastly, the PROG resistor, as mentioned before, can vary between
0.8KQ to 2.4KQ.
Given the relative sizes of Road to Ronmp2 and Rbat, the Load(s) transfer function
can be simplified to Load(s) =
S(Ro1-2Rba)CI
, thus the pole location of the
transfer function can vary anywhere between 6 KHz in the high internal battery
54
resistance and high load capacitance case to 130 KHz in the low battery resistance
and low load capacitance case.
The DC gain of the loop from kc to i
prog
also varies from 0.8 in the 1.5A charge
mode to 2.4 in the 0.5A charge mode. Thus, an error amplifier needs to be designed
such that acceptable operation is achieved under all varying DC gain settings and
load pole frequencies.
6.2.2
Analysis of Constant Battery Current Error Amplifier
In order to reduce the error between the command battery current and the actual
battery current, a high gain amplifier is needed. The amplifier was designed to have
a DC gain of roughly 150.
In one extreme case. where the DC gain from , to
load pole is at 130 KHz, the gain at 200 KHz from Oc to
'&pog
is equal to 2.4 and the
p,,og is equal to roughly 1.6.
Thus, the gain of the amplifier at 200 KHz must be lower than 0.67.
In the other extreme case, where the load pole is at 6 KHz, and the DC gain from
vc
to vprog
is equal to 0.8, the gain of the amplifier should be greater than 1.25 at 6
KHz in order to ensure that the loop does not cross-over at a frequency lower than
that of the load pole.
As long as the condition is met such that the gain of the error amplifier is greater
than 1.25 at 6 KHz, and less than 0.67 at 200 KHz, the cross-over frequency of the
entire loop will be guaranteed to be between 6 KHz and 200 KHz, with at worst a 90
degree negative phase contribution from the load transfer function. Thus, as long as
the error amplifier does not contribute more than 60 degrees of negative phase at any
frequency between 6 KHz and 200 KHz, the loop gain will cross-over with sufficient
phase margin.
A slight adjustment of the circuit was made to further improve the phase margin
of the circuit. The idea behind the improvement is that when the battery charge
current is programmed to be high, the entire gain from tc to Vprog decreases, thus
the error amplifier can have a higher high frequency gain, which can be accomplished
by supplying the amplifier with more bias current.
55
Essentially, the IBCGMAMP
~-
node from figure 6-1 can be connected to a current mirror in the error amplifier to
supply the error amplifier with more tail current. The reason for this circuitry is to
decrease variation in the high frequency gain of the loop under different charge current
conditions. Thus, we narrow down the range of possible cross-over frequencies of the
loop transfer function and a more precise compensation circuit can be employed to
improve the phase margin of the loop.
The circuit implementation of the constant battery current error amplifier and its
frequency response are shown in figures A-9 and A-10 of appendix A.
6.3
Stabilizing Constant Battery Current Loop with
Lower Deck Regulation
If the battery voltage is too low, we need to maintain the lower deck voltage of 3.6
volts at the output node, given the user-determined constant charge current. A means
to maintain the lower deck voltage at the output given a constant charging current is
for the gate of MP2 in figure 6-1 to no longer be tied to ground. By controlling that
gate voltage, the drain to source resistance of MP2 can be adjusted to the appropriate
level. Thus the topology of the battery current measurement and output load with
the lower deck considerations is shown in figure 6-3.
MAX DR V
0
BATGATE
-
CLOAD
MAXDRSRLOAD
VGATE
.
<VBAT,
3-2
40/.
VBATBA
V
VOUT
+
RPROG
2 4K>0
RBAT
CA
g
o0
Figure 6-3: Circuit topology of battery current measurement with lower deck circuitry
56
-~
Analysis of Blocks in Control Loop
6.3.1
Since the lower deck amplifier controls the gate voltage of the charge FET, it also
controls the gate voltage of the battery current sense FET. Thus, by changing the
gate voltage, additional small signal change to the battery sense current are added.
The block diagram for the entire loop is shown in figure 6-4:
'II
+I~±
G~( G~~,
kZ21e
H~)
iNd
Figure 6-4: Block Diagram for Constant Battery Loop with Lower Deck Amplifier
The load impedance may be modeled as:
LIRout
Load(s)
Ron
s~u~u
+ 1
CC
sRou~tCout + i
Road
Rtoad + Ron
(6.3)
where
Rout =: Roadj/ (Ronmp2 + Rbat + Rbat ) ~ Rload// (Ronmp2 + Rbat )
(6.4)
The reason why the approximation can be made is that when the lower deck
amplifier is in regulation, the drain to source resistance of the charging FET, MP2,
is quite large compared to the battery's internal resistance.
We can further conclude that:
,bsl
2
out
_
1
sRo
0 tCu
*
+ 1
1
Rioad
Road
=
+ Ron
b~s2
Ron
tout
sRout Cou + 1
-*
1
s R0 utCat + 1
R*oad
Road + Ron
57
Rioad
R*
Rload +
R0 n
* Idiode(s) * gm(sense)
*
1
1000
(6.5)
(6.6)
since the sense FET is 1/1000 the size of the charge FET, Ron
*
gm(sense)
is equal
to 1/1000 Therefore,
1Rload
=____
_
_
*
sRout Cot + 1
iout
Zbs2
__
*
Road +
Ron
1
* Idiode(s)
(6.7)
1000
Essentially, in order for the battery current loop to remain stable, we need to
design Idiode(s) such that it has high DC gain, and has a dominant pole at a low
enough frequency such the transfer function has a cross-over frequency lower than
the cross-over frequency of the constant battery control loop. If that condition can
at the cross-over
be satisfied, the magnitude of 4 is much smaller than that of N
70'at
Zout
frequency, and thus the right hand branch of the block diagram would be insignificant
and can be ignored leaving us with the block diagram much similar to the one in figure
6-2 for when the lower deck circuitry was not required. The only difference in this
case is that the load pole can actually occur at a much lower frequency due to the
higher R,, resistance. In the extreme case, the battery might go as low as 2.7 volts,
which leaves a voltage drop of 0.9 across the drain and source of the charge FET,
MP2. If we are regulating at the minimum Current of 500mA, it leads us to conclude
that the largest drain to source resistance of MP2 is equal to 1.8Q. Thus, the lowest
frequency for the load pole is now at 900 Hz. Looking at the frequency response of the
error amplifier in figure A-9 of appendix A, we can conclude that under the lowest
gain conditions (1.5A programmed battery charge current), the loop gain transfer
function will still cross-over at a frequency beyond 6 KHz. Thus, given that, as was
shown in the case of no lower deck voltage regulation considerations, the constant
battery current loop will be stable and cross-over with sufficient phase margin.
6.3.2
Analysis of the Lower Deck Regulator Circuitry
The transfer function for out to
EOgate,
Idiode(s), needs to be designed in such a way
that its transfer function will reach unity gain before the cross-over frequency of the
loop. The ideal diode not only must have the important property of setting the gate
voltage of the charging FET to the appropriate value in order to maintain a 3.6 volts
58
output when the battery voltage is low, but it must also be able to quickly discharge
the gate voltage to ground when the load actually needs to draw current from the
battery in the case when the power limitation at the input is less than the power
needed at the load. Under that condition, the battery is actually supplying current
into the load, and the output voltage is set to be regulated at 15mV below the battery
voltage. Lastly, the ideal diode circuitry must have the functionality that when the
battery voltage is above 3.6 volts, which leads to the output voltage to be greater
than 3.6 volts, the gate voltage of the charge FET needs to be grounded to ensure the
least amount of power dissipation through the charge transistor. One possible circuit
implementation of this lower deck circuitry, Idiode(s), is shown in figure 6-5.
m
0
R3
45K
R
30
MP1
50/1
MP
501
50/1
R1
MAXDRV
15
VT1
<
MP4
10/.6
+
-
c_ diodeam
14
MN1
10/2
2MEG
R2
1MEG
25P
C
"MN2
10/2
MN3
10/2
MN4
10/2 0
MN5
200/.6
Figure 6-5: Circuit Implementation of the Ideal Diode Functionality
Analyzing this circuit, we find that all the conditions are met. When both the
battery node and output node voltages are above 3.6 volts, the signal at node VT1 is
set to high, thus shutting off the transistor MP4. With MP4 turned off, the VGATE
node will discharge through MN4 and the charge transistor will be fully turned on.
When the battery node is below 3.6 volts. the amplifier 15, whose schematic is
shown in figure A-II of appendix A, will regulate the output node to be near 3.6 volts
with negative feedback. This is because as the output voltage goes too high, VT1
59
will increase, thus decreasing the VGATE voltage, which will decrease the resistance
of the charge FET leading to a decrease in the output voltage. A miller capacitance
was added between the positive terminal of the amplifier, 15, and the VGATE node
to produce a dominant low frequency pole that will allow the gain of the frequency
response of Idiode(s) to start to decrease at a very low frequency.
The transfer
function, Idiode(s), from VOUT to VGATE is shown in figure A-12 of Appendix A,
and it can be noted that at roughly 3 KHz, the gain of Idiode(s) has already dropped
to unity gain, which is sufficiently lower than the cross-over frequency of the constant
battery current loop under all modes of operation.
Lastly, if the power requirement at the load is too high for the input to supply,
15 will simply ground the gate of MP4, and the common gate amplifier through the
branch R3 and R4 will set the output voltage to be roughly 15mV below the battery
voltage. Another important point to note in this circuit regards operation under a
sudden load pulse. Suppose the circuit is in lower deck regulation, where the output is
being regulated at 3.6 volts with some VGATE voltage, and a sudden slug of current
is pulled from the output such that current needs to be drawn from the battery. In
this case, the VGATE voltage needs to be discharged immediately to ensure that the
output node does not fall too far below the battery voltage. This was accomplished
through the use of a high speed comparator. The FASTON node goes high when the
output voltage drops to 45mV below the battery voltage, and once that node goes
high, MN5 is immediately turned on to discharge the gate capacitor of the charge
FET.
60
Chapter 7
Constant Battery Voltage Control
7.1
Overview
Once the battery is near full charge, the current supplied to the battery should decrease in order to maintain a constant voltage at the battery node. It is also required
for the error in the float regulation to be extremely small, so that the actual regulated
voltage will have less than 0.5% error from the desired 4.2 Volts.
7.2
Stabilizing Constant Battery Voltage Control
Loop
Stabilizing the constant battery voltage loop is relatively simple due to the lack of
varying modes of operation which were present in both the constant battery current
loop and the input current limit loop. Also, since the battery voltage is above 3.6V,
which is the case when the constant voltage control is in regulation, the charge FET
is fully turned on, thus making the resistance looking down the charge FET branch
a lot less resistive than the resistance looking into the load. Thus, the the transfer
function of the incremental battery voltage is equal to the internal battery resistance
times the incremental inductor current multiplied by the load pole.
The battery voltage then gets down scaled by 4.2/1.2 and the result is compared
61
to the reference voltage and amplified through a high gain amplifier to produce the
voltage for the command current.
The Block Diagram for the Constant Voltage Control Loop is shown in Figure
7-1.
Vre
:(
Gas):+ls1
H(s)
Load(s)
1.2/4.2
Figure 7-1: Block diagram form constant voltage control loop
Again, in the frequencies of interest (below the crossover frequency).
Load(s) =
bat
sRoriCoet + 1
=
.
(7.1)
RO,, is the series resistance of the charge FET with its gate grounded and the
internal battery voltage of the battery. We have concluded previously that the onresistance of the charge FET is roughly .07Q and the internal battery resistance ranges
from .05Q to .2Q. Thus, the load pole again ranges from 6 KHz to 130 KHz, with
the DC gain from
The error amplifier
to d ranging from .0143 to .0571.
Gbcomp
is designed to have a DC gain of 1500 to limit DC
error of the constant battery voltage regulation. Given this, the DC of the entire loop
varies from 20 to 80. Thus operation is acceptable as long as the Gbcomp(,s) drops to
a gain of 1500/80 before the earliest possible load pole at 6 KHz
The circuit implementation and its frequency response is shown is shown in figures
A-13 and A-14 of appendix A.
62
Chapter 8
Interaction between Control Loops
Sections 5 through 7 have described methods such that each control loop will remain
stable and behave appropriately under the appropriate load conditions. For instance,
if the battery is at 3.6 volts supporting a load of 1.8 watts, the charger is programmed
for 500mA of constant charging current, and the input current limit is set to 500mA,
the duty cycle of the switcher will be controlled by the input current limit loop. This
is because under these conditions, the battery wants to sink 1.8 watts of power, but
the power supplied at the input is limited to 2.5 watts. Thus, the constant battery
current and the constant battery voltage loops are asking for more inductor current,
but the input current limit loop is limiting the inductor current since the power drawn
from the load and battery sums to be greater than the input power supply. Now,
suppose the load is disconnected, then the input current limit loop and the constant
battery voltage loop are asking for more current but the 500inA battery charge current
regulation is limiting the amount of inductor current. Even though each individual
loop has been shown to be stable and can regulate the inductor current appropriately,
circuitry is still required to decide which of the three loops should actually be used
to control the inductor current.
63
8.1
Minimizer Circuit
Essentially, the inductor current should be controlled by the loop that is requesting
the smallest inductor current. The reason for this is that each of the loops acts as a
restriction to how much current can actually flow through the inductor. That is, the
default conduction of each control loop is to deliver power, the control signal seeks
only to retard power. In order to satisfy all three restrictions, the actual inductor
current must be controlled by the loop that commands the least amount of current.
In order to accomplish this, the outputs of the error amplifier for all three loops must
be passed into a minimizer circuit that chooses the lowest command current out of
the three. This can be accomplished using a simple circuit as shown in figure 8-1.
MAXDRV
R6
500K
100/.6
MN22
MP3
25/.6
MP3
S25/.6
10.
M P36
25!.6
R8 V
C4R7
U-
500K
-
250OK
Figure 8-1: Circuit implementation for minimizer circuit
The signals VC1, VC2, and VC3 are the outputs of the error amplifiers of the three
loops. Thus, if all three error amplifiers are connected together through this minimizer
circuitry, the resulting circuit looks like what is shown in figure A-15 of appendix A.
This entire circuit is named erroramp, and it takes as input the scaled measurements
of input current, battery current, and battery voltage as well as information about
the modes of operation for input current limit loop and the constant battery current
loop, and outputs a voltage that commands the inductor current.
The motivation behind choosing a circuit such as a minimizer to decide which
loop is in control is so that there is a smooth transition from one loop to the next.
Suppose VC1 is the output of the error amplifier for the input current limit loop, VC2
is the output of the error amplifier for the constant battery current loop, and a large
64
load step is pulled at the output node, forcing the chip to transition from constant
battery current control to input current limit control. What would happen is that
the VC2 node will increase but stabilize at a certain value such that the inductor
current will be equal to the programmed constant current for the battery plus the
current demanded by the load. However, as the inductor current is rising to meet
those criteria, the input current is also increased, and the CLPROG node of figure
4-1 will start to rise, which will lead to the decrease of the voltage on the VC1 node.
At some point, the voltage at node VC1 will fall below the voltage at node VC2,
and the input current limit loop will be in control of the inductor current. Naturally,
when this happens, the inductor current will start to decrease, resulting in less current
flowing into the battery, which will cause a decrease in the voltage on the PROG node
(Figure 6-3) and a consequent rise in the VC2 node. Due to this design topology for
the minimizer circuit, errors due to transistor matching and offset are not really a
problem due to the large gains of the outer loops.
Simulations demonstrating the correct behavior in the transitions between control
loops are shown in appendix B.
8.2
Improvement on Input Current Violation
Even though transition between loops will occur with changes in load conditions,
these transitions are not instantaneous. This becomes a huge problem when there is
a large increasing current step at the output node, because the input current limit
loop can't start regulating immediately, and the inductor current is controlled by one
of the other two loops. Thus, the inductor current will be regulating at a current
that violates the input current specification of the USB port, which will lead to a
decrease in the input voltage. Since the input voltage is the source of power for all of
the circuitry in the chip, a significant decrease in that voltage can lead to erroneous
chip behavior.
In order to ameliorate the effect of input current violation, we would want to make
the input current limit loop able to respond as quickly as possible, while drastically
65
slowing down the response of the other two loops. The way this was accomplished was
to set a slew rate limitation on the VC2 and VC3 nodes of figure A-15 in appendix
A. By doing so, the command current from the constant battery current loop and the
constant battery voltage loop will increase slowly, and thus will drastically hinder the
response speed of the constant battery current and constant battery voltage loops
to an increasing load step at the output.
Thus, the inductor current will not rise
as fast, and the time for which the input current limitation is violated is drastically
decreased.
66
Chapter 9
Conclusion
This thesis delved into the design and simulation of a new architecture for a USBpowered battery charger chip. The two main advantages of the new architecture over
its predecessor are the improved charging efficiency as well as the decrease in USB
current limit violation time.
The battery charger chip was designed using a synchronous switching buck converter with average current control. It had three main loops that limited the maximum
specified current drawn from the USB port, regulated constant charging current into
the battery when power is available and battery is not fully charged, and maintained
a float voltage of 4.2 volts for a nearly charged battery. While regulating all this,
the chip maintains the ability to regulate the output voltage at or above 3.6 volts
regardless of the battery voltage as long as there is sufficient power from the USB
port.
Simulations of these behavior are shown in appendix B.
67
68
Appendix A
Schematics and Behaviors
5uA
2uA
MAXDRV
MP7
6/6
MP6
6/6
MP8
6/6
MP5
6/6
MP1
5/2
MP2
5/2
A
BIAS
5U
VU
MN8
8/1.2
MN5
8/1.2
MN7
8/8
MN6
8/8
MP3
10/2
5
MN4
5/2
MP4
10/24
R
125K
MN2
5/2
MN
5/2
MN3
5/2fCr
20P
C2
.13P
Figure A-i: Circuit for error amplifier of average current control loop
69
V(vout)
-
80
44dB,
-
00
40dB-
- -8*
36dB-
-- 16*
32dB-
-- 24*
28dB-
-- 320
24dB-
-- 400
20dB-
-- 48*
'40Ud
16dB-
-- 560
12dB-
-- 64*
8dB-
-- 720
4dB-
-800
OdB10 Hz
100Hz
1KHz
10KHz
100KHz
1MHz
-880
10 MHz
Figure A-2: Frequency response for the error amplifier of average current control loop
70
R8
35K
S1CR
W--10
R10
R9
35K
35K
SIOR S1CR
VV-1O--10
R12I
35K
SICR
w=I--10
R11
35K
S1CR
w=--10
R13
35K
S1CR
W10
R14
35K
SICR
R15
35K
SIOR
W -10
W -10
4
4
M P4
160/2
10/2
12087
100/.6
12088
100/.6
RI
200K
a-
P
z
z
Q2
04
3.0X3.0
2
2
Q
2
20uA
R3
35K
SICR
W=6
SICRSICRS.C
W=1K
1 OuA
20uA
1 OuA
Figure A-3: Circuit implementation of ilimopamp
71
4K
O
QK
K
R.O.
OuA
X
0X3.0
3.0X3.
Q1
3.0X3.0
R2
35K
S3CR
W=6
160/2
H
ACR
W=-LOOKATME 7 6
iX
nAn
60/2
10
W1
20uA
V(vout)
1
900
dB
600
90dB-
30*
00
-300
40dB30dB20dB10dB40dB-10dB-20dB--
-30dB-40dB-50dB1Hz
-600
-90
-120*
-- 1500
-1800
-- 2100
-2400
-- 2700
-- 3000
-330*
r,.,,--3600
10Hz
100Hz
1KHz
10KHz
100KHz
1MHz
Figure A-4: Frequency response of ilimopamp
72
10MHz
100MHz
8uA
9uA
9uA
MAXDRV 36uA
54uA
1
4
528mV
o
4
MPO
10/3
R3
W-
560mV
ic=837
I
2
2
2
MP4
MP5
20/0.820/0.8
.5A
MP9
MP8
10/4
MP7
10/4
SICR2
2
14
-M
ic=77
4
10/4
10/4
18uA
9uA
54uA
10/4
MPhl
10/3
B
+
a-VOUT
0
0
1
R2
29.044K
S1CR
MN2
VV-13.
MN1
5/5
1
MP3
30/.6
0
MP6
30/.6
0
5/5
5
214mV
ic=12
MN3
10/2
302mV
ic-24
MN4
10/2
MN5
10/2
302mV
ic-24
z
>
MN7
10/0.8
MN6
10/2
3
3
Figure A-5: Circuit implementation of PWM comparator
73
V(vout)
105dB-
00
98dB-
- -30*
91dB-
- -60*
84dB~900
77dB70dB_
-- 120*
63dB-
-- 1500
56dB-
-- 180*
49dB-
-- 210*
42dB-
--240*
35dB28dB1Hz
-270*
10Hz
1MHz
100KHz
1KHz
10KHz
100Hz
--- C:Projects\stevejunior\2.0\schem\c-pwmcomp ---
10MHz
100 MHz
Figure A-6: Frequency response of PWM comparator
V(vinp)
V(vinn)
2. 6V2. 4V2. 2V2.
8V6V4V-
V(vout)
5. 5V4. 5V3. 5V2. 5V1. 5V0. 5V-0. 5V-
Ons
3ns
6ns
9ns
12ns
15ns
18ns
21ns
24ns
---C:\Projects~stevejunior\2.O\schemkc-pwmcomp.cir --Figure A-7: Transient response of PWM comparator
74
27ns
30ns
ONE1AftAD___________
(TENT HAMP
5'uA
+
MAXDRV
MP2
6/6
MP1
6/1.5
1 OUA
5uA
1uA
MP9
MP12
2/1.
MP8
6/6 .11M14
MP15
MP.
MP14
MP4
5/4
MP3
5/4
5U
MP5
MNN1
8/1.2
MN5
8/8
A
M NN2
8/1.2
MN6
.020/2
MP6
20/2
21
250K
MN3
MN2
MN
2
MN4
CP
8/8
O0P
Figure A-8: Circuit implementation of error amplifier for input current limit
75
AXDRV
MP16
8/8
MP18
8/8
MP17
8/2
MP19
8/2
0 MP20
4/2
14
MP21
4/2
5U
MP22
MNN3
10/1.2
MN7
10/8
MNN4 MP25
2/1.2
2/2
MP24
100/2
MN8
2/8
MN11
MN104/2
100/8
MN9
2/8
10/1
MP23
10/1
0
MN12
4/2
22
1
MN13
14/2
'MNl4
14/2
R2
25P
C4
10P
R4
1MEG
R3
90K
Figure A-9: Circuit implementation of error amplifier for constant battery current
loop
76
V(vc)
45dB
80
40dB-
QO0
35dB-
8
30dB-
.- 160
25dB-
0
20dB-
-240
0
--320
*
0
15dB-0
0
- 400
*
0
5dB-
0
*
,
560
0dB-
-- 640
-5dB
--720
-10dB- 1
100mHz
1Hz
10OHz
100OHz
1 KHz
10OKHz
100OKHz
1MHz
-800
10MHz
--- :CProjectskstevejun i o r2.Oschemkc-e rro rampp-
Figure A-10: Frequency response for error amplifier for constant battery current loop
77
5uA
2uA
MAX :nRV
MP2
6/6
MP7
6/6
MP1
6/1.5
MP8
6/1.5
MP3
5/2
MP6
5/2
5U
MNN1
8/1.2
z
JMNN2
8/1,2
MN4
8/8
MN3
8/8
MP4
10/1
MN1
5/2
MN5"
5/2
MP5
10/1
_
MN2
5/2
-- CVUT
MN6
5/2
Figure A-11: Implementation for lower deck amplifier
V(vgate)
80dB70dB60dB50dB40dB30dB20dB10dB-
200
00
N
-- 20*
-40*
-60*
-80*
-- 1000
-- 1200
OdB-10dB-20dB-30dB-40dB-50dB1mHz
10mHz
100mHz
1Hz
1 00Hz
10Hz
1 KHz
10KHz
Figure A-12: Frequency response for Idiode(s)
78
100KHz
-140*
-160*
-- 180*
-- 2000
-- 2200
-240*
1MHz
MAXDRV
M P26
8/8,
MP27
8/8
MP28
8/2
MP29
8/2
0
1
MP30
1/10
15
5U
'5U
MP31
1/10
vC
MNN5
10/1.2
MNN6
2/1.2
MN15
10/8
MN16
2/8
MP32
10/1
8
MN17
1/10
MP33
10/1
MN18
1/10
C5
25P
MN19
1/10
1
MN20
1/10
-
C6
2.5P
R5
1MEG
7
Figure A-13: Circuit implementation for battery voltage error amplifier
V(vc)
20*
70dB60d B-
- 0*
50dB-
-- 20*
40d B-
-40*
30dB-
-60
20dB-
-80
10dB-
-- 100*
OdB-
-- 120*
-10dB-
--140*
-20dB-
--160*
-30dB-
-- 180*
-40dB-
-- 200*
-220*
100mHz
1Hz
10Hz
100Hz
1KHz
10KHz
100KHz
1MHz
-- C:\Projects steveju nior\2. \schem~cerroram p.cir ---
10 MHz
Figure A-14: Frequency response for battery voltage error amplifier
79
ONEAMP
(
TENTHAMP
5uA
+
10 uA
5uA
1uA
MAXDRV
MP2
6/6
MP9
12/6
MP12
6/6
MP15
12/6
MP1
6/1.5
MP8
1,2/1 .5
MPh
6/1,5
MP14
12/1.5
MAXDRV
R6
500K
MP7
MP10
MP13
10L 6
1
10/.6
MP3
.6
KMN21
100/.6
MP4
514MN22
5/4
MP3
MP5
MP5 M625/,6
MNN1
0
MNN2
8/1.2
8/1.2
R1
20/2
C2
~ -
2
MN3
MN5
6/68
20/2
M4
MN6
8/6
MN2
MN4
MP3
MP36
25/.6
250.6
M2
100/.6
25KR7
500K
P
T20
AXDRV
MP16
MP18
MP17
MP19
8/2
8/2
MP21
4/2
/ MP20
mV
4
15U14
V 2
MP22
MNN3
10/1.2
MNN4
2/1.2
MP25
2/2
MN7
MN2
MN9
10/8B
2/6
MP24
100/2
10/1
10/1 .
.
MN11
MN1O4/2
2/8
MP23
MN12
4/2
MN13
4/2
MN14
4/2
100/8
R2
25P
C4
lP
R4
R3
i MEG
90K
C5
20
25P
C6
-> 25
2 .5P
MAXDRV
MP26
|Z
<
MP28
8/2
MP27
MP29
__ _8/2
MP30
1V03/1
15
5UMP32
MNN5
10/1,2
MNN6
2/1.2
MN15
MN16
10/8
MP31
u
MP33
10/1
10/1
M 1
MN17
1/10
MN18
1/10
MN19
1/10
MN20
1/10
R5
2/8IMEG
Figure A-15: Circuitry for the complete error amplifier for all three loops with minimizer circuitry
80
R8
250K
V
00
CDq
CDt
Oq
C)
0
CLK
P
SV40N
s wno Q
PGATE~F
V
"N
S
NJ
CFIM-N
150
40/0.
z
,REVN
ISW
-,SWON
12147
>-.-ATe'
>p.
,RESEf-g""
VGSR
vCMD
MAXD
S
VE
PGATE
BLKN
_ nA
+
0S
100015
SA7
VSAMpy
NTHAMP
oA
- - - - - - -VGATU
MPLE
111.6
T
0
MAX
.V.AT
RATGATE
AVGATE
VGATE
>
12K,
30K
VBAT
+
1.v VOUT Vo_
VBAT -
401.6
3000
82
Appendix B
Simulation Results
83
V(vgate)
2.6V1.6VV(ierroramp:vout3)
5.0000V
4.9990V
4.9980V
V(ierroramp:vout2)
5. 1 V3.6VV(ierroramp:voutl)
5.OV-.
3.7V2.4V
V(vout)
3.70V3.55V
3.40V
3.25V3.1 -
(i
)
1. 1A-
0.8A0.5A
0.2A-. 1AO.Oms
.ms
0.2ms
0.3ms
0.4ms
0.5ms
0.6ms
0.7 ns
Figure B-1: Response to a IA load step increase at the output w/ battery voltage at
3.2V. Constant current charging and input current limit both set to 500mA
84
V(vgate)
2.5V-
0.9V---
V(ierroramp:vout3)
5.00004.9990V4.9980V-
V(ierroramp:vout2)
5.2V
3.7V2.2V
V(ierroramp:voutl)
5.2 -3.8V2.4 V
V(VOUt)
3.60V
3.35V
(IL)
3.10V1.2A
0.6A-0.1A-
I(Iload)
1.1A
0.8A0.5A0.2A_
-. A-0.
0.4ms
0.6ms
0.8ms
1.Oms
1.2ms
1.4ms
1.6ms
1.8ms
2.Oms
Figure B-2: Response to a IA load step decrease at the output w/ battery voltage at
3.2V. Constant current charging and input current limit both set to 500mA
85
V(vgate)
) 52O
I--
2.19V1.86V
V(ierroramp:vout3)
5.0002V
4.9991 V14.
9?lV
980
5.4V-
V(ierroramp:vout2)
4.OV2.6 V-
V(ierroramp:voutl)
5.4V4.8V4.2V3.6V
3.0V
V(VOUt)
4.23V3.74V3.24V
1.8AMMMMMMW-
Q.8A-~
-u .l
I(Iload)
1.1A-
0.8A0.5A0.2A-0.1A
O.Qms
.ms
0.2ms
0.3ms
0.4ms
0.5ms
0.6ms
0.7ms
0.8ms
0.9ms
Figure B-3: Response to a IA load step increase at the output w/ battery voltage at
3.2V. Constant current charging and input current limit both set to IA
86
V(vgate)
2.6V
2.4V2.2V2.OV1.8V
V(ierroramp:vout3)
5.0000V
4.9990V
4.9980V-
V(ierroramp:vout2)
5.2V4.6V-
4.OV3.4V2.8V-
V(ierroramp:voutl)
4. 1V3.1 V
V(VOUt)
4.2V
5. 1 V-______
3.3V-
3.OV
1.7A
1.4A-
0.8A1. 1 AC
0.5A0.2A- Rsoset5AA odse decreasead)
FiueB4.
-0.1A
0.3ms
0.6ms
uptw
0.9ms
bteyvlaea
1.2ms
Figure B-4: Response to a IA load step decrease at the output w/ battery voltage at
3.2V. Constant current charging and input current limit both set to IA
87
V(vgate)
25rm
OmV-25mV-
V(ierroramp:vout3)
3.4V2.8V
2.2V1.6V-
V(ierroramp:vout2)
5. 1V4.2V3.3V2.4V-
V(ierrorampvout1)
5.1V4.2V3.3V2.4V-V(VOUt)
4.28V4.22V-,
4.16V4.1 OV-
4.04V
(Li)
750mA-
600mA45OmA300mA--w
150mA8%(Iload)
1.1A-
0.8A0.5A0.2A-. A-0.
.Oms
0.2ms
0.4ms
0.6ms
0.8ms
1.Oms
1.2ms
1.4ms
1.6
ns
Figure B-5: Response to a IA load step increase at the output w/ battery voltage at
4.15V. Input current limit both set to 500mA
88
V(vgate)
2.6V
2.4V2.2V-
2.OV1.8V
V(ierroramp:vout3)
5.0000V
4.9990V
4.9980 V
V(ierroramp:vout2)
5.2V
4.6V-
4.OV3.4V2.8V
V(ierroramp:voutl)
5. 1V
4 .1V - --- --------- -3.1V
V(VOUt)
4.2
3.3V3.OV1.7A-
14 A
0.8A-
0.5A
I(Hoad)
1.1A-
0.8A0.5A0.2A-0.1A
0.3ms
0.6ms
0.9ms
1.2mTs
Figure B-6: Response to a 1A load step decrease at the output w/ battery voltage at
4.15V. Input current limit both set to 500mA
89
V(vgate)
4mV-18mV-
-4umV--
V(ierroramp:vout3)
5.001V
4.985V-
4e
.968V---
V(ierroramp:vout2)
L968V-
5.2V3.9V2.6V26V-
V(ierroramp:voutl)
5.2V4.6V
4.OVV(vout)
3.4V
4.20V4.OOV
(L)
3.80V-
1.8A-
0.8A-1.2A-
(Iload)
1.lAr
_________________
0.8A0.5A
0.2A-0. 1A-
0.3ms
0.4ms
0.5ms
0.6ms
0.7ms
0.8ms
O.9ms
Figure B-7: Response to a 1A load step increase at the output w/ battery voltage at
3.8V. Constant current charging and input current limit both set to IA
90
V(vgate)
-4mV-34mV-
-64mV
A 50f00VI
V(ierroram p:vout3)
4.980V14.960UV-
V(ierroramp:vout2)
D. I V-t
1
3.9V2.8V-
V(ierroramp:vout1)
0.1V-
4.OV3.0 v
V(VOUt)
4. 1OV-
4.OOV3.90V3.80V(
(L1)
1.5A
I
1.OA0.5A-
I(Iload)
1.1A-
0.8A0.5A
0.2A
-0.1A-
0.1 ms 0.2ms 0.3ms 0.4ms 0.5ms 0.6ms 0.7ms 0.8ms 0.9ms 1.Oms 1.ms 1.2ms
Figure B-8: Response to a IA load step decrease at the output w/ battery voltage at
3.8V. Constant current charging and input current limit both set to 1A
91
V(vgate)
6.6mV4.8mV
3.OmV
1.2mV-
V(ierroramp:vout3)
-0.6mV2.5V1.9V-
V(ierroramp:vout3)
1.2V
V(ierroramp~vout2)
5.1 V4.2V3.3V2.4V
V(ierroramp:voutl)
4.8V-
4.OV3.2V2.4V-
V(vout)
4.244V-
4.208V4.196V(L)
650mA375mA-
I
1um
(Iload)
1 AmA
.OmA
-1 .0m m
Oms
2ms
4ms
6ms
8ms
1 Oms
12ms
Figure B-9: Response to a IA load step decrease at the output w/ battery charging
to float voltage. Constant current charging set to 500mA
92
Bibliography
[1] "LTC4061 - Standalone Linear Li-ion Battery Charger with Thermistor Input,"
Linear Technology, pp. 1-20.
[2] "LTC4088 - High Efficiency Battery Charger/USB Power Manager,"
Technology, pp. 1-24.
Linear
[3] John G. Kassakian, Martin F. Schlecht, George C. Verghese, Principles of Power
Electronics, Massachusetts: addison-Wesley, 1991. pp. 251-403.
[4] Robert W. Erickson, Dragan Maksimovie, Fundamentals of Power Electronics,
Massachusetts: Kluwer Academic Publishers, 2nd Edition, 2001.
[5] D.A. Johns, K. Martin, Analog Integrated Circuit Design, Massachusetts: Wiley,
1997.
[6] R. D. Middlebrook and Slobodan Cuk, "Modeling and Analysis Methods for Dcto-Dc Switching Converters," IEEE Transactions on Aerospace and Electronic
Systems, Vol. AES-9, pp. 376-385, May 1973.
[7] Slobodan Cuk, "Modeling, Analysis, and Design of Switching Converters," Ph.D.
thesis, California Institute of Technology, November 1976
[8] R. D. Middlebrook, "Measurement of Loop Gain in Feedback Systems," International Journal of Electronics, Vol. 38, No. 4, pp. 485-512, 1975.
93