RF Spiral Inductors in iUHD for
Voltage Controlled Oscillators in
Configurable RF Integrated Circuits
by
Charvak Karpe
S.B. Electrical Science and Engineering
Massachusetts Institute of Technology, 2004
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2006
© Charvak Karpe, MMVI. All rights reserved.
The author hereby grants to MIT permission to reproduce and distribute publicly paper
and electronic copies of this thesis and to grant others the right to do so.
Author
Depaltment oylectrical Engineering and Computer Science
September, 2006
Certified by Certified by
John R. Lachapelle
Charles Stark Draper Laboratory
Thesis Supervisor
Certified by
Luca Daniel
Assistant Professor of Electrical Engineering and Computer Science
MIT Thesis Supervisor
Accepted by
,
-
--
-
Arthur C. Smith
Chairman, Department Committee on Graduate Theses
MASSACHUSETTS IN• fTUTE.
OF TSOMNOL,
OCT 03 2007
LIBRARIES
ARCHIVES
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Spiral Inductors in iUHD for
Voltage Controlled Oscillators in
Configurable RF Integrated Circuits
by
Charvak Karpe
Submitted to the Department of Electrical Engineering and Computer Science on
September 8, 2006, in partial fulfillment of the requirements for the degree of Master of
Engineering in Electrical Engineering and Computer Science
Abstract
The miniaturization of radio frequency wireless communications circuitry has resulted in
a need for smaller inductors. This thesis presents designs of spiral inductors to be
fabricated in Draper Laboratory's integrated Ultra High Density packaging process. The
inductor designs are simulated using Ansoft's High Frequency Structure Simulator and
the resulting inductor performance parameters are used to design a voltage controlled
oscillator (VCO) meeting 802.1 lb wireless specifications. The design demonstrates the
importance of inductor quality factor in minimizing phase noise. It is also shown that
further improvements can be made to RF integrated circuits by increasing the maximum
load impedance seen by the VCO.
Technical Supervisor: John Lachapelle
Principal Member of Technical Staff, Charles Stark Draper Laboratory
Thesis Supervisor: Luca Daniel
Assistant Professor of Electrical Engineering and Computer Science
Acknowledgements
First and foremost, I would like to acknowledge my thesis supervisor, John Lachapelle,
for demonstrating his commitment to my completion of my thesis. John provided me
with valuable advice and guidance, as well as technical knowledge, making this a
personal learning experience in addition to an academic exercise. I would also like to
thank Scott Uhland, my supervisor during the initial portion of the work, for getting me
started and making sure I still had a new group to work with when the initial project plans
hit a roadblock. I am indebted to Stan Shanfield for initially hiring me as a Draper
Fellow and keeping me on for the second year even though I could have been let go when
I left for a summer and the first project fell through. I would like to thank my MIT thesis
supervisor, Luca Daniel, for his technical advice and his patience in dealing with
situations in which it appeared as though I would not finish. Thanks to Luca for trusting
that I would follow through eventually.
I would also like to thank Jay Bruso for helping me learn to use the test and
measurement equipment at Draper and taking time to help me with things in the lab.
Thanks to Will Schmitt for sticking around the lab late in the evening when few others
would be around and providing me with stimulating discussions about theoretical physics
and math, keeping me mentally sharp.
I want to acknowledge Jeanne-Marie Cabe for being my best friend and providing
me with unwavering personal support and any help I needed under all circumstances.
Finally, I want to thank my family for supporting my endeavors regardless of the path I
chose and making it possible for me to attend MIT.
Acknowledgement of Sponsorship
9/13/2006
This thesis was prepared at The Charles Stark Draper Laboratory, Inc., under
Publication of this thesis does not constitute approval by Draper or the
sponsoring agency of the findings or conclusions contained herein. It is
published for the exchange and stimulation of idea.
(Author's signature)
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Contents
1
Introduction ............................................................................................................... 12
1.1
2
Background .............................................
1.1.1
RF Applications ..............................................................................
12
1.1.2
RF Use at Draper ............................................................................
13
1.1.3
RFIC Project ............................................................
1.1.4
RF Building Blocks..........................................................................
13
1.1.5
Inductors in RF Circuits...............................................
14
1.1.6
RF Fabrication in i-UHD Process ......................................
4
...... .. 16
VCO Design............................................
VCO Architectures..........................................................................
2.1.2
Phase Noise Considerations .........................................
2.1.3
Inductor Requirem ents.............................................
Inductor Theory .............................................
18
.................................................... 18
2.1.1
18
............ 19
22
..................................................... 23
3.1
Inductor Basics..........................................
3.2
Parasitic Effects ...............................................................
.................................................. 23
........................... 23
3.2.1
Skin Depth ..........................................
3.2.2
Proximity Effect..............................................................................
24
3.2.3
Capacitance .....................................................................................
25
3.2.4
Eddy Currents ................................................................................
26
................................................ 24
3.3
Quality Factor ..........................................
3.4
M utual Inductance ..................................................................................
................................................... 27
27
Inductor Design......................................................................................................... 29
4.1
5
........................... 13
Voltage Controlled Oscillators .......................................................................
2.1
3
.................................................... 12
Inductors in i-UHD ...........................................................................................
29
4.1.1
Properties of Interest ................................................................................. 29
4.1.2
Design Choices ................................................................................
30
4.1.3
Ground Planes ................................................................................
32
4.1.4
Alternative Topologies..............................................
34
Multi-Chip M odules..........................................
.................................................. 35
6
7
5.1
M CM -D at Draper.......................................................... 35
5.2
I-UHD Process ........................................... .................................................. 35
5.2.1
Fabrication Sequence ...................................................... 36
5.2.2
Feature Limitations ................................................................................ 38
5.2.3
Process Results........................................................39
Ansoft HFSS .............................................................................................................
6.1
HFSS Introduction .............................................................
6.2
FEA Techniques.........................................
6.3
Inductor Setup ............................................................................................... 42
6.4
Solution Results ..........................................................................................
43
Fabrication and Testing......................................................................................
48
7.1
8
.......................... 41
.................................................. 41
M easurement..................................................................................................... 48
7.1.1
Probe Calibration ............................................................
................... 48
7.1.2
Data Extraction ............................................................
........................ 49
7.1.3
Interference M easurement .....................................
.....
............ 50
RFIC VCO using iUHD Process .......................................................................
8.1
51
Contemporary VCO Design Improvements.............................................. 51
8.1.1
Symmetric Inductors ....................
8.1.2
Tuning .................................................
8.1.3
Tail Current....................................................................................
8.1.4
Quadrature Generation .....................................
8.1.5
Harm onic Tuning ...................................................................................
............................................. ................ 52
53
...... 55
...................... 55
56
8.2
Perform ance Specifications ............................................................................. 57
8.3
Design Implementation...
......
.................................................................. 60
Results ........................................
9
41
64
Conclusion ........................................
70
Bibliography ..................................................
71
Properties to be Tested.......................................... ..................................................
75
Appendix B Results (to be completed in future work) .................................................... 76
Simulation Results ......................................................
M easurem ent Results ................................................
76
............................................ 76
Figures
Figure 1.1: Wireless Usage Growth ....................................................................
12
Figure 1.2: RF Block Diagram ....................................
............................................... 14
Figure 1.3: M EM S Resonator .....................................
............................................... 16
Figure 2. 1: V CO Architectures ......................................................................................... 19
Figure 2.2: N oise Sources ...........................................
............................................... 20
Figure 2.3: Tank Im pedance ............................................................
.......................... 21
Figure 2.4: Noise according to Leeson's Equation ......................................
.......
22
Figure 3.1: Capacitive current path.......................................................................
26
Figure 4.1: Spiral Inductor Test Layout................................................................
29
Figure 4.2: Patterned Ground Shield ....................................................................
33
Figure 5.1: Process Diagram .......................................
................................................ 36
Figure 5.2: M etal layer-0 ...............................................................
............................ 36
Figure 5.3: Die placed, buried in epoxy layer....................................
............. 37
Figure 5.4: Vias drilled, cathodic layer deposited .....................................
........ 37
Figure 5.5: Metal layer-1, unfinished ....................................................................
Figure 5.6: M etal Layer-1 ..........................................
38
................................................. 38
Figure 5.7: Undercut from etching..........................................................................
39
Figure 5.8: Overexposure of Vias ......................................................
40
Figure 6.1: HFSS Setup for 2.5 turn spiral ..........................................
42
...........
Figure 6.2: Magnetic field direction and intensity for 2.5 turn spiral ........................... 44
Figure 6.3: Magnetic field intensity for 90 turn toroidal inductor ................................ 45
Figure 6.4: Inductance of 3.5 turn spiral ......................................
...
.............. 46
Figure 6.5: Quality factor of 3.5 turn spiral, measured at both ports............................ 47
Figure 7.1: Measurement Setup .............................................................................
Figure 8.1: Octagonal Symmetrical Inductor..................................
Figure 8.2: V aractor Tuning .............................................................
48
.............. 53
......................... 54
Figure 8.3: Cross-Coupled VCO's for Quadrature Generation ..................................... 56
Figure 8.4: Double-Frequency VCO with Flip-Flops for Quadrature Generation .......... 56
Figure 8.5: Differential Clapp VCO ......................................................................
Figure 8.7: Phase noise at 0.5 V tuning voltage. .......................................
60
........ 65
Figure 8.8: Phase Noise at 2.5 V tuning voltage.................................
Figure 8.9: Phase noise for lower inductor Q........................................
........... 66
.......
67
Figure 8.10: Phase noise for lower load resistance .................................................
68
Figure 8.11: Varactor tuning curve .....................................
......
................. 69
Tables
Table 3.1: Metal Properties and Skin Depths .......................................
Table 6.1: Inductor Size vs. Solution Time ........................................
.......... 24
............ 44
Table 8.1: WLAN VCO Specifications ................................................................
Table 8.2: Loaded Inductor Q ...............
59
...................................................................... 62
Table 8.3: VCO Simulation Results..................................................
64
Table B.0.1: Simulated Inductor Values .......................................................................
76
Table B.0.2: Measured Inductor Values .........................................
.............. 76
Table B.0.3: Inductor Coupling ..............................................................................
11
77
Chapter 1
Introduction
1.1 Background
1.1.1 RF Applications
With the explosive growth in the use of wireless communications, small and portable
radio frequency (RF) circuitry has recently come into high demand. As of June 2005,
there are nearly 195 million cell phone subscribers in the US [3]. 802.11 wireless
networking capability is standard for computers and is finding its way into networking
other devices. Cars and homes are equipped with receivers for direct broadcast satellite
services. XM Satellite Radio has 6 million subscribers, Sirius has 4 million, and 26
million US households subscribe to satellite television [9][10][11][12]. Over 10% of new
vehicles sold in the US are equipped with GPS navigation systems and GPS is used
extensively for military applications [8]. RF circuitry is used in industry for low data rate
communications on the unlicensed ISM (industry, scientific, and medical) bands. Air and
space navigation and communication systems also rely on RF capabilities.
Woddwle WIF! Handset Revenue
su .
I$s
Sim, .
ROs$
Cn
cV
cM
c r
Calendarr
Source: Infonetics
Figure 1.1: Wireless Usage Growth
e
CYDo
1.1.2 RF Use at Draper
Draper Laboratory engages in a wide range of projects for the US government. Many of
these projects require RF communication devices. Inertial measurement units (IMU's),
which use accelerometers and gyroscopes to determine position, must be periodically
calibrated by GPS receivers. Wireless LAN transceivers are used to communicate with
robotic devices. Biomedical implanted devices will require wireless communications to
provide interfaces to external objects or other devices located elsewhere in the body.
Transmitters and receivers used for classified operations may use the UHF, L, or S bands.
Reducing development time and cost for RF circuits is useful because Draper is involved
in such a variety of efforts that use RF devices.
1.1.3 RFIC Project
The Draper RFIC (radio frequency integrated circuit) project aims to create a small and
low power configurable RF circuit framework to facilitate rapid development for custom
RF applications with size or power constraints. The RFIC project will consist of
predesigned implementations of various RF circuit building blocks, with selectable
parameters and variable configurations. The RF engineer will be able to choose
operating frequencies, power levels, amplification, selectivity, noise, etc. Using a
standard RFIC framework will allow RF designers to take advantage of design work that
has already been completed and save them from having to design custom circuits from
scratch.
1.1.4 RF Building Blocks
An RF circuit has several building blocks. On the receive side, when a signal comes in
from an antenna, it is first passed through a low noise amplifier (LNA) to boost the signal
to a usable amplitude. Then, it may go through an image reject filter to isolate the
frequencies of interest. The signal is recovered by multiplying the RF with the output of
a local oscillator (LO), which demodulates the signal down to an intermediate frequency
(IF). The IF is always a fixed frequency so the downstream circuitry can be designed for
just that frequency. The IF signal will again be filtered to remove the images created by
the demodulation. Finally, it is amplified with automatic gain control to make its
amplitude compatible with the range of the analog to digital converter or whatever the
final destination of the signal may be.
On the transmit side, the signal is modulated with the output of a LO using a
mixer. It must be filtered before transmission to avoid emitting power at neighboring
frequencies. The RF signal is passed through a power amplifier that drives the
transmission antenna. If the same LO modulates both the receive and transmit signals,
either different IF's or time-duplexing must be used. Time-duplexing means that the
transceiver is never transmitting and receiving at the same time, so the same frequency
can be used for transmission and reception. Alternatively, different IF's used with the
same LO give different transmit and receive frequencies. However, this does not allow
for separate tuning of the transmit and receive circuits.
The LO is usually implemented as a voltage-controlled oscillator (VCO) with
tuning circuitry. The tuning circuitry will include a feedback loop to compensate for
unwanted changes in VCO output frequency due to factors such as temperature changes.
The VCO frequency can also be intentionally varied within the band when using
frequency modulation.
Amplifier
Tx Filter
Mixer
Bandpass
Figure 1.2: RF Block Diagram
1.1.5 Inductors in RF Circuits
Inductors play a crucial role in RF circuits because of their high frequency analog
properties. Common uses of inductors in RF circuits include bias chokes and tank
oscillators. Bias chokes are routinely used to provide DC connections while isolating
high frequency interference. Bias chokes are found in the power supply connections of
LNA's. Tank oscillators use inductors and capacitors as reactive energy storage elements
that resonate together at a controllable frequency. Accurate frequencies are needed in RF
circuits to modulate or demodulate signals. High quality inductors are required in the
VCO. Inductors can be fabricated on-chip or off-chip. Off-chip inductors can be coils of
wire, traces on the board, or bond wires. Off-chip inductors usually offer higher quality
factors because of their lower resistance, but they are larger and their inductance can vary
due to manufacturing inconsistencies. On-chip inductors tend to be fabricated as spirals,
although other geometries such as toroids or rectangular helices are possible and may
become more common as process parameters change and make vias less resistive.
An alternative to using inductors for L-C tank resonators in RF circuits is to use
MEMS resonators. Resonators provide very high quality factors, but are not tunable,
making them unusable in VCO's [36]. Mechanical resonators are also not currently
useful at frequencies above approximately 1 GHz because they must be sized inversely
proportional to frequency and they cannot handle enough power if they are too small. It
is important to note that MEMS resonators use mechanical vibration and are not EM
wave resonators. Figure 1.3 shows a MEMS resonator, designed at Draper, which
functions somewhere in the 200 MHz to 1 GHz range.
Figure 1.3: MEMS Resonator
1.1.6 RF Fabrication in i-UHD Process
The components most easily fabricated on integrated circuits are transistors, capacitors,
and resistors. Inductors have, in the past, been mounted on printed circuit boards as
discrete components. They generally consist of coils of copper wire, sometimes with a
ferromagnetic material in the core. This approach to fabricating inductors limits the
miniaturization afforded by the i-UHD (Integrated Ultra High Density) packaging
process. Therefore, improving ways to fabricate inductors within the i-UHD process is a
worthwhile endeavor.
In-process inductors are usually fabricated in silicon by forming square or circular
spirals of conductive material. The concentric turns have mutual inductance, improving
the total inductance of the spiral. Due to the resistivity of silicon, this method results in
inductors with relatively low quality factors, on the order of 2 to 5. Low quality factor
inductors cause resistive power loss when used as bias chokes and excessive phase noise
when used in tank oscillators for VCO's. To overcome this challenge, copper structures
can be fabricated in the metal interconnect layers of the i-UHD process. The advantages
of making spiral inductors in the metal interconnect layers are two-fold. Firstly, the 2 um
thick copper has much lower resistivity than silicon. Secondly, the SU-8 epoxy between
the metal and die layers provides physical isolation from the conductive substrate. This
distance helps because one of the loss mechanisms in inductors which lowers the quality
factor is eddy currents in the underlying substrate.
Chapter 2
Voltage Controlled Oscillators
2.1 VCO Design
2.1.1 VCO Architectures
Common VCO architectures are Hartley, Colpitts, and Clapp, which is a version of the
Colpitts architecture. Each of the oscillators employs an L-C tank circuit to induce the
oscillation. The frequency is varied by using a varactor to modify the capacitance.
Because there is resistive loss in the tank, power must be replaced by an active device
such as a transistor or FET. Figure 2.1 shows basic schematics of the three oscillators.
The Hartley oscillator uses one capacitor and two inductors, while the Colpitts uses a
single inductor with two capacitors. The Hartley oscillator is used less in modem designs
because inductors are more difficult to fabricate in integrated circuits. However, in a
Colpitts oscillator, the amplitude of the output signal varies as the capacitance is varied to
achieve different frequencies. This happens because the ratio of the two capacitors which
provide feedback to the transistor changes, changing the loop gain. The Clapp oscillator
solves this problem by placing the varactor in series with the inductor for tuning. This
allows the capacitors connected to the transistor to remain fixed, reducing variations in
oscillator performance over the tuning range.
R
R_Load
R
RLoad
C
Cbig
ClIpp Oscillor
(b)
(a)
R
R_Load
H.dley Oscllwr
Figure 2.1: VCO Architectures
2.1.2 Phase Noise Considerations
2FkT
r
Leeson's equation describes phase noise at the output of a VCO and is given by [2] :
L(Ao)=10.P1og
IL P.
2QAm
2QAw
1+ Amf
IAI)j
(2.1)
F is the empirically derived oscillator amplifier noise factor, Psi is the oscillator output
power, %ois the carrier frequency, Q is the loaded quality factor of oscillator, and A~
i,
is the active device flicker noise corner frequency.
Thermal noise and flicker noise are the two types of noise sources characterized
by Leeson's equation. Charge carriers have thermal energy, proportional to their
temperature, which causes them to exhibit random motion. This results. in small random
currents equally distributed across the frequency spectrum, causing white noise. Active
devices exhibit a source of noise called flicker noise. Flicker noise is caused by
impurities in the semiconductors, which randomly trap and release electrons. Because
flicker noise drops off proportionally to frequency, it is also known as 1/f noise.
Noise (dB)
Flicker noise
Thermal noise
,
-10 dBldec
Frequency (Hz)
Figure 2.2: Noise Sources
The kT term in Leeson's equation represents the thermal energy of the charge
carriers, which is proportional to the thermal noise which they generate. Thermal noise is
independent of output power, so the thermal noise term is divided by Pig to obtain the
ratio of noise to signal. Because thermal noise consists of random currents, it must be
multiplied by the impedance of the tank oscillator to obtain the noise voltage.
The impedance of an L-C tank oscillator is given by:
Z(o)= jL
1
j C
jo
(2.2)
1- 02LC
At an offset frequency of Aw:
j(w + A
)L
Z(Oo + A O)=j(o+A0
1-(o9 + 2cooAo + AW 2 )LC
(2.3)
Using:
o°o
1
and Aw = 0
(2.4)
We get:
Z(wO + Aw) =
(2.5)
-2
00Substituting
equation
the
for
unloaded tank Q [2]:
Substituting the equation for unloaded tank Q [2]:
Q=
(2.6)
OoGL
Gives:
Z(wo + Awo
= 1
co
G 2QAao
(2.7)
Therefore, the impedance of an L-C tank oscillator drops off proportionally with the
deviation from the resonant frequency. As shown in figure 2.2, the impedance of the tank
does not continue to drop indefinitely, because the parasitic series resistance imposes a
minimum impedance. This explains the second term in Leeson's equation. The noise
current is multiplied by the impedance of the tank to get voltage and then squared to get
noise power.
Impedance
(dB Ohms)
Tank reactance
-10 dBdec
Tank resistance
.I--
Frequency (Hz)
Figure 2.3: Tank Impedance
The third term in Leeson's equation represents flicker noise, which causes an
inverse cubic relationship between noise and offset frequency near the carrier frequency.
Flicker noise occurs mainly in transistors, where imperfections in the crystal lattice can
trap and release charge carriers, affecting current flow [4]. Flicker noise is also called 1/f
noise because its amplitude varies inversely with frequency. This is due to the relatively
large time constant of the variation in charge carriers in the device.
The combination of all the terms in Leeson's equation gives a noise profile as
shown in Figure 2.3:
Noise
Flicker noise
/
/f corner frequency
-3
Frequency (Hz)
Figure 2.4: Noise according to Leeson's Equation
2.1.3 Inductor Requirements
As seen in Leeson's equation, phase noise in a VCO depends primarily on the output
signal power and the tank loaded Q. The tank oscillator consists of an inductor and a
varactor and the loaded Q depends on the Q of both elements in the oscillator. Increasing
the output power can reduce phase noise by dominating the thermal and flicker noise.
However, because varactor Q drops off at low bias voltages, the output power is limited
by the voltage swing of the varactor. Once the tradeoffs between varactor bias voltage
and output power are optimized, the remaining element to improve phase noise is the
inductor.
In addition to maximizing the inductor's quality factor, the resonant frequency
must be considered. Resonant frequencies of inductors are difficult to control in
fabrication because the parasitic capacitance of the inductor depends on many variables.
The accuracy of the fabrication and nearby structures may significantly affect the
inductor's parasitic capacitance. To ensure that the inductor behaves predictably, with a
precise value of inductance, the estimated resonant frequency must be kept at least 3
times higher than the operating frequency.
Chapter 3
Inductor Theory
3.1 Inductor Basics
Ideal inductors are simply devices that resist changes in current with opposing voltages.
Their behavior is governed by a differential equation relating the voltage to the change in
current:
v(t) = Ldi(t)
dt
The equation for power:
P=V.I
Rewritten, we get:
dU
dt
dl
dt
Integrating:
1
fdU = LId = 2 2L
Therefore, the magnetic energy stored in an inductor is given by:
E= L12
2
An ideal inductor has no associated resistance or capacitance.
Physical implementations of inductors, like any other manifestations of theoretical
devices, have many non-ideal properties. The creation of a good inductor involves
optimizing the many tradeoffs to match performance with needs.
3.2 Parasitic Effects
The inductors being fabricated in the i-UHD process will be used at high frequencies, on
the order of 1 GHz. Operating at radio frequencies introduces many effects not present at
low frequencies. These include skin depth, proximity effect, capacitance, and eddy
currents.
3.2.1 Skin Depth
Skin depth describes the tendency of electric current to flow along the outer surface of a
conductor. The formula for skin depth is:
2
d=
Table 3.1 shows skin depths for various metals at 1 GHz and 2.5 GHz, frequencies of
interest to the RFIC project.
Material
Relative
3ulk
Skin
Skin
Permeability
Con ductivity
Depth at
Depth at
(Siennens/m)
1 GHz
2.5 GHz
Aluminum
1.0000
3.80E+07
2.58E-06
1.63E-06
Copper
1.0000
5.80E+07
2.09E-06
1.32E-06
Gold
1.0000
4.10E+07
2.49E-06
1.57E-06
4000.0000
1.03E+07
7.84E-08
4.96E-08
600.0000
1.45E+07
1.71 E-07
1.08E-07
Platinum
1.0000
9.30E+06
5.22E-06
3.30E-06
Silver
1.0000
6.10E+07
2.04E-06
1.29E-06
Titanium
1.0002
1.82E+06
1.18E-05
7.46E-06
Iron
Nickel
Table 3.1: Metal Properties and Skin Depths
The i-UHD process uses copper and gold for metal layers. Both metals have skin depths
comparable to the 2 um thickness of the metal layers. This means that copper will
conduct significantly better than gold, resulting in higher quality factors. If the metal
layers were much thicker than the skin depths, the difference between conductivity of
gold and copper would be less because of gold's deeper skin depth.
3.2.2 Proximity Effect
A similar effect to skin depth is the proximity effect. The proximity effect is the
tendency for high frequency currents in nearby conductors to draw closer together. This
effect occurs because currents try to find the path of least impedance. Impedance, Z, is
given by:
Z = R+ jaoL
At low frequencies, impedance derives mainly from resistance. To minimize impedance,
the currents seek the path of least resistance. At higher frequencies, where inductance
begins to dominate the impedance, the currents try to minimize inductance along their
path. In spiral inductors, this causes the currents to tend to flow along the inside edges of
the spirals to minimize the area enclosed by the current path.
3.2.3 Capacitance
Capacitive impedance is given by:
X=
jcoC
As frequency rises, capacitive impedance falls. This allows current to begin flowing
across the insulating region between conductors. The physical reasoning for this is that at
high enough frequencies, the current can oscillate back and forth within the conductors.
This oscillation results in virtual current flow in between the turns instead of current
flowing around through the turns. At the inductor's self resonant frequency (SRF), the
capacitive impedance is equal to the inductive impedance. The inductor behaves more
like a capacitor at frequencies above the SRF.
Capacitance is most problematic when two conductors are physically close to each
other, but far apart along the desired current path. Designers must be careful to avoid
such capacitive short cuts along the current path so the resonant frequency is not reduced.
Figure 4.1 shows examples of capacitive paths for high-frequency current. Current may
flow directly across Cl, from the probe to ground. This capacitance is calibrated out in
the test setup, but that reduces the precision of the measurement. To avoid the effects of
capacitance from probe to ground, two-port test structures are used whenever possible.
C2, C3, and C4 represent capacitance between adjacent rings of the spiral. At high
enough frequency, the current can jump across the rings, resulting in capacitive behavior
and decreased inductance.
Figure 3.1: Capacitive current path
3.2.4 Eddy Currents
When a conductor is in the presence of a uniformly oriented, changing magnetic field,
small circular currents are induced in the conductor. They are called "eddy currents"
because the current profile resembles eddies in flowing water. The changing magnetic
fields generated by a spiral inductor also induce currents in nearby conductors. These
induced currents are also referred to as eddy currents, even though their profile may no
longer resemble eddies. The induction of eddy currents has two effects on the inductor.
First, any current in a resistive material results in energy loss, which translates to a lower
quality factor. Additionally, the induced currents counter the magnetic field of the
inductor, lowering the value of the inductance. A highly conductive material will have
less resistive loss for a given current. This will lower the quality factor less than a
material with moderate conductance. A highly resistive material will not sustain any
eddy currents and have little effect on the inductor.
The current in the coil has a circular profile, creating axially oriented magnetic
fields that penetrate the substrate. These fields tend to induce circular currents in the
substrate, that form an image of the current in the coil, but traveling in the opposite
direction.
Factors to consider regarding eddy currents are the distance to nearby conductors,
their conductivity, and whether or not they are patterned in such a way as to allow
circular image currents to flow. The i-UHD process provides 90 [im of non-conducting
epoxy below the spiral inductor, providing significant isolation from any underlying
conductors. Furthermore, the test inductors were fabricated with no conductors present in
the lower layers of the i-UHD stack, giving over 200 [tm of distance to the silicon
substrate. Therfore, eddy currents are not expected to affect the inductor performance.
3.3 Quality Factor
In addition to inductance, quality factor is an important attribute of real inductors. The
quality factor refers to the ratio of the amount of energy stored by the inductor in one
cycle to the energy dissipated during the cycle. Therefore, the quality factor is related to
the ratio of inductance to parasitic resistance. To maximize quality factor for a given
value of inductance, resistive parasitics like the skin effect, proximity effect, and eddy
currents need to be minimized. Techniques for minimizing the resistive parasitics will be
discussed in Chapter 4.
3.4 Mutual Inductance
The derivation for the magnetic energy stored by an inductor is shown in equations [3.xx
to 3.xx]. If a single turn loop has an inductance of L, the energy that a current, I, would
create is:
E =L12
2
A coil with N coincident turns, with each turn carrying a current,
I
, would have exactly
the same current profile as the single turn carrying current, I. Therefore, the magnetic
energy must be the same for the N turn coil. If the N turn coil has an inductance of L',
the following must hold:
1
_
I
-LI 2 -L'
2
[2
Ni
From equation [above], it is clear that for an N turn coil:
L'= N 2L
The increased inductance associated with multiple turns can be explained by the concept
of mutual inductance. When two conductors induce magnetic fields in the same space,
they are said to be magnetically coupled. The degree to which the conductors share
magnetic fields is known as the coupling coefficient, k. The mutual inductance of two
conductors is given by the formula:
M=k 4L 2
The mutual inductance of concentric turns of spiral inductors is what motivates
the spiral geometry. The mutual inductance is maximized by keeping the turns as close
together as possible.
Chapter 4
Inductor Design
I IrOW__
I
L.J
rr
A
C
L=JL
D0
:
=
!_,70..
!'
U
I"""
G
H
L0
--
-7---
L
Figure 4.1: Spiral Inductor Test Layout
4.1 Inductors in i-UHD
4.1.1 Properties of Interest
The properties of the inductors fabricated in the i-UHD process to be controlled are
inductance, quality factor, resonant frequency, and physical size. The value of
inductance required is dictated by the circuit application. The resonant frequency needs
to be substantially higher than the operating frequency to maintain predictable inductive
behavior. A possible goal of optimization can be to minimize physical size while
achieving the quality factor required by the application.
The inductance of a spiral inductor depends on a few different factors. The length
of the current path creates self-inductance. A general rule of thumb for self-inductance is
10 nH/cm [5]. The spiral geometry allows a long length of conductor to be placed in a
small space to form an inductor. Another factor affecting inductance is the mutual
inductance between different parts of the current path. In a spiral, the multiple turns store
their energy in the same magnetic field, reinforcing each other. The total inductance is
the sum of the self-inductance of each turn and the mutual inductances of every
combination of turns. So, if coupling between turns is high, mutual inductance can
become the dominant source of inductance.
The quality factors of i-UHD fabricated inductors depend primarily on the
resistance of the traces. Losses due to eddy currents induced in nearby materials and
radiative losses can also lower the quality factor. Resonant frequency is reduced by
parasitic capacitances in the inductor.
4.1.2 Design Choices
The first decision to make was between using copper or gold for the inductor
traces. As discussed in section 3.2.1, the skin depth of copper is high enough, even at 2.5
GHz, to penetrate into the 2 um thick traces. That makes copper a significantly lower
resistance choice than gold.
The second choice was between circular or square spiral inductors. Both
geometries have their respective advantages. Square spirals offer efficient utilization of
space, giving slightly higher inductance values than circular spirals in a fixed amount of
space. Square spirals are also easier to draw and their theoretical inductance values can
be calculated by treating them as a series of straight conductors that are parallel or
perpendicular to each other. Circular spirals give higher quality factors because they
avoid the sharp turns that cause radiative losses in squares. Given the advanced layout
and simulation software currently available, the quality factor advantages of circular
spirals were chosen over the efficient packing of square spirals.
Varying the inner radius of an inductor also results in a tradeoff between
inductance and quality factor. Using a lower inner radius allows more trace length to be
placed in the same area, resulting in higher inductance. However, the coupling factor of
the innermost coils with the rest of the coils is lower so the added resistive losses are
relatively more prominent for the given increase in inductance, lowering the quality
factor.
The spacing between coils affects the parasitic capacitance. Decreasing the
spacing increases the capacitance. However, less spacing between turns allows for more
turns in a given area and greater magnetic coupling between the turns. Minimizing
spacing gives maximum inductance values, but the benefits to the self-resonant frequency
of increased spacing between turns may be necessary if self-resonant frequency is a
constraining variable.
Lowering the width of the traces allows more turns in the same area, increasing
inductance. The capacitance will also be reduced because of the smaller conductors. At
low frequencies, the resistance will rise proportionally to the decrease in width because
the cross section of the current path is reduced. At frequencies where the skin effect is
dominant, the increase in resistance will be lower because the current flow will be on the
surface of the conductor and only the top and bottom surfaces will be reduced in size.
When the proximity effect begins to dominate at the highest frequencies, there should be
little change in resistance because most of the current will be flowing on the inner or
outer surfaces of the conductor. The loss in quality factor with lower trace widths will
vary depending on the frequency of operation and the skin depth and proximity effects.
Increasing the thickness of the traces proportionally reduces the parasitic
resistance of the coil both at low frequency and at frequencies where the proximity effect
dominates. The accompanying disadvantage is an increase in capacitance.
In summary, varying factors such as width, spacing, thickness, inner radius, and
shape of the spiral affects the inductance, quality factor, and self-resonant frequencies in
intricate ways, with different effects at different frequencies.
4.1.3 Ground Planes
Ground planes are sometimes used underneath spiral inductors in attempts to
increase quality factor or provide isolation from underlying circuitry. In silicon
processes, eddy currents in the substrate can be a major source of resistive loss. A
ground plane allows the eddy currents to occur in a lower impedance material, reducing
the energy loss. However, the eddy currents in the low impedance ground plane counter
most of the magnetic field and prevent the field from extending below the ground plane.
This nearly halves the inductance of the inductor by allowing most of the magnetic field
to extend only above the inductor. Increasing the distance to the ground plane can help,
but the material in between the inductor and ground plane must not be as lossy as the
substrate from which the ground plane is providing shielding.
One common solution used to maintain inductance while reducing eddy current
losses is to place a patterned ground shield below the inductor.
Figure 4.2: Patterned Ground Shield
The radial slits in the ground shield prevent image currents of the inductor current from
flowing and canceling the magnetic field. This reduces the shielding effect of the ground
shield, but still allows smaller loops of eddy currents to flow. By blocking only eddy
currents that are not images of the main current flow, the ground shield reduces resistive
losses while maintaining the magnetic fields that hold the energy of the inductor. This
has been shown to increase the quality factors of inductors 25-36% [28][29][30].
In the i-UHD process, the SU-8 epoxy substrate is not conductive and does not
cause resistive loss. Any conductive devices below the inductor are farther than 90 gm
away. Therefore, ground shields would be of little benefit to the i-UHD inductors
considered here.
4.1.4 Alternative Topologies
Discrete inductors are generally coils of wire, sometimes with a ferromagnetic core.
Inductors fabricated in photolithographic processes are usually spirals because they are
the simplest way to create long, magnetically coupled current paths. The main drawback
with spirals is that the fields extend above and below the inductors. Toroidal inductors
solve this problem by keeping induced magnetic fields primarily inside the toroidal
structure. They are effectively orthogonal complements to spiral inductors because the
current flows and magnetic field paths switch orientations. This reduces the possibility of
magnetic interference with underlying circuit elements or other inductors. It also reduces
induced eddy currents, allowing toroidal inductors to achieve quality factors higher than
most spirals [32].
In the i-UHD process, with the current fabrication capabilities, the minimum size
of a toroidal inductor would be approximately 1 mm square. That is a little too large for
most applications, but may be a prudent way to fabricate inductors of the highest values.
Another issue is the high number of vias required for a toroid. Vias are less conductive
than the traces because they are not solid conductors, which would increase resistive
losses in a toroid. However, as the i-UHD process improves, toroidal inductors may
become viable alternatives to spirals.
Another way to prevent magnetic fields from extending below the inductor,
without canceling them as a ground plane does, is to provide an alternative path using
magnetically permeable materials. A highly permeable sheet placed below the inductor
would channel the magnetic fields out to the sides of the inductor. A more magnetically
permeable path for the fields would also increase the inductance. SU-8 epoxy can be
doped with magnetically permeable nickel particles, so such an inductor could be
fabricated. Unfortunately, magnetically permeable materials exhibit hysteresis, which
results in energy loss every time the orientation of the magnetic field changes. Therefore,
the hysteretic losses rise proportionally with frequency. This makes the use of
magnetically permeable materials impossible at radio frequencies.
Chapter 5
Multi-Chip Modules
5.1 MCM-D at Draper
Prior to the development of i-UHD, Draper's cutting-edge packaging technology was
MCM-D, or Multi-Chip Module-Deposited. Work had been performed in designing
spiral inductors for use in MCM-D [38]. A tool was developed for selecting spiral
inductors of maximum quality factor for a given inductance, area, and operating
frequency.
The MCM-D process involves stacking bare chip dice in layers separated by 25
um polyimide dielectric insulators. Each die layer includes a spacer to fill the gaps
between the dice. This arrangement requires all dice to have the same 150 um thickness.
Connections between layers are made with laser drilled vias. Metal interconnect layers
are 5 um thick. In the MCM-D fabrication, metal trace widths exhibited fabrication
errors of over 10 um, making minimum widths of about 50 um reasonable. Also, the via
depth was limited to 25 um, which causes high parasitic capacitance in two-layer spiral
inductors as seen in Chapter 4. The i-UHD process is a significant improvement because
it allows for smaller interconnects and vias through die layers, along with the capability
to integrate wafers of varying thicknesses.
5.2 I-UHD Process
Draper's Integrated Ultra High Density (i-UHD) process was developed to miniaturize
the packaging of electronic circuits. Since the 1960s, integrated circuits (IC's) have
combined numerous electronic components onto one silicon chip. These IC's are usually
enclosed in a plastic package and soldered to a printed circuit board. Draper's i-UHD
process takes packaging one step further by combining several IC's into one package.
Multi-chip modules have combined multiple IC's into one package before, but Draper's
i-UHD process allows the IC's to be placed on different layers, allowing more compact
form factors. The IC's in the multiple layers of the i-UHD process are connected by
photodefined vias.
5.2.1 Fabrication Sequence
0.1 um Ti,adheres Cu or Auto Si
[I0.1 um A-Si, adheres metd to SU-8
Figure 5.1: Process Diagram
An i-UHD module begins as a 525 urn thick wafer of silicon. 0.1 um of titanium is
sputtered onto the silicon to facilitate adhesion of gold. 1 um of gold is sputtered onto the
titanium, followed by another 0.1 um of titanium on top. That forms the Ti/Au/Ti metal
layer-0. To form a pattern of connections in the metal, a layer of photoresist is spun onto
the surface and exposed to ultraviolet light through a mask. This removes the photoresist
in the areas above the metal to be removed. Then, metal layer-0 is wet-etched, removing
metal wherever it is not protected by the photoresist.
0.1 urn Ti, adheres Cu or Au to Si
Figure 5.2: Metal layer-0
After processing metal layer-0 is complete, a 2 um layer of SU-8 epoxy is pressed
onto the silicon wafer and the 1.2 um of Ti/Au/Ti traces. A hard mask, consisting of a
0.1 um layer of titanium and a 0.1 um layer of aluminum, is sputtered over the SU-8. The
hard mask is wet etched using photoresist, followed by a dry etch to remove the SU-8 not
protected by the hard mask. This leaves adhesive SU-8 pads wherever the silicon dice
are to be placed. The silicon dice are placed on the SU-8 and then 90 um of SU-8 is
pressed flat onto the silicon wafer, metal layer-0 traces, and silicon dice.
-..
-
U.1 Un II,
iers• SUOrAUtoS•0
-
I
Figure 5.3: Die placed, buried in epoxy layer
To connect to the silicon dice and metal layer-0, vias are made in the SU-8. First,
a photo mask is used to expose the SU-8 everywhere except where vias are to be formed.
Exposure to UV cross-links the SU-8 molecules, which prevents them from being
dissolved away. The unexposed areas are chemically removed, forming the wells for the
vias. A 0.1 um layer of amorphous silicon is then deposited onto the SU-8 to adhere the
subsequent metal to the epoxy. 0.1 um of titanium is deposited over the amorphous
silicon, followed by 0.1 um of copper, which acts as the cathode for the subsequent
electroplating.
I/'4
,.,,u.
• T
0.1
um
TI,
adheres
Figure 5.4: Vias drilled, cathodic layer deposited
At this point, 2 um of copper are electroplated into the via wells and the top
surface, forming the vias and metal layer-1. Metal layer-i is finished with 0.1 um of
titanium, for adhesive purposes.
I". •
Cu
or
A .•
Au
to
ZI
Si
0.1 un Ti, adheres Cu or Au to Si
0.1 ur A-Si, adheres metal to SU-8
Figure 5.5: Metal layer-1, unfinished
Just like metal layer-0, metal layer-I is wet-etched using photoresist. This is
followed by more layers of SU-8 adhesive, silicon dice, more SU-8, vias, and metal
interconnect layers.
0.1 umTl,
adheresCuor Auto Si
0.1 um A-Si, adheres metal to SU-81
Figure 5.6: Metal Layer-1
5.2.2 Feature Limitations
The iUHD process has various feature size limitations. The dimensions to consider for
the spiral inductors are the metal trace width, spacing, and thickness. Because the metal
traces are photodefined and etched, the minimum width and spacing are currently both 20
gm. As seen in Figure 3.7, the photoresist which protects metal from being etched away
does not protect the etching agent from attacking the metal from the sides. As the etching
agent penetrates deeper into the metal, it also erodes the metal sideways, underneath the
photoresist.
Figure 5.7: Undercut from etching
The undercut effect limits not only the minimum trace width and spacing, but also the
thickness of the metal layer. If the metal layer is made thicker than 2 gim, the trace
widths and spacings must be proportionally increased because thicker metal causes more
undercut as the etching takes more time.
For the reasons stated in section 4.1.2, using the maximum thickness of 2 gm is
optimal for minimizing parasitic resistance. Any increases in metallization layer
thickness in the iUHD process would result in valuable increases in quality factors for
inductors. Also, reductions in the minimum spacing would allow for more inductance in
a given area. Reducing minimum trace widths is the least important goal for future
developments in the iUHD process.
5.2.3 Process Results
The iUHD test run at Draper began successfully and metal layers 0 and 1 were fabricated.
Vias between the layers with minimum diameters of 30 um yielded 100% success rates.
The inductors designed for this thesis were to be fabricated in metal layers 2 and 3. Vias
between metal layers 2 and 3 were successfully created in some areas, but were
completely missing in others. An analysis of the failure determined that feature
definition was dependent of surface chemistry and exposure time. It was hypothesized
that some areas were over exposed during photodefinition, due to the optical clarity of the
SU-8 and the reflectivity of metal layer 1, causing the vias to close up. Metal areas in
layer 1 reflected UV light back up through the SU-8, exposing areas that were supposed
to be protected to form vias.
UV Light Source
I1lIII11111
11
II111111111 111111 I
Photoresist
-n
proper via
formation
SU-8
Copper
via closed by
stray UV
reflections
Figure 5.8: Overexposure of Vias
Multiple solutions were proposed for the uneven exposure problem. One idea
was to coat the lower metal layers with an anti-reflective coating so they would not
interfere with fabrication of subsequent layers. Another proposal suggested using two
masks for each layer, so that areas that would be overexposed could be exposed for less
time and areas with no underlying metal could be exposed longer. A third solution was
to tweak the exposure time so that areas with and without underlying metal would both
be satisfactorily exposed. In the end, the lower wavelengths were filtered out during
exposure, which made feature definition relatively independent of surface chemistry and
exposure time.
Once the via exposure problem was handled, the process resumed fabrication.
Unfortunately, the curing of the additional SU-8 on top of existing SU-8 caused excessive
stresses that were beyond its Young's modulus of approximately 4.4 GPa [37]. This
caused cracks in the structure and the process failed. The SU-8 stress issues are being
resolved at the time of this thesis' submission. Therefore, the focus of this thesis has
shifted more to the design of a VCO to utilize the high performance inductors discussed.
Suggested experimental setups are included in the appendix as future work once the
iUHD process successfully fabricates the inductors.
Chapter 6
Ansoft HFSS
6.1 HFSS Introduction
Ansoft Corporation's High Frequency Structure Simulator (HFSS), version 9.2.1, was
used to simulate the inductor models created. HFSS is a powerful tool that allows
designers to define metal structures and simulate their performance. It is commonly used
for designing components such as antennas, waveguides, and on-chip passives.
6.2 FEA Techniques
HFSS uses Finite Element Analysis (FEA) to find electromagnetic properties of a
structure and extract the s-parameters at user-designated ports. The user must define the
structure and choose material properties for its parts. Additionally, boundary conditions
must be specified for each outer surface and an initial solution frequency must be chosen.
The software begins by dividing the structure into a mesh of tetrahedra, which are not
necessarily regular. Maxwell's equations are applied to each tetrahedron and electric and
magnetic fields are found at all points in the structure. HFSS uses a process called
"adaptive mesh refinement" to improve the accuracy of the solution. In areas with high
field gradients, the software breaks up the tetrahedra into smaller pieces before
performing another solution pass. The mesh is refined and solved repeatedly until the
variation in the s-parameters with each solution pass is lower than some threshold,
normally set to 2%.
Once the final s-parameters are found at the solution frequency, HFSS can find sparameters over a range of frequencies. If the user selects an interpolating frequency
sweep, the same mesh is solved at different frequencies until the values of the sparameters begin to fall within a specified threshold of the s-parameters predicted by
interpolating the values at adjacent frequencies. This threshold is normally set to 0.5%.
Once the interpolating sweep is complete, HFSS has found s-parameters for the ports of
the structure as a function of frequency.
6.3 Inductor Setup
J
Figure 6.1: HFSS Setup for 2.5 turn spiral.
Various spiral inductors were designed in HFSS to replicate the inductors to be fabricated
as closely as possible. Ansoft recommends that the space enclosing the structure be at
least 50% larger than the structure itself to give space for the fields to travel and couple
with other parts of the structure. Therefore, a large 2 mm x 2 mm x 400 um epoxy
substrate with 400 um of air above it was created. The outer boundaries of the air/epoxy
were set as radiative boundaries so that no fields would be reflected back inside. The
spiral was created using a parametric model, which allowed the number of turns, inner
radius, trace width, spacing, and thickness to be varied. Figure 6.1 shows a 2.5 turn spiral
with a 160 um inner radius, 30 um width and spacing, and 2 um thickness. Also, the
depth of the underpass and via length to the underpass was parametric so that the distance
to the lower metal layer could also be varied. The depth was set to 10 um in Figure 6.1.
Each port of the spiral was made with HFSS's "perfect electrical conductor"
material and consists of a rectangular prism with 3 10 um x 10 um pins coming down to
contact the ground ring and inductor pads. The spacing between the pins is 150 um,
equal to the probe pitch of the Cascade Microtech probe station.
6.4 Solution Results
Solving each inductor structure for s-parameters from DC to 10 GHz took between 2
minutes and 3 hours, depending on the number of turns of the spiral. The solution time
increased approximately linearly with the complexity of the structure until it reached a
point where the computation required more memory than the installed RAM and it began
to use hard disk space. The machine used had a 3.2 GHz Pentium 4 processor and 1 GB
of RAM running Microsoft Windows 2000. There were three signs that indicated when
the solver exceeded available RAM and began to use the hard disk. First, the CPU usage
would drop from 100% to less than 20% because the data flow was too slow to use all the
computational power. Second, the system memory use would exceed 1 GB, the installed
RAM capacity. Third, the hard disk access indicator light would begin flashing rapidly
and regular disk access sounds could be heard. Therefore, additional installed RAM is
recommended for further use of HFSS for modeling larger structures. Current 32 bit
Windows systems have a RAM limitation of 4 GB because they can only access 2^32
RAM addresses. HFSS v. 9.2.1 can also be run on Sun Solaris systems, which support 16
GB or more of RAM. However, because computation speeds were significantly lower on
the Solaris server available at Draper, using HFSS version 10 on a 64-bit Windows
system with large amounts of RAM is recommended for further computationally
intensive work with HFSS, such as simulating dual-layer spirals or inductors with values
greater than about 20 nH. Table 6.1 shows the amount of CPU time required to solve
inductor structures at a single frequency as a function of the number of turns.
Performance for Single Frequency Solution
Number of Turns
Minutes of CPU Time
1
3
2
8
3
18
4
24
5
30
6
98
Table 6.1: Inductor Size vs. Solution Time
Figure 6.2: Magnetic field direction and intensity for 2.5 turn spiral.
Figure 6.2 shows the directions of the magnetic field induced by the spiral
inductor in the air. The field points upwards in the center of the inductor, implying that
the current is flowing counter-clockwise during the phase at which this field was
modeled. However, because the return current through the ground ring travels in the +X
direction on both sides, the field on the farther half of the inductor goes back down
between the spiral and the ground ring while the field on the nearer half goes back up
over the ground ring. This demonstrates that the fields behave as expected.
Figure 6.3: Magnetic field intensity for 90 turn toroidal inductor.
One of the initial designs created was a 90-turn toroid, about 1 mm x 1 mm in
size. This topology was not pursued further because it was too large for Draper's
applications and the resistive losses incurred by 180 vias would make it impractical to
fabricate. However, a simulation of the magnetic field intensity shows that most of the
field is contained within the turns of the toroid. The darker area at the center of the
inductor, in Figure 6.3, shows the field induced in the center by the effectively 1-turn
loop created by the toroid.
Ansolt Corporation
Inductance
3.5 turn spiral
28 Jun 2006
17:01:03
Y1--0L11
4 rM-"
1.90E.08-
r
i-
00
0
0F0
0.-- T
0.0
X1= 2.70GHz
YI= 5.39E-09
----
-
Iq
200
"rq
[Oz)
-------3.I
X2= 2.80GHz
Y2= 5.43E-09
&a
~--Figure 6.4: Inductance of 3.5 turn spiral.
Figure 6.4 shows the inductance of a 3.5 turn spiral inductor. The inductance is
calculated using equation 7.6. The value calculated appears to rise with frequency
because the capacitance affects the imaginary part of the y-parameters.
17:02:23
Ansoft Corporation
qualty factor
3.5 turn spiral
28 Jun 2006
" 1
-
Y1-0abs(Q11)
-
Y1--abs(Q22)
30.00-
20.00-
10.00-
0.000.(
X1= 270GHz
Y1= 28.98
D
O
~2.(1
2A0
YX2=
280GHz
IY2= 29.34
0SII
D
4LI
6.A
0
8.10
10.
Freq [GHz]
X3= 3.80GHz
1Y3= 31.35
Figure 6.5: Quality factor of 3.5 turn spiral, measured at both ports.
The quality factor is calculated using equation 7.8. The self-resonant frequency can be
found by locating the frequency at which the value calculated drops to 0. This is
discussed in Chapter 7. There are two plotted curves for Q because it is calculated at
both ports. They are not identical because the inductor is not symmetric and the
arrangement of parasitic capacitances is different. However, both curves are similar and
can be averaged to estimate the Q of the actual inductor.
Chapter 7
Fabrication and Testing
7.1 Measurement
The fabricated inductor structures were going to be measured using an Agilent E8363B
network analyzer connected to a Cascade Microtech Model 44 probe station with 150 ptm
probes.
Figure 7.1: Measurement Setup
For each of the thirteen test setups, two-port s-parameters were to be measured for
frequencies ranging from DC to 10 GHz in 10 MHz steps. These measured Y-parameter
data would have been compiled into a spreadsheet to be processed and compared to the
values found by simulation in HFSS.
7.1.1 Probe Calibration
For the probe station to produce accurate measurements, the electrical characteristics of
the probes themselves must be characterized and removed from the measurements. This
is done by a procedure known as SOLT, which stands for short, open, load, and through.
In the calibration process, the network analyzer made measurements with each probe of
terminators that were known to be short circuits, open circuits, or 50 Ohm loads. Also,
both terminals were connected to each other and a through measurement was taken. This
calibration must be performed multiple times per day because environmental changes
such as thermal expansion can cause the electromagnetic properties of the cables and
connectors to vary noticeably at multiple GHz frequencies.
7.1.2 Data Extraction
The measured S-parameters were to be converted to Y-parameters using the formulas [6]:
1
y,=
(1+s 22 X1-s 11 )+sS12S21
ZO (1+ sI X1+s
1
Y12
Zo
1
y21
Zo
y22
1
Zo
22)-S 12S21
-2"s
12
2
(1+s 11 )(1+
22)-
-2-s
(7.2)
S 12 S21
l
2
(1+ s )(l + s22 - SI2 S21
(1+ S,1)(1-
(7.1)
2
S22)+
S12S21
(1+ S1I)(1 + s 22)-
S2S21
(7.3)
(7.4)
Y-parameters are called admittance parameters because they represent the current as a
function of applied voltage. At low frequencies, where capacitance can be neglected, an
inductor can be modeled as an ideal inductor in series with an ideal resistor. This model
gives us the equation:
Yl
-
1
R + jw L
R- jca)L
R2
+
2L2
(7.5)
Equation 7.5 shows that, at frequencies low enough that capacitive effects are small,
inductance can be represented by:
L=I
- im
(7.6)
The equation for quality factor:
CwL
Q =
(7.7)
R
Using equations 7.5 and 7.7 we can obtain:
Q
(y
)
re(yl1 )
(7.8)
At the self-resonant frequency, the inductive and capacitive reactances of the structure
complement each other and the admittance appears as only a conductance. At that point,
im(y, ) = 0. Therefore, S.R.F can be found by observing the point at which Q is zero, as
defined in Equation 7.8.
7.1.3 Interference Measurement
There were three test structures (B, F, and J) to be used to characterize the relationship
between inductor spacing and coupling coefficient. Because these six coils are measured
using only one port, the equation to determine their inductance is different:
L, = 1im(z
11 )
and
L2 =
im(z 22)
(8.8)
The mutual inductance between two coils in a structure is given by:
M
i
-i{
(8.9)
The coupling coefficient can be calculated from those values using equation 8.10:
k MM
(8.10)
Chapter 8
RFIC VCO using iUHD Process
To demonstrate the usefulness of the high Q inductors available in the iUHD process, a
VCO was designed and simulated. The VCO was chosen as the target application
because it is the part of the RF circuit that imposes the most stringent demands on
inductor specifications. As discussed in Chapter 2, inductor quality factor is directly
related to the phase noise of a VCO.
8.1 Contemporary VCO Design Improvements
Around the mid-1990's, integrated circuit technology reached a point at which fabricating
VCO's in an IC became feasible [13]. This was primarily because increases in transistor
transition frequencies made operation in the 800 MHz to 2.5 GHz bands possible. Since
then, there have been numerous papers written on monolithic VCO designs. They
illustrate many innovative ways to improve VCO performance measures such as phase
noise and tuning range. Because monolithic VCO's are generally used in portable
devices due to their small size, low power consumption is also an important goal.
Challenges faced by monolithic VCO designs are the low power supply voltages and
relatively poor quality factor inductors.
Many researchers use CMOS IC technology for VCO designs for cost and
convenience reasons. CMOS fabrication requires fewer masks and testing can be
performed on wafers before packaging them, keeping manufacturing times short and
costs low [35]. BiCMOS, on the other hand, allows fabrication of exotic structures such
as film capacitors and resistors, at the cost of incorporating additional masks.
Additionally, BiCMOS designs offer smaller physical sizes than CMOS. To achieve the
best performance, commercial designers currently use RFIC-specific BiCMOS processes
for VCO's [13]. Draper's RFIC project will use a SiGe BiCMOS process. Transistors in
the SiGe process exhibit particularly low flicker noise and low turn-on voltages [19][34].
Because Draper is not involved in a commercial application, the added cost of choosing
SiGe BiCMOS is not an issue.
Most monolithic VCO's now use a differential architecture, which helps to reject
common mode noise such as power supply fluctuations. Differential signals, used inchip, help prevent unwanted coupling of signals by reducing the area enclosed by the
path of signal currents. In single-ended architectures, the signal current will flow along a
trace and the return current will flow through the ground plane. This causes potential
coupling with nearby signals. With a differential connection, the return current will flow
near the signal current, nearly canceling the magnetic field induced by the current flow.
This reduces interference with other parts of the circuit. Differential connections are also
important off-chip because of the large parasitic resistance, capacitance, and inductance
of the lengthy connections. The large parasitics affect both of the differential connections
equally, which reduces their effect because common-mode effects are rejected in
differential circuits. The use of differential signals also underlies two key techniques for
improving VCO performance.
8.1.1 Symmetric Inductors
Substituting one center-tapped symmetric inductor for the two separate inductors
in a differential VCO design provides a dramatic improvement because of the mutual
inductance added [15][23][24]. Additionally, by interleaving turns, it reduces
capacitance by increasing the spacing between consecutive turns in the current path. The
area of the symmetric inductor may also be less than the combined area of the two
inductors replaced because of the shared hollow area in the center.
Source: Wireless Design Magazine
Figure 8.1: Octagonal Symmetrical Inductor
8.1.2 Tuning
A VCO is generally tuned by varying the varactor control voltage, changing the
capacitance of the tank. The change in frequency divided by change in voltage is called
the VCO gain constant, or Kvco. Kvco depends on the varactor gain (its capacitance
sensitivity to voltage changes) and the ratio of varactor capacitance to the fixed
capacitance. A high VCO gain constant increases phase noise because any fluctuations
of the varactor control voltage translate into greater fluctuations in frequency.
Differential tuning, which uses two varactors in the place of one, reduces phase noise by
nearly eliminating the effect of common mode voltage fluctuations [20].
Frequency vs. Capacitance with 3 nH Inductor.
3
2.8
-------
Frequency
(GHz)
2.6
2.4
---------
2.2
2
-·-------
1.8
1.6
·-·--------
1.4
-----·~-----
1.2
1
no
1
2
3
4
5
6
7
8
9
10
Capacitance (pF)
Figure 8.2: Varactor Tuning
Fixed capacitors must be used along with varactors in a VCO because varactors
have greater series resistance than capacitors and therefore lower quality factors. Also,
varactors exhibit non-linear values of capacitance as a function of voltage. By combining
a varactor in series and/or in parallel with fixed capacitors, overall quality factor and
linearity can be increased. In addition to the non-linearity of varactors, the frequency of
oscillation is a non-linear function of capacitance, as shown in Figure 8.2.
Discrete tuning schemes paired with varactor tuning allow greater tuning range
while keeping Kvco low and allow for the possibility of switching bands. A common
method for discrete tuning of a VCO is to connect additional capacitors in parallel with
the varactor using MOSFET switches [21][33]. Draper's RFIC project aims to cover the
whole range of bands from 800 MHz to 2.5 GHz. To avoid the increased noise and
losses that come with MOSFET switches, the RFIC project will allow designers to select
from different inductor sizes to determine the frequency range. Another possible way to
discretely tune the VCO is to include connections for an external capacitor. That way, a
single RFIC design would be able to be configured for operation at different frequencies
by simply changing the external capacitor value.
54
8.1.3 Tail Current
The differential VCO has a current source connected to the emitters of the transistor pair
to set their bias currents. Usually, this current source is implemented using a current
mirror. The gain of the current mirror is usually high, on the order of 10, to minimize
power consumption. Unfortunately, the high gain results in the amplification of any
current fluctuations due to power supply noise. Also, the transistor used in the current
mirror generates additional flicker noise. There are various solutions to this problem.
Some VCO designs eliminate the current source and substitute a resistor to avoid the
flicker noise [23]. Other designs place a choke inductor in series with the current source
to block noise [16]. In CMOS VCOs, a capacitor placed on the drain of the current
source can reduce the noise in the differential transistors by reducing the current through
them during certain parts of the oscillation cycle [20].
8.1.4 Quadrature Generation
VCOs used in CDMA applications must provide both in-phase and quadrature-phase
oscillation to modulate the I and Q signals. This can be accomplished by different
methods. Using two cross-coupled differential VCOs such that their output phase must
be 90 degrees apart (see Fig. 10.2) requires twice the area as a single VCO, but consumes
the least amount of power and provides the highest output swing [21][23]. A common
alternative is to make a single VCO that operates at double the frequency and use flipflops to divide the frequency by two, providing both in-phase and quadrature outputs.
This requires less area, because the VCO is smaller, but the power consumption is greater
due to the flip-flops operating at high frequency.
lout +
Figure 8.3: Cross-Coupled VCO's for Quadrature Generation
Figure 8.4: Double-Frequency VCO with Flip-Flops for Quadrature Generation
8.1.5 Harmonic Tuning
Minimizing phase noise does not require production of a perfect sine wave. A square
wave contains the fundamental frequency and a series of odd harmonics. Since the
harmonics are far from the fundamental, they can easily be filtered out in later stages.
Low phase noise requires avoiding small deviations from the desired frequency, but not
necessarily harmonics. Adding filters to remove the even harmonics of the tank can
reduce phase noise by reducing fluctuations in tail current and voltage, even though this
makes the output look more square than sine [16].
8.2 Performance Specifications
Initially, a CDMA (code division multiple access) specification was chosen as the goal,
but an 802.11 wireless LAN specification was chosen as a more reasonable first goal.
The 802.11 VCO specifications were drawn from a combination of the official IEEE
802.11 document [40], prior work that also implemented an 802.11 VCO in SiGe
BiCMOS technology [39], and requirements defined in Draper's RFIC project proposal.
Table 8.1 lists the specifications for the WLAN VCO. The startup/settling time is
the amount of time required for the VCO to begin oscillating and stabilize at a constant
oscillation voltage when started from rest. The VCO designed here demonstrated a
startup + settling time of less than 2 ns. This is expected, because the startup and settling
times will be dominated by the phase lock loop (PLL). The PLL is a feedback controller
that controls the VCO tuning voltage to keep the output frequency at the desired value. It
will take some amount of time for the PLL to adjust the tuning voltage until the desired
frequency is reached. The settling time is critical for systems that repeatedly change
frequencies, such as those that employ frequency multiplexing or frequency hopping, like
802.11b.
The pulling figure is found by inserting a transmission line between the VCO
output and its load and varying the length of the transmission line through a full 360
degrees. The maximum variation in VCO oscillation frequency throughout the load
phase sweep is the pulling figure. No pulling figure specification was given for the
WLAN application. Pulling figures are usually met by buffering the VCO output with an
amplifier. An output buffer amplifier is recommended for use with this VCO because
load resistance is the variable that affects phase noise the most.
The pushing figure measures how much the oscillation frequency varies with
changes in supply voltage. The VCO designed here exhibited a 145 kHz change in
output frequency when supply voltage was varied between 2.7 and 3.3 V, giving an
average pushing figure of 242 kHz/V. Initially, the VCO was simulated using an ideal
current source and the pushing figure was 0, so the 242 kHz/V pushing figure can be
attributed to the variations in bias current with power supply voltage changes.
Phase noise is the measure of the noise present at frequencies close to the
oscillation frequency. It is measured in terms of decibels below the carrier at a specified
offset frequency. When a VCO is used to modulate the transmitted signal, limits on
interference with nearby bands drive phase noise limits. When the VCO is used to
demodulate a received signal, phase noise results in demodulation of nearby frequencies,
which adds noise to the extracted signal and lowers the signal-to-noise ratio. Limiting
phase noise helps meet signal-to-noise ratio requirements on the receive side. Because
phase noise generally drops at 20 dB/decade, as described in Section 2.1.2, phase noise
specified at only a few frequencies tends to determine phase noise across the spectrum.
Meeting the phase noise specification was the most challenging part of designing the
VCO.
The current specification determines the power drawn by the VCO. For high load
impedances, less current reduces noise by lowering the non-linearity effects of the
transistors. However, with the 200 Ohm load used in this VCO, more current was
necessary to provide enough gain to overcome the losses in the loaded tank. The
maximum current value was used, 6.8 mA, and more current would have further reduced
phase noise.
The 802.11 spec uses the ISM band frequency range from 2.412 GHz to 2.484
GHz. A minimum tuning range of 100 MHz and center frequency of 2.45 GHz gives the
VCO the ability to operate between 2.4 and 2.5 GHz. To account for variations in
operating frequency, the band was made wider. The tuning range can easily be set by
varying the ratio of varactor capacitance to fixed capacitance. With the tuning range of
2.386 GHz to 2.510 GHz for control voltages of 0.5 to 2.5 V, Kvco has an average value
of 62 MHz/V.
The VCO is designed to function with a 3 V power supply, but the voltage may
range from 2.7 V to 3.3 V if power is coming from a lithium cell or other battery. Also,
power supplies in computers and laptops may experience voltage variations and the VCO
must continue to function properly.
Specification
Value
Unit
System Drivers
Startup/Settling Time
<1
us
Frequency multiplexing
Pulling Figure
unspecified
+/-kHz
Varying load impedance
Pushing Figure
< 1.3
MHz / V
Battery voltage changes
-106@600,
-110@ 1000
dBc/Hz@kHz
offset
Interference with nearby
bands, signal to noise ratio
Current
<=
6.8 mA
Power consumption
Tuning Range
100 MHz
MHz
802.1 lb specified range
Center Frequency
2.45
GHz
802.11 b specification
Vcc
2.7-3.3
V
Variations of 3 V power
source
Table 8.1: WLAN VCO Specifications
8.3 Design Implementation
Figure 8.5: Differential Clapp VCO
Figure 8.5 shows the circuit schematic of the VCO designed. The varactor tuned tank
oscillator is seen at the top, coupled to the negative resistance generator through an
oscillator port. The oscillator port is a measurement tool provided in ADS to make
measurements of oscillating circuits and does not affect the behavior of the circuit. The
differential output voltage is measured using a 2-port box that takes V+ and V- and
outputs the sum and difference of the two. At the bottom and left of the circuit are the 3
current mirrors used to set the VCO bias' current.
The VCO was implemented as a differential Clapp oscillator. A Clapp oscillator
was chosen over a Hartley because a Hartley oscillator would have required two
inductors instead of one for each half of the circuit. A Colpitts oscillator would have
used one fewer capacitor in each half, by placing the varactor with the feedback
capacitors at the base of the transistor. However, as discussed in Section 2.1.1, the Clapp
arrangement keeps the output voltage constant throughout the tuning range. Figures 8.6
and 8.7 show that the output voltage remains at 400 mV P-P at both ends of the tuning
range, verifying this property of the Clapp oscillator.
Initially, the 3.6 nH inductor with a Q of approximately 30 and S.R.F. of 10.8
GHz, letter K in Figure 4.1, was chosen for this VCO. It has the highest Q among the
inductors simulated, small size, and its relatively low inductance seemed to make it
suitable for operation at 2.4-2.5 GHz. When designed with that inductor, the limiting
factor for phase noise seemed to be the VCO load impedance. The reason for this was
that the loaded Q of the tank depended more on the energy lost to the load than the
energy lost in the inductor. To find a more appropriate inductor size, the equivalent
series inductance and resistance of a parallel L-R combination was analyzed:
R 2 L2R + jo9LR
R IIjwL =
R2 + 02 L2
2
(8.1)
Giving:
S
R' =
co 2L2 R
R2 +
w 2L2
,
and L'
j LR 2
R2 + 2L2
(8.2)
(8.2)
Table 8.2 shows the results of applying Eqs. 8.2 to 3.6 nH and 1.6 nH inductors in
parallel with the 100 Ohm load impedance seen by each half of the circuit (total load
resistance is 200 Ohms).
L (nH)
R (Ohms)
f (GHz)
L' (nH)
R' (Ohms)
Q'
3.6
100
2.45
2.75
23.5
1.8
1.6
100
2.45
1.51
5.72
4.1
Table 8.2: Loaded Inductor Q
Clearly, the smaller inductor offers better loaded Q, so a 1.6 nH inductance was chosen
for the design. Further reductions in inductance would likely sacrifice the Q of the
inductor because resistances in connecting traces would become more dominant. To
account for the lower effective Q of smaller inductors, the 1.6 nH inductor was modeled
with a series resistance of 2 Ohms, giving it an approximate Q of 12.
To simulate the performance that would be achieved if both the 1.6 nH inductors
were interwoven to form a single symmetric inductor, a coupling coefficient of 0.21 was
introduced between them, as a mutual inductance. This effectively increases the Q by
increasing the total inductance without increasing the parasitic resistance of the inductor.
Several capacitors needed to be sized for the VCO. In each half, there is a
capacitive divider pair to provide feedback to the transistor, a capacitor as part of the
tank, and the diode varactor. The varactor size was chosen as 0.8 pF to set the tuning
range of the VCO. The total capacitance, given the value of inductance and mutual
inductance would need to be 2.47 pF for a 2.4 GHz operating frequency. This required
the remaining capacitors to add up to 1.67 pF. A 1.5 pF capacitor was used in the tank
and the bias capacitors have a series capacitance of 0.09 pF, making the total capacitance
approximately 2.39 pF, close to the calculated value of 2.47 pF.
The ratio between the two transistor feedback capacitors was determined by
trying different combinations and observing which combination optimized the tradeoff
between gain and noise. If the capacitor to ground is made larger, there is less feedback,
increasing the gain of the transistor and also the phase noise due to this added gain. On
the other hand, if the capacitor to ground is smaller, there may not be enough gain for the
circuit to oscillate.
Finally, the current biasing circuitry was designed. Initially, a simple BJT current
mirror was used, but the frequency pushing figure was orders of magnitude out of range.
Generally, multistage current mirrors like Wilson or Widlar current mirrors are used for
more accuracy than a basic current mirror. However, in this application, the precision of
the current on the reference side of the mirror is essential while accurate reproduction of
the reference current is of little importance. Using a simple resistor to set the reference
current did not work because voltage supply fluctuations would change the current
through the resistor. To address this, a string of three diodes was used in an attempt to
stabilize the voltage across the reference current resistor. If a resistor had been used to
feed the diodes from the power supply, the current through the diodes would vary greatly
with power supply changes and the diode voltage would not remain constant. Therefore,
a PNP current mirror was used to feed current into the diode chain and reference current
resistor. This improved the pushing figure greatly, but it was still not within the 1.3
MHz/V specification. The same diode concept was repeated, creating a two-stage buffer
to isolate the reference current resistor from changes in power supply voltage. By using a
10:1 BJT area ratio in the final current mirror, the current consumed by the biasing circuit
was kept down to about 2.5 mA while pulling 3.85 mA through the VCO.
The current biasing circuitry added significant phase noise to the VCO, as
expected, due to the flicker noise from the transistor. An 8 nH, 150 Ohm, choke inductor
was placed in series with the current sink [16], along with a 10 pF capacitor on the
collector of the transistor [20] to filter noise and block phase noise.
Results
L
(nH)
R
Vcc
(0) (V)
Vtune
(V)
Inductor Q
Z_load
(0)
Freq
(GHz)
phase noise
@ 1 MHz
Icc
(mA)
Ivco
(mA)
(dBc/Hz)
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
2
2
2
2
2
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
2.7
2.7
2.7
3.3
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
1.3
0.5
2.5
1.3
1.3
1.3
1.3
0.6
0.7
0.8
0.9
1
1.1
1.2
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
12.32742
200 2.452462
11.99187
200 2.385707
12.61908
200 2.510487
12.32785
200 2.452548
12.32712
200 2.452403
4.863453
200 2.418883
12.30261
100 2.447527
12.04504
200 2.396285
12.09423
200 2.406071
12.13991
200 2.415158
12.18248
200 2.423628
12.22229
200 2.431547
12.25963
200 2.438975
12.29474
200 2.445961
12.35914
200 2.458773
12.38878
200 2.464669
12.41691
200 2.470265
12.44365
200 2.475586
12.46913
200 2.480655
12.49344
200
2.48549
12.51666
200
2.49011
12.53888
200 2.494531
12.56017
200 2.498767
12.5806
200 2.502831
12.60022
200 2.506734
Table 8.3: VCO Simulation Results
-112.8
-113
-112.5
-112.8
-112.8
-108.8
-105
-112.9
-112.9
-112.9
-112.9
-112.8
-112.8
-112.8
-112.7
-112.7
-112.7
-112.7
-112.6
-112.6
-112.6
-112.6
-112.6
-112.5
-112.5
6.68
6.35
6.35
6.35
6.99
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
6.35
3.87
3.85
3.85
3.85
3.89
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
3.85
Table 8.3 shows the simulation results as various values were varied. Individual
parameters, such as supply voltage, tuning voltage, inductor Q, and load impedance were
varied individually while holding all other variables constant.
Osciation
frequency
2.386707 GHZ
Phase Noise Plot
m-
,.
I
I",I
I
IX
time, psec
nosrUmq
1.000
=
2.154
4.642
10.00
21.54
48.42
100.0
215.4
H1i
Hk
Hz
HI
464.2 H
1.000 kk
2.164 kH1
4.042 kHz
10.00 kHz
21.654 kH
40.42
klkz
100.0 kHz
215.4 kH
404.2 kHz
1.000
kMH
2.164 M44.842 MH1
10.00 MHz
21.64 Mlz
40.42
MHi
100.0 1I
V tune = 0.5 V
o0.003 +jO.IO0o
vtA f.pnmx
Hz
HN
H,
H
1.81403 +JO.00000
22.50 dec
13.74 dlc
4.484 deo
-4.880
doC
-14.06 dCB
-22.77 dBo
-30.00
dbo
-38.47 doC
-46.64 dB0
-62.65dEo
-50.34 d4o
-0.07 dBc
-72.70 dko
-79.44 dco
40.12 dBe
-92.80 dEc
-99.51 dbe
-106.3 dbo
-113.0 dko
-119.7 dEo
-126.3 deC
-133.0 doc
-130.8 dbo
-148.3 dko
-163.0 deo
-0.0036 +O .000O00
Figure 8.6: Phase noise at 0.5 V tuning voltage.
Figure 8.6 shows the oscillator performance at a tuning voltage of 0.5 V. The phase
noise meets the specification and the frequency is below 2.4 GHz. The phase noise
profile predicted by Leeson's equation can be seen, with a flicker noise corner frequency
of about 30 Hz. In Figure 8.7, the tuning voltage is 2.5 V and the oscillation frequency
rises to 2.51 GHz. The phase noise is higher by 0.5 dB, but still within the specification
of -110 dBc/Hz at 1 MHz offset from the carrier.
Oscillation
frequency
Phase Noise Plot
freq1)
2.510487
GHz
I
Am
K'
ýI " I
tl .'
" I
f
~tI
IO
I
I
I'
time, psec
noisefreq
1.000 Hz
2.154 Hz
4.642 Hz
10.00 Hz
21.54 Hz
46.42 Hz
100.0 Hz
215.4 Hz
464.2 Hz
1.00 kHz
2.154kH
4.042 kHz
10.00 kHz
21.54kHz
46.42 kHz
100.0 kWz
215.4kHz
464.2 kHz
1.000 MHz
2.154MHz
4.642 MHz
1000MHz
21.54MHz
4.42 MHz
100.0 MHz
VTune = 2.5 V
BhasCunrwat.i
0.00385 +j.00000
Figure 8.7: Phase Noise at 2.5 V tuning voltage.
threedi"ps
1.81403 +j.00000
vout_diff.pnmx
24.84
15.14
5.340
-4.299
-13.60
-22.39
-30.56
-38.16
-4.33
-52.25
-659.04
-65.77
-72.46
-79.14
-85.82
-92.40
-99.10
-105.8
-112.5
-110.2
-125.8
-132.5
-139.2
-146.8
-152.5
-0.00635 +j.00000
dBc
dBe
dBe
dBe
dBo
dBo
deB
dBe
dBe
dec
d~e
dBc
dec
dBc
dBe
dec
dBc
de
d~e
d~e
dec
d~e
dBo
dBe
dBe
OscIton
frequency
Pase
Noise
Pq[lot
I 2.418883 ll0
Phase Noise Plot
i
t
>
t
-
I
-
S(
4
o
s
--
-
na
a
4a
a
m
aW a
a
time. psec
1i
El
voudrgt.pnmx
33.16 d-o
21.79 dNo
noweheq
1.000 1H
2.164 1k
11.04 dlk
4.642 HI
V tune = 1.3 V
Inductor Q = 4.9
EIsu
I
0.00366 +JO#.000
8004.0 mdno
-8.762 d4o
-17.96 dbo
-20.31 d4o
-34.13 dko
-41.46 d4o
-46.46 dko
-5•.20 d~o
-62.04 d4o
-W0.74 dko
-75.43 d6o
-82.10 dko
-68.70 dBo
-06.46 dso
-102.1 dko
-10e.8 d o
-116.6 dlo
-122.1 dko
-126.8 deo
-136.6 d4o
-142.1 dio
-140.8 d4o
10.0 H
21.64 W
46.42 1t
100. HI
216.4 H1
464.2 HE
1.000 ki
2.164 kI
4.642 kH
10.00 kHl
21.54 k•
46.42 ki
100.0 kWk
216.4 kf
404.2 kHl
I
10o0
MH
2.164 4k
4.842 MHz
10.00 Mi
21.64WMH
46.42 MH
100.0 Mil
"S
I\
1.81403 +J.D000000
-0
"36+j.00000
Figure 8.8: Phase noise for lower inductor Q.
Figure 8.8 shows how reducing the inductor quality factor increases phase noise.
Changing the inductor Q from 12.3 to 4.9 increased phase noise from -112.8 dBc @ 1
MHz to -108.8 dBc @ 1 MHz. Figure 8.9 shows how reducing the load impedance from
200 Ohms to 100 Ohms raises the phase noise to -105.0 dBc @ 1 MHz. Changes in load
impedance affect the loaded Q of the tank, so they are expected to have a significant
effect on phase noise. This relationship between load resistance and VCO performance
necessitates the addition of a buffer amplifier to follow the VCO. The input impedance
of the amplifier should be made as high as possible, given the constraints of the process
such as maximum transmission line impedance at the operating frequency.
Oscillation
frequency
frq[1]
2.447527 GHz
Phase Noise Plot
E
SI
M
_~_____
noselmq
0.00385 + jO.00000
I
I
1000 HW
2.154 Hz
4.642 Hz
10.00 Hz
21.54 HW
46.42 Hr
100.0 Hz
215.4 Hz
464.2 Hz
1.000 kHz
2.154kH
4.642 kHz
10.00 kHz
21.54kHa
4.42 kH
100.0 kHz
215.4kHz
404.2 kHz
1.000
MH"
2.154 MHz
4.642MHk
1000 MIH
21.54 MHz
46.42
100.0 Mil
MHz
VTune = 1.3 V
Load Impedance = 100 Ohms
.assurreni
time. psec
TTpfm
_X
V
no~~.iruq
vourTiffpnmx
th"edmps
I
1.81403 +j.00000
Figure 8.9: Phase noise for lower load resistance.
30.57
26.56
10.61
6.700
-2.9022
-12.30
-21.20
-20.60
-37.10
-44.43
-51.30
-58.21
-04.94
-71.64
-78.32
-85.00
-91.67
-98.34
-105.0
-111.7
-118.3
-125.0
-131.7
-138.4
-146.1
W'
.
-0.00035 +j0.00000
dec
dec
dBc
dec
dBc
dBc
dBe
dBe
dBe
dBe
deo
dBo
dB0
d9c
dec
dBe
dBe
dBc
dBo
d8c
dBo
dBe
dec
deo
die
Varactor Tuning
2.52
2.5
2.48
2.46
S2.44
i---- tuning curve i
2.42
2.4
2.38
2.36
0
0.5
1
1.5
Tuning Voltage
2
2.5
3
Figure 8.10: Varactor tuning curve.
Finally, the VCO frequency was plotted as a function of tuning voltage in Figure 8.10.
The non-linearity of the tuning curve can be seen here. This is mainly due to the higher
varactor gain at lower bias voltages. Varactor gain refers to the varactor's incremental
change in capacitance divided by the incremental change in voltage around an operating
point. It is a term used by industry although it refers to a transfer function, not a gain.
Tuning between 0 and 0.5 V was avoided because of the non-linear performance of the
varactor at low bias voltages.
Chapter 9
Conclusion
This thesis consisted of three phases of work. The initial work focused on inductor
design optimization. Then, inductors to be fabricated in the iUHD process were
designed. The fabrication run failed, but work on improving the process is a high priority
at Draper and future fabrication attempts may succeed. The final phase of the work was
the design of a VCO for use in an RFIC circuit.
The inductor design work highlighted where improvements could be made to the
iUHD process. In particular, greater metallization thickness is expected to improve
quality factor for iUHD inductors. Lower minimum spacings between traces would
reduce area occupied and possibly also increase quality factor. Therefore, achieving
higher aspect ratios for fabricated features should be a future performance goal for iUHD.
The VCO design validated much of the theoretical and experiential knowledge
found in the journal articles and literature reviewed. Some of the suggested techniques
were employed to meet the phase noise specifications, such as using symmetric inductors
and a tail current choke. The current biasing circuitry to meet the pushing figure
specification, on the other hand, was not derived from prior work. The design uncovered
the importance of maximizing the VCO load impedance. At RF frequencies, achieving
impedances greater than 200 Ohms may be difficult due to effects such as capacitance
and inductance inherent to the BiCMOS process. To design an integrated VCO that
meets CDMA specifications, the limitations of the output buffer's input impedance must
be investigated so that the VCO load impedance can be set to a higher value.
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Appendix A Experimental Setup
Properties to be Tested
Test
Expected Results
Proximity Effect
At higher frequency, extra trace width has less effect on Q.
Mutual
Inductance
Adding an extra turn to the inside or the outside of a spiral raises
L proportionally by more than the increase in conductor length.
Tradeoff
between Land
Circular vs.
Square
Keeping area fixed, increasing number of turns and reducing
width should increase L and reduce Q. Does SRF increase
because of decrease in C or does it decrease because of
increase in L?
Circular spiral should provide higher Q for same L than square,
but occupy more area.
Dual Layer
Spiral
Dual layer spiral should provide more than double, up to four
times the inductance of a single layer.
Interference
Increased distance between two coplanar spirals should
decrease mutual inductance substantially.
Q
Measured
Results
Table A.1: Tested Phenomena
Each fabricated inductor will be measured using the probe station and network analyzer
to find the s-parameters at 1600 evenly spaced frequencies from DC to 10 GHz. From
these s-parameter data, values for inductance and quality factor can be plotted as
functions of frequency, which will enable quantitative comparison of the different
structures. The results of the measurements will be compared to the hypothesized
differences between the inductors.
Appendix B Results (to be completed in future work)
Simulation Results
Structure
L @ 2.75 GHz
Q @ 2.75 GHz
S.R.F (GHz)
(nH)
A
Peak Q @ f
(GHz)
5.41
29.16
8.25
31.35@3.8
8.06
26.75
5.8
27.15 @ 3.1
H
4.22
27.6
9.6
31.24@4.3
K
3.6
30.88
10.8
32.25@4.8
L
7.46
25.75
7.05
26.35@3.3
C
E
G
N
Table B.0.1: Simulated Inductor Values
Measurement Results
Structure
L @ 2.75 GHz
Q @ 2.75 GHz
S.R.F (GHz)
(nH)
A
C
E
G
H
K
L
N
Table B.0.2: Measured Inductor Values
Peak Q @ f
(GHz)
Structure
Spacing
Ll
L2
(um)
B
150
J
450
F
750
Table B.0.3: Inductor Coupling
M
k