Single
Instruction
Michael
Butler,
Tse-Yu
Department
and
Computer
Mitch
Is Greater
Alsup,
Hunter
Microprocessor
Since
Recent
(less
studies
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have
two
cycle)
streams.
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the
should
it is important
ists.
study
benchmarks
repeat
the
hardware
we get similar
all constraints
semantics
allelism
and
amount
the amount
constraints
except
struction
stream
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to design
hand,
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and
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performance
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unconstrained
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The model
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and discusses
the
on performance.
which
in six sections.
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a brief
6 offers
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work
was not simulated
mark
consists
of seven independent
straints,
we omitted
these loops.
276
cycle.
program,
when
benchmarks,
Section
plementation
Permission
to copy without fee all or part of this material IS granted
provided that the copies are not made or distributed for direct commercial
advantage, the ACM copyright nonce and the title of the publication and
its date appear, and notice is given that copying is by permission of the
Association for Computing Machinery. To copy otherwise, or to republish,
requires a fee and/or specific perrmssion.
did not
constraints
on a processor
is organized
the
identified.
Q 1991
cycle
Section
and Johnson[l],
cycle.
per
in excess
available
tested.
lations
features
non-
how
could
today.
paper
simulator,
fact
also
on an
that
parallel
are removed
one can sustain
be exploited.
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was
have
to quantify
benchmarks
undue
of the
we show that
cusses restricted
paral-
warrants
that
This
func-
technique
of parallelism
Finally,
design
to
instructions
by the semantics
instructions
One
instruction-level
parallelism
to support
of
We
benchmarks
in order
with
hand,
balanced,
motivated
numbers
This
of
applications
16]
has
performance.
is to
amount
applications
more
utilize
single
the
in
5,
VLSI
computational
elements
on
if
of
to
improve
fective
the
density
mod5] and
Jouppi[2].
to sustain
two
cle.
perfor-
Hwu[3,
of the processor
that,
than
degrees
Introduction
show
it is difficult
more
quired
1
if the artifacts
per-
the
execution
and
of these
in these
have
compute-bound
measured
by Patt
model
exists
programs
that
it.
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2.0
in
and
execution
parallelism
be exploited
in-
[l]
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ten
of the
applications
on several
studied
we have
nine
have
benchmarks
those
by Smith
of par-
exploiting
We
im-
degrees
for
used
do this,
in optimized,
standard
when
~equired
To
influ-
to verify
parallelism
a set of real
de facto
should
it is important
exists.
We have
els, including
those
balanced,
per
mance
parallelism
of available
benchmarks.
we have found
parallelism
to 5.8 instructions
We
of available
suite,l
the
formance
show
they
other
become
SPEC
and
code.
Group
West
78735
parallelism
SPEC
Shebanow
of the processor,
a study
compiled
in the
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constraints.
On the
important
hardware
of the
researchers,
of 17 instructions
most
really
much
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of available
execution
resource
results.
how
in sin-
of the processor,
resource
are removed
in excess
sonable
the
parallelism
parallelism
previous
oft he program,
perhaps
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differing
of the
under
posed,
how
work
little
is available
the design
we model
under
the
that
influence
to verify
In this
that
per
gle instruction
parallelism
concluded
operations
Drive
Texas
ence the design
Michael
Two
Technology
Cannon
Austin,
Abstract
and
Memory
William
48109-2122
than
Incorporated
and
6501
of Michigan
Michigan
Scales,
Motorola
Engineering
Science
University
Arbor,
Parallelism
Yeh, and Yale Patt
of Electrical
The
Ann
Stream
loops.
today,
discussion
some
ma-
are
all
of im-
concluding
we have planned.
because
Due
to
this benchtime
con-
2
The
RDF
To exploit
whatever
stream,
facts
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that
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Processing
those
instructions
namic
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The
that
from
present
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of time.
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appear
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size
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the
dynamic
issue
tions
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and
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latency
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size and
model
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all
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size
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on is-
present
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ters
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parallelism
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we obtain
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that
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It
All
of
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implementable
size, issue
execution
parameon the
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size and
tigate
277
We
point
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effect
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latencies,
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produced
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Johnson[l].
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latency
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cies for
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of
integer
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[10]
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question.
[2]
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on Multiple
Third
N.P.
Jouppi,
Level
tems,
for
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