Design and Characterization of a Radio-Frequency
dc/dc Power Converter
by
David A. Jackson
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degrees of
Bachelor of Science
and
Master of Engineering
at the
IMASSACHUSETTS
iNST'TWJE
OF TECHNOLOGY
JUL 18 2005
LIBRARIES
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2005
© Massachusetts
Institute of Technology, MMV. All rights reserved.
Anithnr
Department of Electrid Engineering and Computer Science
May 19, 2005
Certified by.
David J. Perreault
Associate Professor of Electrical Engineering
sis npervisor
Accepted by
Arthur C. Smith
Chairman, Department Committee on Graduate Students
CH NVES
Design and Characterization of a Radio-Frequency dc/dc Power
Converter
by
David A. Jackson
Submitted to the Department of Electrical Engineering and Computer Science
on May 19, 2005, in partial fulfillment of the
requirements for the degrees of
Bachelor of Science
and
Master of Engineering
Abstract
The use of radio-frequency (RF) amplifier topologies in dc/dc power converters allows the
operating frequency to be increased by more than two orders of magnitude over the frequency of conventional converters. This enables a reduction in energy storage capacity by
several orders of magnitude, and completely eliminates the need for ferromagnetic material
in the converter. As a result, power converter size, weight and cost can all potentially
be reduced. Moreover, converter output power and efficiency remain high because of the
soft-switching capabilities of RF amplifiers. This document describes the design, implementation and measurement of a dc/dc power converter cell operating at 100MHz, with
approximately 10 to 30W of output power at around 75% efficiency. The cell is designed
for an input voltage range of 11 to 16V, and a user-determined output voltage on the same
order of magnitude. The design of this cell also allows an unlimited number of identical
cells to be used in parallel to achieve higher output power. This type of converter has
applications in a broad range of industries, including automotive, telecommunications, and
computing.
Thesis Supervisor: David J. Perreault
Title: Associate Professor of Electrical Engineering
Acknowledgements
I would like to thank Prof. David J. Perreault, Ph.D., my thesis supervisor, for his support,
guidance, insight, and ingenuity. I have learned a great deal from him, and I have truly
enjoyed working with him.
I would also like to thank the members of my research group, Juan Rivas, Yehui Han, and
Olivia Leitermann, who comprise the greatest team that I have ever worked with. They
helped to make this work possible in many ways, and I value their friendship.
I am very grateful to my girlfriend, Tracy Gilliland, for her unending patience, support and
help.
I am also grateful to all of the people in the MIT Laboratory for Electromagnetic and
Electronic Systems (LEES) who have helped me: Brandon Pierquet, Josh Phinney, and Rob
Cox for answering my many questions; Wayne Ryan for providing materials and technical
advice; Vivian Mizuno for cheerfully handling so many purchases; Yihui, Frank, Padraig,
Natalija, Leandro, Shiv, Dasha, Riccardo, Vasanth, Tushar, Alejandro, Steven, Ian, Kyomi,
Karin, and all of the other people in LEES who make it a great place to work.
I would like to thank Dr. John Moyle, of the Bronxville School for developing my interest
in science and technology. His dedication to teaching, along with his keen interest and
enthusiasm for science, are unparalleled.
I would also like to thank all of my friends and family members for being understanding
during my work on this project.
I owe my deepest gratitude to my parents, Juli and Robert Jackson, for providing immeasurable support, inspiration and patience over the past 23 years. Without their love and
friendship I would not be where I am today.
-5
-
Contents
1 Introduction
2
3
17
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.2
Thesis Objectives and Contributions . . . . . . . . . . . . . . . . . . . . . .
20
1.3
Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Background
23
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.2
Class E Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.3
Alternatives to the Class E Topology . . . . . . . . . . . . . . . . . . . . . .
24
Inverter Design
27
3.1
Introduction........
3.2
Specifications and Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
3.2.1
D uty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.2.2
Loaded
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.2.3
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.2.4
Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
3.2.5
Efficiency, Output Power, Physical Size
. . . . . . . . . . . . . . . .
29
Switch Device Comparison Using Datasheet Information . . . . . . . . . . .
29
3.3.1
Selection of Devices
. . . . . . . . . . . . . . . . . . . . . . . . . . .
29
3.3.2
PSPICE Modelling with Datasheet Information . . . . . . . . . . . .
32
3.3.3
Inverter Performance Comparison Using PSPICE Simulation . . . . .
34
3.3
3.4
Q Factor
...............
Switch Measurement and Modelling
.....
...............
27
. . . . . . . . . . . . . . . . . . . . . .
35
3.4.1
Measurement of ac Characteristics . . . . . . . . . . . . . . . . . . .
35
3.4.2
Measurement of dc Characteristics . . . . . . . . . . . . . . . . . . .
37
-7-
Contents
PSPICE Modelling using Measured Data . . . . . . . . .
. . . . .
38
3.5
Final Switch Selection . . . . . . . . . . . . . . . . . . . . . . .
. . . . .
39
3.6
Retuning for Higher Efficiency or Output Power
. . . . .
40
3.7
Adding Drain to Source Capacitance for Higher Output Power
. . . . .
42
3.8
Choke Inductor Implementation . . . . . . . . . . . . . . . . . .
. . . . .
44
3.9
Inductor Loss Reduction . . . . . . . . . . . . . . . . . . . . . .
. . . . .
49
3.10 Switch Packaging . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . .
51
3.4.3
4
5
6
. . . . . . . .
Gate Drive Design
55
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . .
55
4.2
Initial Gate Drive Design
. . . . . . . . . . . . . . . . .
. . . . .
56
4.3
Gate Drive Circuit Redesign . . . . . . . . . . . . . . . .
. . . . .
56
4.3.1
Multi-Resonant (MR) Circuit Design . . . . . . .
. . . . .
57
4.3.2
Self-Oscillating (SO) Circuit Design . . . . . . .
. . . . .
57
4.3.2.1
AC Considerations . . . . . . . . . . . .
. . . . .
58
4.3.2.2
DC Considerations . . . . . . . . . . . .
. . . . .
61
4.4
Simulated Performance of Complete Gate Drive Circuit
. . . . .
62
4.5
Gate Drive Startup Circuit
. . . . .
62
. . . . . . . . . . . . . . . .
Impedance Compression Network Theory
65
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
5.2
Motivation for Impedance Compression
. . . . . . . . . . . . . . . . . . . .
65
5.3
Compression Network Theory of Operation . . . . . . . . . . . . . . . . . .
66
5.4
Application of a Compression Network to the Converter . . . . . . . . . . .
67
Rectifier Design
71
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
6.2
Selection of Switch Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
6.3
Selection of Topology and Diode . . . . . . . . . . . . . . . . . . . . . . . .
72
-8-
Contents
81
7 Impedance Compression Network Design
8
7.1
Introduction .........
7.2
Design .........
....................................
.......................................
81
81
Matching Network Design
85
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
8.2
D esign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
89
9 Printed Circuit Board Layout
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
9.2
Gate Drive PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
9.3
Inverter and Matching Network PCB Layout
. . . . . . . . . . . . . . . . .
91
9.4
Compression and Rectifier PCB Layout
. . . . . . . . . . . . . . . . . . . .
92
10 Converter Construction and Measured Results
95
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
10.2 Gate Drive Construction and Tuning . . . . . . . . . . . . . . . . . . . . . .
95
10.3 Inverter Construction and Tuning . . . . . . . . . . . . . . . . . . . . . . . .
97
10.4 Construction and Tuning of Compression and Rectifier Stages . . . . . . . .
99
10.5 Measurements of Completed Converter . . . . . . . . . . . . . . . . . . . . .
101
10.6 Additional Tuning of LMRS
...........................
104
10.7 Investigation of Other Inverter Tuning and Measurement Methods . . . . .
107
10.7.1 Resonant Tank Tuning with Impedance Analyzer . . . . . . . . . . .
107
10.7.2 Inverter Output Power Measurement with Power Meter . . . . . . .
108
11 Conclusions
109
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.2 Evaluation of Thesis Objectives and Contributions . . . . . . . . . . . . . . 109
. . . . . . . . . . . . . . . . . . . . . . . . .
110
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
11.3 Evaluation of Lessons Learned
11.4 Future W ork
-9
-
Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
11.4.2 Long Term Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
11.4.1 Short Term Goals
113
A PSPICE Simulation Files
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
A .2 Library File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
Inverter Measurement Code . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
A.4 Comparison of Higher Coss vs. Added CEXTRA in the Inverter . . . . . . .
120
A.5
Comparison of Four Devices Using Datasheet Information . . . . . . . . . .
123
A.6
Comparison of M/A-COM and Freescale Devices Using Measured Data
. .
124
A.7
Comparison of MR and non-MR inverters . . . . . . . . . . . . . . . . . . .
125
A.8
Gate Drive Simulations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127
A.9
Simulations of Rectifier Alone . . . . . . . . . . . . . . . . . . . . . . . . . .
130
A.10 Simulations of Compression Network and Rectifier Together . . . . . . . . .
133
A .1
A.3
B LDMOS and VDMOS Search Results
137
C Power Schottky Diode Search Results
143
D Measured LDMOS Device Data
149
D .1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
149
D.2 AC M easurements
................................
149
D.3 DC M easurements
................................
150
E Derivation of Multi-resonant Topology Equations
155
F MATLAB Code for Compensating Impedance Analyzer Measurements
159
G Passive Component Datasheets
165
Bibliography
169
-
10
-
List of Figures
1.1
Ideal Class E inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
1.2
Unregulated current source cell. . . . . . . . . . . . . . . . . . . . . . . . . .
18
1.3
Multiple current source cells used in parallel with a voltage regulator to form
a dc/dc converter with a regulated output voltage. . . . . . . . . . . . . . .
19
Typical Class E amplifier switch voltage and current waveforms with D =
50% and QL = 3 .. . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . .
24
A simplified view of the connection of parasitic capacitances in an LDMOS
device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Layout of the PSPICE LDMOS model used to compare candidate LDMOS
devices based upon datasheet information. . . . . . . . . . . . . . . . . . . .
32
Structure of the PSPICE inverter model used to compare candidate LDMOS
devices based upon datasheet information. . . . . . . . . . . . . . . . . . . .
33
Simulated inverter performance for four LDMOS devices using datasheet
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Measured and modelled nonlinear Coss vs. VDS for the Freescale LDMOS
device MRF373ALSR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Simulated inverter performance based upon measured data for M/A-COM
MAPLST0810-030CF and Freescale MRF373ALSR1. . . . . . . . . . . . . .
40
3.7
Simulated effect of retuning the inverter for maximum efficiency . . . . . . .
41
3.8
Simulated effect of retuning the inverter for increased output power . . . . .
42
3.9
Simulated external VDS (Fig. (a)) and internal VDS (Fig. (b)) for an inverter
with CEXTRA = 20pF with and without LMRS for package inductance compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
3.10 Simulated inverter performance for a range of LMRS values. . . . . . . . . .
45
2.1
3.1
3.2
3.3
3.4
3.5
3.6
3.11 Idealized MR topology for controlling the first three harmonics of any waveform. 46
3.12 Magnitude vs. frequency of the impedances Zp and Zs (3.12(a)) and ZMR =
Zp 1| Zs (3.12(b)) in the MR circuit. . . . . . . . . . . . . . . . . . . . . . .
46
3.13 Class E inverter with MR choke.
47
. . . . . . . . . . . . . . . . . . . . . . . .
- 11 -
List of Figures
3.14 VDS of the inverter with MR choke.
. . . . . . . . . . . . . . . . . . . . . .
50
3.15 Final Class E inverter design. . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.1
SO gate drive circuit used in the original design (1] . . . . . . . . . . . . . .
55
4.2
Magnitude and phase of the transfer function G (w) used in the first gate
drive design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
Redesigned gate drive circuit composed of an MR circuit and an SO gate
drive circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
Generic topology of the redesigned SO gate circuit (4.4(a)) and its Thevenin
equivalent (4.4(b)), ac considerations only. . . . . . . . . . . . . . . . . . . .
59
4.5
Redesigned SO gate drive, ac considerations only. . . . . . . . . . . . . . . .
60
4.6
Magnitude and phase of the transfer function VDSM2
vG
for the SO circuit with
ac components only for four values of LFB. . . . . . . . . . . ..
. . . ..
60
Magnitude and phase of the transfer function -Gsm
for the SO circuit with
VDSM2
dc and ac components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
Complete gate drive circuit (ac and dc considerations) with MR and SO
circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
Impedance magnitude at the gate of Mi vs. frequency, including SO and MR
circuits with ac and dc considerations. . . . . . . . . . . . . . . . . . . . . .
63
4.10 Gate to source voltage of the main MOSFET (M 1 ), and of the SO circuit
MOSFET (M 2 ), with the component values used in simulation. . . . . . . .
64
4.3
4.4
4.7
4.8
4.9
5.1
The effect of changing RLOAD on the Class E inverter VDs waveform.
. . .
66
5.2
The network to be used for compression. . . . . . . . . . . . . . . . . . . . .
67
5.3
A plot of Eq. 5.3 (Fig. 5.3(a)) and a basic compression network (Fig. 5.3(b))
that can be used to realize impedance compression. . . . . . . . . . . . . . .
68
5.4
Compression network with symbolic rectifier connections.
. . . . . . . . . .
68
6.1
An ideal single-switch rectifier . . . . . . . . . . . . . . . . . . . . . . . . . .
72
6.2
Basic single-resonance (SR) rectifier topology and associated waveforms. . .
74
6.3
Basic MR rectifier topology and associated waveforms. . . . . . . . . . . . .
75
6.4
Efficiency vs. OIN for several MR and SR rectifier tunings, and phase range
(over power level range) for each tuning. . . . . . . . . . . . . . . . . . . . .
76
Maximum diode voltage (at maximum input power, ~ 15W) vs. qIN for
various MR and SR tunings. . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
6.5
- 12 -
List of Figures
6.6
An ideal two-diode rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
6.7
A comparison between the two-diode rectifier shown in Fig. 6.6 and the SR
rectifier of Fig. 6.2(a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
6.8
Plots of VRECTIN, the fundamental of VRECTIN, and IRECTIN for
the two
diode rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Basic compression network with symbolic rectifier connections and with a
low-impedance path indicated. . . . . . . . . . . . . . . . . . . . . . . . . .
82
Compression network with the inductor and capacitor added to reduce higher
order harmonic currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
Power balance between upper and lower rectifiers as a function of sinusoidal
input current magnitude for various values of a. . . . . . . . . . . . . . . . .
84
8.1
Two candidate L-section matching networks.
. . . . . . . . . . . . . . . . .
86
9.1
The gate drive portion of the PCB. . . . . . . . . . . . . . . . . . . . . . . .
90
9.2
The inverter, matching network and gate drive portions of the PCB. . . . .
92
9.3
The compression network and rectifier PCB. . . . . . . . . . . . . . . . . . .
93
7.1
7.2
7.3
10.1 Typical gate drive waveform.
. . . . . . . . . . . . . . . . . . . . . . . . . .
96
10.2 A photograph of the completed converter. . . . . . . . . . . . . . . . . . . . 101
10.3 Measured converter output power and efficiency. . . . . . . . . . . . . . . . 102
10.4 Measured converter waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.5 Comparison between measured and simulated compression network input
voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.6 Measured converter performance for a range of
LMRS
values.
. . . . . . . . 105
10.7 Cycle-to-cycle variation in the peak value of VDS over five consecutive cycles
of VDS, and over the range of LMRS values. . . . . . . . . . . . . . . . . . . 106
E.1 Idealized MR topology for controlling the first three harmonics, same as
F ig. 3.11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
- 13 -
List of Tables
3.1
Simulated effects on inverter performance of varying the nominal value of
Coss used to calculate the other MR circuit values. . . . . . . . . . . . . .
48
3.2
Retuning the MR inverter resonant tank for maximum efficiency operation.
49
3.3
Simulated comparison between MR and non-MR inverters . . . . . . . . . .
49
3.4
Simulated inverter performance across VIN for three
for eight values of CEXTRA. .........-................................
53
LCHOKE
values, and
.....
6.1
Simulated SR rectifier performance for several values of Cp. . . . . . . . . .
78
8.1
Simulated converter performance for four matching network ratios. . . . . .
87
10.1 Component values for the final gate drive design.
10.2 Inductance-compensated load resistor information.
...............
97
. . . . . . . . . . . . . .
98
10.3 Measurements of the inverter and matching network with inductance-compensated
25Q load, and inverter component values used to make these measurements.
99
10.4 Component values for the compression network and rectifier design.
. . . . 100
A.1 Simulated comparison between various MR and SR tunings. . . . . . . . . . 130
B. 1
Selected datasheet information for all LDMOS devices considered for use in
this design, table 1 of 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
B.2 Selected datasheet information for all LDMOS devices considered for use in
this design, table 2 of 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
B.3 Selected datasheet information for all LDMOS devices considered for use in
this design, table 3 of 3, and a table of selected datasheet information for
some VDM OS devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
C.1 Results of a search for power Schottky diodes rated for I
146
> 1.5A.
. . . . .
C.2 Results of a search for power Schottky diodes rated for VRRM = 60V and for
Io > 1.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
- 15
-
List of Tables
D.1 Impedance analyzer measurements of the Freescale MRF373ALSR1 and the
M/A-COM MAPLST0810-030CF. . . . . . . . . . . . . . . . . . . . . . . . 151
D.2 Solution to the non-linear Coss equation for the M/A-COM MAPLST0810030CF.................................................
152
Solution to the non-linear Coss equation for the Freescale MRF373ALSR1.
152
D.3
D.4 RDS vs. VDS measurements for the M/A-COM MAPLST0810-030CF. . . . 153
D.5
RDS vs. VDS measurements for the Freescale MRF373ALSR1.
- 16
-
. . . . . . . 153
Chapter 1
Introduction
1.1
Introduction
Pressing issues in the design of electronic equipment include system size, cost and energy
efficiency. The focus on these three metrics is driven by a high and increasing demand for
inexpensive, portable, battery powered devices, as well as demand for more efficient and
inexpensive versions of larger systems, such as automobiles. However, improvements in
most areas of electronics have a limited effect upon these three metrics because the greatest
limiting factor remains the power supply and processing subsystem. These limitations have
become increasingly problematic as many segments of the electronics industry have moved
toward distributed power systems, in which a single large supply is replaced by numerous
smaller power converters, placed in close proximity to loads [2]. This approach requires
high-efficiency converters to prevent excessive heating, as well as low-cost converters to
justify the increased number of power modules. Fortunately, advances can still be made
in the area of power electronics by moving away from conventional topologies and out of
conventional operating spaces (e.g. by greatly increasing the operating frequency, pushing
it into the radio-frequency range [3]).
In many electronic systems, dc/dc power converters are used to convert from an unregulated
voltage to a tightly regulated voltage that can be used to power loads that are sensitive to
voltage variations, and that have time-varying power requirements. This conversion is accomplished most efficiently with a switching power converter, which inverts the unregulated
dc to ac, performs intermediate processing, such as a step up or down in voltage, and then
rectifies the ac back to dc. Control circuitry maintains the desired output voltage by driving
one or more power switches. Such converters typically require physically large energy storage devices (inductors and capacitors) to perform transformations at ac and to smooth the
rectified dc to a constant voltage, among other functions. These storage elements are often
larger and heavier than most other elements in the system, and are expensive because they
cannot currently be integrated due to their size and complexity.
One way to reduce the size of these elements is to increase the converter switching frequency
(fs) [4, chapter 6). Pushing fs to 100MHz and above has the potential to greatly reduce
-
17
-
Introduction
LCHOKE
LR
+
VDN (DC)
DRIE
I
VSw
CR
+
y"
C,
RLOAD
VOUT
Figure 1.1: Ideal Class E inverter.
Class E Inverter
Matching
Network
Compression
Network
AC
Unregulated dc VIN
DC
Rectifier
DC
Unregulated
dc current
AC
Co-r RLoA
VouT
(DC)
Self
Oscillating
Gate Drive
ON/OFF
Control
Figure 1.2: Unregulated current source cell.
passive component size, and in some cases makes it possible to integrate the passive components, either in silicon or as part of the printed circuit board. However, conventional dc/dc
power converters cannot be operated at such high frequencies because of unacceptably large
switching and gating losses, and the difficulty of realizing appropriate controls.
An excellent solution to this problem, developed in (3] and elsewhere, is to apply the topologies and techniques associated with radio-frequency (RF) power amplifiers to dc/dc power
converter design. In the work presented here, which builds upon the work shown in [1], a
Class E RF power amplifier [5, 6, 7 and 8, chapter 13] is used as an inverter (Fig. 1.1) and
combined with a gate driver, an impedance matching network, a compression network, and
a rectifier to form a dc/dc converter cell that operates at 100MHz (Fig. 1.2). The unregulated dc input voltage is transformed by the cell to an unregulated dc output current. Only
on/off external control is required.
One or more such current source cells may be connected to the load in parallel with a voltage
regulator to form a dc/dc voltage converter (Fig. 1.3). The voltage regulator maintains the
desired load voltage. As the load varies, the current source cell or cells are modulated on
and off to minimize the power demand on the voltage regulator. Because the voltage source
output power is low, this source can be made physically small, relatively inefficient, and
therefore inexpensive. To illustrate this fact, a linear regulator (rather than a switching supply) can be used. The details regarding the interconnection and control of the unregulated
- 18
-
1.1
Unregulated
DC voltage bus
Introduction
Unregulated
Current Source
Cell
V IN
CUe
Unregulated
Caurrent Source
Celll
Un regulated
Current Source
a fCOUToni[d
cell
On/Off
On/Off
On/Off
Regulated
Control Cell
Voltage
Sense
Current Sense
Voltage
Control
-
-
-
Voltage Source
Cell
Figure 1.3: Multiple current source cells used in parallel with a voltage regulator to form
a dc/de converter with a regulated output voltage. The number of cells can be increased
arbitrarily to increase output power level.
current source cells can be found in [1].
This converter topology has numerous merits, one of which is the high
fs of the
unregulated
cells. As a result, each cell requires only small capacitors (not more than a few hundred
picofarads) and small air core inductors (not more than a few hundred nanoHenries), which
makes the cell quite small, light and inexpensive. The absence of ferromagnetic inductor
core material also makes the converter less sensitive to extreme ambient temperatures and
mechanical stresses. Despite the high fs, the cell has low switching loss, and therefore
requires relatively little heat sinking. The switch device chosen for the inverter is rated to
dissipate enough power that no external heat sinking is required. High fs also allows each
cell to be modulated at high frequency to respond rapidly to changes in load resistance.
Another merit of this design is modularity. Because all of the unregulated cells are identical, any number may be used in parallel to achieve a desired converter output power.
This parallel architecture may also be used as a way of increasing converter reliability by
preventing total converter failure in the event of cell failure. Finally, unlike many other
dc/dc converter topologies, each converter cell has inherent short-circuit tolerance [8, page
366]. This is explained further in chapter 2.
- 19
-
Introduction
1.2
Thesis Objectives and Contributions
The goal of this thesis is to design, build, and test an RF dc/dc converter cell with improved
performance over the cell described in [1]. Potential improvements include increased output
power, increased efficiency, decreased board area and increased fs. To explore the possibility
of making improvements in each of these areas, all segments of the converter are redesigned,
including the inverter, gate drive, impedance transformation and compression stages, and
rectifier.
Achieving improvements in the inverter entails a search for a more suitable switch device,
including measurement and computer modelling of potential devices using PSPICE. Inverter
performance is modelled for several candidate devices over the input voltage range and over
a range of potential operating frequencies. The device that provides the best performance is
chosen, and the effects of retuning for maximum efficiency or increased power are considered.
Replacing the choke inductor with a discrete-component multi-resonant (MR) circuit to
reduce switch voltage stress is also investigated here. Several inverter implementation issues,
such as printed circuit board (PCB) design, inductor design, switch package inductance
compensation and switch packaging, are considered.
A gate driver is designed to meet the requirements of the inverter's switch, which are
different from the requirements of the device used in [1]. Gate drive tuning and PCB layout
are discussed.
A matching network is used to match the input impedance of the compression stage to the
impedance that the resonant inverter requires for efficient operation. Although a conventional network is used, it must be tuned to produce the most efficient inverter operation.
Several tunings are calculated and compared through simulation.
A compression network is used to reduce the effect of load resistance variations on the
resonant inverter operation. The theory of such a network is explained. An improved
version of the basic compression network is designed for better management of harmonics.
All aspects the rectifier design are discussed, including selection of rectification style (synchronous or diode), topology and switch device. The PCB layout of the rectifier is also
discussed.
Once all parts of the converter are designed, the converter is built and measured in stages,
and then characterized as a whole. All of the measurements made at the various stages
are sensitive to the parasitic elements in the measurement equipment, and are limited by
equipment voltage limits. Methods for making accurate measurements in spite of equipment
-
20 -
1.3
Organization of Thesis
non-idealities are discussed, as are methods of tuning certain converter stages to improve
performance and to come closer to the simulated performance.
Because this thesis treats the design of every stage of the converter in detail, it makes
significant contributions as a guideline for future RF converter design.
1.3
Organization of Thesis
In chapter 2, background information about the Class E topology is provided, along with
a brief comparison of the Class E topology to other similar topologies (Class F, 1/F, etc.)
Chapter 3 describes the inverter design, including the switch selection process, the selection of an operating point, and the investigation of alternative topologies. Chapter 3 also
explains how the inverter is modelled using PSPICE. Chapter 4 explains the design of the
self-oscillating gate drive circuit. Chapter 5 explains the theory and implementation of the
impedance compression network. The design of the rectifier is detailed in chapter 6, including the process of selecting appropriate diodes. Chapter 8 illustrates the purpose and design
of the impedance matching network. The design of the printed circuit board is discussed
in Chapter 9. Chapter 10 explains how the converter is constructed and measured. This
chapter also analyzes the effects on overall efficiency and output power of tuning various
parts of the converter. The thesis is concluded with chapter 11, where the contributions of
this thesis are summarized, and potential future work is described.
-
21 -
Chapter 2
Background
2.1
Introduction
This chapter provides background information about the structure and operation of the
Class E amplifier, and compares it to other similar topologies (e.g. Class F, Class 1/F, etc.)
to motivate the choice of the Class E topology. Each topology has distinct advantages over
the others, such as lower voltage or current stress on the switch, or lower design complexity.
2.2
Class E Amplifier Operation
The Class E amplifier' (Fig. 1.1, [5, 6]) is powered by an unregulated voltage source in
series with a choke inductor. Together, these provide nearly constant current to the rest of
the amplifier while maintaining an average voltage at the drain equal to the supply voltage.
The rest of the circuit can be viewed as two resonant tank configurations with a switch to
alternate between them. One tank configuration is the series combination of CR, LR and the
load impedance, and dominates the behavior of the circuit when the switch is on. The other
tank configuration is the series combination of C1, CR, LR and the load, and dominates
when the switch is off. The resonant frequency of the first tank (switch closed, fCLOSED)
is lower than that of the second tank (switch open, fOPEN), and the switch is operated at
a frequency between the two tank frequencies (fs). This produces the harmonics necessary
to create the typical Class E waveforms shown in Fig. 2.1. Of note in this figure is the
fact that both the switch voltage and the derivative of the switch voltage are zero at the
time of switch turn on. The voltage and current of capacitor C1 at turn-on are therefore
both zero, creating zero voltage switching (ZVS) under ideal operation. Ideally, no energy
is dissipated from C1 into the switch when it turns on, which facilitates operation at very
high frequencies. Moreover, the low dv/dt at turn-on reduces the required speed of the gate
'To avoid confusion, the term amplifier is used to refer to the generic Class E circuit, and the term
inverter refers to the Class E circuit when used as a power inverter. The inverter is functionally the same
as the amplifier, except that the design parameters are chosen with the inverter application in mind.
-
23
-
Background
Typical Class E Switch Voltage and Current
6.5
60
6
VswTcH-
5.5
50
5
SWITCH
4.5
. ... ...........
40-
4
30
-
......... . .......... ............ .....
- :
3.5 S
I
3
........
........
20
2
-.
10
.. .
-
I
1.5
1
0.5
0
0
1.9 75
2.5_
1.98
1.985
time [sec]
1.99
1.995
x 10-6
Figure 2.1: Typical Class E amplifier switch voltage and current waveforms with D = 50%
and QL = 3.
drive circuitry.
As noted in chapter 1, the Class E topology inherently limits the current into the load
under short-circuit conditions, because the tank impedance remains high due to LR and CR
even with RLOAD = 0. This high tank impedance prevents the short circuit from appearing
across the switch, which could destroy the choke.
The Class E topology also has several drawbacks, including high peak device voltage, high
sensitivity to load impedance, and a dependence of output power on switch capacitance,
which appears in parallel with C1. These drawbacks are discussed further in chapter 3.
The values of C 1 , CR, LR and RLOAD are determined based upon the choice of fs, the
switch duty cycle (D), and QL. The choice of fs, D, and QL is discussed in chapter 3,
where equations for the passive components are given.
2.3
Alternatives to the Class E Topology
Several circuits similar to the Class E topology have been designed to trade off voltage and
current peaking to reduce the required switch ratings. Unlike the Class E amplifier, these
circuits contain filters to manage the higher order switch harmonics.
-
24
-
2.3
Alternatives to the Class E Topology
One such circuit is the Class F amplifier [9, 10], which suppresses the even switch voltage
harmonics, and presents a high impedance to all odd harmonics, producing a square switch
voltage under ideal operation. Because this minimizes switch voltage peaking, a switch with
a lower voltage rating can be used in a Class F amplifier than in a Class E amplifier. At
D = 50%, the Class F maximum switch voltage is 2 times the input voltage, as compared to
the Class E factor of 3.56. The Class F topology also produces more sinusoidal switch current
than the Class E amplifier, which results in greater RMS switch current and therefore in
increased conduction loss.
The Class 1/F (or Class F inverse) amplifier [11, 12] allows only odd current harmonics to
flow through the switch, which ideally produces a square switch current. The RMS switch
current, and consequently the conduction losses, are minimized. However, the required
switch voltage rating is increased because of higher switch voltage peaking.
Any combination of even and odd voltage and current harmonics may be controlled to
produce a desired tradeoff between voltage and current flattening, which is generally referred
to as an E/F tuning (13].
One disadvantage of these topologies (F, 1/F, E/F, etc.) is their increased component count
and design complexity compared to the Class E amplifier. Moreover, the benefit available
from these circuits is limited by the characteristics of the available switch devices. As a
result, neither full Class F nor Class 1/F is considered for this design. However, the use of a
resonant network to provide some harmonic control is considered in section 3.8 as a means
of increasing the switch voltage headroom slightly to protect the device.
-25
-
Chapter 3
Inverter Design
3.1
Introduction
This chapter describes the process of inverter design, and presents the necessary steps in
the order that was found to be most efficient, beginning with a description of the design
goals. The selection of an inverter topology is then explained, followed by an extensive
discussion of switch device selection, which is especially important because switch nonidealities dominate converter loss. The processes of retuning the design to achieve higher
efficiency or output power are then described, as is the process of reducing the choke inductor
size to reduce the required PCB area. This chapter also considers the use of a discretecomponent multi-resonant choke to reduce switch voltage peaking. Several other issues,
such as switch package inductance compensation, switch packaging, and inductor design,
are also treated.
3.2
Specifications and Goals
The first step in designing this inverter is to bound the design space by deciding which
variables will be held constant, and which will be varied. This decreases the number of
dimensions in the inverter design space, which simplifies the analysis of the tradeoff among
output power, efficiency and inverter size. In this design, the constant parameters are the
input voltage range, the duty cycle, and the loaded quality factor (QL) of the resonant tank
composed of LR, CR and the RLOAD- QL is defined by Eq. 3.1 [7, page 150], where ws is
the switching frequency in radians per second, and fs is the same frequency in Hertz.
QL
WSLR
RLOAD
_
2rrfsLR
RLOAD
(3-1)
Parameters such as the switching frequency and the capacitance across the switch are varied
to explore design tradeoffs. This section explains why each of the parameters is either fixed
-
27
-
Inverter Design
or varied in this design.
3.2.1
Duty Cycle
Two of the important metrics of a Class E amplifier design are the peak-to-dc ratio of the
switch voltage, VYDC , and the peak-to-dc ratio of the switch current, IDC
I
[7, pages 154-155].
[,pgs1
These quantities are proportional to the amount of energy that is lost in parasitic resistances
due to the oscillation of energy through passive components. These ratios are also measures
of switch stress, and should be minimized for both reasons. A duty cycle of 50% is chosen
for this design because it minimizes the union of the two ratios, thereby maximizing the
power-output capability [8, pages 356-357]. A 50% duty cycle is also easier to achieve at
high frequency than a very small or very large duty cycle.
3.2.2
Loaded
Q
Factor
QL is chosen to obtain the desired tradeoff between output sinusoidal purity and low peak
switch current. In power amplifier applications, high QL is selected such that the voltage
across the load is as sinusoidal as possible. This produces narrow-band amplification, which
is useful in communication applications. However, high QL also produces a large ratio of
peak-to-dc switch current. This corresponds to a higher RMS switch current, and therefore
to greater switch conduction losses and passive component parasitic resistance losses. In
an inverter application, the spectral purity of the output voltage is not as important as
efficiency, and QL can be sized to give low tank loss. QL = 3 is chosen for this design based
upon the plots given in [7, page 154].
3.2.3
Input Voltage Range
An input voltage range of 11 to 16V is chosen to make the converter compatible with
conventional automotive systems and other 12V battery applications. Since the peak switch
voltage in the Class E topology is about 3.6 times the input voltage (given a 50% duty
cycle [8, page 362]), this design requires a device rated for at least 57.6V. To allow for
sufficient switch headroom, only devices rated for 65 or 70V (industry standard values for
communications devices at the time of writing) are considered for this design.1 A peak
'Refer to chapter 11.3 for a discussion regarding switch voltage headroom.
-
28
-
3.3
Switch Device Comparison Using Datasheet Information
switch voltage of ~ 60V is convenient because most of the next smaller available switch
devices are rated for 40V, and the next larger devices are rated to 100V.
3.2.4
Operating Frequency
The switching frequency fs is selected to accommodate the strong interaction between
frequency and both efficiency and output power. It was considered desirable, but not
essential, that fs be at least 100MHz to match or exceed the operating frequency of the
previous design [1]. This ensures that the energy storage requirements are not greater in
this design than in the previous design.
3.2.5
Efficiency, Output Power, Physical Size
Exact specifications are not set for inverter efficiency, output power and board size because
these variables are governed primarily by switch non-idealities, such as on-state resistance,
output capacitance and package size. At the time of writing, the evolution of appropriate
switch devices is so rapid that hard limits placed on these variable can become obsolete in
a few months.
3.3
Switch Device Comparison Using Datasheet Information
This section explains the process of identifying viable switch devices for the inverter. Selection of a switch is of foremost importance in this inverter design because the non-idealities
of currently available devices are strong limiting factors for inverter efficiency, output power,
size, and controllability. It is therefore advantageous to compare a variety of switches available from different manufacturers to find a device that will produce the best tradeoff among
inverter efficiency, output power, and size.
3.3.1
Selection of Devices
A variety of RF power transistors could be considered for this design, including Lateral
Double-diffused MOS (LDMOS) devices, Vertical Double-diffused MOS (VDMOS) devices,
and bipolar devices. However, most power VDMOS devices cannot be operated efficiently
at or above 100MHz because of high gating loss due to large gate-source and gate-drain
-
29
-
Inverter Design
Drain
CRSS
Gate ooCOSS
CISS
Source
Figure 3.1: A simplified view of the connection of parasitic capacitances in an LDMOS
device.
capacitances. These capacitances are greater in vertical devices than in lateral ones because
vertical devices have larger overlap between the gate and drain diffusion and between the
gate and source diffusion [14] [15, page 227, Fig. 2]. Bipolar devices also have high gating
losses due to their finite current gain. A more detailed comparison of bipolar and LDMOS
devices is given in [16].
As a result of the drawbacks of bipolar and VDMOS devices, the decision was made to limit
the device search primarily to LDMOS devices. LDMOS offers a combination of low on-state
resistance (RDSON), low output capacitance (Coss), and low input capacitance (Ciss),
which results in high efficiency inverter operation at very high frequencies, as explained
below. The capacitances Coss and CISS are shown, along with the reverse capacitance
CRss, in Fig. 3.1.
Minimizing RDSON reduces inverter conduction loss, increasing inverter efficiency. Ideally,
this parameter should be zero, since no aspect of converter performance is improved by
RDSON- CISS should also be minimized to reduce gating loss. As CIss is decreased, less
charge must be moved on and off of the gate in each cycle. Since the gate charge moves
through the gate resistance and the gate drive circuit parasitic resistances, moving less
charge on and off of the gate results in a higher gate-drive efficiency.
As Coss increases, the amount of energy that resonates through Coss to the load in each
cycle is increased. Similarly, as fs is increased, more energy is transferred to the load per
unit time. Inverter output power is therefore proportional to both Coss and fs. Thus, lower
values of Coss allow fs to be raised without increasing output power. This allows efficiency
to be kept constant as fs is increased, since output power is proportional to current, and
passive component loss is proportional to current squared. External capacitance (CEXTRA)
can be added from drain to source if a higher output power level is desired at a given fs.
This has several benefits over higher Coss.
-
30
-
3.3
Switch Device Comparison Using Datasheet Information
The most obvious benefit is that adding external capacitance affords greater design flexibility, because external capacitance can be added with only a slight modification to the
tuning of the resonant circuit. This allows the inverter operating point to be changed after
a switch has been chosen, and even after the printed circuit board has been laid out. In
this design, 20pF is added from drain to source in the final design to achieve the desired
output power level, which means that the board space requirement increases only slightly.
Additionally, discrete capacitors have a higher quality factor than the intrinsic LDMOS
output capacitance. Consequently, inverter operation is more efficient with a given amount
of external capacitance than with the same amount of internal capacitance.
Finally, the fixed external capacitance causes less peaking of VDS than a comparable amount
of additional internal Coss. This is attributable to the nonlinear relationship between Coss
and VDS [17, 18], governed by equation 3.2 where Cj, is the value of Coss at VDS = OV, V
is the built-in junction potential, and M is the grading coefficient. These three constants
are determined as explained in section 3.4.3.
Coss = CMO
(3.2)
When the switch turns off, VDS rises due to the oscillation of the resonant tank. As VDS
becomes larger, Coss becomes smaller. Since the current in Coss is roughly constant,
the smaller value of Coss causes an increase in the slope of VDS, as governed by the
constitutive equation for a capacitor. This causes VDS to rise more than it otherwise would,
thereby decreasing Coss further. An inverter with a larger value of Coss and no external
capacitance has significantly less voltage headroom than an inverter with low Coss and
fixed external capacitance. To demonstrate this, two inverters are compared in simulation
(see appendix A.4). Both inverters use the switch that was chosen for the final design. In
the first inverter, Cj, is increased by 20pF from its measured value, and no Coss is added.
In the second inverter, CjO is kept at its actual value, and 9.6pF of extra capacitance is
added such that the inverters have the same output power to within 1mW, and the same
efficiency to within 0.01%. The inverter with added external capacitance has a peak voltage
that is lower by 2.86V than the 70.28V peak of the other inverter.
Because of the benefits of low RDSON and low Coss, as described above, LDMOS devices
with a low product of RDSON and Coss are sought in the device search. When two devices
are compared based upon their RDSONCOSS products at a given value of VDS, the device
with the lower product will operate the inverter more efficiently. To form the product,
RDSON in ohms and Coss in picofarads are used, such that a device with RDSON = 10OMQ
- 31 -
Inverter Design
Drain
RGATE
Gate )--,1
S
D
Coss
Ciss-
(Ideal
RBIG
(100k
RDSON
Source
Figure 3.2: Layout of the PSPICE LDMOS model used to compare candidate LDMOS
devices based upon datasheet information.
and Coss = 10pF has an RDSONCOSS product of 1. CISS is not considered until the device
selection is narrowed down because it is typically on the same order of magnitude as Coss.
Appendix B contains information about all of the LDMOS devices that were identified in
this device search. This appendix also includes a table that contains information about a
number of VDMOS devices. Almost all of the VDMOS devices have a lower RDSONCOSS
product than the LDMOS devices, which supports the decision to focus on finding LDMOS
devices for use in this inverter design.
3.3.2
PSPICE Modelling with Datasheet Information
Comparison of devices based upon the product of RDSON and Coss gives an estimate of
how efficiently devices will perform relative to one another. To get absolute estimates of
inverter efficiency and output power with a given device, simulations can be performed in
software such as PSPICE using information obtained from device datasheets. This saves time
and money by eliminating certain devices from consideration before samples are ordered
and characterized. This section describes how LDMOS devices and the passive components
in the inverter can be modelled using datasheet information. Section 3.3.3 then explains
how these models can be used in simulations. A schematic of the switch model is shown in
Fig. 3.2, and a schematic of the entire inverter is shown in Fig. 3.3. The netlists for these
simulations are given in appendix A.5.
For each candidate LDMOS device, Coss is modelled as a fixed capacitance, rather than
a nonlinear capacitance governed by equation 3.2. This is because some datasheets give
Coss only at a single voltage, and a fair comparison is attained by using the same type
of information for all candidate devices. The equity of this comparison is increased by the
fact that most manufacturers of 65 and 70V LDMOS devices specify Coss in the range
-
32
-
3.3
Switch Device Comparison Using Datasheet Information
.......................................
...........
VIN
.......
LR
R
DMORLOAD
(13)
VSWITCH (sine)
device
model
Figure 3.3: Structure of the PSPICE inverter model used to compare candidate LDMOS
devices based upon datasheet information.
26 to 28V. The change in Coss over this range is quite small. As an illustration of this
fact, consider that the datasheet for the Freescale MRF373ALSR1 (appendix B) shows
Coss decreasing by about 0.5pF from 26 to 28V. By comparison, the other devices under
consideration have Coss values that differ from that of the MRF373ALSR1 by tens of
picofarads.
The value of CIss is also taken from the datasheets, where it is typically specified at the
same voltage as Coss. Like Coss, CIss is a nonlinear capacitance. However, CIss changes
very little over the VDS range of interest. As a result, CIss is considered constant, and its
nonlinearity is not measured in the device characterization described in section 3.4.
RDSON is given in the datasheets either explicitly, or as
VYsf,
. The values of the gate
resistance (RGATE) and the equivalent series resistance of Coss (Rscoss) are not typically
given in the datasheet, but are set at 300mQ for all candidate devices based upon typical
values for LDMOS devices. Estimating these values gives more accurate simulated estimates
of efficiency and output power.
The diode Dsw shown in Fig. 3.2 is ideal, and is intended to model the ability of the LDMOS
device to carry current only in the forward direction. The switch Si has a gain of over 126,
which is appropriate because the device is driven as a switch instead of as an amplifier. As
indicated in [19, page 2-97], the gain should not be made too great, or numerical problems
may arise. The switch is set to have a very low on-state resistance, such that the resistance
RDSON dominates the on-state resistance of the model, and a very high off-state resistance
of 1OIQ. The high off-state resistance is appropriate because typical LDMOS devices have
an RDSOFF which is on this order of magnitude (see Tables D.4 and D.5 in appendix D.3).
Also of note is the absence of a body diode in the LDMOS model. Unlike vertical devices,
lateral devices do not have a parasitic diode from source to drain.
The simulated inverter circuit, shown in Fig. 3.3, includes the LDMOS model described
- 33 -
Inverter Design
above, and passive components with non-idealities modelled as described here. The capacitor CR is modelled with a Q of 3000, based upon the datasheets for Cornell-Dubilier
Electronics (CDE) surface mount mica capacitors. The inductor LR is modelled using a Q
of 120 at 150MHz, which is typical for Coilcraft Mini Spring and Midi Spring surface mount
inductors. For the choke inductor LCHOKE, the dc resistance of 90mQ is modelled along
with the Q of 104 at 50MHz. The datasheets for the inductors and capacitors are shown in
appendix G.
To reduce the complexity of the circuit at this preliminary stage in the inverter design,
the LDMOS device is driven with an ideal sinusoidal voltage source, instead of with a selfresonant gate drive. The peak voltage of this source (18V) is approximately the voltage
that the self-resonant driver would apply to the gate, which gives a good approximation to
gate loss for each candidate device.
3.3.3
Inverter Performance Comparison Using PSPICE Simulation
Once the candidate LDMOS devices and the inverter passive components are modelled,
inverters can be designed at a range of frequencies and with a number of different devices.
The tank components are selected using Eq. 3.3 from tabular results in [7] with D = 50%,
QL = 3, no CEXTRA, and fs from 100 to 240MHz:
RLOAD
CR
-
=
0.2150
2150
27r fsCDS
(3.3a)
0.4166
27rfsRLOAD
LR = 3. 7 ORLOAD
27rfs
(3.3c)
This set of equations is implemented as functions in PSPICE to automatically generate
Class E tunings at a range of frequencies. Transient simulations are performed with a
stepping of the switching frequency, and efficiency and output power are plotted versus
frequency (Fig. 3.4). These plots allow the designer to decide which devices to purchase for
further characterization and simulation.
Based upon the data shown in Fig. 3.4, it was decided that the MRF373ALSR1 and the
MAPLST0810-030CF should be obtained and characterized. The AGR09080GUM was also
obtained, but was not characterized because it has a packaged area of 3.14 times that of the
M/A-COM and Freescale device packages. It was also decided that an operating frequency
-
34
-
3.4
Switch Measurement and Modelling
Efficiency vs. Frequency
Output Power vs. Frequency
93
40
Freescale MRF373ALSR1
-4- M/A-COM MAPLST0810-030CF
--
92
35
91
ST PD57018
-- Agere AGRO9030GUM
30
90
25
)
0
898-
....
...
.....
....
....
411
1111
m20
wU
86 - 87.
gr
0
GO00U
15
7
85. -e--
1
10
APLST010-030CF
re7GRMRF373ALSR1
Freescale
AgrST PD57018
1.2
1.4
1.6
1.8
Frequency [Hz]
2
2.2
2.4
1
1.2
1.4
1.6
1.8
Frequency [Hz]
x 108
(a) Efficiency
2
2.2
2.4
x 108
(b) Output Power
Figure 3.4: Simulated inverter output power and efficiency vs. frequency for four LDMOS
devices using datasheet information. The ST device was used in the first converter, and
is shown for reference. VIN = 16V. Plots include gate losses with ideal sinusoidal voltage
source drive.
between 100 and 160MHz would provide the most desirable performance. As can be seen
from Fig. 3.4, the maximum inverter efficiency for each device falls within this frequency
range (or below, where the passive components become larger than those used in [1]).
3.4
Switch Measurement and Modelling
This section describes the process of measuring certain ac and dc characteristics of the
candidate LDMOS devices. These measurements are made both to verify the datasheet
information and to obtain more information needed to model the devices more accurately
in PSPICE. The measured parameters are Coss, CIss, the ESR and ESL associated with
Ciss and Coss, and RDS. The gate threshold voltage is estimated based upon the RDS
measurement, as is RDSON.
3.4.1
Measurement of ac Characteristics
The ac measurements are made with an Agilent 4395A in impedance analyzer mode. An
Agilent 43961A RF impedance test adapter is connected to the analyzer, and an Agilent
16092A spring clip fixture is connected to the adapter.
-
35
-
An external dc power supply is
Inverter Design
connected via coaxial cable to the adapter, and a digital volt meter (DVM) is connected
at the output of the dc supply. The impedance analyzer calibration is done with the dc
supply connected and set to zero, and with the DVM connected. An averaging factor of
four is used to average out noise. The intermediate frequency bandwidth is low (30Hz)
to achieve accurate representation of the sharpness of the self-resonant points of CIss and
Coss, which allows accurate measurement of the impedance at this point. This impedance
is the equivalent series resistance (ESR) of the given capacitance [20, pages 305-307]. The
frequency sweep begins at 500kHz to allow accurate measurement of CIss and Coss without
including the effect of the self-resonance of these capacitances. The sweep goes up to
500MHz to allow the self resonant point (and therefore the ESR) of Ciss and Coss to be
measured accurately, since this point occurs at nearly 500MHz for some devices. The upper
frequency limit is also high because measurement of the equivalent series inductance (ESL)
of these capacitances requires impedance information for frequencies above the self-resonant
point.
To measure Coss, a short is soldered from gate to source, and a series capacitance measurement is made from drain to source at 1MHz, which is more than two decades below the
self resonant frequency. VDS is stepped from OV to the voltage at which Coss is specified in
the datasheet. Measurement of the M/A-COM MAPLST0810-030CF is accurate to within
4.65% of the datasheet value, and measurement of the Freescale MRF373ALSR1 is accurate
to within 1.95%.
The ESR and ESL are measured with an impedance magnitude measurement and a series
RLC equivalent circuit model. This measurement is made only with VDS = OV, because
the decision was made to simplify the PSPICE model by ignoring any voltage dependence
in ESR and ESL.
Similarly, CIss is measured only at VDS = OV, despite the nonlinear dependence of CIsS
on VDS. One reason is that CIss changes very little with voltage as compared with Coss,
and can therefore be reasonably approximated as constant. Furthermore, measuring gate
to source capacitance with a drain to source voltage connection requires three terminals.
Since the measurement fixture has only two terminals, the voltage connection would need
to be made at the device under test (DUT), and the wire for this connection would introduce far more noise than the coaxial connection made to the adapter from the dc supply.
Furthermore, the effect of this type of measurement setup on the test fixture is unknown.
To keep VDS = OV, a short is soldered from drain to source. The capacitance CIss, the
ESR and the ESL are measured using the impedance analyzer as described for Coss.
Shorting the drain to source to measure CIss has the drawback that the reverse capacitance
(CRss) appears in parallel with C 1ss. As a result, CIsS and CRss are not measured
- 36 -
3.4
Switch Measurement and Modelling
independently. However, this is unimportant for the measurement of Ciss since CRSS
is much smaller than Ciss for the switches being considered. For example, the CRSS is
2.03% of CIss for the Freescale MRF373ALSR1, and 2.4% of CISS for the M/A-COM
MAPLST0810-030CF. CRSS is small enough that it is not even estimated in the PSPICE
model.
All of the impedance analyzer measurements are shown in appendix D.2.
3.4.2
Measurement of dc Characteristics
To measure RDS as a function of VGS, a digital ohmmeter is connected from drain to source,
and a dc supply is connected from gate to source. The gate to source voltage is stepped
from zero to within a few volts of the maximum gate to source voltage, and the resistance is
recorded at each step, along with the measured value of VGS- To improve measurement accuracy, the resistance of the test setup is measured with both measurement leads connected
to the same lead of the DUT. This is an attempt to account for all of the contact resistances
involved. The resulting test setup resistance measurement is subtracted from the measured
values of RDS. The resistance data for both the M/A-COM MAPLST0810-030CF and the
Freescale MRF373ALSR1, along with more detailed information about the measurement
setup, is provided in appendix D.3. The measured and datasheet-specified values of RDS
are compared at the value of VGS for which RDS is specified. For the MAPLST0810-030CF,
the measured value of RDSON is greater than the specified typical RDSON value by 30%
to 60%, depending upon measurement variations, while for the MRF373ALRS1, RDSON is
10% to 54% greater than the specified typical RDSONFour-wire resistance measurements are also made of these devices in an attempt to reduce
the discrepancy between the measured and specified values of RDSON. Two short wires of
equal length are soldered to the drain terminal, and two more to the source terminal. These
wires are also connected to an HP 34401A digital multimeter by banana plugs. The gate
voltage is brought to the DUT with alligator clip lines, and the voltage VGS is measured at
the DUT. Using this technique, the RDSON of the M/A-COM part is found to be 296mQ,
or 48% greater than the datasheet-specified typical value, and the RDSON of the Freescale
part is found to be 146mQ, or 6.83% greater than the specified typical value.
The fact that the four-wire measurements do not yield significantly improved results suggests
that the (devices should be measured under the same conditions specified in the datasheets.
This involves forcing significant drain current through the device (3A for the Freescale
MRF373ALSR1 and 1A for the M/A-COM MAPLST0810-030CF) at the specified VGS
and measuring the resulting VDS. A curve tracer would be well suited to this type of
-
37
-
Inverter Design
measurement, as well as for measurement of threshold voltage (VTH). Because of concerns
about device damage, this type of measurement was not made, but should be considered
for future work.
A crude estimate of gate threshold (VTH) is the voltage at which RDS drops to single-digit
ohms. The value of VTH for the M/A-COM part is estimated at 4V and for the Freescale
device as 3.25V. More accurate measurements of VTH could be made using a curve tracer,
in which case VTH would be defined at the voltage at which the device begins to conduct
measurable current.
3.4.3
PSPICE Modelling using Measured Data
Once both ac and dc characteristics have been measured for the devices of interest, a more
accurate PSPICE model is created. This new model has the same topology as the one shown
in Fig. 3.2, except that Coss is modelled as a nonlinear capacitor, as explained below.
The values CIss and RDSON in the model are specified based upon the measurements
described above. The ESR of Coss and of CIss are used for the values Rscoss and
RGATE, respectively. The threshold voltages VON and VOFF of S1 are kept at the original
values of 0.9 and 0.1, respectively, because the inverter is driven with an ideal sinusoidal
source until the inverter design is complete and a self-resonant gate drive circuit can be
designed. This is because the self-resonant gate drive circuit affects the inverter duty cycle
significantly, such that modelling duty cycle non-idealities using switch threshold values is
irrelevant without the self-resonant effects. Once the self-resonant gate drive is designed,
VON is changed to VTH, and VOFF to VTH - 0.8V.
To model the nonlinearity of Coss, a voltage dependent current source with a current of
COSSL' is used [21, page 3/3]. A low pass filter is used to take the derivative, and must have
a cutoff frequency well above fs. If the cutoff frequency is too low, the voltage and current
of the nonlinear capacitor will not be 90' out of phase, and the element will introduce
additional loss. Experiments indicate that a cutoff at 30fs causes the capacitor model to
produce significant loss. A cutoff frequency three orders of magnitude above the switching
frequency produces no significant loss.
A PSPICE function is used to specify Coss. This function implements Eq. 3.2 for VDS
greater than or equal to zero, and fixes Coss at the zero bias value, C,0 , for VDS less than
zero. The text of the model may be found in appendix A.2.
A MATLAB script, shown in appendix D.2, uses Co and the value of Coss measured on the
impedance analyzer at two different voltages to solve for the variables M and Vj for use
-
38
-
3.5
Final Switch Selection
Coss vs. V
160'
-a- Measured
-
150
Modelled
140
130
120
... ...........
-.
110
100
Co 090
80
70
60
50
0
5
15
V DS]
10
20
Figure 3.5: Measured and modelled nonlinear Coss vs.
MRF373ALSR1.
25
30
VDS for the Freescale device
in the PSPICE function. Because of slight measurement errors and/or because Coss does
not match Eq. 3.2 exactly, different values of M and Vj are obtained for Coss at different
values of VDS. The best solution is chosen as the one with the minimum mean squared
error (MMSE) between the measured and modelled points. Only the capacitance values
at VDS between OV and 16V are used to calculate this MMSE, because the average value
across the choke, and therefore the average value across the switch, is not more than 16V.
Therefore, the most important values of Coss to simulate accurately are those between OV
and 16V. Fig. 3.5 shows the measured values of Coss and the optimal function selected
using this limited MMSE. Appendix D.2 provides the details about calculating this MMSE
for the M/A-COM MAPLST0810-030CF and the Freescale MRF373ALSR1. The optimal
function could alternatively be chosen as the one with the MMSE over all measured values
of Coss with minimal impact upon the simulation results.
3.5
Final Switch Selection
Once the candidate devices have been modelled in PSPICE, additional inverter simulations
are performed (see appendix A.6 for circuit files), and efficiency and output power are
plotted versus frequency, as shown in Fig. 3.6. It is clear from this figure that higher
efficiencies could be achieved by decreasing fs below 100MHz, but at the expense of reduced
-
39
-
Inverter Design
Output Power vs. Frequency
Efficiency vs. Frequency
e
M/A-COM MAPLST0810-030CF
- - - -Freescale
MRF373ALSR1
89
-4-
20
88
-e-
Freescale MRF373ALSR1
M/A-COM MAPLST0810-0300CF
18
87
916
> 86
a. 14
0
84
-..
- -..... -. ..... --............
-.
85
w
'S 12
ic
83
82
1
1.2
1.4
1.6
1.8
Frequency [Hz]
2
2.2
2.4
x 108
(a) Efficiency
1.2
1.4
1.6
Frequency
1.8
[Hzl
2
2.2
2.4
x 108
(b) Output Power
Figure 3.6: Simulated inverter performance based upon measured data for M/A-COM
MAPLST0810-030CF and Freescale MRF373ALSR1. VIN = 11V. Plots include gate losses
with ideal sinusoidal voltage source drive.
output power.
The dramatic improvement in output power of the Freescale MRF373ALSR1 over the M/ACOM MAPLST0810-030CF as shown in this figure is due to the higher output capacitance
of the Freescale device. The accompanying decrease in efficiency is not very great because
the Freescale device has significantly lower RDSON than the M/A-COM device. For these
reasons, it was decided to use the Freescale device. The datasheet for this device is shown
in appendix B.
3.6
Retuning for Higher Efficiency or Output Power
Up to this point, only the ideal Class E tuning as given by Eq. 3.3 has been considered. This
tuning provides zero voltage switching and high efficiency, but does not necessarily maximize
efficiency [6, page 13]. By retuning the Class E circuit to achieve maximum efficiency, it
is possible to determine whether and by how much the output power will decrease. This
allows the designer to decide whether retuning for maximum efficiency will be beneficial.
Retuning may be accomplished by carrying out simulated sweeps of LR (or CR) at a given
fs. Other methods of retuning, such as changing LR and RLOAD simultaneously, may be
more accurate but were deemed unnecessarily complicated for this design. The effects of
maximum efficiency retuning are shown in Fig. 3.7 for the Freescale device. This plot led
- 40 -
3.6
Retuning for Higher Efficiency or Output Power
Output Power vs. Frequency
18
-u-
17
-
Efficiency vs. Frequency
'0.5
No Retune
Max. Eff. Retune
Max. Eff. Retune
-0- No Retun
161589.5
14
-
89
13
aO 12
12
-
88.5--
-w
11
88
0 10
9
9
-
~87.5-
-
----
8
7
1
1.1
1.2
1.3
1.4
1.5
Frequency [Hz]
1.6
1.7
8
1.8
X 106
1
1.1
(a) Output Power
1.2
1.3
1.4
1.5
Frequency [Hz]
1.6
1.7
1.8
XW
(b) Efficiency
Figure 3.7: Simulated inverter performance vs. frequency for original tuning and maximum
efficiency retuning. Both inverters use Freescale MRF373ALRS1 and VIN = 11V. Plots
include gate losses with ideal sinusoidal voltage source gate-drive.
to the conclusion that the drop in output power caused by this retuning was too great to
justify the efficiency increase.
The ideal Class E tuning given by Eq. 3.3 can also be changed to gain higher power by
reducing RLOAD. The results of increased power retuning for the Freescale device are
shown in Fig. 3.8.
Of note in this figure is the fact that no maximum in output power
is reached despite the broad retuning range, which indicates that retuning for maximum
output power is impractical. It was decided that the drop in efficiency outweighed the power
increase gained by any of the retunings shown in Fig. 3.8.
An operating frequency of 100MHz was chosen to achieve the maximum efficiency attainable
without decreasing fs below 100MHz. Selecting a relatively low fs also makes the resonant
gate drive design easier by increasing the impedance (of CIss) that this circuit must drive,
as discussed in chapter 4. The ideal Class E tuning, as given by Eq. 3.3, was also chosen
because retuning for maximum efficiency or increased output power were ruled out, as
discussed above.
-41
-
Inverter Design
Output Power vs. Frequency
Output Power vs. Frequency
50%2.
-8-
8
S60%
17
--
8786---
100%
-.---
16 15
E14 -
-w
--
13
-
84
-
-
12 11.
1.1
1.2
090%
-7070
--
--
83-
--- 100%-
82 90%
80%/
81 --e-70%
60%80.-
--
1
--
-
18-8
-
-
1.3
1.4
1.5
Frequency [Hz]
-50%
1.6
1.7
71
1.8
x 108
(a) Output Power
1.1
1.2
1.3
1.4
1.5
Frequency [Hz]
1.6
1.7
1.8
X 108
(b) Efficiency
Figure 3.8: The effects of retuning for greater output power by setting RLOAD to various
percentages of the optimal Class E value. Percentages indicate percent of original RDSON
used in each tuning. Both inverters use Freescale MRF373ALRS1 and VIN = 11V- Plots
include gate losses with ideal sinusoidal voltage source drive.
3.7
Adding Drain to Source Capacitance for Higher Output
Power
Adding extra drain-to-source capacitance (CEXTRA) in parallel with Coss is another way
to achieve higher output power. This creates a lower impedance path to ground when the
switch is off, which draws more current into the parallel combination of Coss and CEXTRA
than would be drawn into Coss alone. The extra energy is then resonated to the output,
resulting in higher output power. This method of increasing the inverter output power is
preferable to mistuning the Class E topology for higher output power because CEXTRA can
be included in Eq. 3.3 when the inverter is tuned, such that ZVS is maintained.
Unfortunately, any capacitance added in parallel with the switch resonates with the package
inductance (LPACKAGE) of the MOSFET. This causes greater peaking of both the external
and internal VDS waveforms, where the internal voltage measurement does not include the
voltage across the package inductance. Of the two simulated voltages, the internal is the
more important because it represents the voltage that will appear across the semiconductor.
The device voltage rating may not take this type of oscillation into account, and should
be treated as the maximum voltage that can appear across the semiconductor without
damaging it.
-
42
-
3.7
Adding Drain to Source Capacitance for Higher Output Power
The increased voltage peaking reduces the switch voltage headroom, putting the switch at
greater risk of burnout during transient events. The RMS switch current also increases due
to these oscillations. This causes increased losses in RDSON and the passive component
parasitic resistances, thereby lowering efficiency.
The solution to this problem is to increase the impedance of CEXTRA at the offending
resonant frequency by adding an inductor LMRS in series with CEXTRA. Initial (erroneous) measurements of the frequency of this oscillation indicated that it occurs at roughly
three times the resonant frequency of the inverter in steady-state with the switch open,
fOPEN. It is assumed that the oscillations occur in the series LC circuit composed of
Coss, LPACKAGE, and CEXTRA, and that the oscillations can be suppressed by adding
LMRS to make this circuit low impedance at the oscillation frequency. LMRS is calculated
using Eq. 3.4.
LAIRS
COSS+ CEXTRA
COSSCEXTRA (2'w3fOPEN)
(3.4)
where the factor of 3 reflects the initial assumption that the undesired resonance occurs at
three times fs. Simulations indicate that although the oscillation frequency is actually much
higher, setting LMRS as in Eq. 3.4 gives nearly the best performance, which is compared to
the uncompensated performance in Fig. 3.9. These plots were produced with a file like the
ones shown in appendix A.6 using the values VIN = 16V, fs = 100MHz, CEXTRA = 20pF,
LCHOKE = 538nH, CPDS = 5.9pF, and RPDS = 5.3343Q. The Freescale MRF373ALSR1
is modelled with RDSON = 0.16Q, RSCOSS = 0.3Q, LPACK = 2.84nH, RGATE = 0-27,
CIss = 109.68pF, C 0 = 161.13pF, V = 0.69152V, and M = 0.32434. The following tank
values were calculated with Eq. 3.3 assuming Coss = 64.3970pF (Freescale MRF373ALSR1
Coss at VDS = 11V): LR = 21.3582nH, CR = 163.5338pF, RLOAD = 4.0544Q, where
LPACKAGE has been subtracted from the calculated value of LR to get the value given
here. This subtraction is made with the assumption that LR and LPACKAGE are in series,
which is reasonable because the choke impedance is very high at fs.
LMRS was also varied around the value calculated with Eq. 3.4.
The results (shown in
Fig. 3.10) indicate that the inverter is fairly sensitive to variations in LMRS. As LIRS
is swept over a range, the interference between the various oscillations in the inverter is
alternatingly constructive and destructive, which creates the pseudo-periodic spikes in the
VDS vs. LIRS plot. Because the location of these spikes is dependent upon LPACKAGE and
many other parameters which are difficult to measure exactly, LMRS must be set empirically
once the inverter is built, as described in chapter 10.6. Fig. 3.10 indicates that 4.25nH is
a good starting value for LAIRS because internal and external peak voltages are low, and
power and efficiency are high at this inductance.
-
43
-
Inverter Design
External VDS vs. time
60
A=3.1298V
-
50
LMRS= .
-- . NoLMRS
-
30
nH
LMRS=
5o
-
-
0
E
a
C
2985
-
.No
.
nH
LaRS
4
3
0-
--
0**
10
-
a
-
I
I
2.99
5 494 7
2
ai
a
-In
a
A=7.313V
5.
0
vs. time
6
'
5 49 47
40
Internal V
70
time [sec]
2.995
3
x 10-,
2 985
(a)
2.99
time [sec]
2.995
3
x 10'
(b)
Figure 3.9: Simulated external VDS (Fig. (a)) and internal VDs (Fig. (b)) for an inverter
with CEXTRA = 20pF with and without LMRS for package inductance compensation.
Although inductance cannot be added in series with the parasitic drain to source capacitance
(CPDS) because of its distributed nature, the results shown in Fig. 3.10 include 5.9pF of
CPDS, which indicates that acceptably low peak internal and external VDS can be achieved
by varying LMRS.
The next section provides further guidance regarding the choice of CEXTRA by giving the
simulated results for a wide range of capacitances.
3.8
Choke Inductor Implementation
As discussed in chapter 2, the purpose of the choke inductor (LCHOKE) is to provide a
nearly constant current to the rest of the inverter. The choke also acts in conjunction
with input capacitors as an input filter to minimize the switching ripple that appears on
the unregulated input bus. As a result, LCHOKE is the largest passive component in the
inverter, and it is advantageous to investigate the possibility of reducing the size of LCHOKE.
Table 3.4 on page 53 shows inverter efficiency, output power, and maximum VDS for three
values of LCHOKE, as well as for a range Of CEXTRA values. The first LCHOKE value,
538nH, was used in the first converter design [1], and is the largest value inductor in the
largest air core inductor package made by Coilcraft, the Maxi Spring. The 120nH inductor
is the largest value in the next smaller Coilcraft package, the Midi Spring. The 120nH
-
44
-
3.8
Maximum V
Choke Inductor Implementation
vs s
Power and Efficiency vs.
s
89
30.5
0 -
800
-
29.5
70
88
Eff
-30
75
-
-
29
65
0
E
-86
C
E -2827.5-
6%
E
87
28.5
.
-
..
I.I
85
M0
-84
55
27
0
2
4
83
26.5 -
-+- Internal VDS
.... External V2
50
6
8
LMRS [nH]
10
12
14
10
2
4
6
8
LMRS [nH]
10
12
14
Figure 3.10: Simulated inverter performance for a range of LMRS values.
inductor is less than half the volume of the 538nH coil, and has a typical Q of 125, 20.19%
greater than that of the 538nH coil. The model for each choke includes the nominal Q
and maximum dc coil resistance (RDC), as specified by the Coilcraft datasheets shown in
appendix G. The effect of using two 120nH inductors in series is also shown in Table 3.4.
The choke inductor could instead be implemented as a multi-resonant circuit or structure [22]. In this case, the choke not only functions as a current source for the rest of
the inverter and an input filter, but also as a filter for reducing the peak value of VDS. A
multi-resonant choke presents a low impedance to the first n even switch voltage harmonics
and a high impedance to the first m odd harmonics. This produces a VDS waveform which
is closer to a square wave, and which therefore has a lower peak value than the Class E
VDS waveform [22]. The tradeoff is that switch current peaking increases. This type of
operation is similar to that of the Class F amplifier.
The possibility of using an integrated multi-resonant (MR) structure is not considered extensively for this design because of the added complexity of such a design. However, an
MR circuit made of four discrete components, shown in Fig. 3.11 with components related
by Eq 3.5, was designed and simulated in place of a single-inductor choke [9, page 106].
LMR1 =
1
9CMRlfSw2
CMR2 ==15 CMR1
16
LMR2 =
1
15CMR1fsr 2
45
-
(3.5a)
(3.5b)
(3.5c)
Inverter Design
ZP
Zs
LMR2
CMR1
LMR1
CM2
ZMR
,
Figure 3.11: Idealized MR topology for controlling the first three harmonics of any waveform.
Magnitude vs. Frequency
Magnitude vs. Frequency
80
80
60-
604-40
20
-c
c 20
Ca
CO
v
-
Il
30.
0
-
--
0
--
--
E
E
-20
-20
0.5
1
-40
1.5
3
2
2.5
Frequency [Hz]
3.5
4
-40
4.5
5
x 108
(a) Impedances Zp and Zs
0.5
1
1.5
3
2
2.5
Frequency [Hz]
3.5
4
4.5
5
x 10
(b) Impedance ZMR
Figure 3.12: Magnitude vs. frequency of the impedances Zp and Zs (3.12(a)) and ZMR
Zp 1 Zs (3.12(b)) in the MR circuit of Fig. 3.11. For this simulation, CMR1 = 100pF,
and PSPICE functions are used to determine LMR1 = 11.2579nH, CMR2 = 93.75pF and
LMR2 = 6.7547nH.
The set of equations 3.5 are derived in appendix E. However, the multi-resonant effect can be
understood qualitatively by considering the impedance of the parallel circuit (Zp) formed
by LMR1 and CMR1, and the impedance of the series circuit (Zs) formed by LMR2 and
CMR2. The magnitude of these two impedances are plotted in Fig. 3.12(a). When these two
impedances are placed in parallel, the overall impedance magnitude at any given frequency
is dominated by the lower of the two impedances at that frequency. Also, when the two
impedances are equal in magnitude and opposite in phase at a given frequency, the resulting
overall impedance has a peak at that frequency, just as in a parallel LC combination. Given
these facts, it may be understood that the impedances shown in Fig. 3.12(a) combine to
produce a peak at 100MHz, a null at 200MHz, and a peak at 300MHz, as desired and shown
in Fig. 3.12(b).
-
46
-
3.8
IN
VIN (DC)
LMRI
+
Choke Inductor Implementation
LR
CR
LMR2
LR!Gate
-
Drive
RLOAD
CMR2T
Figure 3.13: Class E inverter with MR choke.
When used as a choke, the MR circuit can be configured with the series connection LMR1CMR2 connected to true ground instead of to the dc supply, as shown in Fig. 3.13, because
node IN is an incremental ground. This placement of the LMR1-CMR2 leg prevents the
second harmonic current from being drawn through the supply, thereby reducing input
ripple. In simulation (with an ideal voltage source for VIN), moving the LMR1-CMR2 leg
from node IN to ground has no effect on performance.
The fact that node IN is an incremental ground also allows CMR1 to be composed entirely
of Coss, thereby reducing the component count. However, because of the nonlinearity of
Coss, the nominal Coss value that is used to determine LMR1, LMR2, and CMR2 must be
swept in simulation to determine their optimal values. Sweep data for the Freescale part is
shown in Table 3.1. These simulations are done with VIN = 16V, fs = 100MHz, D = 50%,
CEXTRA = OpF, CPDS = 5.9pF, and RPDS = 5.3343Q. The Freescale MRF373ALSR1 is
modelled with RDSON = 0.16Q, RsCOSS = O.3Q, LPACK = 2.84nH, RGATE = 0.27Q,
Ciss = 109.68pF, Cj,, = 161.13pF, V = 0.69152V, and M = 0.32434. The following
tank values (specified with greater precision than necessary) were calculated (using PSPICE
functions) with Eq. 3.3 assuming Coss = 64.397OpF (Freescale MRF373ALSR1 Coss at
VDS = 11V): LR = 28.8735nH, CR = 124.7804pF, RLOAD = 5.3137Q, where LPACKAGE
has been subtracted from the calculated value of LR to get the value given here. The values
LMR1, LMR2, and CMR2 are calculated from Eq. 3.5 using the listed nominal Coss values
for CMR1The inverter with the highest-efficiency MR tuning (with nominal Coss = 90pF) is chosen
from Table 3.1 and retuned for optimal Class E operation using the methods described in [6].
This is accomplished by first sweeping CR and then RLOAD to achieve maximum efficiency,
as shown in Table 3.2. The optimal tuning is indicated in this table and produces the VDS
waveform shown in Fig. 3.14(a), which clearly lacks ZVS. This is because the frequency at
which LVIR1, LMR2 and CMR2 are calculated (fs) is too low.
The values LMR1, LMR2 and CMR2 should instead be calculated using the frequency of the
resonant tank with the switch open (fOPEN). However, retuning would also be required
in this case because the open-switch resonant tank does not oscillate in steady state, and
-
47
-
Inverter Design
External
Internal
Coss
Nominal
[pF]
[%]
[W]
[V]
[V]
120
110
75.48
76.79
17.626
16.956
54.118
52.440
85.130
80.205
100
78.03
16.316
50.511
75.104
90
80
70
78.92
78.84
77.73
16.190
16.334
16.215
49.391
49.624
48.647
71.522
69.975
66.653
64.3970
77.08
16.005
48.020
65.263
60
55.5
60
76.25
75.29
73.48
15.900
15.727
15.624
48.362
47.469
47.443
64.972
62.968
62.258
7j
POUT
VDSMAX
VDSMAX
Table 3.1: Simulated effects on inverter performance of varying the nominal value of Coss
used to calculate the other MR circuit values. Measured parameters are efficiency (a),
output power (POUT), and external and internal maximum VDS.
therefore has no well-defined natural frequency. Instead, the switch duty ratio is decreased
to allow more time for VDS to reach a zero-value and zero-slope condition before the switch
is turned on. This can be accomplished in both simulation by changing the dc offset of the
gate drive sinusoid. Fig. 3.14(b) shows the internal VDS waveform of the inverter with an
MR choke and a duty ratio of 43.61% accomplished with a dc offset of -3.OV at the gate.
The MR circuit exhibits ZVS, indicating that little to no improvement can be achieved by
retuning the MR inverter. A non-MR circuit with higher efficiency and output power is
also shown. 2 The two circuits are compared in Table 3.3, which provides a loss breakdown
for both circuits. Notice that this loss breakdown does not include loss in LMR2 or CMR2
because these components are ideal in the MR simulation. Clearly the MR circuit's efficiency
will drop further when losses in these components are considered.
Based upon the data in Table 3.3, it was decided to use a non-MR inverter. It was also
decided to add 20pF of CEXTRA, and to use two 120nH choke inductors, based upon the
data in Table 3.4 on page 53. The resulting inverter is shown in Fig. 3.15 with a table
of component values. This inverter design provides nearly 30 watts of output power at
maximum input voltage, while maintaining an efficiency of greater than 87%. Given a
simulated rectifier efficiency of 93% (see chapter 6), this produces an overall efficiency of
over 80%. This choice of choke inductor size also allows the 538nH choke to be used in
practice because of the length of two 120nH inductors is roughly that of a 538nH coil.
Measurements of inverter performance are also made with a single 120nH inductor, as
explained in chapter 10.
2
The output power of the non-MR circuit is only higher because this circuit has
the MR circuit has CEXTRA = OpF.
-
48
-
CEXTRA
= 10pF, while
3.9
CR
RLOAD
POUT
T7
[pF]
Q
[%|
[W]
124.7804
5.3137
""))
""
78.92
16.190
78.40
80.03
24.321
25.488
80.82
83.17
25.864
25.995
83.40
25.720
83.56
83.55
83.56
83.55
83.41
83.47
83.39
83.61
25.443
25.124
24.798
24.480
24.184
23.773
23.511
25.602
70.7804
72.7804
73.7804
79.7804
80.7804
81.7804
82.7804
83.7804
84.7804
85.7804
86.7804
87.7804
81.7804
""
""
""
""
""
5.2137
Inductor Loss Reduction
5.0137
83.76
25.903
4.8137
4.6137
4.4137
4.2137
83.68
83.69
83.43
83.22
26.121
26.582
26.714
26.977
<-Optimal
Table 3.2: Retuning the MR inverter resonant tank for maximum efficiency operation. The
first line is the best tuning from Table 3.1, where the optimal MR choke tuning is found.
Average Power Dissipation in:
Inverter
Type
MR
non-MR
Ti
POUT
RDC
in LMR1
RDSON
Rscoss
CR
LR
RGATE
[%]
[W]
[mW
[mW
[W]
[mWj
[mW
[W]
[mW
86.32
88.89
24.531
26.466
279.9
305.6
277.9
3.82
1.3701
1.2082
636.48
386.12
18.07
13.22
1.0003
1.0669
RAC
in LMR1
207.7
207.7
Table 3.3: Simulated comparison between MR and non-MR inverters. Measured parameters
are: efficiency (rq), output power (POUT), RMS current through RDSON, and loss in all
resistances. The full simulation is shown in appendix A.7.
3.9
Inductor Loss Reduction
As shown in Table 3.3, the loss in the ac resistance of LR is comparable to the switch
conduction loss in RDSON. This indicates that significant efficiency improvements can be
achieved by increasing the Q of LR. One way of increasing the Q of an inductor is to
increase the usable cross sectional area of the wire. Although this can be accomplished
with Litz wire, coupling between the strands, as well as winding non-idealities, make Litz
wire less effective above 1MHz [23].
Another way of increasing the Q of a linear coil is to make the ratio of coil length to diameter
unity [24]. Many of the Coilcraft air core inductors have an aspect ratio that is either much
larger or smaller than unity. However, the 12.5nH Coilcraft inductor used for LR has a ratio
of 1.16, which is sufficiently close to unity that a hand wound inductor was not attempted
for this design.
-
49
-
Inverter Design
Internal V
Internal VD
0 vs. time
MR Choke
- -- Single-Inductor
60 -
vs. time
MR Choke, D=43.61%
60 -
Choke
-5
-
50 - -
-
50
Single-Inductor Choke, D=50%
- -
40-
40-
30 -
-cc-
I
10
30 --
-
--
--
0
-
-
--
-
*0a
-
**
0[
1.486
1.488
a
1.49
1.492
time [sec]
1.494
1.496
2.984 2.986 2.988
X 10-a
2.99
2.992 2.994 2.996 2.998
time [sec]
(a)
x 10,
(b)
Figure 3.14: Fig. 3.14(a) shows VDS of the inverter with an MR choke, tuned for maximum
efficiency, and with D = 50%. Fig. 3.14(a) also shows VDS for an inverter with a singleinductor choke and CEXTRA = OpF. Fig. 3.14(b) shows VDs of the MR inverter with the
highest efficiency tuning at D = 43.61%. Fig. 3.14(b) also shows VDs for an inverter with
a single-inductor choke and CEXTRA = 10pF. Note that the non-MR inverters do not
have perfect Class E (ZVS) waveforms because the decision was made to use tank values as
calculated with Eq. 3.3.
The use of powdered iron cores designed for 100MHz operation was also considered. A
core contains the flux lines far more effectively than air, reducing the eddy currents that an
inductor of a given inductance creates in nearby conductors, and thereby reducing the loss
in these conductors. Powdered iron cores also have the potential to increase the Q of LR,
despite the added loss introduced by the core. This is because powdered iron cores have a
higher permeability than air, and therefore require fewer turns for a given inductance. For
a given volume, the turns can be spaced apart more, reducing the capacitance between each
turn. This increases the coil's self-resonant frequency, where the Q of the coil is zero.
Powdered iron cores suitable for 100MHz operation are available from CWSBytemark. The
smallest three core sizes (0.125", 0.160", and 0.200" outside diameter) were considered
for this design because their dimensions are comparable to the 12.5nH inductor used for
LR (see Table 10.3 and appendix G). Unfortunately, these cores do not have the flux
density required for this application. This is determined by calculating the number of turns
required to achieve 12.5nH using Eq. 3.6a [25], where the inductance L is given in pH and
the inductance index AL is given in pHO100turns. AL is specified by the manufacturer
for each core. Eq. 3.6b [26] is then used to find the flux density 3 in gauss, were E is the
maximum RMS voltage across the inductor, Ae is the core cross sectional area in cm 2 . A
-
50
-
3
3.10
ROUT
-CHOKE
0
LR
R
CEXTRA
VIN
(DC)
CN-Gate
LCHOKE
M
RLOAD
LmRs
C
g
240nH
RLOAD
3 L4.0544Q
r
Switch Packaging
I
LR
CR
21.3582nH
163.5338pF
CEXTRA
LMRs:
20pF
5.4947nH
DC Voltage Source 1
(a) Final inverter topology
(b) Table of values
Figure 3.15: Final Class E inverter design.
margin of safety is achieved by using the peak voltage, instead of the RMS voltage, across
the inductor for the variable E.
N = 100
E x 108
4.44AeNfs
(3.6a)
(3.6b)
12.5nH can be achieved with N = 5.976 ~ 6 turns on a size 20, material number 0
(0.200"O.D., Ae = 0.025cm 2, AL = 3.5piH100turns) CWSBytemark core. Simulation
of the final inverter design at VIN
16V shows that 2 3 .17 VRMS appears across 12.5nH of
LR (total 21.3582nH). The resulting flux density is 34.92 gauss without the recommended
safety margin. Although data is not available for the maximum allowable flux density of
this core at 100MHz, 34.92 gauss exceeds the allowable flux density at 28MHz [27]. Since
flux density decreases monotonically with frequency for the CWSBytemark cores, 34.92
gauss undoubtedly exceeds the 100MHz flux limit. The flux density in a 12.5nH inductor is
even higher in smaller cores, and in the other three core materials rated for use at 100MHz.
Moreover, the Q of this inductor is nominally 128 at 150MHz [28], as compared to the
Coilcraft A04TJ 12.5nH air core inductor with a Q of 137 at 150MHz. For these reasons,
powdered iron cores were not tested in this design.
3.10
Switch Packaging
The largest component in the inverter is the MOSFET, primarily because the available
RF power LDMOS devices are intended for use as linear amplifiers rather than switches.
Because of the relative inefficiency of amplification, the device packages are far larger than
necessary for a switching application. The Freescale MRF373ALSR1, for example, is rated
-
51 -
Inverter Design
for a total device dissipation of 278W at 250. Assuming 87% inverter efficiency and a
maximum output power of 30W, this design requires the MRF373ALSR1 to dissipate a
maximum of 4.48W. Package size reduction is clearly both possible and advantageous. In
addition to reducing PCB area, reduction in package size also has the potential to decrease
package inductance by allowing shorter bond wires to be used. The remainder of this section
discusses the preliminary investigative work that was done in the area of switch packaging.
This work was done before the Freescale MRF373ALSR1 was found, and therefore this
section treats only the M/A-COM MAPLST0810-030CF.
A set of unpackaged MAPLST0810-030CF dice, a wire bonding diagram (not shown) and
bonding specifications were provided by M/A-COM. Unfortunately, the available bonding
machine could not be set up for 0.002" aluminum bond wire as required by the bonding
specifications. The possibility of having the die packaged professionally was then considered,
as were a variety of packages. Due to the high aspect ratio (- 5) of the die, none of the
packages with sufficient length were narrower than the original M/A-COM package. Other
packaging techniques, such as chip-on-board (COB, which refers to mounting the die directly
to the PCB and covering it with epoxy), were then considered. Because of the discovery of
devices with lower RDSONCOSS products like the Freescale MRF373ALSR1 and the Agere
AGR09030GUM, COB was not pursued further.
-
52
-
-
]-
CC
CEXTRA
CAD
[pF]
LmRS
[nH]
0
0
RDC
POUT [W:
Ext. VDSMAX[VI:
Int. VDSMAX[V:
5
24.0355
11
% 88.1172
10.991
VIN[V]:
SOUT [WJ
Ext.
:l
10
11n6945
10
VDSMAX[VI
V11
88.0104
77[%]:
9)
PO11.741
Ext. VDSMAX[V]:
Int. VDSMAX [V:
15
7.5690
V
[]:
POUT W:
Ext
I_ Int. VDSMAX [V:
20
5.4947
I
i[%J:
PouWT ]:
Ext. VDSMAX[VI:
Int. VDSMAX[VI:
25
4.0000
VIN[V:
POUT[WI:
2.8000
35
1.8000
-
. POUTW]: 1
_
_
-III
_,
mt.
V:
VDSMAXVI:
13.5
88.3417
12.510
19.316
-DMXV:
--
16
89.0202
24.509
58.037
62 .369
16
88.8340
26.151
57.249
60.090
16
88.6166
27.701
56.666
-59.679
11
13.5
87.5971
13.247
88.0936
20.429
-
-
11
87.4499
14.052
_
111
1 %J: 1 87.3530
POUT[W: 1 14.952
Ext. VDS-nt. VDSMAX
|I:
"IN(V:
11
[ 87.1600
-VDSMAX
-13.5
88.5406
18.162
-
VDSMAX[V]:In-t. VDSMAX[V:
30
13.5
88.7050
17.036
-
11
87.8376
VIN(V]:
CD
= 90MQ
-
_
[
__
11.6945
CD
= 104 at 50MHz
1 of Coilcraft 132-20SMJ
11
13.5
16
88.1975
88.8299
89.1545
10.166
15.810
22.858
58.641
65.071
VIN[V:
QL = 125 at 150MHz
RDC = 2 x 17.3m1
2 series Coilcraft 1812SMS-R12J
LHOKE = 120nH
QL = 125 at 150MHz
RDC = 17.3mQ
I of Coilcraft 1812SMS-R12J
11
88.5955
10.430
11
88.5179
10.750
LCHOKE = 538nH
QL
15.889
-
13.5
87.9195
2149
-Ext.
-
13.5
87.7301
23.034
-
LCHOKE =
-
-
-
-
11
88.5716
11.230
-
13.5
89.1338
17.475
11
88.5011
12.059
-
13.5
89.0091
18.679
11
88.3477
12.850
-
13.5
88.8635
19.847
-
16
88.4005
29.274
56.167
61.116
11
88.1745
13.568
16
88.1503
30.958
55.935
62.268
11
88.0529
14.390
16
11
87.9839
15.319
-
87.9346
32.919
56.495
61.782
13.5
89.1858
16.251
-
-
-
-
-
-
13.5
88.6337
20.993
-
13.5
88.4930
22.187
240nH
16
89.4931
23.484
60.491
67.451
-
--
63.157
71.021
11
13.5
16
88.5518
11.548
89.0477
17.965
-
89.3062
25.887
61.928
67.15 1
13.5
88.9837
19.153
-
16
89.2221
27.543
60.883
64.166
_
16
89.2832
26.851
58.681
_
11
88.5018
12.343
---
61.671
16
89.1184
28.498
58.169
61.275
16
88.9082
30.043
57.552
62.452
|
|
-
11
88.4149
13.122
_
-
13.5
88.8516
20.327
--
16
89.0920
29.203
59.980
62.796
11
13.5
88.2353
13.872
-
88.6655
21.464
-
16
88.8774
30.802
59.472
64.118
-
11
88.0412
15.623
-
16
88.5657
33.759
57.574
-
62.547
-_ _
88.3495
23.662
24.249
16
11
88.1117
14.690
_
-
13.5
16
89.3079
89.4238
25.073
59.410
64.077
16
88.7081
31.827
57.358
63.278
-
13.5
89.0349
16.772
-
-
-
13.5
88.5080
22.691
_
-
13.5
88.3923
24.098
-
16
88.7205
32.546
59.169
65.011
16
88.5796
34.519
59.331
64.149
13.5
87.4890
16
87.6451
11
87.8183
13.5
88.1555
16
88.3054
11
87.8855
13.5
88.1697
16
88.3241
24.418
-
34.869
57.403
60.551
16.292
-
25.077
35.825
58.960
16.612
25.586
--
36.602
---
63.252
-
-
61.965
__-
60.668
Chapter 4
Gate Drive Design
4.1
Introduction
One of the most challenging aspects of high frequency dc/dc converter design is the design
of gate drive circuitry with sufficiently low loss. When active, hard-switched gate drive
control is used, all of the energy placed on the gate capacitance in each cycle is dissipated
as heat. Resonant gate control reuses this energy, and therefore has much higher efficiency.
This chapter discusses the design of a resonant inverter gate drive circuit that uses feedback
to sustain 100MHz oscillation in the absence of external control. A small regulated supply
is used to power the gate drive, and on/off control circuitry (described in section 4.5) is
used to start and stop inverter operation. The design of this stage of the converter was
carried out in conjunction with Juan Rivas.
Drain
Gate
CrBLIIMOSFET
CFB
RGE
AAT
RD2R
RFB
LFB
1
Iss
Figure 4.1: SO gate drive circuit used in the original design [1].
startup/inhibit circuitry is not shown.
-
55
-
For simplicity,
Gate Drive Design
Magnitude and Phase vs. Frequency
0
180
-20
135
Phase
-40
90
a
-60
-80
0(
a
.r
aL
0
'0
C
Magnitude
-1002
-45
-120
-90
-140
6
-135
10 4
8
-160
10
10
Frequency [Hz]
Figure 4.2: Magnitude and phase of the transfer function
1010
s
(w) used in the first gate drive
design.
4.2
Initial Gate Drive Design
The self-oscillating (SO) gate drive circuit used in [1] and shown in Fig. 4.11 was initially
considered for this converter design. This circuit utilizes the fact that the fundamental of the
drain voltage lags the necessary gate waveform by 163', as determined through simulation.
Accordingly, LFB, CFB and RFB are used to advance the drain waveform fundamental by
163 , scale it to within gate voltage limits, and apply the resulting voltage to the gate. The
impedance into the gate drive from the drain is made high such that the Class E resonance is
not damped significantly. The duty cycle of this circuit can be adjusted slightly around 50%
by applying dc offset to point A in Fig. 4.1. The parallel combination of LD2R and RD2R is
included to present a high impedance at the frequency of an unwanted oscillation (roughly
2GHz). However, as described below, this design requires a different design approach.
4.3
Gate Drive Circuit Redesign
The gate drive shown in Fig. 4.1 cannot be used in this design because the gate of the
Freescale MRF373ALSR1 is rated for -0.5 to +15V, rather than for a symmetrical voltage
like the ±20V rating of the ST PD57018 used in [1]. The possibility of applying a large
'All figures from [1], including Figs. 4.1 and 4.2, are reproduced with permission of the authors
-
56
-
4.3
Gate Drive Circuit Redesign
dc offset to the gate voltage sinusoid can be ruled out immediately because this increases
the duty cycle by an unacceptable amount. Clipping the negative portion of a zero-offset
sinusoid with a diode works in principle, but the diode capacitance allows negative gate
voltage excursions.
The solution used in this design is to drive the gate with an approximation of a square
wave, offset to fall within the gate voltage limits. The remainder of the section describes
the design of such a gate drive, beginning with an explanation of a circuit that produces a
square wave approximation, and followed by the design of a suitable SO circuit.
4.3.1
Multi-Resonant (MR) Circuit Design
A reasonable approximation (for this application) to a square wave can be made by controlling the first three harmonics of the gate voltage using the MR circuit explained in
chapter 3.8.
Fig. 4.3 shows an SO gate drive with an MR circuit composed of LMR1, CMR2, LMR2.
CMR1 is the parallel combination of CIss of the main device (M 1 , the MRF373ALRS1)
and Coss of M 2 . This relies upon minimally-inductive connections between M 1 and M 2 as
discussed in chapter 9.2.
The capacitor used for CBp is chosen to have a self-resonance at fs such that CBP is
a lower impedance than RVGIN at this frequency 2 . This makes point B an incremental
ground, and LMR1 appears in parallel with CMR2, LMR2 and the parallel combination
CISSMI 11COSSM2. The configuration of LMR1 also allows the dc offset of VGsM1 to be set
by the gate drive supply voltage, VGIN, since the average voltage across LMR1 is zero. This
allows the gate voltage to be offset such that it does not go negative.
4.3.2
Self-Oscillating (SO) Circuit Design
The rest of the circuit shown in Fig. 4.8 is a self oscillating gate driver for M 1 . The additional
MOSFET M 2 is a Polyfet L8821P, which has a symmetrical gate voltage limit. This device
was also chosen because it is designed to dissipate less than 1/3 PDISS of the Freescale
MRF373ALRSR1, and is therefore much smaller. The L8821P also has maximum VGs and
VDS ratings of ±20 and 36V, respectively, which are both higher than the maximum VGS
2
RVGIN
tion 10.2.
is a discrete resistor. In practice, this resistance can be reduced to zero, as discussed in sec-
-
57
-
Gate Drive Design
Class E Tank
and LCHOKE
Self-Oscillating Gate Drive
MR Circuit
RVGIN
LMR
M1
Freescale
MRF373ALSR1
I
LMR2
VGIN (DC)
-
C BP
SelfOscillating
Passive
Feedback
Network
I
I1
I
_
CMR2
T
L
-
-
-
M2
VGSM1
I
-I I_
Figure 4.3: Redesigned gate drive circuit composed of an MR circuit and an SO gate drive
circuit.
rating of M 1 . The Mitsubishi RD01MUS1 was also considered for this design because it
requires less than 0.6 times the board area of the L8821P, and has acceptable (but lower)
maximum VGS and VDS (±10 and 30V respectively). However, this part could not be
obtained in sufficiently small quantities.
Like the original gate driver (Fig. 4.1), the new gate driver must phase-shift and attenuate
the fundamental of the drain waveform (of M2 in this case) and apply it to the gate (also of
M 2 in this case). However, the new gate driver must shift the drain waveform fundamental
by 180 , rather than by 163' as in the first gate drive design. This is because VGM1 is
nearly 3 half-wave symmetric, as imposed by the MR circuit. As illustrated by Fig. 4.2,
the magnitude at ~ 1800 is well below the magnitude at 163', because a phase shift of
~ 180' can be attained only asymptotically with two reactive elements. This motivates
the redesign of the SO passive feedback network with an additional reactive element. To
simplify the design of the new SO circuit, we first consider only the ac performance of the
network. DC bypassing and blocking is then treated.
4.3.2.1
AC Considerations
The SO passive feedback network shown in Fig. 4.4(a) is chosen for this design. To determine
what type of reactive element should be used for each impedance, the network's transfer
function, gmg2 (w), must be found.
3
The nonlinearity of the switch M 2 , and of COSSM2 and Cissmi, prevents this circuit from having the
perfect half-wave symmetry of an ideal MR circuit. However, VGM1 is nearly half-wave symmetric, as shown
- 58 -
Gate Drive Circuit Redesign
4.3
M2 Drain
ZT
M2 Gate
ZR
M2 Gate
IRGATEM2
VDM2
I+
g
RGATEM2
II
+
VGM2
ZBISSM2
(a)d
ZR
ZF
VF
CISSM2
-irc -it
-
(b
(a) Generic gate drive circuit
VGM2
Thevenin-e-u-v
-
I-nt
(b) Thevenin equivalent
Figure 4.4: Generic topology of the redesigned SO gate circuit (4.4(a)) and its Thevenin
equivalent (4.4(b)), ac considerations only.
First, the Thevenin equivalent impedance (ZF) and voltage
as follows:
(VF) of VDM2, ZB
ZF = ZT 11 ZB
VF = VDM2
(Z
VDM2
ZBZ
Z ZBZ
)TZ(L\T)
and ZT are
(4.1a)
=VDM2 (Z
ZB)
(4. 1ib)
Plugging Eq. 4.1a into Eq. 4.1b gives:
VF = VDM2
(L)
(4.2)
ZT
The resulting simplified circuit is shown in Fig. 4.4(b).
The drain to gate transfer function can then be written as:
VGM2
VDM2
Defining
ZCISSM2
+
(
ZF)(
ZT
RGATEM2 = ZG,
ZCISSM2
+
ZF + ZR
RGATEM2
+Z
CISSM2
(4.3)
Eq. 4.3 becomes:
VGM2
(ZF )(
ZCISSM2
VDM2
ZT
ZF + ZR + ZG
in Fig. 4.10
-
59
-
(4.4)
Gate Drive Design
M2 Drain
LFB
VDM 2
VF2
M2 Gate
RGATEM2
L
SSM2
CFB
VGM2
Figure 4.5: Redesigned SO gate drive, ac considerations only.
40
20
-
Magnitude vs. Frequency
__-
Phase vs. Frequency
7OnH
90nH
0
110nH
a--
----
-.
-45
130nH
70nH
90nH
110nH
130nH
-900
-
-135
-20
-180225
-40-
-270
-60-
-315-360-
-
1W"
Frequency
[Hz]
10"
le
107
I 09
Frequency [Hz]
(b) Phase
(a) Magnitude
Figure 4.6: Magnitude and phase of the transfer function
components only (as shown in Fig. 4.5) for four values of
k~sm2
VDSM2
for the SO circuit with ac
LFB.
To make the specification of the impedances simpler, the necessary 1800 of phase is provided
It follows that ZT must be an inductor (called
entirely by the impedance (ZCI sS2)(a).
LFB), and that the terms ZF and ZF + ZR + ZG must be purely resistive at fs. To make
ZF resistive, ZB must be a capacitor (CFB) sized to oscillate with LFB at fS. Similarly,
ZR must be an inductor (LFB2) sized to oscillate with CISSM2 to make ZG resistive. The
gate inductance of M 2 , which is typically no more than 0.5nH, can easily be absorbed into
LFB2. The resulting circuit is shown in Fig. 4.5. The overall transfer function magnitude
and phase, with 180' of phase at 100MHz, is shown in Fig. 4.6 (see chapter A.8 for full
PSPICE simulation). This figure illustrates that the magnitude can be controlled by LFB
independently of the phase. Unlike the high-frequency peak in the original gate drive design,
the peaks in this design do not create unwanted oscillations because the phase at both peaks
is - 0', or equivalently ~ 3600.
-
60
-
4.3
180
Gate Drive Circuit Redesign
Magnitude and Phase vs. Frequency
-20
135-2
9045-0
00
-20 v
-45
Magnitude
-90
0)
-40
-135-180
-225
-270
--
e
60
Phase
-315
-80
-360_
10
10
10
Frequency [Hz]
Figure 4.7: Magnitude and phase of the transfer function
for the SO circuit with dc
and ac components.
4.3.2.2
DC Considerations
The SO circuit in Fig. 4.5 will not function properly as shown because the dc voltage at the
gate of M 2 is equal to the dc gate supply voltage, VGIN. The startup/inhibit circuit must
therefore pull down the voltage source VGIN to turn off M 2 (and therefore the inverter). To
solve this problem, a capacitor CBLOCK is placed in series with LFB. To avoid significantly
increasing the impedance ZT around fs, this capacitor is made large. However, because of
board space concerns, simulations are used to determine how small this capacitor can be
made before the ac performance is degraded significantly.
Adding CBLOCK causes node C in Fig. 4.5 to float at dc. As a result, the voltage at the gate
of M 2 can rise, turning on M 2 , when the circuit should be off. This can be solved by adding
a large inductor LBYPASS in parallel with CFB. Like CBLOCK, this inductor is made large,
and then decreased in simulation to the lowest value that does not affect performance at
fs. It was found that CBLOCK = lnF and LBLOCK = 82nH are large enough to leave the
ac performance unaffected, and small enough to increase board space only minimally. The
complete frequency response of the SO circuit with these dc block and shunt impedances is
plotted in Fig. 4.7. Comparing this figure to Fig. 4.6, it is clear that the addition of the dc
blocking and bypass elements does not affect the circuit's performance at or near fs.
- 61 -
Gate Drive Design
Class E Tank
and LCHOKE
MR Circuit
RVGIN
Self-Oscillating Gate Drive
LMR1
--H
+
VGIN
(C
BP
I
CMR2
I
M
-]
:
BLF B
FB 2
BLCI
F2
LBYPASS
9M
M1
Freescale
MRF373ALSR1
VGSM1
CFB
Figure 4.8: Complete gate drive circuit (ac and dc considerations) with MR and SO circuits.
4.4
Simulated Performance of Complete Gate Drive Circuit
Having completed the design of the MR and SO circuits (shown together in Fig. 4.8), it
is necessary to ensure that the two function well together in simulation. Specifically, the
impedance of the SO circuit should be high compared to the high impedance of the MR
circuit at fs and 3fs such that these frequencies are not suppressed. Although this cannot
be achieved perfectly using the selected topology, Fig. 4.9 indicates that the impedance at
and around 100MHz is reduced by about 1.3dBQ out of 45dBQ. The resonant peaks do
not occur at exactly 100 and 300MHz, and that the null does not occur at exactly 200MHz,
because standard value components were used in place of exact values. This illustrates that
the gate driver must be tuned after it is built, as explained in chapter 10.2.
The time-domain waveform VGSM1 is also checked in simulation to verify that stable oscillations of the correct magnitude are achieved. This waveform is shown in Fig. 4.10.
Notice that the M 1 gate voltage minimum is -329mV, greater than the device minimum
of -500mV, and that the maximum is less than the +15V gate limit. Also notice that the
M 2 gate waveform has zero offset due to the dc blocking capacitor (CBLOCK) and inductor
(LBYPASS). Furthermore, the two gate waveforms are 180' out of phase, as desired. In this
simulation, fs happens to be 120MHz.
4.5
Gate Drive Startup Circuit
The gate drive circuit can be started by applying a short pulse of - 5V to point C in Fig. 4.8.
For purposes of testing the gate drive and inverter, this is done by hand by touching a 5V
-
62
-
Gate Drive Startup Circuit
4.5
Magnitude vs. Frequency
70
60
A=1.9583MHz
Component values for frequency domain simulation
50
A=1.3067dBQ
40
U0
0E
(M
.
---
RVGIN
30
20
-10
-20
LFB
4nH
100nH
82nH
COSSM2
L
CBP
2nF
LMR2
LBYPASS
10
0
I
50f
48pF
CM R2
|
CBLOCK
1nF
]
84nH
RGATEM2
3P
RGATEM1
300mQ2
CISSM1
114pF
LFB2
|
LMR1
8.O992nH
150.55pF|
CFB
47pF
CISSM2
30pF
SO circuit alone
MR circuit alone
SO and MR
10
r
Frequency [Hz]
Figure 4.9: Impedance magnitude at the gate of M, vs. frequency, including SO and MR
circuits with ac and dc considerations. The full simulation is given in appendix A.8
supply to point C. However, to automate this operation a gate drive startup circuit will be
designed after the time of writing this thesis.
-
63
-
Gate Drive Design
Gate voltages vs. time
1
10
Component values for time domain simulation
M, gate
M2 gate
<
-
-
5
0
RVGIN
CBP
LMR1
CMR2
0.1mf2
not used
8.0992nH
130.3125pF
LMR2
LFB
CBLOCK
CFB
4.8595nH
40nH
1nF
63.3257pF
RGATEM2
CISSM2
1.5Q
30pF
LBYPASS
LFB2
82nH
58nH
COSSM2
(D
30pF
I
M2
I
-5-
-198
4.985
4.;9
time [sec]
4. 95
|
CISSM1
RGATEM1
109pF
300mQ
voltage controlled switch properties
ROFF
RON
VOFF
1OMQ
600mQ
2V
I
ON
2.5V
5
x 10'
Figure 4.10: Simulated gate to source voltage of the main MOSFET (MI), and of the SO
circuit MOSFET (M 2), with the component values used in simulation. The full simulation
is shown in appendix A.8.
-
64
-
Chapter 5
Impedance Compression Network Theory
5.1
Introduction
An impedance matching network and a compression network are connected between the
inverter and the rectifier as shown in Fig. 1.2. This chapter introduces compression networks, beginning with an explanation of why impedance compression is needed for this
design. The theory of compression network operation is then introduced, followed by a
discussion of the characteristics that the rectifier must have to be compatible with the compression network. The design of the rectifier, compression, and matching stages is treated
in subsequent chapters.
5.2
Motivation for Impedance Compression
To motivate the discussion of compression network theory, it is helpful to consider how the
Class E inverter and an arbitrary rectifier would function without any network between
them. When a rectifier is connected to a Class E inverter, the input impedance of the
rectifier (RRECTIN) takes the place of RLOAD. The performance of the Class E inverter
is therefore directly related to RRECTIN, which is derived below for the half-wave rectifier
shown in Fig. 6.6 and extended to the general case. The following analysis assumes that the
rectifier output voltage (VouT) is constant, that the diodes (or, more generally, switches)
are ideal, and that the input is a sinusoidal current with magnitude IRECTIN and frequency
fs.
We define RRECTIN of the half-wave rectifier as the ratio of input voltage fundamental
magnitude to the input current magnitude (IRECTIN). This is reasonable, as power is
only transferred due to the fundamental component of voltage (because of orthogonality
of the current with other voltage components), and because this rectifier is designed such
that the voltage fundamental and current are in phase. Since the input voltage is a 50%
duty cycle square wave varying between 0 and VOUT (i.e. with an amplitude of VO2"), the
magnitude of the input voltage fundamental is 2VOLT . RRECTIN is therefore 2 VOUr
r IRECTIN
-
65
-
Impedance Compression Network Theory
Drain to Source Voltage vs. Time, Class E Inverter
70
60-
R=2.7Q
50-
Rin
"
0
20
0
-
10-
0
02
04
06
08
time [s]
1
12
14
1.6
X10-
Figure 5.1: The effect of changing RLOAD on the Class E inverter VDS waveform.
The input impedance of a full-wave rectifier is double that of the half-wave rectifier, or
A.RE TIN, because the input voltage is a square wave that varies between ±VOUT (i.e.
with an amplitude of VOUT). Similar analysis can be carried out for many other types of
rectifiers, as discussed in [29]. For convenience, the input impedance of these rectifiers can
be expressed as k yvT , where k is a constant specific to each rectifier topology.
7r IRECTIN'
It can also be appreciated that when the Class E inverter and a rectifier are connected,
IRECTIN is a function of the input power, and therefore of the inverter input voltage VIN.
Consequently, variations in VIN cause RRECTIN to change such that ideal Class E operation
can be achieved at only one input voltage, as illustrated by Fig. 5.1, where only one of the
waveforms achieves ZVS. This is clearly undesirable in this design, where VIN is allowed to
vary from 11 to 16V.
5.3
Compression Network Theory of Operation
The solution to the problem described above is to insert a network between the inverter and
the rectifier having an input impedance that varies relatively little as its output impedance
is changed over a wide range. This type of network, developed in [30, 29], is termed an
impedance compression network, because the output impedance range is compressed to
form the input impedance range. One such network is developed below, and other networks
are explained in [30, 29).
Consider the network shown in Fig. 5.2 where both resistors have the same value (R). The
-
66
-
5.4
Application of a Compression Network to the Converter
ZT
R
ZB
ZCIN
[
Figure 5.2: The network to be used for compression.
input impedance of this network
ZIN
Setting ZB = -ZT,
=
(ZCIN)
is:
(ZT+ R)(ZB + R)
(ZT+ R)+(ZB + R)
ZTZB
2(51)
this becomes:
2
ZCIN =Z
Making ZB =
+ R(ZT + ZB) +
ZT +ZB + 2R
+ R2
(5.2)
2R
jX results in:
ZCIN =
X 2 +R
2+
2R
2
X2
R
=2R
+ R
2
(5.3)
This equation is plotted in Fig. 5.3(a) for X = 20, which illustrates that for a change
in R by a factor of 400, ZCIN changes by only a factor of 10. This figure also shows that
maximum compression is attained by making the value of R at the center of the range equal
to X. This yields a range with a geometric mean of the minimum and maximum of R. The
relationship between ZCIN and R can be achieved (assuming ideal components) by replacing
the arbitrary impedances ZT1 and ZB1 with a capacitor and an inductor (Fig. 5.3(b)).
5.4
Application of a Compression Network to the Converter
The compression network development in the previous section assumes (and requires) a
matched pair of resistors. Therefore, the converter design requires a pair of rectifiers with
input impedances that are equal, but that can vary together. The following derivation
demonstrates that this can be accomplished by using two identical rectifiers whose outputs
are connected in parallel with a single load. Consider Fig. 5.4, where a compression network
-
67
-
Impedance Compression Network Theory
ZCIN vs. R
200
180
160
140
cc
120
N
R
100-
8060- -C
40
10
-ZCIN
R
102
10
-
R [Q]
(b)
(a)
Figure 5.3: A plot of Eq. 5.3 (Fig. 5.3(a)) and a basic compression network (Fig. 5.3(b))
that can be used to realize impedance compression.
is driven by a sinusoidal voltage of magnitude VAC. The load resistance for each branch is:
k
VOUT
(5.4)
RRECTIN - k VOUT _
7r IRECTIN
assuming that the output voltage VOUT of the rectifiers is a constant (VDC). Now consider
only the top branch. The rectifier input impedance is:
RRECTIN = k
VDC
lii
(5.5)
lii|
-jX
ii44
i2
VAC
'V
RRECTINTOP
kVDC
+jX
V AC-j-I7
f l
RRECTIN
BOTTOM
kVDC
12
Figure 5.4: Compression network with symbolic rectifier connections. The impedances of
the capacitor and inductor at the fundamental are shown.
- 68 -
5.4
Application of a Compression Network to the Converter
The branch current magnitude is:
VA C
VAC
+RRECTIN
Squaring both sides and solving for
VAC
2
(5.6)
2k2
gives:
k 2 VDC2
12X2
AC 2
(5.7)
This can be rearranged in terms of Iii | as:
VAC 2
-
=2
k 2VDc 2
Xii
(5.8)
Eq. 5.8 demonstrates that the branch current magnitude is a function only of variables
that are equal for both branches (assuming identical rectifiers, as we did from the start).
Therefore, the current in both branches is the same, and the two rectifiers act as the matched
pair of load resistances that are required for proper impedance compression.
Further issues regarding compression network design are treated in chapter 7 after a discussion in chapter 6 of the rectifier design process.
-
69
-
Chapter 6
Rectifier Design
6.1
Introduction
This chapter describes the design and implementation of the rectifier stage of the converter.
As explained in chapter 5, the impedance compression network requires a pair of rectifiers
with matched input impedances. However, all of the other rectifier attributes can be chosen
freely. The choice between a synchronous and diode rectifier is considered first, followed by
a discussion of switch device selection. The choice of either a one- or two-switch half-wave
rectifier is then treated. 1 Simulation results are provided to support the decisions that were
made.
6.2
Selection of Switch Type
As in most dc/dc converter designs, the rectifier switch devices can either be diodes or
MOSFETs (for synchronous rectification). The advantages of synchronous rectification,
which are well documented in [20, pages 73-74], [8, page 36], and elsewhere, include the
fact that MOSFET devices typically have lower on-state forward voltage drop than diodes
designed for comparable power and frequency operation. Consequently, the efficiency of a
given synchronous rectifier topology is inherently higher than a similar diode-based topology.
This can be illustrated for a single-switch rectifier like the one shown in Fig. 6.1 as follows:
Assuming that any passive components in the rectifier are ideal, the efficiency (q) of a
single-switch rectifier is given by Eq. 6.1.
POUT
PIN - PSW
__=
=
PIN
-
PIN
= 1-(6)
PSW
(6.1)
PIN
where PSw is the time average power loss in the switch. This power loss can be written as
'In this design, only half-wave rectifiers are considered because of the larger size and device drops of
full-wave rectifiers.
-
71
-
Rectifier Design
+ Vsw
'IN
sif(f/)
-
'OUT
Lossless
Energy
Storage
-
U
VOUT
Figure 6.1: An ideal single-switch rectifier. The energy storage allows the switch to be
turned off without violating KCL, but introduces no loss.
VSWIOUT, where Vsw is the on-state switch forward voltage. Eq. 6.1 can then be rewritten
as
VSW IOUT
PIN
VSW IOUT VOUT
PIN
VSW POUT
VSW
PINVOUT
VOUT
VOUT
6.2)
Solving for 77 yields:
VOUT
VOUT + Vsw
(63)
From this equation it is clear that efficiency is maximized by selecting the device with the
lowest forward voltage drop. It is also clear that rectifier efficiency increases as VOUT is
increased, and that typical values of VOUT should be taken into account when choosing the
rectifier switch type. Assuming a typical power Schottky diode drop of 0.5V, and lossless
passive components, rectifier efficiency increases from 90.91% for VOUT = 5V to 96% for
VOUT = 12V.2 Based upon this type of analysis, it was decided to design the converter for
VOUT = 12V, where the benefits of synchronous rectification are reduced, and to use diodes
rather than MOSFETs. This reduces the converter cost, design complexity and PCB area
by eliminating the need for synchronous rectifier drive circuitry. This drive circuitry would
also introduce additional loss mechanisms into the converter. 3
6.3
Selection of Topology and Diode
Having decided to use a diode rectifier with a 12V output, a topology and an appropriate
Schottky diode must be chosen. Unfortunately, these choices are interdependent. The selection of a diode is guided by the maximum repetitive reverse voltage (VRRM) requirements
and 12 volts are both considered as potential nominal output voltages, because both are typical supply
voltages for many types of loads.
3
This analysis clearly does not prove that a 100MHz dc/dc would not benefit from a synchronous rectifier
topology. More rigorous analysis of synchronous rectifiers could be carried out as part of future work (chapter
11.4.2).
25
- 72 -
6.3
Selection of Topology and Diode
of the selected topology. Conversely, the choice of a topology is dependent upon diode
non-idealities, such as capacitance (CD), on-state forward voltage drop (VF) and VRRM.
This is because these quantities significantly influence each topology differently. In some
cases, switching from one diode to another can even require slight topological changes, as
illustrated in section 6.3. The selection of a topology and a diode device is therefore an
iterative process. As a starting point, a search for diodes rated to at least 1.5A was carried
out (Table C.1). This minimum acceptable value is determined as follows:
In a half-wave rectifier, each diode must be rated to carry all of the rectifier output current, which is half of the total converter output current in this two-rectifier topology. The
converter output current is found by dividing the target converter output power (30W
maximum in this design) by the output voltage. Estimating the rectifier efficiency at 90%4
results in a converter output power of 27W, which corresponds to an output current of
2.25A for a 12V output. Consequently, each diode must be rated for at least 1.125A average forward current (I).
Diodes with Io > 1.5A are therefore potentially usable in
half-wave topologies. It was decided that initial simulations would be carried out with the
diode used in the previous design [1], the MBRS1540T3 made by OnSemiconductor. This
device has the lowest VF of all devices that were considered except for those with lower
reverse breakdown limits. Since this rectifier has a higher output voltage and output power
than the rectifier in [1], these lower voltage devices are unlikely to work in this design. The
small surface mount package used for the MBRS1540T3 also makes this part better than
the larger, through-hole devices shown in Table C.1.
Two single-diode topologies are evaluated using the MBRS1540T3. The first topology (Fig.
6.2(a)) is known as a single-resonance (SR) rectifier because it has only a single resonant
frequency, 2L1CR1.
When the voltage across the capacitor and inductor (VRECTIN) is
less than VOUT, the diode is off, and the voltage is approximately sinusoidal. Once VRECTIN
reaches VOUT, the diode turns on, holding VRECTIN at VOUT. This produces the waveforms
shown in Fig. 6.2(b). The angle
#IN
between the fundamental of VRECTIN and IRECTIN
is non-zero due to the nonlinearity of the diode capacitance CD, which is governed by the
same equation that sets Coss in LDMOS devices (Eq. 3.2 on page 31). This capacitance
appears in parallel with LR1 because the positive output node, fixed at +12VDC, is an
incremental ground. As the rectifier input power is increased, the input voltage magnitude
increases, which results in greater diode off-state voltage. This decreases the effective5 diode
capacitance, thereby mistuning the rectifier. Consequently, the effective resonant frequency
of the rectifier is equal to the operating frequency fs for only one value of input power.
490% is a reasonable estimate since one goal of this design is to create a converter
with 80% efficiency,
and since the inverter and rectifier losses are comparable.
5It is convenient to think of this nonlinear capacitor as having
a pseudo-average value that changes with
average off-state voltage. "Effective" refers to these pseudo-averages.
- 73 -
Rectifier Design
Input Voltage and Current vs. Time
30 20 - --
10
- -
-
Fundamental of V
3ETI
2
RC
RCI
-
> -10 -
-
-20--
5|
LR
CR1
-
----
-
--- 3
-YRECTIN
2.98
VOUT
4
--
-40 --
IRECTIN
-
-
-30 --
2.985
2.99
time [sec]
3
2.995
X 10,
(b)
(a)
Figure 6.2: Single-resonance (SR) rectifier topology and associated waveforms. The phase
'IN between the input current and the input voltage fundamental is shown for reference.
The plot corresponds to SR tuning number 3, as shown in Fig. 6.4.
Hence, qIN = 0 at only one input power level. The severity of this problem can, in theory, be
reduced by adding enough linear capacitance in parallel with LR1 to make the effect of CD
insignificant. However, this can cause LR1 to become too small to realize with a sufficiently
high-Q discrete inductor. Furthermore, an increase in CR1 and the associated reduction in
LR1 cause the impedance of this parallel combination to decrease, which increases loss by
allowing more current to flow through these non-ideal elements. This is demonstrated in
simulation, as discussed later in this section.
The initial SR rectifier design is carried out with CR1 composed entirely of the nonlinear
diode capacitance CD. LR1 is then calculated using equation 6.4. In this equation, CD
is estimated as the diode capacitance at VD = VOUT = 12V because the average voltage
across LR1 must be zero, which makes the average diode voltage equal to VOUT. LR1 is
then varied in simulation.
LR1
1
=
(6.4)
2,r fs2CD
The second single-diode topology (Fig. 6.3) that was considered for this design is known
as a multi-resonant (MR) rectifier because LRI, CR1, LR2 and CR2 form an MR circuit,
explained in chapter 3.8. This topology squares up VRECTIN, making OIN closer to zero.
This can be understood by considering the limiting case of a square wave input voltage,
-
74
-
6.3
Selection of Topology and Diode
Input Voltage and Current vs. Time
40-
4
30
Fundamental of VRECTIN
3
-
RECTIN
20-----
2
-10
1
z
>
3
0
-10
0
-
-
--
P
-1
-20
VRECTIN
-30
-40
+L
'RECTIN
LR1
CR1
--
-4
VOuT
2.985
2.98
2.99
time [sec]
C
(a)
3
2.995
X 10
(b)
Figure 6.3: Basic MR rectifier topology and associated waveforms. The phase #IN between
the input current and the input voltage fundamental is shown for reference. The plot shows
MR tuning number 3, as shown in Fig. 6.4.
which must have a 50% duty cycle such that the diode is on (and VRECTIN = VOUT) when
IRECTIN > 0. If this were not the case, the diode would be required to simultaneously
carry forward current and support a reverse voltage, which clearly violates the operating
principle of a diode. The advantage of a square input voltage is that its fundamental is also
in phase with IRECTIN, which makes #IN = 0' and the rectifier input impedance purely
resistive. Controlling only the first few harmonics does not yield zero phase, but has the
potential to reduce the phase significantly compared to the SR rectifier. However, the MR
circuit may also have lower efficiency than the SR rectifier, which is why both topologies
are considered.
Initial simulations of the SR and MR rectifiers using OnSemiconductor diode MBRS1540T3
indicate that both rectifier topologies cause this 40V device to break down. This problem
appears in the time domain as clipping of the negative portion of the input voltage waveform, and in rectifier performance plots as a sudden decrease in efficiency as input power is
increased beyond a certain level. Breakdown is eliminated in the MR rectifier simulations
by increasing the diode breakdown voltage to 50V, and in the SR rectifier simulations by
increasing the breakdown voltage to 60V. A device search for higher voltage diodes is discussed later in this section. Fig. 6.4(a) shows rectifier efficiency vs. #IN for several tunings
of the MR and SR rectifiers with these artificial breakdown voltages. The exact simulation
results, along with the simulations used to achieve them, are shown in appendix A.9. In
these simulations, two parallel MBRS1540T3 diodes are used for each rectifier, although
the average forward current does not make this necessary.
-
75
-
Rectifier Design
Phase Range for SR Rectifier Tunings
Efficiency vs. Phase at Minimum Power (P N=6W)
94
5
92-
3
4~
2
a
E
n
~
4
Y 3
AD
LU
6
5
4
2
' -20
-10
0
10
20
Efficiency vs. Phase at Maximum Power (PN=15W)
94.0_
30
10
0
Phase [degrees]
30
2)
-
-10
10
20
-10
0
Phase Range for MR Rectifier Tunings
-3
-a-20
-20
E 6
92.5-io
0
30
5
93- - -
2
-
-
.-
93.5-
CL,C
1
%
.2
5
0
10
Phase [degrees]
SR Rectifier
- MR Rectifier
20
0
30
(a)
-20
-10
20
(b)
Figure 6.4: Efficiency vs. 4IN for several MR and SR rectifier tunings (6.4(a)), and #IN
range (over power level range) for each tuning (6.4(b)). The tuning numbers shown in both
plots and in Fig. 6.5 refer to the same tunings, and are used only for reference.
Every point on each plot corresponds to a different tuning of either the MR or SR rectifier.
The various tunings of the MR rectifier are accomplished by varying the nominal value of
CR1 in Eq. 3.5. The actual value of CR1 in the circuit is the nonlinear capacitance CD, which
is determined by the manufacturers diode model, and is unchanged in these simulations.
CR1 used in the MR equations must be swept because an equivalent average value for the
capacitance CD is impossible to determine without numerical methods. This is both because
CD is nonlinear, and because the average value of CD depends upon the diode duty cycle,
which in turn depends upon the voltage waveform VRECTIN. This voltage is determined by
the product of the input current and the input impedance. Since the input impedance is a
function of the diode capacitance, no closed form solution for an average diode capacitance
can be found.
Similarly, tuning of the SR rectifier is accomplished by varying the nominal capacitance
CR1 used in equation 6.4 to calculate the inductance LRI. The actual value of CR1 in the
circuit is the nonlinear capacitance CD, just as in the MR rectifier. In this rectifier, LR1
could be swept directly, but sweeping CR1 maintains consistency between the two rectifier
simulations.
It is clear from Fig. 6.4(a) that the SR rectifier has significantly higher efficiency than the
MR rectifier. However, the range over which OIN varies as PRECTIN is increased from 6
to 15W is significantly smaller for the small-angle tunings of the MR rectifier than for the
small-angle tunings of the SR rectifier (Fig. 6.4(b)). This means that the MR rectifier can
be tuned to be less reactive over the operating range than the SR rectifier, and that the
76
-
6.3
Selection of Topology and Diode
Maximum Diode Voltage vs. Phase
54
57-
5
550
SR Rectifier
MR Rectifier
-.-0
12
52-2
4
48
46
E
5
44 --
~42-3
40
-
0
-6
.7
-25
-20
-15
-10
-5
Phase [degrees)
0
5
10
Figure 6.5: Maximum diode voltage (at maximum input power,
MR and SR tunings.
15W) vs.
#IN
for various
compression network will function more effectively with an MR rectifier than an SR rectifier.
The end result is that the inverter is more well-tuned over the operating range when used
with the MR rectifier. Another advantage of the MR rectifier is that its maximum diode
voltage is lower for all tunings than for any tuning of the SR rectifier (Fig. 6.5), which
affords more freedom in diode selection. Despite the advantages of the MR rectifier, it was
decided that the MR rectifier would not be used for this design because of its significantly
lower efficiency and larger required board area.
As mentioned above, the MBRS1540T3 does not have a sufficiently high reverse breakdown
voltage for this design. A second device search was carried out, and yielded the results
shown in Table C.2. The MBRS260T3, a 2A, 60V device, was selected from this list because
of its low capacitance and reasonably low VF. The datasheet for this device is shown in
appendix C. In retrospect, a device with a lower VF, like the ST part STPS3L60U, should
have been chosen despite its higher CD. This is because external capacitance (Cp) had
to be added in parallel with LR1 in the SR design to keep the peak reverse diode voltage
below 60V, as shown in Table 6.1. The added capacitance decreases the impedance of the
parallel combination of LR1 and CR1, thereby decreasing the voltage that appears across
this combination for a given current. Moreover, LR1 must be decreased to maintain the
resonant frequency of the parallel combination to keep &IN small. This further decreases
the impedance of the parallel combination. An SR rectifier design with Cp = 30pF and
LR1 = 18.9nH was chosen based upon Table 6.1 because this circuit produces a good
compromise between low peak power and high efficiency.
One two-diode half-wave rectifier (Fig. 6.6) was also considered and compared against the
30pF, 18.9nH SR design. In the two-diode topology, the current source input requires that
one diode be on at all times. When the input current is positive (for 50% of the cycle), Di
conducts, and VRECTIN = 12V. During the other half-cycle, D conducts, and VRECTIN =
2
-
77
-
Rectifier Design
C,
LR1
[pF]
10
30
80
[nH]
23.1
18.9
13.13
Average
Angle
Angle
Angle
Difference Angle
at
at
PIN=6W PIN=15W
[degrees] [degrees] [degrees] [degrees]
0.18
24.12
-11.88
12.24
-2.2
24.4
-14.4
10
-1.8
25.2
-14.4
10.8
Maximum Reverse
Diode Voltage at
PIN=15W
[V]
57.7
50.8
43.3
Efficiency
at
6
PIN= W
[%]
93.5
93.3
92.7
Efficiency
at
PIN=15W
[%]
93.9
93.7
93.2
Table 6.1: Simulated SR rectifier performance for several values of Cp. Simulations were
carried out using the SR rectifier PSPICE code shown in appendix A.9 with the diode
model DMBRS260T3 and and ideal 2nH of package inductance. The data in this table is
reproduced from [31] with permission.
D,
'RECTIN
I7
D2
§
VOUT (DC)
Figure 6.6: An ideal two-diode rectifier.
is therefore zero, and the input impedance of the rectifier is purely resistive.
However, the nonlinear diode capacitance CD prevents instantaneous switching, which has
the effect of delaying the voltage waveform with respect to the input current, thereby
increasing OIN significantly. Fig. 6.8 compares the ideal waveforms and the capacitively
delayed waveforms at peak input power. This figure also shows the effect of the package
inductance of each diode, which further distorts the waveforms, but decreases the range
over which OIN varies.
OV.
OIN
The SR rectifier and the two-diode topology were compared using OnSemiconductor device
MBRS260T3. The comparison was made by sweeping the rectifier input power by varying
the input current magnitude, which produces the waveforms shown in Fig. 6.7. It is clear
from this figure that OIN varies by roughly the same magnitude over the input power range
for both rectifiers. The figure also shows that the two-diode rectifier has lower efficiency
than the SR rectifier, which indicates that the loss associated with an additional diode
is significantly higher than the loss associated with the added passive components in the
single-diode rectifier. As a result, the two-diode rectifier is ruled out for this application.
The final rectifier design is therefore an SR circuit with Cp = 30pF and LRI = 18.9nH.
-
78
-
6.3
Efficiency vs.
Selection of Topology and Diode
Input Phase vs. PIN
PIN
95
30
94
20
93
9 2 -.-.-
.-
10
91C
90
0
W
89
-10
88
87
-20
86 -0--
85
6
'
8
Two-diode
One-diode SR
'
10
'
12
-4- Two-diode
-30
14
PIN (W)
One-diode SR
-
6
8'
10
12
14
PIN (W)
Figure 6.7: A comparison between the two-diode rectifier shown in Fig. 6.6 and the SR
rectifier of Fig. 6.2(a). Simulations include an ideal 2nH package inductor.
-
79
-
Rectifier Design
Ideal Two-Diode Half-Wave Rectifier
20
-
-
15 - -
-
-
..--
-
.
r-
10
--
1-
-
- -1
-
IN
VN
VIN Fund
-
---
0
-10
2.982
2.98
-
- -
-
-5 -
0 Degrees Phase Shift
2.986
2.984
2.99
2.988
2.992
2.994
2.996
3
2.998
x 10
Two-Diode Half-Wave Rectifier with MBRS260T3 Diodes, no I'PACKAGE
20
10N
5 -
-/
5
-
14457 Degrees
-10 2.98
2.982
2.986
2.984
2.99
2.988
2.992
2.994
2.996
3
2.998
X 10-8
Two-Diode Half-Wave Rectifier with MBRS260T3 Diodes, with 'PACKAGE
20
IN
15-
-...
--
10
-
-
---
V.
-- -
VIN Fund
5 -
0.
74 Degrees
5, I15.
-2
2aa
2982i
295
29R
2988
299
time [sec]
2992
2.994
2.996
3
2.998
X10,
Figure 6.8: Plots of VRECTIN, the fundamental Of VRECTIN, and IRECTIN for the two
diode rectifier shown in Fig. 6.6 at minimum power (- 6W). Three diode models are
used to illustrate the effects of the various non-idealities. The simulation file is shown in
appendix A.9.
- 80 -
Chapter 7
Impedance Compression Network Design
7.1
Introduction
Chapter 5 introduced the concept of the compression network, and explained the requirements that this network places on the rectifier stage design. More details regarding the
rectifier design were then treated in chapter 6. This chapter discusses the design of the
compression network based upon the chosen rectifier design. This design progression is
important because the rectifier input impedance determines the characteristic impedance
of the compression network, as explained below.
7.2
Design
In chapter 5, the compression and rectifier stages are considered only in terms of the fundamental frequency. However, the SR rectifier has significant harmonic content in its input
voltage waveform due to the sharp diode transitions. Without additional filtering, a low
impedance loop for harmonic current exists because of the loop shown in Fig. 7.1. This path
contains parasitic resistances, and thereby increases converter power dissipation. Furthermore, simulation indicates that these harmonic currents cause an imbalance in the output
power of the two rectifiers because of a change in rectifier duty cycle. This causes the constant k to be different for the two rectifiers such that the rectifier input resistances are no
longer matched.
To increase the impedance of this path at the higher order harmonics, an inductor LC 2
can be added in series with the top branch of the compression network, and a capacitor
CC2 can be put in series with the bottom branch. If the inductor has an impedance at
the fundamental of +jX2, and if the capacitor has an impedance at the fundamental of
-jX 2 , the compression network reactance will continue to be tuned at the fundamental.
This provides the desired low impedance path for the fundamental (which transfers power
from the Class E tank to the rectifiers). However, the partial loop impedance magnitude of
-
81 -
Impedance Compression Network Design
-jX 1
iiRRETINTOP=-,
k VDC
low impdnc
harmonic path
'2
V AC '
R RECTIN
BOrrOM
=
k
Figure 7.1: Basic compression network with symbolic rectifier connections and with a lowimpedance path indicated. The impedances of the capacitor and inductor at the fundamental are shown.
the reactances at the second harmonic is now:
X1+
Z2fs =
(7.1)
X2
instead of the smaller impedance !X 1 provided by the components Cci and Lci alone.
These expressions are derived using the fact that when the frequency is doubled, the impedance of the inductors doubles, and the impedance of the capacitors is halved. Eq. 7.1
can be simplified by defining
Xi = aX 2
(7.2)
where a is a constant, and by defining
(7.3)
Xo = X 1 - X2
which is the total impedance magnitude of each branch at the fundamental. The second
harmonic impedance magnitude becomes:
(a+)
Z 2 f, = -(a + 1)X 2 =
2
2 a- 1
X
(7.4)
Similarly, the nth harmonic impedance magnitude is:
=
n2
; 1
n
(:a + )
) (--1)
(7.5)
This indicates that the impedance magnitude at all of the higher order harmonics becomes
greater for a given value of Xo as a is decreased. Thus, decreasing a should, in theory,
decrease the loss in the compression network. However, simulations indicate that this is
-
82
-
7.2
Upper Rectifier
L
c,
T
LI
LR1
1
i2i2
VAC
LC2
Design
CRI
-
I---------------I ----------------
C02
--
12VDC
I
I
Compression Network
CR2
LR2
L---------------'
L
- -- ..-
-
I
Lower Rectifier
Figure 7.2: Compression network with the inductor and capacitor added to reduce higher
order harmonic currents.
not the case. For these simulations, Xo was chosen as approximately the geometric mean
of the rectifier input impedance. This puts the center of the ZCIN curve in the middle
of the logarithmic RRECTIN range, as shown in Fig. 5.3(a). This, in turn, provides the
greatest amount of compression over the converter input voltage range, and therefore over
the rectifier input power range. For the final rectifier design, the input impedance ranges
from 27.5Q at PRECTIN 6-08W to 12.03Q at PRECTIN = 15.00W, which has a geometric
18.13. This value was rounded to 20Q and used for X 0 . The
mean of V27.5 x 12.03
four components in the matching network (Fig. 7.2) were then calculated automatically in
PSPICE using the following set of equations, which follow from Eqs. 7.2 and 7.3:
(7.6a)
Cc2 = 2
2,7rfsXo
= C
a
(7.6b)
0
(a - 1)27rfs
LC 2 = aLci
(7.6c)
Cci
Lci =
(7.6d)
The resulting circuit is driven by a sinusoidal current with frequency fs, and the input
power balance between the two rectifiers is observed, along with the total efficiency of the
two stages. The simulated results are shown in Fig. 7.3, and the PSPICE file is shown in
appendix A.10. These data indicate that a = 3 provides the best balance between the two
rectifiers. However, it was decided to use a = 2, because the data in Fig. 7.3 was not available
when this decision was made. In addition to providing relatively good performance, this
-
83
-
Impedance Compression Network Design
Rectifier input power difference vs. ICIN amplitude
a 1.
0
-....
-----
0.
0.
+
-.5 --
a=3.75
a=3.5
a=3.25
a=3.0
-157
-- a=2.75
2 -- a=2.5--a=2.25
--2 .5 .5
-- a=2.0
- 3.-- a=1.75
.- a=1.5
T1
1.2
.2545
328
--
-
--
1.4
1.3
1CIN amplitude [A]
1.5
1.5
439
--... 6
1.6
1.6
-
Figure 7.3: Power balance between upper and lower rectifiers as a function of sinusoidal
input current magnitude for various values of a. Xo = 20 for all curves. The input current
is used as a simplified model of the inverter output waveform. The mean squared value of
each tuning is shown above the curve.
design has the benefit that none of its components are unreasonably large (above 100nH or
lOOpF) or too small to realize with accurate and sufficiently high-Q discrete components.
-
84
-
Chapter 8
Matching Network Design
8.1
Introduction
This chapter describes the design of the matching network used to connect the inverter to
the compression and rectifier stages. This network is necessary because of the impedance
mismatch between the compression network input impedance and the value of RLOAD
required by the inverter for optimal operation. Without a matching network, the Class
E inverter would not achieve ZVS, and would therefore not operate efficiently.
8.2
Design
To determine which type of matching network to use, the ratio of network input to output
impedance,
RLAD,
is determined. The final inverter design, as given in Fig. 3.15, requires
a nominal RLOAD = 4.0544Q ~ 4Q. The value of RCIN is found to be between 20 and
24.5Q, depending upon the rectifier output power, and therefore upon the input voltage.
This results in a required matching ratio between 4.93 and 6.04, which indicates that a
single-stage transformation can be accomplished with reasonable Q components, and with
reasonably high tolerance to slight variations in fs. 1
Two L-section networks (Fig. 8.1) were considered for this design. The network shown
in Fig. 8.1(a) is chosen because this network allows CM, to be combined with CR of the
inverter to produce a smaller total capacitance. In the network in Fig. 8.1(b), LM1 combines
with LR of the inverter to form a larger total inductance, thereby increasing converter size.
The values LM, and CM1 for the network in Fig. 8.1(a) are governed by Eqs. 8.1, which are
Matching ratios of greater than 10 are typically realized with more than one transformation stage. Using
a single stage is advantageous because it allows for minimum component count.
- 85 -
Matching Network Design
NetworkI
Matching
r ------
Matching Network
0
CR
CM1
LR
R
LR
L
I
LMl
I
'
To inverter
switch and
choke
To compression
and rectifier
To inverter
switch and
choke
To compression
and rectifier
stages
stages
(b)
(a)
Figure 8.1: Two candidate L-section matching networks.
derived from basic matching network theory [32].
Lml
CM1
=
=
RLO ADRCIN
- RLOAD)
L(RCIN (2ffS)
2
(LMl2rfs) + RIN
2
LI (RcIN27rfs)
(8.1a)
(81b)
Because the value of RCIN is variable, but the matching network must be designed with a
fixed ratio, simulations of converter performance are carried out using a range of matching
ratios. The results are shown in Table 8.1, and indicate that matching into 25Q is nearly
optimal in terms of inverter efficiency. This matching ratio gives LM1 = 17.51nH and
CM1 = 172.7pF. Combining CM1 and CR = 163.5338pF (see Fig. 3.15) gives a total
capacitance (in place of CR) of 83.99pF.
-86
-
n
0
.
U,
(D~
i-)
~0
0
M(
Converter Total
0ecr*
(D~
0
VIN
PIN
POUT
IV]
[W]
[W]
Inverter
External
V DSMAX
ROUT
P
%
[W)
[%
IV]
Internal
VDSMAX
[V])
Compression & Rectifier
Bottom
Rectifier Rectifier
RCIN
PI N[W| PIN [W]
[Q|
Top
10[
Step down from inverter to compression network by a factor of 4.9329 (equivalent to matching RLOAD = 4.0544Q into 20Q)
11
11.896
9.703
80.1540
10.499
86.7366
41.056
45.324
7.5512
2.8628
29.827 1 -5.4649
16
34.189
29.921
80.0876
29.921
86.982
63.011
66.923
14.147
15.216
22.302
11.2632
Step down from inverter to compression network by a factor of 5.4262 (equivalent to matching RLOAD = 4.0544Q into 22Q)
11
12.413
10.225
81.0077
11.052
87.556
39.663
43.636
7.5865
3.3747
28.028
-5.1175
16
35.207
28.413
80.2257
30.929
87.330
61.460
65.943
14.596
15.738
22.586
11.3207
00
-4
n
ID~.
c
Step down from inverter to compression network by a factor of 6.1661 (equivalent to matching RLOAD = 4.0544E2 into 25Q)
11
13.182
10.938
81.6848
11.808
88.177
37.495
41.153
7.6357
4.0736
25.962
-4.4052
16
36.275
29.323
80.3753
31.954
87.585
59.566
64.297
15.040
16.282
22.877
11.4072
Step down from inverter to compression network by a factor of 6.6594 (equivalent to matching RLOAD =
11
13.727
11.353
81.4591
12.248
87.8856
36.529
39.390
7.6669
4.4776
16
37.076
29.864
80.0972
32.565
87.3406
58.446
61.873
15.304
16.605
4.05442
24.864
23.014
into 27Q)
-4.0328
11.3005
Chapter 9
Printed Circuit Board Layout
9.1
Introduction
To make the actual operation of the converter similar to the simulated performance described in the preceding chapters, a carefully laid out printed circuit board (PCB) is necessary. This is because the high switching frequency makes the discrete passive components small enough that board parasitic resistance, capacitance and inductance (collectively
termed "parasitics") are a significant fraction of many of these discrete components. Although many of the parasitics can be compensated for with smaller discrete components,
the parasitic capacitances and inductances have lower quality factors than the discrete elements.1 Consequently, the parasitics can introduce significant loss. Furthermore, many of
the parasitics are not in locations where an improvement can be made by simply decreasing
a discrete component size. The goal of this PCB design, as described in this chapter, is
therefore to minimize the board parasitics. This chapter begins with a discussion of the
layout of the gate drive circuit. The inverter and matching network are then designed
around the gate drive. To conclude the chapter, the layout of the compression and rectifier
stages is presented. All parts of the PCB are designed using CadSoft's Eagle 4.12, and
manufactured by Advanced Circuits (www.4pcb.com) using 2oz. copper. The effects of this
copper thickness are discussed in chapter 10.5.
9.2
Gate Drive PCB Layout
The most important aspect of the gate drive layout is minimizing the inductance between
MOSFETs Mi and M 2 along both the signal and ground paths. This ensures that COSSM2
and CISSM1 appear in parallel to form CMRS1 for the multi-resonant portion of the circuit.
Simulations indicate that as little as lnH between the two MOSFETs causes undesired
ringing in the M 1 gate waveform. This has the potential to cause spurious turn-on of
M 1 . A low inductance connection is accomplished by placing the two MOSFETs as close
'Chapter 11 discusses the possibility of designing high-Q passive components within a PCB.
-
89
-
Printed Circuit Board Layout
MRF373ALSR1
MRF373ALSR1
D
M1 to M2 connection
LMR
LMR1
s
SLFB1
u
place CBP
jii1
anywher~e
CBLOCK
CBLOCK
along these
hash marks
FBL
LFB2
LFB
LBYPASS
PoeLBYPASS
+ Gate -Power
+ Gate~
Power
Gate Dve
GaeDieInput
Startup Node
Input
(b)
(a)
Figure 9.1: The gate drive portion of the PCB, top (Fig. 9.1(a)) and bottom (Fig. 9.1(b)).
The bottom layer is mirrored such that the top and bottom layers line up. All of the
components are labelled, although M, is labelled with its part number, MRF373ALSR1.
The pad areas are denoted by the diagonal line fill style. The gate, drain, and source
contacts of M 1 are indicated with the uppercase letters G, D, and S. Likewise, the gate,
drain and source of M 2 are denoted with lowercase letters g, d and s. As noted at the left
of Fig. 9.1(a), LMR1 can be changed by moving CBP. Shifting CBP down increases LMR1.
Fig. 9.1(b) shows the top side component placement for reference. Notice that the ground
plane overlaps the top side components only minimally.
together as possible. Unfortunately, the primary ground path is on a different layer than
the signal path because of the unavoidable location of other components. Consequently, a
relatively thin (0.020inch) FR4 board is used to minimize via length. A high density of
vias is then placed in the source pads of both MOSFETs. These vias are connected on the
bottom side with wide traces. Fig. 9.1(a) shows the top side of the PCB (gate drive only),
and Fig. 9.1(b) shows the bottom side of the PCB. The location of the vias is clearer in
Fig. 9.2(b). Also note from Fig. 9.1 that certain paths are relatively long, which helps to
keep the M 1 to M 2 trace short. This is especially true of the path in series with LFB2, which
is a sufficiently large discrete inductor that added board inductance is not problematic.
A second important consideration in this PCB design is ease of circuit tuning. Capacitances are relatively easy to tune, because the chip mica capacitors used in this design can
be stacked in prototype construction such that extra pad area is not typically required.
Inductors are more difficult to tune because they are available in fewer sizes and multiple
inductors cannot be placed on the same pad. However, when an inductor is in series with
a capacitor, the placement of the capacitor can be varied to control the amount of board
inductance that appears in series with the discrete inductor. To allow this type of tuning,
-
90
-
9.3
Inverter and Matching Network PCB Layout
multiple capacitor pads are placed in parallel, and this parallel structure is place in series
with the inductor pad. In this design, a parallel structure is used for CBP such that board
inductance can appear either in series with LMR1 or in series with the supply VGIN, where
it is insignificant. The space occupied by this feature was otherwise unused in this layout.
The structure can be seen in Fig. 9.1(a) on the left side of the image and to the right of the
black measurement ticks.
An effort is also made to minimize parasitic capacitances to ground. This is accomplished
by overlapping the bottom side metal (ground) and the top-side signal traces only where
necessary. Thus, bottom side metal appears only under top side ground traces and between
the M 1 and M 2 source vias, as illustrated in Fig. 9.2.
9.3
Inverter and Matching Network PCB Layout
Once the gate drive PCB layout is complete, the inverter and matching networks are added.
The primary goal of this portion of the layout is to introduce as little parasitic resistance,
capacitance and inductance into the resonant tank as possible. Low series inductance and
resistance are accomplished by minimizing the length of the path from drain to source
through the tank and by making this path wide where possible. As a result, insufficient
space is left on the top side for CEXTRA and LMRS, which are therefore placed on the
bottom side. This is acceptable because the inductor LMRS is small enough that it can be
composed of low-Q board inductance without significant loss of efficiency.
As mentioned above, low capacitance to ground in the resonant tank is also important.
This prevents power from being diverted from the compression network into ground, and is
ensured by placing no ground plane under the resonant tank (Fig. 9.2).
Another consideration in this portion of the layout is the high current magnitude in the
inverter. One potential problem that these currents create is flux linkage between inductors.
This is prevented by placing LR perpendicular to the choke and to LM1, the matching
inductor. The choke and LR are also separated by the distance required for CR.
The high current magnitude can also cause significant loss in the traces in this part of the
layout. To alleviate this problem, bottom side metal is placed under the top side power
and ground traces, and the two sides are connected with a high density of vias as shown in
Fig. 9.2. An additional advantage of placing power and ground metal on the bottom side
of the PCB is that half of the input filter capacitors can be placed on the bottom side, as
shown in Fig. 9.2(b). This allows better utilization of board area.
-
91 -
Printed Circuit Board Layout
01,
(b)
(a)
Figure 9.2: The inverter, matching network and gate drive portions of the PCB, top
(Fig. 9.2(a)) and bottom (Fig. 9.2(b)). The bottom layer is mirrored such that the top and
bottom layers line up. LMRS can be changed by moving CEXTRA along the line of hash
marks near the center of Fig 9.2(b). Shifting CEXTRA left increases LMRS. Fig. 9.1(b)
shows the top side component placement for reference. Notice the minimum overlap between the ground plane and the top side components. Also notice the large BNC connector
in the upper right portion of Fig. 9.2(b). This is used only for testing the inverter alone,
and is replaced by the rectifier board in the completed converter.
Another important consideration is the ease with which the inverter can be tuned. The
designer's ability to tune LMRS is especially important because of the simulated converter's
sensitivity to this value (Fig. 3.10). As a result, the inverter contains a structure similar to
the one used in the gate drive layout for tuning LMR1. This structure, shown in Fig. 9.2(b),
allows LMRS to be adjusted with the placement of CEXTRA-
9.4
Compression and Rectifier PCB Layout
Most of the considerations in the layout of the compression and rectifier stages are similar
to the issues discussed above. For example, the inductors are placed perpendicular to
one another where possible, and the traces are made as wide as possible to reduce their
inductance and resistance.
One additional challenge in this portion of the layout is compatibility with the previously
designed parts of the PCB. This is especially difficult because the compression and rectifier
stages are laid out on a separate board for the first prototype of this design. This allows
-
92
-
Compression and Rectifier PCB Layout
9.4
Output
Capacitors
Positive
Connection
To inverter
Board
CC1
Zener
Diodes
CC2
CR2
Ground
Connections
To Inverter
Board
(b)
(a)
Figure 9.3: The compression network and rectifier PCB, top (Fig. 9.3(a)) and bottom
(Fig. 9.3(b)), both on the same scale. The bottom layer is mirrored such that the top and
bottom layers line up. Notice the three large holes that form the corners of an isosceles
triangle. These line up with the BNC-connector holes on the inverter board, and are used as
part of the ground connection between the two boards when the BNC connector is replaced
by the rectifier board.
the two halves of the converter to be built and tested separately, and then interconnected.
If only one of these two halves works, the other can be redesigned and rebuilt on a new
PCB without affecting the working half. This design methodology requires that the rectifier
board physically fit on the inverter board, and that a large-area ground connection exist
between the two. These requirements are met by the rectifier board designed by Yehui Han
and shown in Fig. 9.3.
-
93
-
Chapter 10
Converter Construction and Measured
Results
10.1
Introduction
This chapter discusses how the final converter design was built, tuned, and measured. The
converter is constructed in stages, such that performance problems are easily locatable.
Construction of the converter is discussed in approximately the order that it was carried
out. After the construction of each stage is treated, the final measured results are given.
The chapter concludes with a discussion of some alternative techniques for building and
testing various stages of the converter.
10.2
Gate Drive Construction and Tuning
The gate drive is built and tuned first because in the event that it is inoperable, design
changes affecting other parts of the converter may be necessary. Furthermore, tuning the
gate drive is more complex than tuning the other parts of the converter because of the MR
circuit in the gate drive. To simplify gate drive tuning, a small PCB is ordered with only the
gate drive on it. Unlike the PCB with both gate drive and inverter, this board fits vertically
into an Agilent 16092A test fixture (connected to an Agilent 4395A impedance analyzer)
such that the ground planes of the board and the fixture are perpendicular and do not form
a large capacitor. The only significant parasitic between the board and the fixture is series
inductance, which can be measured and subtracted out far more easily than distributed
capacitance. This smaller board does not become part of the converter, although its exact
layout is replicated on a larger board, as discussed in the next section.
To tune the MR portion of the gate drive circuit, M 1 and M 2 are soldered to the PCB,
and the capacitance COSSM2 11 CIssM1 is measured and used to calculate LMR1, CMR2 and
LMR2 using Eq. 3.5. Because the inductance between the board and the fixture dominates
these measurements, it is subtracted out using the MATLAB script shown in appendix F.
-
95
-
Converter Construction and Measured Results
VOs,
VGSM1 vs. Time
0
12
11
12
10
9
8
10
vs. Time
--
11
-I
9
8
7
7
S0
6
5
4
3
2
6
A-
5
4
3
2
'-4
-
- --
0
-1
0
-1
-1
-0.5
0
Time [sec]
0.5
1
VGIN
VGN
-1
x
1045
-0.5
0
Time [sec]
0.5
1
X10,
(b)
(a)
Figure 10.1: Typical gate drive waveform (VGSM1) measured using a Tektronix P6158 Low
Capacitance Probe on a Tektronix TDS7254B with full bandwidth (2.5GHz). Fig. 10.1(a)
shows the gate waveform with RVGIN - 33Q and no averaging. Fig. 10.1(b) shows the gate
waveform with RVGIN ~ 33Q and RVGIN = OQ with an averaging factor of 16 (to remove
noise from the measurement). The two waveforms are nearly identical, which demonstrates
that no resistance needs to be added to the gate drive circuit.
CMR2 and LMR2 are then soldered on, and tuned to ensure that the requisite null occurs
at 200MHz. This tuning is accomplished by adding or removing discrete capacitance and
inductance. The board inductance is sufficiently high for this part of the circuit that LMR2
is replaced by a piece of flat copper foil, trimmed to give the desired performance. LMR1 is
then soldered to the board and adjusted by moving CBP until the desired MR performance
is achieved. The SO circuit is then populated in a single step, and the gate drive is tested
with the drain to source of Mi shorted to prevent simultaneously high VGSM1 and VDSM1. A
typical gate waveform is shown in Fig. 10.1. The simulated and actual gate drive component
values are shown in Table 10.1.
The effects of changing various component values are then measured. Changes in LFB2 by
up to tens of nanoHenries have no effect upon the circuit. Similarly, changes in RVGIN do
not affect the shape of VGSM1 by a perceptible amount (Fig. 10.1(b)). This allows RVGIN
to be reduced to zero, thereby reducing the power consumed by the gate drive.
-
96
-
10.3
Inverter Construction and Tuning
Gate drive component values
Value
(Desired)
Nominal
Value
2nF
lnF
CMR2
8.0992nH
4nH
150.55pF
LFB1
100nH
2.5nH
Copper foil shorting pads
(68nH±5%) x 2
12pFi5%
100nH
1nF
lnF
CFB
25.3303pF
56pF±5%
LBYPASS
LFB2
82nH
84.4343nH
(8pF±0.25pF) x 2
82nH
68nH
Component
Name
CBP
LMR1
LMR2
CBLOCK
Manufacturer
and Part Type
Part Number
Kemet 50V Ceramic Chip
C0805C103K5RAC
Coilcraft Mini Spring Air Core
A01TJ
x 2
CDE 100V Chip Mica
CDE 100V Chip Mica
Coilcraft Midi Spring Air Core
Kemet 50V Ceramic Chip
CDE 100V Chip Mica
MC12FA680J
MC08EA120J
1812SMS-R1OJ
C0805C103K5RAC
MC12FA560J
CDE 100V Chip Mica
MC08CA080C
Coilcraft Chip Inductor
1008HQ-82NXJB
Coilcraft Midi Spring Air Core
1812SMS-68N
Table 10.1: Component values for the final gate drive design.
10.3
Inverter Construction and Tuning
As mentioned above, a second board with both the gate drive and inverter layouts is made,
and populated with components so that it can be used as part of the complete converter.
However, before any components are placed on this second board, the parasitics of the
resonant tank are measured and included in a PSPICE simulation. This allows the designer
to determine whether adjustments must be made to the resonant tank to achieve proper
operation. In this design, this process indicated that the tank layout contains 8.91nH of
series inductance, which can be compensated for by reducing LR by this amount. No other
adjustments are made.
The next step in the inverter construction is to populate the board with gate drive components. This is accomplished by observing the placement of each component on the smaller
gate drive board and placing a component of the same nominal value in the same location on
the larger board. Surprisingly, both of the inverter boards built using this method worked
without any retuning, even though all component tolerance are 5% or greater.
Once the gate drive on the larger board is tested, the rest of the inverter and matching
network components are added. A 25Q resistor is used in place of the compression and
rectifier stages. This resistor is composed of five 5.1Q resistors in series with a capacitor
sized to resonate with the measured series inductance of the five resistors. The specifications
for these components are shown in Table 10.2
Once the board is fully populated, the gate drive and inverter power inputs are connected
to two separate variable supplies (CircuitSpecialists.com HY3002D-3) by twisted pair wire
wrapped around small ferrites (Fair-rite part number 2643002402) for common mode rejection. The input voltages are measured at the input to the board using Hewlett Packard
-
97
-
Converter Construction and Measured Results
Nominal
Resistance
5 x 5.1Q2
Measured
Series
Inductance
44.4nH
Required
Series
Capacitance
57pF
Nominal
Series
Capacitance
l0pF+47pF
Measured
Measured
#
Resistance
at 100MHz
[degrees]
1 0.56 to 1.25
24.950
Measured
Q
0.02193
|
Table 10.2: Inductance-compensated load resistor information. Note that a low Q value
makes the load less sensitive to the exact value of fs. The resistors are 25W, TO-220
thick film power resistors valued at 5.1Q ± 5%, Ohmite part number TBH25P5R10J. These
measurements are made at room temperature on an Agilent 4395A impedance analyzer with
a 43961A RF impedance test adapter and a 16092A spring clip fixture. The components
are connected exactly as they are used in the inverter. A heat sink is used to keep the
resistors close to their room temperature values. The capacitors are Cornell-Dubilier silver
mica capacitors, part numbers CD4CD100CO3 (10pF) and CD4ED470JO3 (47pF).
34401A multimeters, and the input current was measured between the board and the common mode choke using a Fluke 77111 handheld multimeter. These input current and voltage
measurements were verified using Tektronix current and voltage oscilloscope probes. The
output voltage waveforms are measured using a Tektronix P6158 Low Capacitance Probel
connected to a Tektronix TDS7254B oscilloscope. The RMS output voltage (calculated by
the scope) is squared and divided by the measured resistance of the load to determine the
output power.
To ensure that the drain voltage at VIN = 16V would not exceed the rating of the Freescale
MRF373ALSR1, VDSMAS is measured at a low value of VIN for several values of LMRS.
These values include a discrete 5nH inductor, a copper foil short across the LMRS pads, and
a short from CEXTRA directly to the vias connected to the drain. This last configuration of
LMRS is the minimum inductance connection for this board layout, and was found to allow
unacceptable levels of oscillation on VDRAIN. The copper foil short is used initially because
it provides sufficient damping of these oscillations.
After this initial tuning of LMRS, measurements are made of the converter input power,
output power and efficiency over the input voltage range. To allow for tuning of the tank
without intentional deformation of a surface mount inductor, two loops of magnet wire are
placed in series with a discrete inductor to form LR. The spacing and orientation of these
two loops is changed to achieve the performance shown in Table 10.3. This table illustrates
the uncertainty associated with this measurement by providing two measurements of the
inverter at VIN = 11 and 16V. This uncertainty is due to noise at the output, which
alters the calculated RMS output voltage.
This problem is reduced somewhat in these
'These probes are rated for a maximum continuous RMS voltage of 22V, but are subjected to roughly
28VRMS in this measurement and measurements described in section 10.5. This is possible by exceeding the
rated voltage for only the time required to capture the data by manually inhibiting oscilloscope triggering.
Post-measurement probe tests indicate that no degradation in scope probe performance occurs due to this
type of use.
-
98
-
10.4
Construction and Tuning of Compression and Rectifier Stages
Inverter and Matching Network Measured Results
PIN I RMS(VOUT)
POUT
r7
VIN
[V
IIN
[A]
[W]
[V]
[W]
[%]
11.00
1.22
13.42
17.22
11.86
""
89.20
""
""
17.75
12.60
93.90
1.51
1.76
20.39
28.16
21.64
25.5
18.73
26.01
86.55
92.37
""
""
24.63
24.27
86.17
13.5
16.0
""
Inverter and compression network component values used to achieve the above results
Simulated
Component
Value
Nominal
Manufacturer
Name
(Desired)
Value
and Part Type
Part Number
CIN
-
LCHOKE
CEXTRA
LMRs
CR
240nH
20pF
5.4947nH
83.99pF
2.2 1LF
0.681pF
0.047pF x 12
120nH x2
lOpFi0.5pF)x2
Copper foil shorting pads
82pF±5%
35V Chip Tantalum
35V Tantalum Chip
PCT6225CT
PCT6684CT
Kemet 50V Ceramic Chip
C0805C473M5UAC
Coilcraft Maxi Spring Air Core
CDE 100V Chip Mica
1812SMS-R12G
MC08CA100D
-
CDE 100V Chip Mica
MC12FA8205
CDE 100V Chip Mica
MC08CA020D
Coilcraft Mini Spring Air Core
18 AWG
A04TJ
Coilcraft Mini Spring Air Core
Freescale RF LDMOS
B06T6J
MRF373ALSR1
2pF+0.25pF
LR
21.3582nH
12.5nHi5%
Two turns of magnet wire
8.9nH board parasitic
Lmi
M
17.51nH
-
17.5nH±5%
70V max VDS
Table 10.3: Measurements of the inverter and matching network with inductancecompensated 25Q load, and the inverter component values used to make these measurements. The gate drive components are the same as those given in Table 10.1. These
measurements do not consider gate drive power.
measurements by using an averaging factor of 16 while maintaining the full scope bandwidth.
However, this does not solve the fundamental problem that the output power is consistently
lower than the predicted results shown in Table 3.4. This is most likely due to a mismatch
between the inverter and the load due to the frequency dependence of the load. The decision
was made to connect the rectifier in place of the load, instead of retuning the inverter and
matching network with the load connected. This produces the results shown in section 10.5.
10.4
Construction and Tuning of Compression and Rectifier
Stages
The compression and rectifier stages can be built concurrently with the inverter and matching network because the two halves of the converter are built on separate boards and then
joined, for reasons discussed in chapter 9.4. The first components placed on the compression/rectifier board are the inductor LC 1 and capacitor Cc1 in each rectifier. This allows
-
99
-
Converter Construction and Measured Results
Compression network and rectifier component values
Component
Name
Simulated
Value
(Desired)
Cci
39.79pF
Cc 2
79.58pF
LC 1
31.83n
63.67nH
30pF
19.8nH
LC 2
CR1, CR2
LR1, LR2
Dl, D2
COUT
-
Manufacturer
and Part Type
Part Number
CDE 100V Chip Mica
CDE 100V Chip Mica
CDE 100V Chip Mica
CDE 100V Chip Mica
Coilcraft Midi Spring Air Core
Coilcraft Midi Spring Air Core
CDE 100V Chip Mica
Coilcraft Mini Spring Air Core
OnSemiconductor Power Schottky
Kemet 50V Ceramic Chip
MC08EA180J
MC08EA150J
MC12FA560J
MC08CA070J
1812SMS-33N
1812SMS-68N
MC08EA150J
A05TJ
MBRS260T3
C0805C104M5UAC
Nominal
Value
18pF+5%
15pF±5%
56pFi5%
7pF±0.25pF
33nH±5%
68nH±5%
(15pF±5%) x 2
(18.5nH±5%) x 2
60V, 2.OA
O. 1 F x 19
Table 10.4: Component values for the compression network and rectifier design.
the resonant frequency of these two components to be verified using an impedance analyzer
without the complexity of diode nonlinearities. In this design, no tuning of these components is necessary because the parasitics in this part of the layout are sufficiently low. All
four of the compression network components are then added, and the impedance into the
compression network is measured and compared to simulation results. This impedance is
tuned by varying the compression network capacitances. Once the desired impedance is
achieved, the assembly is completed by adding the two rectifier diodes. The component
values for the completed compression and rectifier stages are given in Table 10.4.
Before the rectifier and compression network board is connected to the inverter and matching network PCB, proper operation of the compression network is verified. This can be
accomplished by loading the compression network with an HP 6063B DC Electronic Load,
set to hold the rectifier output voltage constant at 12VDC. The rectifier is driven with an
Amplifier Research Model 150A100B power amplifier, which is, in turn, driven by a function
generator unit composed of a General Radio Company 1363 VHF Oscillator and a General
Radio Company 1264B Modulating Power Supply operating together and set to 100MHz.
Because the current into the rectifier is difficult to measure, the inductance-compensated
25Q resistor described in Table 10.2 is placed in series with the compression network input.
If the compression network and rectifiers are functioning properly, the compression network
input voltage should be approximately equal to the input voltage divided by 2, with minimal phase difference between the two. This is due to the fact that the compression network
input impedance is mostly resistive, and varies between about 20 and 25Q. The performance just described was achieved without additional tuning of the rectifier or compression
stages, and the rectifier board was connected to the inverter board. The two connections
between these two boards (matching network to compression network positive connection,
and connection of the ground planes) are made with 0.010" copper foil soldered in place.
The foil is made as wide as reasonably possible to reduce the inductance and resistance of
the connection. The drawbacks of this type of connection are discussed in chapter 11. A
-
100
-
10.5
Measurements of Completed Converter
Figure 10.2: A photograph of the completed converter. The compression network and
rectifier board is in the upper right corner. The quarter dollar in the lower right corner is
used for scale. Note that a significant portion of the board is unused (except that it contains
ground plane that provides insignificant shielding).
photograph of the completed converter is shown in Fig 10.2.
10.5
Measurements of Completed Converter
Once the entire converter has been assembled, its performance is tested. This is accomplished connecting the inverter and gate driver to two separate dc supplies and to a number
of voltmeters and ammeters, as described in section 10.3. The output is connected to the
electronic load mentioned in section 10.4. The output voltage is measured at the board
using a Hewlett Packard 34401A multimeter, and the output current is measured with a
Tektronix TX3 True RMS handheld multimeter. Fig. 10.3 shows measured converter power
and efficiency data. All of the components for this converter are the same as the values
given in Tables 10.1, 10.3 and 10.4, except that the value of Cci is reduced by 3pF (to
two 15pF capacitors) and the value of CC2 is reduced by 4pF (to a 56pF capacitor and a
-
101
-
Converter Construction and Measured Results
Output Power vs. V N
Efficiency vs. VIN
76.7917
27-
76
2575-
23
74
21
19 -
a
17
(L
15
1
-
-
--
14.2489
132606
--
13-
O
0
-
72
71-
11
Intended Converter Operating Range
70-
9
7
5 --8
73-
Intended Converter Operating Range
69-
-9
10
11
12
13
14
15
6
1
9
10
11
12
13
14
15
16
Figure 10.3: Measured converter output power and efficiency. Two measurements are taken
at each voltage, and the average of these voltages is shown as the solid line. Several points
outside of the intended operating range are shown to demonstrate that the converter is
functional over a broad range.
3pF capacitor). This accounts for the fact that the measured operating frequency is around
102MHz, rather than at 100MHz.
Fig. 10.3 indicates that the measured minimum output is more than 2W higher than the
simulated minimum of 10.938W, shown in Table 8.1. The figure also shows that the measured maximum output power is almost equal to the simulated output power of 29.323W.
Unfortunately, the efficiency is lower by roughly 5.5% at the minimum input voltage, and
by roughly 7.4% at the maximum input voltage.
One possible explanation for this lower efficiency could be a lack of Class E switching.
However this possibility is immediately ruled out by the waveforms shown in Fig. 10.4,
which were recorded on the same converter, and at the same time, as the waveforms shown
in Fig. 10.3. Fig. 10.4 shows the voltages at the M 1 drain, M1 gate, and matching network
2
output (compression network input VCIN), which are measured using carefully deskewed
Tektronix P6158 Low Capacitance probes connected to a Tektronix TDS7254B oscilloscope.
The drain waveform clearly indicates that the inverter has the desired Class E switch voltage
waveform. The drain waveform also shows that the device rating of 70 volts is repeatedly
exceeded, an issue which is addressed later in this section.
Another possible explanation for the low converter efficiency is the apparently low quality
2
Deskew is accomplished by simultaneously connecting all three probes to function generator operating
at 100MHz. The function generator is the General Radio Company device described in section 10.4.
-
102
-
10.5
Measurements of Completed Converter
Measured Converter Waveforms vs. Time
. . '.
015
>
9 -
S8
0
20
-2
-1.1-.
-15
. V.
80
60
5
-0.5
-1
0.5
0.5
0
1.5
1.5
1
1
2
2.5
. X1..I.. .
..
. .. ....
pe50--p
40
3020--10-
U)
0
>
-.... .
.
-..
3 10
-
.
VN =16.V
VIN
- VI=16V
12-
-
-
..-...-
-.
0
-2
-1.5
-1
0
-0.5
0.5
1
1.5
2
2.5
YY
10
Measure covete waveforms....... Osilocp is...
samsapeasth
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network outpu votae a.s shw
inFg..5.Ti
Afarre.4 plasbled explnaeton aeforms. lowsffciencyp is hat te refier bandt compressio
vice vera) Thraisg. Tdenitely sprae a wdlya possible deptfr fc htte w
inrteen meaure
avsof teconverter
ovrtrwstueiihchneng.cn
covrtea opratinaltr butute
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eficdiecy. tHowever, the onvlierteyi not tued
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mefenywer, the trcswroneter qite ot
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surhrt eriodaohr
power. This problem is discussed more in chapter 11.
-
hecmlt
103
-
ertno
yas of oprtoeethe
Converter Construction and Measured Results
VCIN vs. Time
50
Measured
Simulated
-
40
30
a
20-
5
0-10-20-30
.
-40-1.5
-1
-0.5
0
0.5
Time [sec]
1
1.5
X 10
Figure 10.5: Comparison between measured and simulated compression network input voltage. The measured waveform is the same as the VIN = 16V value shown in Fig. 10.4.
The simulated waveform was created with the same circuit used in chapter 8.2. The only
modification that has been made to the waveforms is a time shift.
Chapter 3.8 mentions the possibility of using a single 120nH choke instead of two in series.
However, lowering the choke inductance would cause it to act less like an ideal current
source, and increase the magnitude of its oscillations with other circuit elements. Because
of the high peak value of VDS, measurements of the converter were not made with a 120nH
choke.
10.6
Additional Tuning of LMRS
As stated in section 10.3, the value of LMRS is tuned to achieve the final measured results
given in the previous section. This is accomplished by measuring the peak value of VDS for
several values of LMRS, including a copper-foil short across the LMRS pads, and choosing
the inductance that provides the lowest peak value of VDS.
However, only three values of LMRS are used in this initial tuning. A broader and more
finely spaced stepping of LMRS is needed to determine if the performance of the actual
converter and of the simulated converter are affected by LMRS in the same way. This
requires plotting the peak value of VDS, and the converter output power and efficiency, as
functions of LMRS, as was done in simulation and shown in Fig. 3.10. Because the required
-
104
-
10.6
Peak VDS (in five cycles) vs.
Additional Tuning of LMRS
RSTuning
66
>
64
CU
62-
-
6)
CL
60
5
10
Converter Output Power vs.
15
MS
Tuning
20
25
20
25
25.5
250
CL
24.5
-
0.
0
5
10
Converter Efficiency vs.
15
LMRS Tuning
LMRs Tuning Number
Figure 10.6: Measured converter performance for a range of LMRs values. Compare this
plot to Fig. 3.10. The converter is the same as the design discussed in section 10.5, except
for the location of CEXTRA and the value of LMRs. All points are measured with VIN
15.OV. Tuning 25 (the upper bound of LMRs is accomplished with a 7.9nH loop of wire
soldered to the LMRS pads. Tunings 24, 23 and 22 are made with 5.7nH, 5.0nH, and 4.5nH,
respectively. All other tunings are made by adding loop length between CEXTRA and the
drain in increments of less than 1mm.
inductance increments are so small, the stepping is done by moving a small piece of wire
by increments to increase the length of the loop from the drain to CEXTRA in small steps.
The wire is soldered in place each time it is moved. When larger values of inductance are
needed, small loops of wire are soldered between the LMRs pads. Great care is taken to
increase the inductance monotonically in small increments. The resulting plots are shown
in Fig. 10.6. To protect the main LDMOS device (MAPLST081O-030CF), the input voltage
is set at 15.0V instead of 16.OV. Thus, although none of the peak voltages exceed the 70V
rating of the MAPLSTO81O-030CF, most would exceed this rating with VI1N =16V. The
peak drain voltage at VIN = 16V can be determined by finding the peak-to-dc ratio for
each tuning (at 15V), and multiplying this ratio by 16V.
Unfortunately, the actual value of LMRS cannot be determined at each step, because it
depends far more upon the inductance of the board traces than upon the small piece of wire.
Experience with the available impedance measurement equipment indicates that the error
associated with measuring the trace inductance at each step would render the measurements
-
105
-
Converter Construction and Measured Results
Cycle-to-cycle Variation in Peak V
G8
67-
66--
A5
0
0
S62...
65
a)
d-
1..
2.2
15
20
60-
5958
5
10
'MRS
25
Tuning Number
Figure 10.7: Cycle-to-cycle variation in the peak value of VDS over five consecutive cycles of
VDS, and over the range of LMRS values. The lines follow the minimum and maximum peak
value of VDS over the range of LMRS values. The three dots between the lines correspond
to the peak values of the other three periods at each LMRS tuning. These data were taken
simultaneously with the data shown in Fig. 10.6.
useless. This is why inverter performance is plotted versus tuning numbers in Fig. 10.6.
The tuning scale increases monotonically, like LMRS.
Fig. 10.6 indicates that the performance of the actual converter is not nearly as sensitive to
LMRS variations as the simulated converter. In other words, unlike the simulated inverter,
the actual converter does not exhibit pseudo-periodic pattern of constructive and destructive interference between various resonances in the inverter (see Fig. 3.10 for simulated
performance). The relative insensitivity of the measured converter to changes in LMRS is
further illustrated by Fig. 10.7. This figure shows the peak value of VDS in each of five
consecutive periods of the VDS waveform. The points connected by the solid line are the
same as those given in the top plot of Fig. 10.6. The cycle-to-cycle variation shown in this
plot indicates that any weak trends in Fig. 10.6 are somewhat weaker than they appear.
Several conclusions can be drawn from this experiment. First, tuning LMRS is not actually
as effective for controlling the peak value of VDS as simulation indicates. This is because
low peak values of VDS are accompanied by either low efficiency or low output power, or
both (consider tunings 20 through 25 in Fig. 10.6). In simulation, low peak VDS values
correspond to high values of both output power and efficiency. A second conclusion is that
the act of retuning LMRS degrades converter performance. This is indicated by the fact
-
106
-
10.7
Investigation of Other Inverter Tuning and Measurement Methods
that both output power and efficiency are lower for all values of LMRS in Fig. 10.6 than in
Fig. 10.3 at 15V. This is most likely because the movement of components like CEXTRA
causes degradation of these components. Degradation of the PCB is also possible. The final
conclusion, which follows from the first two, is that other means should be used to ensure
sufficient switch headroom. For example, a switch with a higher voltage rating could be
used, or a partial Class F inverter could be used in place of the Class E inverter. This is
discussed further in chapter 11.
10.7
Investigation of Other Inverter Tuning and Measurement Methods
A number of other techniques for measuring and tuning the inverter and matching network
board were explored. Although only the approach described in section 10.3 was successful,
the other methods are discussed here because of their potential for success in future work.
10.7.1
Resonant Tank Tuning with Impedance Analyzer
In an attempt to improve the similarity between the constructed and designed resonant
tanks, an inverter board is constructed by tuning the resonant tank with an impedance
analyzer. This is an alternative to tuning the tank by measuring converter performance and
by observing the drain voltage waveform. The first components to be placed on the board are
the tank inductor LR and capacitor CR. A short is soldered in place of LM1, the matching
inductor. 1/4" wide leads of 0.020" thick copper are then soldered to the drain and source
pads of M 1 so that the impedance into the tank can be measured. The inductance of these
two leads when soldered together (without the PCB) is measured to allow for compensation
of the tank impedance measurements using the Matlab code shown in appendix F. The
resulting compensated impedance measurements are compared with simulations of the tank
impedance, and the tank is tuned by varying LR. The value of CR is not changed because
it is assumed to be accurate since the capacitance around the loop is small. Because only
small changes in LR are required, the tuning is done by physically distorting the inductor,
which has the unfortunate side effect of reducing the inductor's Q. Alternatively, a small
loop of wire could be added in series with an un-altered Coilcraft inductor. This scheme
is implemented in the inverter that is used for the final converter design, and allows small
changes to be made without adversely affecting most of the inductance.
Once the lead-inductance-compensated measurement of the tank impedance matches simulation, LM, is added in place of the short across its pads. This inductance is tuned in the
-
107
-
Converter Construction and Measured Results
same manner as LR. A 25Q, 1/4W surface mount inductor is then added in parallel with
LR, and the impedance from the drain and source pads is again compared to simulation.
The rest of the tank components are then added, and the inverter is tested as described in
section 10.3. Unfortunately, the drain waveforms do not zero-voltage switch. This is most
likely because of measurement error associated with this tuning technique. Consequently,
although there are no fundamental flaws associated with this tuning technique, it is not
used for the final design.
10.7.2
Inverter Output Power Measurement with Power Meter
As discussed at the end of section 10.3, measuring the output power of the inverter (without
the compression and rectifier stages) is quite difficult because of measurement noise, and
because of the frequency selectivity of the inductance-compensated load resistor.
This measurement can potentially be improved by matching the inverter output into 50Q,
connecting this matching network to a power meter, and connecting the power meter output to a 50Q load resistor. This is implemented with a Bird Electronic Corp. Model 43
wattmeter and a Vectronics 50Q load resistor rated for greater than 100W in continuous
operation. The matching from RLOAD = 4.0544Q to 50Q is accomplished in two stages.
Unfortunately, inaccuracies in the matching stages result in output power readings that are
much lower than the measurements made using the technique described in section 10.3. It
was also discovered that the specific wattmeter used to make these measurements displays
power measurements that are ~ 10% lower than the actual power.
-
108
-
Chapter 11
Conclusions
11.1
Introduction
This chapter concludes the thesis by comparing the contributions made by this work to the
original objectives of the project. Some of the lessons that have been learned from this
work are then summarized. Potential future work that can be done in the area of RF dc/dc
power conversion is then discussed.
11.2
Evaluation of Thesis Objectives and Contributions
The objectives of this thesis, as stated in the introductory chapter, were to design and experimentally demonstrate an unregulated dc voltage to unregulated dc current converter with
improved performance over the design in [1]. Proposed areas of improvement were increased
output power, efficiency, switching frequency, and/or decreased board area. The introductory chapter also indicated that changes would be made to all stages of the converter, with
the goal of increased converter performance.
The goals of this thesis have been achieved. Although measured converter efficiency has
dropped by ~ 2% over the entire operating range, and the switching frequency is unchanged,
the maximum output power of this design is a factor of ~ 4.9 times the maximum output
power of the previous design. Moreover, the minimum output power has been increased
by a factor of - 5.1. The board area is roughly equal despite the fact that the component
count is higher in this design because of the gate drive redesign. Furthermore, changes have
been made in each stage of the converter to improve performance.
The author hopes that the work describe in this thesis will be helpful to those working
on high frequency dc/dc power converters, and that this document will provide valuable
design guidance. It is also hoped that the size and cost of dc/dc power converters can be
significantly reduced by this type of work, thereby enabling improvements in a wide range
of electronics industries.
-
109
-
Conclusions
11.3
Evaluation of Lessons Learned
One important lesson to be learned from this work is that devices rated for higher drain
to source voltage should be used in the design described here. Although no devices were
destroyed by this converter, the repeatability (and manufacturability) of this design is decreased because of the extremely low voltage headroom. Alternatively, a topology with
significantly more headroom could be used. This conclusion is strengthened by the fact
that the peak value of VDS is difficult to control by tuning LMRS.
A second important point that should be taken from this work is that the printed circuit
boards for this converter should be made with at least 4oz. copper, which is more commonly
used than 2oz. copper in PCBs used in power electronics.
One lesson learned from the LDMOS device characterization is that dc resistance measurements should probably be made using a curve tracer, rather than with a low-current
ohmmeter.
This work also demonstrates that using a discrete multi-resonant circuit as a choke does
not produce sufficiently high efficiency inverter operation. Furthermore, although only a
few powdered iron cores were evaluated, using a core slightly reduces the quality factor of
the choke inductor. The investigation into switch packaging indicates that chip-on-board is
probably a better way to significantly reduce the PCB area occupied by the MOSFET M1
than repackaging the device.
Analysis of rectifier topologies indicates that although the MR rectifier topology provides
lower diode voltage stress and a smaller input phase range, the non-MR rectifier provides
significantly higher efficiency over the entire input voltage range.
Finally, it should be remembered that although the inverter and matching network performance was unacceptable when connected to a load resistor, the performance of the entire
converter was relatively close to that of the simulated converter. This is because of the
difference in frequency selectivity between the load resistor and the compression network.
11.4
Future Work
Despite significant reduction in dc/dc power converter size and cost in recent years, there
is still much room for improvement in this area of electronics. To help to realize these
improvements, a considerable amount of work could be done to build upon what is presented
110
-
11.4
Future Work
in this thesis. This work can be roughly divided into short and long term goals.
11.4.1
Short Term Goals
One of the primary short term projects could be the redesign of the PCB with copper
that is at least twice as thick as the traces on the current board. This could significantly
reduce converter loss, as could putting the entire converter on a single PCB. Redesigning the
PCB could also include making it smaller by leaving less room between components and by
utilizing the bottom side of the board more effectively. Furthermore, to reduce the cost of
the board, a board with a greater overall thickness, but with more layers, could be designed.
The cost of the 0.020" PCB used in the present design is much higher than that of a fourlayer board with comparable thickness between each layer. This would also increase the
robustness of the converter. The redesign of the PCB would also be an excellent opportunity
to further investigate the possibility of chip-on-board, as discussed in chapter 3.10. This
would noticeably reduce the required board area.
Another important short term goal could be the addition of a startup circuit to the converter.
As mentioned in chapter 4.5, the verification of a startup circuit design is still in progress at
the time of writing. A related task is the development of the new control circuitry needed
to make a dc/dc voltage converter of the type shown in Fig. 1.3 in which one or more
unregulated voltage to current converters supply a load, and a voltage source maintains the
load voltage.
A third short term project could be to further explore the possibility of building or purchasing inductors with higher quality factors than those currently in use.
11.4.2
Long Term Goals
The most obvious long term work is to continue the search for MOSFETs with lower
RDSONCOSS products. These devices will most likely continue to evolve rapidly as the
telecommunications industry advances.
A more challenging, and potentially more beneficial project would be to integrate the passive
components of the converter into a PCB. This would probably require careful consultation
of literature such as [33], and the careful use of computer programs such as FastHenry and
FastCap. This could allow smaller passive components to be created with higher accuracy
and (hopefully) with comparable quality factors. These smaller passive components would
enable increases in switching frequency.
-
111 -
Conclusions
Yet another challenging long term goal would be to further explore other topologies for the
inverter and other converter stages. For example, Class 1/F could be explored more thoroughly to reduce inverter loss due to switch current peaking. Additionally, the possibility
of using a synchronous rectifier would be worthwhile.
The most long-term vision for this type of work is currently to integrate a converter in silicon.
This would require very high storage density passive components, and might benefit from
bond wire inductance.
- 112
-
Appendix A
PSPICE Simulation Files
A.1
Introduction
This appendix contains the PSPICE library and circuit files used in modelling the performance of each stage of the converter.
A.2
Library File
Shown below is the library file that is included with each of the PSPICE circuit files. In
each of the simulations, this library is referred to as classe.lib
*** LIBRARY OF PSICE MODELS FOR
RF
DC/DC CONVERTER
***
*** BY JUAN RIVAS AND DAVID JACKSON
*** CAMBRIDGE, MA, 2005
* **
***
***
** *****
******
*****
****
******
***
*****************
*MODEL: LQS
* APPLICATION: SIMPLE MODEL OF AN INDUCTOR IN WHICH
*
Q IS SPECIFIED AT A GIVEN FREQUENCY
*PARAMETERS:
*
*L
: INDUCTANCE
*QL
: QUALITY FACTOR
*FQ
: FREQUENCY AT WHICH THE INDUCTOR
*IC
: INITIAL CONDITION *
****
********
**
***
***********
*NODES:
* LSI: INDUCTOR INPUT
* LSO: INDUCTOR OUTPUT
************
*
*
*
*
*
Q IS
***
SPECIFIED
*****
*******
*
*
*
.SUBCKT LQS LSI LSO
+ PARAMS:
+ L=1U
+ QL=300
+
*
FQ=60MEG
+ IC=0
.PARAM: PI=3.1416
- 113
-
PSPICE Simulation Files
.FUNC ESR(L,QL,FQ) {2*PI*FQ*L/QL}
Ri LSI 101 {ESR(L,QL,FQ)}
LI 101 LSO {L} IC={IC}
;SERIES RESISTANCE
;SERIES INDUCTANCE
.ENDS LQS
*MODEL: LCHOKE
*
* APPLICATION: SIMPLE MODEL THE CHOKE INDUCTOR IN WHICH *
*
THE DC RESISTANCE (RDC) AND THE AC
*
RESISTANCE ARE SPECIFIED, THE AC RES.
*
*
*
IS SPECIFIED BY ITS Q AT A GIVEN FREQUENCY*
*PARAMETERS:
*
*L
INDUCTANCE
*QL
: QUALITY FACTOR
*FQ
: FREQUENCY AT WHICH THE INDUCTOR
*RDC
: DC RESISTANCE
*IC
: INITIAL CONDITION
*
***** *************
*********
*NODES:
* LSI: INDUCTOR INPUT
* LSO: INDUCTOR OUTPUT
** **********
Q
IS SPECIFIED
*******
****
*
*
*
*
***
*
*
*
.SUBCKT LCHOKE LSI LSO
PARAMS:
L=1U
+
+
+
+
+
+
QL=300
FQ=60MEG
RDC=1M
IC=O
.PARAM:
+ PI=3.1416
+ OMEGA-={2*PI*FQ/100}
.FUNC ESR(L,QL,FQ) {2*PI*FQ*L/QL}
*DC RESISTANCE AND BYPASS CAPACITOR
RDC LSI 101 {RDC}
;DC RESISTANCE
CBP LSI 101 {i/(RDC*OMEGAO)} IC={IC};BYPASS CAP
*AC RESISTANCE AND BYPASS INDUCTOR
RAC 101 102 {ESR(L,QL,FQ)}
;AC RESISTANCE
LBP 101 102 {ESR(L,QL,FQ)/OMEGA-0} IC={IC}
Li 102 LSO
;CHOKE INDUCTANCE
{L} IC={IC}
.ENDS LCHOKE
*MODEL: CQS
* APPLICATION: SIMPLE MODEL OF CAPACITOR WHICH INCLUDES
*
AN EQUIVALENT SERIES RESISTANCE THAT IS
*
*
DESCRIBED IN TERMS OF THE "Q" AT A GIVEN
*
FREQUENCY
*
*
*PARAMETERS:
*C
*QC
*
: CAPACITANCE
: Q OF THE CAPACITOR AT A GIVEN FREQUENCY
-- 114 -
*
*
A.2
FREQUENCY AT WHICH THE Q IS EVALUATED
INITIAL CONDITION *
*FQ
*IC
*NODES:
* CSP: CAPACITOR POSITIVE TERMINAL
* CSN: CAPACITOR NEGATIVE TERMINAL
*
*
*
*
.SUBCKT CQS CSP CSN
+ PARAMS:
+ C=1U
+ QC=10K
+
FQ=60MEG
+ IC=0
.PARAM PI=3.1416
.FUNC ESR(C,QC,FQ) {1/(2*PI*FQ*C*QC)}
C1 CSP 101 {C} IC={IC}
R1 101 CSN {ESR(C,QC,FQ)}
;SERIES RESISTANCE
;SERIES CAPACITANCE
.ENDS CQS
*
MODEL: MOS1CGRGNOLQNLC
*
* APPLICATION: LD MOSFET TO BE USED IN CLASS E
*
CONVERTER -_WITHOUT-_ AN ANTIPARALLEL DIODE
*
*
*
*
__WITHOUT REAL MOSFET MODEL (IDEAL SWITCH USED INSTEAD)*
*
_WITH__ GATE CAPACITANCE
*
_WITHOUT__ PACKAGING INDUCTANCE LQ
*
GATE RESISTANCE
__WITH.
*
-WITH-_ NONLINEAR OUTPUT CAPACITANCE MODELED
THE MODEL IS SIMILAR TO THE ONE USED IN THE HEPA PLUS *
WHICH MODELS THE ON RESISTANCE, THE SERIES INDUCTANCE *
AND THE PARALLEL CAPACITANCE AND RESISTANCE OF THE
*
*
*
*
*
*
*
*
*
*
*
*
MOSFET
*
THIS MODEL IS FOR SIMULATING USE OF LDMOSFETS, WHICH
DO NOT HAVE AN ANTIPARALLEL DIODE
THIS MODEL ALSO INCLUDES THE DRIVER SO ANY VOLTAGE
REFERENCED TO GROUND CAN BE USED TO DRIVE IT
*
*
*
*
PARAMETERS: (DEFAULT VALUES ARE FOR MACOM MAPLST0810-030CF)
*RON : On resistance of the switch (3m Ohms) Default
*COUT: MOSFET OUTPUT CAPACITANCE (LINEAR CAPACITANCE)
*RCOUT: SERIES RESISTANCE ASSOCIATE WITH RCOUT
*REMOVED LQ: SERES INDUCTANCE ASSOCIATED WITH PACKAGING
*VO: SATURATION VOLTAGE (IN MOSFETS VO=0)
*RG:
GATE RESISTANCE (DEFAULT 0.3 OHM)
*CG:
GATE CAPACITANCE (DEFAULT 62.494P)
*CJO: ZERO VOLTAGE OUTPUT CAPACITANCE (CISS 0 VDS = 0)
*
*VJ: JUNCTION VOLTAGE (FOUND FROM SOLVING CISS AS FUNC(VDS) EQUATION)
*M: EXPONENT IN CISS AS A FUNC OF VDS EQUATION
*
*
* NODES:
* GATE:
* DRAIN:
*
*
*
*
*
SOURCE:
GATE TERMINAL OF THE MOSFET
DRAIN TERMINAL OF THE MOSFET
SOURCE TERMINAL OF THE MOSFET
*
*
*
*
*
.subckt MOS1CGRG-NOLQNLC GATE DRAIN SOURCE
+ PARAMS:
+
*
*
*
*
RON=0.290
- 115 -
Library File
PSPICE Simulation Files
+
RCOUT=O.2
+ VO=0
+ RG=0.3
+ CG=62.494P
+ CJO=85.915P
+
+
VJ=0.3335
M=0.2167
SW
DSW
RDSON
VSWON
DRAIN
101
102
103
101
102
103
SOURCE
GATE2
DIDEAL
{RON}
{VO}
0
SWIDEAL
;ON RESISTANCE
;SATURATION vOLTAGE
*NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT SOURCE
GCNL N101 DRAIN VALUE=IF((V(DRAIN)-V(NI01))<0,CJO*V(201)*(1/LDER),V(201)*(i/LDER)*(CJO/((+((V(DRAIN)
-V(N101))/VJ))^M)))}
; THIS LINE MUST BE MOVED UP TO THE PREVIOUS LINE FOR PROPER OPERATION
{COUT}
;OUTPUT CAPACITANCE
*COUTL
DRAIN
105
RSCOUT
N101
SOURCE
{RCOUT} ;CAPACITOR SERIES RESISTANCE
RGATE GATE GATE2 {RG}
RBIG GATE2
0
100E3
CGATE GATE2
0 {CG} ; GATE CAPACITANCE
.MODEL DIDEAL D (N=0.001)
.MODEL SWIDEAL VSWITCH (RON=IU ROFF=1E+7 VON=0.9 VOFF=0.1)
****SUBCIRCUIT TO EVALUATE THE DERIVATIVE***
*PARAMETERS AND DEFINITION FOR THIS SUBCIRCUIT
.PARAM:
+ LDER=1U
;INDUCT FOR THE DERIVATIVE SUBCIRCUIT
+ PI=3.1416
*FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT
.FUNC RDER(LDER,FS) {1000*2*PI*FS*LDER}
GY 0 201 VALUE={V(N101)-V(DRAIN)}
Li 201 0 {LDER}
R1 201 0 {RDER(LDER,FS)}
.ENDS MOS1CGRGNOLQNLC
*
MODEL: MOS1CGRGNLC
*
*
* APPLICATION: LD MOSFET TO BE USED IN CLASS E
*
*
CONVERTER -_WITHOUT__ AN ANTIPARALLEL DIODE
*
*
_WITHOUT REAL MOSFET MODEL (IDEAL SWITCH USED INSTEAD)
_WITH_- GATE CAPACITANCE
*
*
*
*
_WITH-- PACKAGING INDUCTANCE LQ
*
_WITH__ GATE RESISTANCE
*
*
*
WITH-- NONLINEAR OUTPUT CAPACITANCE MODELED
THE MODEL IS SIMILAR TO THE ONE USED IN THE HEPA PLUS
*
*
WHICH MODELS THE ON RESISTANCE, THE SERIES INDUCTANCE
*
AND THE PARALLEL CAPACITANCE AND RESISTANCE OF THE
*
MOSFET
THIS MODEL IS FOR SIMULATING USE OF LDMOSFETS, WHICH
DO NOT HAVE AN ANTIPARALLEL DIODE
*
THIS MODEL ALSO INCLUDES THE DRIVER SO ANY VOLTAGE
* REFERENCED TO GROUND CAN BE USED TO DRIVE IT
*
*
*
*
PARAMETERS: (DEFAULT VALUES ARE FOR MACOM MAPLST0810-030CF)
*RON : On resistance of the switch (3m Ohms) Default
*COUT: MOSFET OUTPUT CAPACITANCE (LINEAR CAPACITANCE)
*
116
*
*
*
*
-
*
*
-
*
*
*
A.2
Library File
*RCOUT: SERIES RESISTANCE ASSOCIATE WITH RCOUT
*
*LQ: SERES INDUCTANCE ASSOCIATED WITH PACKAGING
*
*VO: SATURATION VOLTAGE (IN MOSFETS VO=O)
*
*RG:
GATE RESISTANCE (DEFAULT 0.3 OHM)
*
*CG:
GATE CAPACITANCE (DEFAULT 30P)
*
*CJO: ZERO VOLTAGE OUTPUT CAPACITANCE (CISS C VDS = 0)
*
*VJ: JUNCTION VOLTAGE (FOUND FROM SOLVING CISS AS FUNC(VDS) EQUATION) *
*M: EXPONENT IN CISS AS A FUNC OF VDS EQUATION
*
*
*
*
*
NODES:
GATE:
DRAIN:
SOURCE:
*
*
*
*
GATE TERMINAL OF THE MOSFET
DRAIN TERMINAL OF THE MOSFET
SOURCE TERMINAL OF THE MOSFET
.subckt MOS1CGRGNLC GATE DRAIN SOURCE
PARAMS:
RON=0.290
RCOUT=0.2
LQ=2.84N
VO=0
RG=0.3
CG=62.494P
CJO=85.915P
VJ=0.3335
M=0.2167
+
+
+
+
+
+
+
+
+
+
SW
DSW
RDSON
VSWON
DRAIN
101
102
103
101
102
103
104
GATE2
0
SWIDEAL
DIDEAL
{RON}
;ON RESISTANCE
{VO}
;SATURATION vOLTAGE
SWTEST 110 0 GATE2 0 SWIDEAL
VSWTEST 111 0 10
RSWTEST 111 110 100
*NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT SOURCE
GCNL N101 DRAIN VALUE={IF((V(DRAIN)-V(N101))<O,CJO*V(201)*(1/LDER),V(201)*(1/LDER)*(CJO/((1+((V(DRAIN)
-V(N1O1))/VJ))^M)))} ;THIS LINE MUST BE MOVED UP TO THE PREVIOUS LINE FOR PROPER OPERATION
DRAIN
*COUTL
105
{COUT} ;OUTPUT CAPACITANCE
RSCOUT N101
104
{RCOUT} ;CAPACITOR SERIES RESISTANCE
LPACK 104 SOURCE
{LQ}
; PACKAGING INDUCTANCE
RGATE GATE GATE2 {RG}
RBIG GATE2
0
100E3
CGATE GATE2
0 {CG} ; GATE CAPACITANCE
.MODEL DIDEAL D (N=0.001)
.MODEL SWIDEAL VSWITCH (RON=1U ROFF=1E+7 VON=0.9 VOFF=0.1)
****SUBCIRCUIT TO EVALUATE THE DERIVATIVE***
*PARAMETERS AND DEFINITION FOR THIS SUBCIRCUIT
.PARAM:
+ LDER=1U
INDUCT FOR THE DERIVATIVE SUBCIRCUIT
+ PI=3.1416
*FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT
.FUNC RDER(LDER,FS) {1000*2*PI*FS*LDER}
GY 0 201 VALUE={V(N101)-V(DRAIN)}
Ll 201 0 {LDER}
-
117
--
PSPICE Simulation Files
R1 201 0 {RDER(LDER,FS)}
.ENDS MOS1CGRGNLC
* MODEL: MOS1CGRGNLC-NORCOSS
*
* APPLICATION: LD MOSFET TO BE USED IN CLASS E
*
* CONVERTER -- WITHOUT_- AN ANTIPARALLEL DIODE
REAL MOSFET MODEL (IDEAL SWITCH USED INSTEAD) *
* -WITHOUT
*
_WITH__ GATE CAPACITANCE
*
*
* __WITHOUT-_ PACKAGING INDUCTANCE LQ
*
_WITH__ GATE RESISTANCE
*
NONLINEAR OUTPUT CAPACITANCE MODELED
*
* -WITH__
* -- WITHOUT-_ RESISTANCE RCOUT IN SERIES W/ NON-LINEAR COSS*
*
THE MODEL IS SIMILAR TO THE ONE USED IN THE HEPA PLUS
*
WHICH MODELS THE ON RESISTANCE, THE SERIES INDUCTANCE
*
AND THE PARALLEL CAPACITANCE AND RESISTANCE OF THE
*
MOSFET
* THIS MODEL IS FOR SIMULATING USE OF LDMOSFETS, WHICH
*
DO NOT HAVE AN ANTIPARALLEL DIODE
*
* THIS MODEL ALSO INCLUDES THE DRIVER SO ANY VOLTAGE
* REFERENCED TO GROUND CAN BE USED TO DRIVE IT
*
*
*
*
*
*
*
*
*
* PARAMETERS: (DEFAULT VALUES ARE FOR MACOM MAPLST0810-030CF)
*RON : On resistance of the switch (3m Ohms) Default
*
*COUT: MOSFET OUTPUT CAPACITANCE (LINEAR CAPACITANCE)
*
*RCOUT: SERIES RESISTANCE ASSOCIATE WITH RCOUT
*
*LQ: SERES INDUCTANCE ASSOCIATED WITH PACKAGING
*
*VO: SATURATION VOLTAGE (IN MOSFETS VO=0)
*
*
GATE RESISTANCE (DEFAULT 0.3 OHM)
*RG:
*CG:
GATE CAPACITANCE (DEFAULT 30P)
*
*CJO: ZERO VOLTAGE OUTPUT CAPACITANCE (CISS 0 VDS = 0)
*
*VJ: JUNCTION VOLTAGE (FOUND FROM SOLVING CISS AS FUNC(VDS) EQUATION) *
*M: EXPONENT IN CISS AS A FUNC OF VDS EQUATION
*
*
*
*
*
*
*
*
*
NODES:
GATE:
DRAIN:
SOURCE:
GATE TERMINAL OF THE MOSFET
DRAIN TERMINAL OF THE MOSFET
SOURCE TERMINAL OF THE MOSFET
.subckt MOS1CGRGNLCNORCOSS GATE DRAIN SOURCE
+ PARAMS:
+ RON=0.290
*+ RCOUT=0.2
*+ LQ=2.84N
+ VO=0
+ RG=0.3
+ CG=62.494P
+ CJO=85.915P
+ VJ=0.3335
+ M=0.2167
SW
DSW
RDSON
VSWON
DRAIN
101
102
103
101
102
103
SOURCE
GATE2
DIDEAL
{RON}
{VO}
0
SWIDEAL
;ON RESISTANCE
;SATURATION vOLTAGE
SWTEST 110 0 GATE2 0 SWIDEAL
VSWTEST 111 0 10
RSWTEST 111 110 100
*NONLINEAR CAPACITANCE EVALUATED AS A CONTROLLED CURRENT SOURCE
-
118
-
A .3
Inverter Measurement Code
GCNL SOURCE DRAIN VALUE={IF((V(DRAIN)-V(SOURCE))<O,CJO*V(201)*(1/LDER),V(201)*(1/LDER)*(CJO/((1+((V(DRAIN)
-V(SOURCE))/VJ))^M)))} ;THIS LINE MUST BE MOVED UP TO THE PREVIOUS LINE FOR PROPER OPERATION
DRAIN
105
{COUT} ;OUTPUT CAPACITANCE
* COUTL
* RSCOUT
N101
104 {RCOUT} ;CAPACITOR SERIES RESISTANCE HAS BEEN REMOVED
* LPACK 104 SOURCE {LQ} ; PACKAGING INDUCTANCE HAS BEEN REMOVED
RGATE GATE GATE2 {RG}
RBIG GATE2
0
100E3
0 {CG} ; GATE CAPACITANCE
CGATE GATE2
.MODEL DIDEAL D (N=0.001)
.MODEL SWIDEAL VSWITCH (RON=1U ROFF=1E+7 VON=0.9 VOFF=0.1)
****SUBCIRCUIT TO EVALUATE THE DERIVATIVE***
*PARAMETERS AND DEFINITION FOR THIS SUBCIRCUIT
.PARAM:
+ LDER=1U
;INDUCT FOR THE DERIVATIVE SUBCIRCUIT
+ PI=3.1416
*FUNC. FOR R OF THE DERIVATIVE SUBCIRCUIT
.FUNC RDER(LDER,FS) {1000*2*PI*FS*LDER}
GY 0 201 VALUE={V(SOURCE)-V(DRAIN)}
Li 201 0 {LDER}
R1 201 0 {RDER(LDER,FS)}
. ENDS MOS1CGRG.NLCNORCOSS
A.3
Inverter Measurement Code
Shown here is a measurement circuit that must be included in each of the simulation files
for proper operation. Each simulation file indicates where the measurement code must be
inserted.
* MEASURMENT CIRCUITS *
METHOD FOR CONVERTING OPERATING FREQUENCY FS TO VOLTAGE FOR
VFS FS 0 {FS}
RFS FS 0 1E15
***
.FUNC LORC(FS) {100/(2*PI*FS)}
* OUTPUT
EPO P001
LPO P001
CPO POUT
RPO POUT
FUNCTION THAT PLACES THE FILTER
COMPONENT OF THE MEASURMENT
CIRCUITS TWO DECADES BEFORE THE
SWITCHING FREQUENCY
POWER MEASUREMENT
0 VALUE={V(RES2)*I(VDRLOAD)}
POUT {LORC(FS)}
0
{LORC(FS)}
0
1
OUTPUT POWER
* VIN SOURCE POWER MEASUREMENT
EPI
LPI
CPI
RPI
.PRINT
PI01 0 VALUE={V(IN)*(-I(VIN))}
PI01 PIN {LORC(FS)}
PIN 0
{LORC(FS)}
PIN 0
1
VIN SOURCE INPUT POWER
-
119
-
COMMAND
PSPICE Simulation Files
* VGATE SOURCE POWER MEASUREMENT
EPI2
LPI2
CPI2
RPI2
PI02
PI02
PIN2
PIN2
0 VALUE={V(GATE)*(-I(Vswitch))}
PIN2 {LORC(FS)}
0 {LORC(FS)}
0 1
GATE INPUT POWER
* SUM VIN AND VGATE INPUT POWERS
EPI3 PINTOT PIN3 PIN 0 1
EPI4 PIN3 0 PIN2 0 1
TOTAL INPUT POWER
RPITOT PINTOT 0 1
* EFFICIENCY MEASUREMENT
EEF EFF 0 VALUE=IF(V(PINTOT)<=1,0,V(POUT)/V(PINTOT))}
; EFFICIENCY
REF EFF 0 1
*
WHEN USING THE ABOVE CODE, PLOT V(EFF) FOR EFFICIENCY, V(POUT) FOR OUTPUT POWER,
* V(PINTOT) FOR INPUT POWER INCLUDING GATE DRIVE POWER, PLOT V(FS) FOR FREQUENCY
A.4
Comparison of Higher Coss vs. Added CEXTRA in the
Inverter
This section contains the PSPICE circuit file used to demonstrate that adding CEXTRA
(second circuit definition) causes less peaking of VDS than increased Coss (first circuit
definition). To make the comparison equitable, both circuits have the same output power
and efficiency, as stated in chapter 3.3.1, which also describes the results of this simulation.
* FIRST CIRCUIT HAS:
CJO HIGHER BY 20PF (TO PRODUCE HIGHER COSS)
THAN ACTUAL DEVICE (FREESCALE MRF373ALSR1)
NO CEXTRA
*
NO RSCOSS IN SERIES WITH COSS
*
NO PACKAGE INDUCTANCE (LQ)
*
* SECOND CIRCUIT HAS: SAME CJO AS ACTUAL DEVICE
CEXTRA (INFINITE Q) SET TO PRODUCE SAME
*
OUTPUT POWER AS FIRST CIRCUIT
*
NO RSCOSS IN SERIES WITH COSS
*
NO PACKAGE INDUCTANCE (LQ)
* BOTH CIRCUITS:
RUN AT VIN=16V, FS=100MHz
*
* FIRST CIRCUIT:
* REQUIRED LIBRARY FILE:
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
* OPTIONS FOR AVOIDING CONVERGENCE PROBLEMS:
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400
+ RELTOL=0.002 VNTOL=0.01MV
.OPTION STEPGMIN
* OPTIONS FOR OUTPUT FILE FORMATTING:
.OPTION NOPAGE NOBIAS NOECHO NOMOD NUMDGT=6
.WIDTH OUT=132
* GLOBAL CIRCUIT PARAMETERS:
.PARAM
-
120
-
*
*
*
*
*
*
*
*
*
*
A.4
Comparison of Higher Coss vs. Added
CEXTRA
+ PI=3.14159
+ FS=100MEG
+ CDS=72.39013E-12
THIS IS COSS 0 11V CALCULATED W/ CJO=
161.13PF+20PF, INSTEAD OF ACTUAL CJO=
64.396966E-12, WHICH GIVES COSS011V W/
CJO=161.13PF
* AUTOMATIC CALCULATION OF RLOAD, CRES, AND LRES BASED UPON FS
.FUNC
.FUNC
.FUNC
.FUNC
WS(FS) {FS*2*PI}
LOAD(WS,CDS) {O.2150/(WS*CDS)}
CR(WS,LOAD) {O.4166/(WS*LOAD)}
LR(WS,LOAD) {3.750*LOAD/WS}
CALCULATE
CALCULATE
CALCULATE
CALCULATE
WS (RADIANS/SEC)
RLOAD
CR
LR
* INPUT VOLTAGE SOURCE:
.PARAM VIN=16
VIN IN 0 DC {VIN}
* CHOKE INDUCTOR:
XLCHOKE IN DRAIN LCHOKE PARAMS: L=538n QL=104 FQ=50MEG RDC=90M
* MOSFET FREESCALE MRF373ALSR1:
XMOS GATE DRAIN 0 MOS1CGRGNLCNORCOSS PARAMS: RON=0.160 VO=O RG=0.27 CG=109.68P
+ CJO=181.13P
; THIS IS THE ACTUAL CJO (161.13PF) PLUS 20PF
+ VJ=0.69152 M=0.32434
* RESONANT TANK INDUCTOR:
XLR DRAIN RES1 LQS PARAMS: L=LRES(LR(WS(FS),LOAD(WS(FS),CDS)))} QL=125 FQ=150MEG
* RESONANT TANK CAPACITOR:
XCR RES1 RES2 CQS PARAMS: C={CR(WS(FS),LOAD(WS(FS),CDS))} QC=3000 FQ=160MEG
* LOAD RESISTANCE:
RLOAD RES2 DRLOAD {LOAD(WS(FS),CDS(CSW))}
* DUMMY VOLTAGE SOURCE FOR MEASURING LOAD CURRENT:
VDRLOAD DRLOAD 0 0
* SINUSOIDAL LDMOS DRIVE VOLTAGE:
VSWITCH GATE 0 SIN(OV 18V {FS} 0 0 0)
*** INSERT MEASURMENT CIRCUIT HERE ***
* ANALYSIS AND OUTPUT COMMANDS:
.tran 0.02N 3U 2.97U 0.02N
.PRINT TRAN V([POUTJ) V([PINTOTI) V([EFF)
.PROBE
.END
; END OF FIRST CIRCUIT
*
SECOND CIRCUIT:
* REQUIRED LIBRARY FILE:
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
* OPTIONS FOR AVOIDING CONVERGENCE PROBLEMS:
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400
+ RELTOL=0.002 VNTOL=0.01MV
.OPTION STEPGMIN
* OPTIONS FOR OUTPUT FILE FORMATTING:
.OPTION NOPAGE NOBIAS NOECHO NOMOD NUMDGT=6
.WIDTH OUT=132
* GLOBAL CIRCUIT PARAMETERS:
- 121 -
in the Inverter
PSPICE Simulation Files
.PARAM
+ PI=3.14159
+ FS=100MEG
+ CSW=64.396966E-12
THIS IS COSS 0 11V CALCULATED W/ CJO=
161.13PF (ACTUAL MEASURED VALUE OF
MRF373ALSR1 DEVICE)
VARIABLE PARAMETER
+ CEXTRA=9.6P
.STEP PARAM CEXTRA 9.62P 9.65P .01P
STEP CEXTRA TO FIND VALUE
FOR WHICH OUTPUT POWER
OF CIRCUITS 1 AND 2 IS EQUAL
.FUNC CDS(CSW) {CSW+CEXTRA}
* AUTOMATIC DETERMINAION OF RLOAD, CRES, AND LRES BASED UPON FREQUENCY
* USE TOTAL DRAIN TO SOURCE CAPACITANCE CDS
.FUNC WS(FS) {FS*2*PI}
CALCULATE WS (RADIANS/SEC)
.FUNC LOAD(WS,CDS) {O.2150/(WS*CDS)}
CALCULATE RLOAD
CALCULATE CR
.FUNC CR(WS,LOAD) {0.4166/(WS*LOAD)}
CALCULATE LR
.FUNC LR(WS,LOAD) {3.750*LOAD/WS}
* INPUT VOLTAGE SOURCE:
.PARAM VIN=16
VIN IN 0 DC {VIN}
* CHOKE INDUCTOR
XLCHOKE IN DRAIN LCHOKE PARAMS: L=538n QL=104 FQ=50MEG RDC=90M
*MOSFET FREESCALE MRF373ALSR1
XMOS GATE DRAIN 0 MOS1CGRGNLCNORCOSS PARAMS: RON=0.160 VO=0 RG=0.27 CG=109.68P
+ CJO=161.13P
; THIS IS THE ACTUAL VALUE OF CJO
+ VJ=0.69152 M=0.32434
CEXTRA DRAIN 0 {CEXTRA}
* RESONANT INDUCTOR:
XLR DRAIN RESI LQS PARAMS: L={LRES(LR(WS(FS),LOAD(WS(FS),CDS(CSW))))} QL=125 FQ=150MEG
* RESONANT CAPACITOR:
XCR RESI RES2 CQS PARAMS: C={CR(WS(FS),LOAD(WS(FS),CDS(CSW)))} QC=3000 FQ=160MEG
* LOAD RESISTANCE:
RLOAD RES2 DRLOAD {LOAD(WS(FS),CDS(CSW))}
* DUMMY VOLTAGE SOURCE FOR MEASURING LOAD CURRENT:
VDRLOAD
DRLOAD 0 0
* SINUSOIDAL LDMOS DRIVE VOLTAGE
VSWITCH GATE 0 SIN(OV 18V {FS} 0 0 0)
***
INSERT MEASURMENT CIRCUIT HERE ***
* ANALYSIS AND OUTPUT COMMANDS:
.tran 0.02N 3U 2.97U 0.02N
.PRINT TRAN V([POUT]) V([PINTOT]) V([EFF])
.PROBE
; END OF SECOND CIRCUIT
.END
- 122
-
A. 5
A.5
Comparison of Four Devices Using Datasheet Information
Comparison of Four Devices Using Datasheet Information
Shown below is the file used to simulate the Agere AGR09080GUM, the M/A-COM MAPLST0810030CF, the Freescale MRF373ALSR1, and the ST PD57018. To use this file for a given
device, commenting must be removed from certain lines as indicated.
* Class E, 16V supply, 100-240MHz with any one of the following devices:
*
AGERE switch AGR09080GUM (DATA SHEET GIVES COSS ONLY AT 28 VOLTS)
*
MACOM switch MAPLST0810-030CF (Cout=32pF 026V) DATA SHEET GIVES COSS ONLY AT 26 VOLTS
*
FREESCALE switch MRF373ALSR1
*
ST switch PD57018
* USE MODEL MOSiCGNOLQRG WHICH CONTAINS NO PACKAGE INDUCTANCE
* NO EXTRA PARALLEL CAPACITANCE ADDED TO THIS SET OF CIRCUITS.
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400 RELTOL=0.002 VNTOL=0.01MV
.OPTION STEPGMIN NOPAGE NOBIAS NOECHO NOMOD NUMDGT=5
.WIDTH OUT=132
.PARAM PI=3.14159 FS=100MEG
* Uncomment one of the following for the listed device:
*+ CDS=15.7P
Uncomment for use with AGERE AGR09080GUM
*+ CDS=32P
Uncomment for use with MACOM MAPLST0810-030CF
*+ CDS=50P
Uncomment for use with FREESCALE MRF373ALSR1
*+ CDS=21P : Uncomment for use with ST switch PD57018
.FUNC WS(FS) {FS*2*PI}
.FUNC LOAD(WS,CDS) {0.2150/(WS*CDS)}
.FUNC CR(WS,LOAD) {0.4166/(WS*LOAD)}
.FUNC LR(WS,LOAD) {3.750*LOAD/WS};
VIN IN 0 DC 16
.STEP PARAM FS 100MEG 240MEG 20MEG
XLCHOKE IN DRAIN LCHOKE
+ PARAMS:
+ L=538n
+ QL=104
+ FQ=50MEG
+ RDC=90M
* Uncomment only one of the following XMOS devices:
**MOSFET FOR AGERE PART AGR09030GUM (15.7pF)
*XMOS GATE DRAIN 0 MOS1_CGNOLQRG PARAMS:
*+ RON=0.25
;SPEC'D FOR AGERE
*+ COUT=15.7P
;SPEC'D FOR AGERE
*+ RCOUT=.3
;APPROX FOR LDMOS DEVICES
*+ VO=0
;FOR ALL MOSFETS
*+ RG=0.3
;APPROX FOR LDMOS DEVICES
*+ CG=56P
;SPEC'D FOR AGERE
**MOSFET FOR MACOM PART MAPLST0810-030CF (Cout=32pF)
*XMOS GATE DRAIN 0 MOS1CG_NOLQ-RG PARAMS:
*+ RON=0.2
;SPEC'D FOR MACOM
*+ COUT=32P
;SPEC'D FOR MACOM
*+ RCOUT=.3
;SET EQUAL FOR BOTH ST PART AND MACOM PART
*+ VO=0
;FOR ALL MOSFETS
*+ RG=0.3
;MEASURED FOR MACOM (APPROX)
*+ CG=50P
;SPEC'D FOR MACOM
**MOSFET FOR FREESCALE PART MRF373ALSR1
*XMOS GATE DRAIN 0 MOS1CGNOLQRG PARAMS:
- 123
-
PSPICE Simulation Files
;SPEC'D FOR FREESCALE
*+ RON=0.16
;SPEC'D FOR FREESCALE AT 27 VOLTS (FROM GRAPH)
*+ COUT=50P
;APPROX FOR LDMOS DEVICES
*+ RCOUT=.3
;FOR ALL MOSFETS
*+ VO=0
;APPROX FOR LDMOS DEVICES
*+ RG=0.3
;SPEC'D FOR FREESCALE AT 27 VOLTS (FROM GRAPH)
*+ CG=99P
**MOSFET FOR ST PART PD57018
*XMOS GATE DRAIN 0 MOS1-CGNOLQRG PARAMS:
;SPEC'D FOR ST
*+ RON=0.72
;SPEC'D FOR ST AT 28 VOLTS
*+ COUT=21P
;APPROX FOR LDMOS DEVICES
*+ RCOUT=.3
;FOR ALL MOSFETS
*+ VO=0
*+ RG=0.3
;APPROX FOR LDMOS DEVICES
*+ CG=34.5P
;SPEC'D FOR ST AT 28 VOLTS
XLR DRAIN RESI LQS
+ PARAMS:
+ L={LR(WS(FS),LOAD(WS(FS),CDS))}
+ QL=120
+ FQ=150MEG
XCR RES1 RES2 CQS
+ PARAMS:
+ C={CR(WS(FS),LOAD(WS(FS),CDS))}
+ QC=3000
+ FQ=100MEG
RLOAD RES2 DRLOAD {LOAD(WS(FS),CDS)}
VDRLOAD DRLOAD 0 0
; DUMMY VOLTAGE SOURCE FOR MEASURING LOAD CURRENT
Vswitch GATE 0 sin(OV 18V {FS} 0 0 0)
***
INSERT MEASUREMENT CIRCUIT HERE ***
*.tran 0.1N 2U 1.97U 0.1N ; FOR TIME DOMAIN VIEW
.TRAN 3U 3U 1N 0.1N
; FOR PUTTING ONLY THE FINAL TIME STEP IN THE OUTPUT FILE
.PRINT TRAN V([FSI) V([POUT)) V([PIN) V([PIN2]) V([PINTOT]) V([EFF])
.PROBE
.END
A.6
Comparison of M/A-COM and Freescale Devices Using
Measured Data
Shown below are the two PSPICE files used to compare the M/A-COM MAPLST0810-
030CF and the Freescale MRF373ALSR1 based upon ac and dc measurements shown in
appendix D. Note that package inductance is not modelled for either part because its value
is not well known. Also note that 5.9pF of PCB parasitic drain-to-source capacitance is
included based upon the measurements in [1]. The new PCB has much lower capacitance,
as described in chapter 9.
-
124
-
A. 7
A.7
Comparison of MR and non-MR inverters
Comparison of MR and non-MR inverters
*The following is two separate simulation files in one
*First circuit: MRS CHOKE, CEXTRA=OpF
*Second circuit: Single-inductor CHOKE, CEXTRA=10pF
*Both circuits: 100MHz, w/ Freescale MRF373ALSR1
*FIRST CIRCUIT:
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400 RELTOL=0.002 VNTOL=0. OMV
.OPTION STEPGMIN
* GLOBAL CIRCUIT PARAMETERS:
.PARAM PI=3.14159 FS=100MEG CSW=64.396966E-12
*AUTOMATIC DETERMINAION OF RLOAD, CRES, AND LRES BASED UPON FREQUENCY:
.FUNC WS(FS) {FS*2*PI}
.PARAM RSUB=0.25
*.STEP PARAM RSUB 0.25 0.35 0.025
.FUNC LOAD(WS(FS)) {0.2150/(WS(FS)*CSW)-RSUB}
.FUNC CR(WS,LOAD) {0.4166/(WS*LOAD)-43P}
.FUNC LR(WS,LOAD) {3.750*LOAD/WS}
*NOTE: 2.84N of LDMOS lead inductance subtracted from LR for better class E waveforms
.FUNC LRES(LR) {LR-2.84N}
*CALCULATE MRS CHOKE VALUES:
;ORIGINALLY 64.366966P
.PARAM C1=90P
.FUNC L1(FS,PI) {1/(9*C1*PWR((PI*FS),2))}
.FUNC L3(FS,PI) {1/(15*C1*PWR((PI*FS),2))}
.FUNC C3(FS,PI) {15*C1/16}
*INDUCTOR Li IN THE MRS CIRCUIT:
XLCHOKE IN DRAIN LCHOKE PARAMS: L={L1(FS,PI)} QL=104 FQ=160MEG RDC=90M
*INDUCTOR L2 AND CAPACITOR C2 IN THE MRS CIRCUIT:
L33 IN CHOKEMRS1 {L3(FS,PI)}
C33 CHOKEMRS1 DRAIN {C3(FS,PI)}
*SUPPLY VOLTAGE:
VIN IN 0 DC 16
*MOSFET FOR FREESCALE SWITCH MRF373ALSR5 (64.396966PF 0 11V)
XMOS GATE DRAIN 0 MOS1CGRG-NLC PARAMS: RON=0.160 RCOUT=0.3 LQ=2.84N VO=0 RG=0.27
+ CG=109.68P CJO=161.13P VJ=0.69152 M=0.32434
;PARASITIC (BOARD) CAPACITANCE, DRAIN TO SOURCE.
CPDS DRAIN CPDS1 5.9P
RPDS CPDS1 0 5.3343
*CEXTRA DRAIN 0 {CEXTRA}
VITEST TP1 0 0
XLR DRAIN RES1 LQS
+ PARAMS:
+ L={LRES(LR(WS(FS),LOAD(WS(FS))))}
+ QL=125
+ FQ=150MEG
XCR RES1 RES2 CQS
+ PARAMS:
+ C={CR(WS(FS),LOAD(WS(FS)))}
+ QC=3000
+ FQ=160MEG
RLOAD RES2 DRLOAD {LOAD(WS(FS))}
- 125
-
PSPICE Simulation Files
VDRLOAD DRLOAD 0 0
DUMMY VOLTAGE SOURCE FOR MEASURING LOAD CURRENT
.PARAM IOS=-3
Vswitch GATE 0 sin({IOS} 18V {FS} 0 0 0)
*** INSERT MEASUREMENT CIRCUIT HERE FOR PROPER OPERATION***
.tran 0.02N 3U OU 0.02N
.PRINT TRAN V([DRAINJ) V(XMOS.104) I(XMOS.RDSON) I(XMOS.GCNL)
.PROBE ; PLOT V(EFF), V(POUT), V(PINTOT). VDS INTERNAL=V(DRAIN)-V(XMOS.104)
.END
*SECOND CIRCUIT
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400 RELTOL=0.002 VNTOL=O.O1MV
.OPTION STEPGMIN
* GLOBAL CIRCUIT PARAMETERS:
.PARAM PI=3.14159 FS=100MEG CSW=64.396966E-12 CEXTRA=10P
.FUNC CDS(CSW) {CSW+CEXTRA}
*AUTOMATIC DETERMINAION OF RLOAD, CRES, AND LRES BASED UPON FREQUENCY:
.FUNC WS(FS) {FS*2*PI}
.FUNC LOAD(WS,CDS) {O.2150/(WS*CDS)}
.FUNC CR(WS,LOAD) {O.4166/(WS*LOAD)}
.FUNC LR(WS,LOAD) {3.750*LOAD/WS};
*NOTE: 2.84N of LDMOS lead inductance subtracted from LR for better class E waveforms
.FUNC LRES(LR) {LR-2.84N}
VIN IN 0 DC 16
XLCHOKE IN DRAIN LCHOKE PARAMS: L=538n QL=104 FQ=50MEG RDC=90M
*MOSFET FOR FREESCALE SWITCH MRF373ALSR5 (64.396966PF 0 11V)
XMOS GATE DRAIN 0 MOS1CGRGNLC PARAMS: RON=0.160 RCOUT=0.3 LQ=2.84N VO=0
+ CG=109.68P CJO=161.13P VJ=0.69152 M=0.32434
CPDS DRAIN CPDS1 5.9P ;PARASITIC (BOARD) CAPACITANCE, DRAIN TO SOURCE.
RPDS CPDS1 0 5.3343
CEXTRA DRAIN MRS1 {CEXTRA}
LEXTRA MRS1 0 11.6945N
XLMRSi MRS1 0 LQS ; INDUCTOR IN SERIES W/ CEXTRA
+ PARAMS:
+ L=11.6945N
+ QL=130
+ FQ=100MEG
*VITEST TP1 0 0
XLR DRAIN RESI LQS
+ PARAMS:
+ L={LRES(LR(WS(FS),LOAD(WS(FS),CDS(CSW))))}
+ QL=125
+ FQ=150MEG
XCR RES1 RES2 CQS
+ PARAMS:
+ C={CR(WS(FS),LOAD(WS(FS),CDS(CSW)))}
+ QC=3000
+ FQ=160MEG
RLOAD RES2 DRLOAD {LOAD(WS(FS),CDS(CSW))}
VDRLOAD DRLOAD 0 0 ; DUMMY VOLTAGE SOURCE FOR MEASURING LOAD CURRENT
Vswitch GATE 0 sin(OV 18V {FS} 0 0 0)
- 126
RG=0.27
A.8
***
Gate Drive Simulations
INSERT MEASUREMENT CIRCUIT HERE FOR PROPER OPERATION***
.tran 0.02N 3U OU 0.02N
.PRINT TRAN V([DRAIN]) V(XMOS.104) I(XMOS.RDSON) I(XMOS.GCNL)
.PROBE
.END
A.8
Gate Drive Simulations
Shown below are the frequency and time domain simulations used to analyze the gate drive
circuit (without startup/shutdown circuitry). A command file (.cmd), used to plot the
appropriate curves in PROBE, is shown after some simulations.
The following is a frequency domain simulation of the gate drive, with MR and SO circuits,
including de blocking and bypass components:
*** CIRCUIT FILE FOR DESIGN OF SELF-OSCILLATING GATE ***
*** DRIVE INCLUDING DC BLOCKS AND MULTI-RES. STRUCTURE***
*** MADE BY: JUAN RIVAS AND DAVID JACKSON
.LIB "..\LIBS\CLASSE.LIB"
.PARAM
+ PI=3.1416
;SWITCHING FREQUENCY
+ FS=100MEG
+ RGATES=3
;GATE RESISTANCE
+ CGSS=30P
;GATE TO SOURCE CAPACITANCE
+ LT=84N
; STANDARD VALUE
*+ LT={1/(4*PI*PI*FS*FS*CGSS)} ; AUTOMATIC CALC.
+ LF=100N
;FEEDBACK INDUCTOR STANDARD VALUE
*+ CF={1/(4*PI*PI*FS*FS*LF)}
STANDARD VALUE
+ CF=47P
*+ RQDAMP=20k
;DAMPING RESISOR
+ RQDAMP=10MEG
.PARAM
+ LBLOCK=82N
+ CBLOCK=1N
*PARAMETERS FOR THE Q OF INDIVIDUAL COMPONENTS
.PARAM QLF=100 QLT=100 QCBLOCK=1K QLBLOCK=100
*CIRCUIT DESCRIPTION *
VCS1
****
DRAIN 0 AC 1
** **** **** **** **** *****
******
*COMPLETE STRUCTURE WITH DC BLOCKS*
VDUCS DRAIN C101 0
*FEEDBACK INDUCTOR
XLFC C101 C102X LQS PARAMS: L={LF} QL={QLF} FQ={FS} IC=0
*DAMPING RESISTOR
RDAMPC C101 C102X {RQDAMP}
*CAPACITOR DC BLOCK
XCBC C102X C102 CQS PARAMS: C={CBLOCK} QC={QCBLOCK} FQ={FS} IC=0
**FEEDBACK CAPACITOR
- 127
-
PSPICE Simulation Files
XCFC C102 0 CQS PARAMS: C={CF} QC=1k FQ={FS} IC=0
*FINDUCTOR DC BLOCK
XLBC C102 0 LQS PARAMS: L={LBLOCK} QL={QLBLOCK} FQ={FS} IC=0
**GATE INDUCTOR
*XLGC C102 C103 LQS PARAMS: L={LT} QL={QLT} FQ={FS} IC=0
;GATE RESISTANCE
*RGATEC C103 C104 {RGATES}
0
{CGSS}
;GATE TO SOURCE CAP
C104
*CGSC
*MULTI RESONANT STRUCTURE
ALONE
.PARAM:
LGLEAD=200P
CG=114P
;GATE CAP. OF MAIN MOSFET
RG=0.3
;GATE RES. OF MAIN MOSFET
CSW=48P
;DRAIN 2 SOURSCE SMALL FET
C1=2N
;DC BYPASS CAP CBP
RIN=50 C3=150.55P L1=8.0992N L3=4N
VDUMR DRAIN MR101 0 ;SOURCE FOR MEASURING INPUT CURRENT
XMRL1 MR101 MR101X LQS PARAMS: L={L1} QL=75 FQ={FS} IC=O
XMRC1 MR101X 0 CQS PARAMS: C={C1} QC=1k FQ={FS} IC=0
RIN MR101X 0 {RIN}
XMRC3 MR101 MR102 CQS PARAMS: C={C3} QC=1k FQ={FS} IC=0
XMRL3 MR102 mr101x LQS PARAMS: L={L3} QL=75 FQ={FS} IC=0
CMRSW MR101 0 {CSW}
;DRAIN 2 SOUCE CAP OF SMALL MOSFET
RMRG MR101 MR103x {RG} ;GATE RASISTANCE OF MAIN MOSFET
LMRG MR103X MR103 {LGLEAD}
{CG}
;GATE 2 SOURCE CAP OF MAIN MOSFET
CMRG MR103 0
+
+
+
+
+
+
.PRINT AC I(VDUCS) I(VDUMR) I(VCS1)
.AC DEC 1000 10MEG 10G
.PROBE
The appropriate .cmd file is:
Window New
Trace Add
-DB(I(VDUCS))
OK
Trace Add
-DB(I(VDUMR))
OK
Trace Add
-DB(-I(VCS1))
OK
The following is a time domain simulation of the gate drive, with MR and SO circuits,
including dc blocking and bypass components:
*** CIRCUIT FILE FOR TRANSIENT ANALYSIS OF THE
*** MULTIRESONANT GATE DRIVER
*** MADE BY: JUAN RIVAS AND DAVID JACKSON
.LIB "../LIBS/CLASSE.LIB" ;LIBRARY OF CLASSE COMPONEN.
* OPTIONS FOR AVOIDING CONVERGENCE PROBLEMS:
.OPTIONS ABSTOL=1nA GMIN=10p ITL1=6000 ITL2=4000 ITL4:=500 RELTOL=0.002 VNTOL=0.OlmV
- 128
-
A.8
Gate Drive Simulations
.OPTION STEPGMIN
* OUTPUT FILE FORMATTING:
.OPTIONS NOPAGE NOBIAS NOECHO NOMOD NUMDGT=8
.WIDTH OUT=132 TO PRINT MORE COLUMNS
.PARAM PI=3.1416 120MEG
+ VIN=5
;INPUT VOLTAGE
.PARAM
+ CG=109P
+ RG=0.3
+ CSW=30P
+ C1={CG+CSW}
+ C3={15*C1/16}
+ L1={1/(9*C1*PWR((PI*FS),2))}
+ L3={1/(15*C1*PWR((PI*FS),2))}
*CIRCUIT DESCRIPTION:
VIN N101 0 {VIN}
RIN NIO1 N102 .1M ;INPUT SOURCE SERIES RESISTANCE
XL1 N102 N103 LQS PARAMS: L={L1} QL=50 FQ={FS} IC=0
XC3 N102 NIOX CQS PARAMS: C={C3} QC=1200 FQ={FS} IC=0
XL3 NIOX N103 LQS PARAMS: L={L3} QL=50 FQ={FS} IC=0
*SWITCH AND GATE DRIVE:
N103 0 {CSW} IC=O
CSW
SIDEAL N103 0 GATE 0 SIDEAL
.MODEL SIDEAL VSWITCH(ROFF=10MEG RON=O.6 VOFF=2 VON=2.5)
*GATE OF MAIN MOSFET:
RGATE N103 N104 {RG}
CGATE N104 0
{CG} IC=O
* ****
************
** *****
** ****
******
*SELF OSCILATING SUBCIRCUIT STRUCTURE:
.PARAM: CGSSMALL=30P RGSMALL=1.5 LT=58N LF=40N CF={1/(4*PI*PI*FS*FS*LF)} RQDAMP=20k
VDUFLEG N103 INFED 0 ;DUMMY SOURCE TO MEASURE THE CURRENT IN THE SO FEEDBACK PATH
*FEEDBACK INDUCTOR:
XLF INFED BLOCKA LQS PARAMS: L={LF} QL=80 FQ={FS} IC=0
.PARAM LBLOCK=82N CBLOCK=1N
CBLOCK BLOCKA CLTAP {CBLOCK}
RDAMP INFED CLTAP {RQDAMP} ;DAMPING RESISTOR
*FEEDBACK CAPACITOR:
XCF CLTAP 0 CQS PARAMS: C={CF} QC=300 FQ={FS} IC=0
LBLOCK CLTAP 0 {LBLOCK}
*GATE OF THE LARGE MOSFET:
LT CLTAP INT {LT}
;SERIES INDUCTANCE
RGATESM INT GATE {RGSMALL}
;GATE RESISTANCE
;GATE TO SOURCE CAP
CGSSM GATE 0 {CGSSMALL}
*STARTUP CIRCUIT:
VSTART CLTAP2 0 PULSE(0 25 IOU ION)
SSTART CLTAP FIVEVOLT CLTAP2 0 SWITCHSTART
VFIVEVOLT FIVEVOLT 0 25
.MODEL SWITCHSTART VSWITCH [ROFF=1000MEG RON=.001 VOFF=O VON=10]
*PARAMETERS OF THE RESONANT STRUCTURE:
VL1 P101 0 {L1}
VC3 P102 0 {C3}
VL3 P103 0 {L3}
.PRINT TRAN V([GATE) V([N104])
.TRAN O.1N 5u 4.980u O.1N UIC
.PROBE
; PLOT V(GATE) AND V(N104) IN PROBE
.END
- 129
-
PSPICE Simulation Files
All simulations below run at 12V output using two parallel diodes, OnSemiconductor part MBRSi 540T3, with the listed breakdown voltage setting
BV. Actual device BV=40. The total diode capacitance 12V 72pF*2=144pF. For these simulations, 145pF is used, and this nominal value is
and L1, C3 and L3 in the MRS
NV indicates a
added to or subtracted from to get to "Cnom" which is used to find L in the SRS
Non Viable tuning (will not appear on graphs). "Mean Phase" is the average of the high and low output power phases."Phase Diff" and
"Abs Phase Dii" are the difference and the absolute value of the difference between the high and low output power phases.
Approx. 12watts/2 output
rox. 30watts/2 output
MRS BV=50V
FILE PSP052K.CIR
Tuning
Li
C3
L3
MRS
BV=50V FILE PSP052KACIR
phase
Off
pout ldrive pk ID pk VD
#
(nH)
(pF)
(nH) Cnom
dt (ps)
phase
eff
pout Idrive pk ID pk VD dt (ps)
185
191.35
6.89 92.55% 15.30
2
3.21 44.56 522.246 18.80 89.37% 4.04 0.8 2.07 37.67
1
6.085 173.44 3.65
89.03% 5.65 0.8 2.65 40.10
175
-129.31
-4.66 92.93% 15.42
2
3.04 42.36 347.531 12.51
2
6.433 164.06 3.86
171
-240.132 -8.64 93.03% 15.30
2 2.97 41.46 72.105
2.60 89.58% 5.84 0.8 2.58 39.20
3
6.584 160.31 3.95
4
6.661 158.44 4.00
169
-291.823 -10.51 93.07% 15.21
2
2.93 41.02 -51.883
-1.87 89.76% 5.86 0.8 2.55 38.77
5
6.741 156.56 4.04
167
-342.287 -12.32 93.12% 15.11
2
2.90 40.57 -167.21
-6.02 89.91% 5.84 0.8 2.51 38.27
6
6.823 154.69 4.09
165
-391.452 -14.09 93.16% 15.00
2
2.87 40.13 -276.36
-9.95 90.01% 5.79 0.8 2.47 37.83
7
7.036 150.00 4.22
160
-502.997 -18.11 93.25% 14.69
2
2.78 39.05 -527.17 -18.98 90.17% 5.56 0.8 2.37 36.70
8
7.263 145.31 4.36
155
-605.599 -21.80 93.33% 14.34
2
2.70 37.99 -750.77 -27.03 90.20% 5.24 0.8 2.26 35.59
9
7.764 135.94 4.66
145
-781.492 -28.13 93.46% 13.57
2
2.55 36.03 -1127
-40.57 90.03% 4.43 0.8 2.04 33.36
10
9.789 107.81 5.87
115
-1155.9
-41.61 93.74% 11.36
2
2.20 31.35 -1868.2 -67.26 88.04% 2.16 0.8 1.44 27.64
11
10.72 98.44 6.43
105
-1245.2
-44.83 93.81% 10.71
2
2.13 30.17 -2032.7 -73.18
1.57 0.8 1.27 26.28
12
11.85 89.06 7.11
95
-1326
-47.74 93.88% 10.09
2
2.07 29.16 -2192.9 -78.94 83.74% 1.01
0.8 1.12 25.22
13
13.24 7969
796
85 -1400.7 -50.43 93.93% 9.51
2
2.03 28.32 -2357.5 -84.87 000% 044 08 098 24.44
14
1501
7031
9.01
75
-1471.4 -52.97 93.97% 8.93
2
200 2784 -2515.9 -90.57
0.00% 0.00 0.8 0.86 23.95
Tuning
L
SRS
BV=60V FILE PSPOS2FC.cir
SRS BV=60V FILE PSP0S2FB.cir
#
(nH) Cnom
dt (ps)
phase
off
pout ldrive pk ID pk VD dt (ps)
phase
elf
pout drive pk ID pkVD
NV
8.44
300
450.943 16.23 93.49% 15.39
2 2.48 55.77
NV
NV
0.00% 0.02 0.9 0.46 23.30
NV
8.73
290
298.756 10.76 93.56% 15.75
2
2.50 55.48
NV
NV
0.00% 0.03 0.9 0.50 24.26
NV
9.05
280
160.062
5.76 93.62% 1594
2
2.51 55.10
NV
NV
0.00% 0.04 0.9 0.55 25.44
NV
9.38
270
29.242
1.05 93.66% 16.00
2 2.51 54.65
NV
NV
0.00% 0.07 0.9 0.61 26.97
NV
9.74
260
-93.882
-3.38 93.71% 15.95
2
2.51 54.15
NV
NV
0.00% 0.16 0.9 0.69 29.10
1
10.13 250
-210.85 -7.59 93.74% 15.80
2
250 53.60 1009.70 36.35
92.08% 5.27 0.9 1.64 45.12
2
10.55 240 -323.201 -11.64 93.78% 15.57
2 2.50 53.01 578.47
20.83 92.66% 6.19 0.9 1.72 45.70
3
11.01
230 -429.396 -15.46 93.81% 15.28
2
2.49 52.39 270.58
9.74 92.92% 6.55 0.9 1.74 45.62
4
11.51
220 -523.513 -18.85 93.85% 14.92
2
2.47 51.74 15.03
0.54
93.08% 6.64 0.9 1.74 45.27
5
12.06 210
-634.09 -22.83 93.89% 14.51
2
245
-21045
-758
657
173 4477
2
2.42 50.36 -416.65 -15.00 93.26% 637
0.9 1.70 44.14
6
12.67 200 -729.511 -26.26 93.91% 14.06
at
is
case,
case.
86.62%
5106
9319%
09
Mean
Phase
12.84
3.93
-3.02
-6.19
-9.17
-12.02
-18.54
-24.41
-34.35
-54.43
-59.00
-63.34
-67.65
-71.77
Mean
Phase
14.38
4.59
-2.86
-9.15
-15.20
-20.83
Phase
Dilf
-11.91
-17.17
-11.24
-8.64
-6.30
-4.14
0.87
Abs
Diff
11.91
17.17
11.24
8.64
6.30
4.14
0.87
5.23
12.44 12.44
25.64 25.64
28.35 28.35
31.21 31.21
34.44 34.44
37.60 37.0
Phase Abs
Dill
Dill
5.23
-43.94 43.94
-32.46 32.46
-25.20 25.20
-19.39 19.39
-15.25 15.25
-1l.26 11.26
Table A.1: Simulated comparison between various MR and SR tunings.
A.9
Simulations of Rectifier Alone
Table A. 1 contains the simulated results of a range of MR and SR rectifier tunings, produced
using the OnSemiconductor PSPICE model for device MBRS1540T3, except that the reverse
breakdown voltage parameter BV has been increased to prevent breakdown. The associated
simulation code is also shown.
For the SR rectifier simulation, use:
*** NON-MRS HALF-RECTIFIER, 12V, 100MHZ, NON-IDEAL DIODE, NON-IDEAL L
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400 RELTOL=0.002 VNTOL=0.01MV
.OPTION STEPGMIN NOPAGE NOBIAS NOECHO NOMOD NUMDGT=6
.WIDTH OUT=132
IDRIVE 10 0 SIN(O 2 {FS} 0 0 0)
VDIDRIVE 1 10 0
.PARAM PI=3.14159 FS=100MEG CNOMINAL=145P ;L1=12.5N
.FUNC L1(FS,CNOMINAL,PI) {1/(PWR((2*PI*FS),2)*CNOMINAL)}
XL1 1 11 LQS
+
+
+
+
PARAMS:
L={L1(FS,CNOMINAL,PI)}
QL=125
FQ=100MEG
VDIXL1 11 0 0
.STEP PARAM CNOMINAL 300P 200P loP
-
130
-
A.9
Simulations of Rectifier Alone
D1 1 30 DMBRS1540T3
D2 1 30 DMBRS1540T3
*D1 1 30 DIDEAL
VD1 30 3 0
VOUT 3 0 DC 12
.MODEL DIDEAL D (N=0.001)
*This model used initially. For the 1.5A, 40V OnSemiconductor MBRS1540T3
* Model Generated by MODPEX (for OnSemiconductor):
.MODEL DMBRS1540T3 D IS=3.54179e-05 RS=0.0306875 N=1.4038 EG=0.6 XTI=1.97409
+ BV=60 IBV=0.0008 CJO=3.18451e-10 VJ=0.4 M=0.428536 FC=0.5 TT=0 KF=0 AF=1
*Note that the BV is artificially increased from 40V. No other params changed
*This model used for the 2A, 60V OnSemiconductor MBRS260T3
* Model Generated by MODPEX (for OnSemiconductor):
.MODEL Dmbrs260t3 d
+IS=0.000119966 RS=0.0624233 N=1.7518 EG=0.652121
+XTI=0.5 BV=60 IBV=le-05 CJO=2.19068e-10
+VJ=0.4 M=0.436049 FC=0.5 TT=0
+KF=0 AF=1
*No params have been altered
*** 100MHZ CENTER FREQ BPF,
EBPF 4 0 1 0 1.0
LBPF 4 5 25.3303N
CBPF 5 6 100P
RBPF 6 0 .1591550
Q=100, FOR MEASURING FUNDAMENTAL OF INPUT VOLTAGE
.FUNC LORC(FS) {1000/(2*PI*FS)} ;LPF FUNCTION TWO DECADES BEFORE FS
POWER INTO VOLTAGE SOURCE) MEASUREMENT
EPO P001 0 VALUE={V(3,0)*I(VOUT)}
LPO P001 POUT {LORC(FS)}
CPO POUT 0
{LORC(FS)}
RPO POUT 0 1 ;OUTPUT POWER
* INPUT POWER (I.E. POWER OUT OF CURRENT SOURCE) MEASUREMENT
EPI PI01 0 VALUE={V(1,0)*(-I(VDIDRIVE))}
LPI PI01 PIN {LORC(FS)}
CPI PIN 0
{LORC(FS)}
RPI PIN 0
1
;INPUT POWER
* POWER-DISSIPATED-IN-DIODE MEASUREMENT
EPD PI02 0 VALUE=V(1,3)*I(VD1)}
LPD PI02 PD {LORC(FS)}
CPD PD 0 {LORC(FS)}
RPD PD 0 1 ;DIODE DISSIPATED POWER
* POWER DISSIPATED IN INDUCTOR L1
EPL PLO1 0 VALUE={V(1,0)*(-I(VDIXL1))}
LPL PLO1 PL {LORC(FS)}
CPL PL 0 {LORC(FS)}
RPL PL 0 1 ;INDUCTOR DISSIPATED POWER
*EFFICIENCY MEASUREMENT
EEF EFF 0 VALUE=IF(V(PIN)<=1,0,(V(POUT)/V(PIN)))}
REF EFF 0 1 ;EFFICIENCY MEASURMENT
* OUTPUT POWER (I.E.
.TRAN 0.02N 3U 2.95U 0.02N
.PRINT TRAN V([POUT]) V([EFF]) V(W) V(30)
.PROBE
.END
I(VDl) I(IDRIVE)
For the MR rectifier simulation, use:
- 131 -
PSPICE Simulation Files
*** MRS HALF-RECTIFIER, 100MHz, 12VOUT, NON-IDEAL DIODE, CDIODE=72p*2~=145, NON-IDEAL L
* *** ** **********
******
*** ** ******
** *** *** ******
** *****
*
.OPTIONS ABSTOL=1NA GMIN=10P ITL1=5000 ITL2=2000 ITL4=400 RELTOL=0.002 VNTOL=O.O1MV
.OPTION STEPGMIN NOPAGE NOBIAS NOECHO NOMOD NUMDGT=6
.WIDTH OUT=132
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
.PARAM PI=3.14159 FS=100MEG CD=145P C1=0P
CD IS THE NOMINAL DIODE CAPACITANCE AT 12V,
C1 ADJUSTS THE NOMINAL DIODE CAP VALUE FOR USE
IN L1, L3, C3 CALCULATION
.FUNC CTOT(CD,C1) {CD+C1}
.FUNC L1(FS,PI,CTOT) {1/(9*CTOT*PWR((PI*FS),2))}
.FUNC L3(FS,PI,CTOT) {1/(15*CTOT*PWR((PI*FS),2))}
.FUNC C3(FS,PI,CTOT) {15*CTOT/16}
.STEP PARAM C1 LIST 40P 30P 26p 24p 22p 20p 15P 10P OP -30P -40P -50P -60P -70P
*FOR REFERENCE: SIN(OFFSET AMPLITUDE FREQ DELAY DAMPING PHASE)
IDRIVE 10 0 SIN(O 2.0 100MEG 0 0 0)
SET AMPLITUDE TO 2.0 FOR MAX OUTPUT POWER OF 15W
SET AMPLITUDE TO 0.8 FOR MIN OUTPUT POWER OF 6W
VDIDRIVE 1 10 0
*C11 1 0 {CACTUAL(CD,C1)}
XL1 1 0 LQS PARAMS: L={L1(FS,PI,CTOT(CD,C1))}
QL=125
FQ=100MEG
XL3 1 2 LQS PARAMS: L={L3(FS,PI,CTOT(CD,C1))}
QL=125
FQ=100MEG
C33 2 0 {C3(FS,PI,CTOT(CD,C1))}
D1 1 30 modDMBRS1540T3
D2 1 30 modDMBRS1540T3
*D1 1 30 DIDEAL
VD1 30 3 0
VOUT 3 0 DC 12
.MODEL DIDEAL D (N=0.001)
* Model Generated by MODPEX:
.MODEL DMBRS1540T3 D IS=3.54179e-05 RS=0.0306875 N=1.4038 EG=0.6 XTI=1.97409
+ BV=40 IBV=0.0008 CJO=3.18451e-10 VJ=0.4 M=0.428536 FC=0.5 TT=O KF=O AF=1
.MODEL modDMBRS1540T3 D IS=3.54179e-05 RS=0.0306875 N=1.4038 EG=0.6 XTI=1.97409
+ BV=50 IBV=0.0008 CJO=3.18451e-10 VJ=0.4 M=0.428536 FC=0.5 TT=O KF=O AF=1
*DI N102 N103 Dmbrsl540t3
Q=100, FOR MEASURING FUNDAMENTAL OF INPUT VOLTAGE
EBPF 4 0 1 0 1.0
LBPF 4 5 25.3303N
CBPF 5 6 100P
RBPF 6 0 .1591550
.FUNC LORC(FS) {100/(2*PI*FS)} ;LPF FUNCTION TWO DECADES BEFORE FS
* POWER-INTO-VOLTAGE-SOURCE MEASUREMENT
EPO POOl 0 VALUE=V(3,0)*I(VOUT)}
LPO P001 POUT {LORC(FS)}
CPO POUT 0
{LORC(FS)}
RPO POUT 0 1 ;OUTPUT POWER
* POWER-OUT-OF-CURRENT-SOURCE MEASUREMENT
EPI PI01 0 VALUE={V(1,)*(-I(VDIDRIVE))}
LPI PI01 PIN {LORC(FS)}
CPI PIN 0
{LORC(FS)}
1
;INPUT POWER
RPI PIN 0
* POWER-DISSIPATED-IN-DIODE MEASUREMENT
EPD PI02 0 VALUE={V(1,3)*I(VD1)}
LPD PI02 PD {LORC(FS)}
CPD PD 0 {LORC(FS)}
RPD PD 0 1 ;DIODE DISSIPATED POWER
*DIODE EFFICIENCY MEASUREMENT
EEFD EFFD 0 VALUE={IF(V(PIN)<=1,0,(1-V(PD)/V(PIN)))}
REFD EFFD 0 1 ;DIODE EFFICIENCY MEASURMENT
*EFFICIENCY MEASUREMENT
EEF EFF 0 VALUE={IF(V(PIN)<=1,O,V(POUT)/V(PIN))}
REF EFF 0 1 ;EFFICIENCY MEASURMENT
* 100MHZ CENTER FREQ BPF,
-
132
-
A.10
Simulations of Compression Network and Rectifier Together
.TRAN 0.05N 3U 2.95U 0.05N
.PRINT TRAN V([EFF) V([POUT]) I(VD1)
.PROBE
.END
A.10
V(1)
V(30) I(IDRIVE) V(6,O)
Simulations of Compression Network and Rectifier Together
The following simulation is used to determine the effect on the compression and rectifier
stages of varying a of Eq. 7.6.
*SIMULATION OF COMPRESSION AND RECTIFIER STAGE PERFORMANCE FOR VARIOUS VALUES OF "a"
.LIB "C:\dc-dc\PSPICE\LIBS\CLASSE.LIB"
* OPTIONS FOR AVOIDING CONVERGENCE PROBLEMS:
.OPTIONS ABSTOL=1NA GMIN=IOP ITL1=5000 ITL2=2000 ITL4=400 RELTOL=0.002 VNTOL=O.OiMV
.OPTION STEPGMIN
* OPTIONS FOR OUTPUT FILE FORMATTING:
.OPTION NOPAGE NOBIAS NOECHO NOMOD NUMDGT=5
.WIDTH OUT=132
.PARAM
+ PI=3.14159
+ FS=100MEG
.PARAM
;RECTIFIER OUTPUT VOLTAGE
+ VOUTDC=12
;RECTIFIER INDUCTOR
+ Lp=19.8n
;RECTIFIER CAPACITOR
+ Cp=30p
Characteristic impedance of the compression network
+ X = 20
+ MULT=2.5
a.k.a "a", the ratio of compression elements tO the high freq. blocking elements
*+ Lp=18.9n
now a function
*+ Ccl=39.79p
now a function
*+ Lcl=31.83n
Originally 79.58p (double the original Cc1=39.79pF)
*+ Cc2= now a funtion
*+ Lc2= now a funtion
Originally 63.67n (DOUBLE the original Lc1=31.83nH)
*+ Cm=198.9p
*+ Lm=15.9n
.FUNC CC1(CC2,MULT) {CC2/MULT}
.FUNC LC2(LC1,MULT) {MULT*LC1}
.FUNC CC2(FS,PI,X,MULT) {(MULT-1)/(2*PI*FS*X)}
.FUNC LC1(FS,PI,X,MULT) {X/((MULT-1)*(2*PI*FS))}
*.STEP PARAM MULT LIST 2.5 2.25 2 1.75 1.5 1.25
*Because Iin uses the one allowed .STEP command, this entire file must be repeated for each
*value of MULT that is to be tested.
* **
***
** **
******
******
***
*******
******
*
*COMPRESSION NETWORK*******************
Iin z 0 sin(OA {idrive} {FS} 0 0 0)
.STEP PARAM IDRIVE 1.1 1.65 0.11
.PARAM IDRIVE=1.65
VDUOUT DUOUT 0 0 ;DUMMY VOLTAGE SOURCE
Vdum Z W 0
* THE PERFORMANCE OF THE CIRCUIT WITH LOSSLESS COMPONENTS IS SIMULATED BY COMMENTING
* OUT THE FOUR PASSIVE COMPONENT SUBCIRCUITS AND COMMENTING IN THE IDEAL COMPONENTS
* CALLED c4, L4, L5 AND C5 (MARKED "IDEAL")
- 133
-
PSPICE Simulation Files
; IDEAL
*C4 W W1 {CC1(CC2(FS,PI,X,MULT),MULT)}
FORMERLY {Ccl)
XC4 W W1 CQS PARAMS: + C={CC1(CC2(FS,PI,X,MULT),MULT)}
+ QC=988.65 FQ={FS} IC=0
*L4 W1 MI {LC1(FS,PI,X,MULT)} ;IDEAL ; FORMERLY {Lc1}
FORMERLY {Lcl}
XL4 W1 M1 LQS PARAMS: L={LC1(FS,PI,X,MULT)}
+ QL=150 FQ={FS} IC=0
*L5 W W2 {LC2(LC1(FS,PI,X,MULT),MULT)} ; IDEAL
XL5 W W2 LQS PARAMS: L={LC2(LC1(FS,PI,X,MULT),MULT)}
FORME RLY {Lc2}
+ QL=150 FQ={FS} IC=0
RC5 W2 M2 100MEG
*C5 W2 M2 {CC2(FS,PI,X,MULT)} ; IDEAL
XC5 W2 M2 CQS PARAMS: C={CC2(FS,PI,X,MULT)}
FORMERLY {Cc2}
+ QC=988.65 FQ={FS} IC=0
VCCJ CC1 0 {CC1(CC2(FS,PI,X,MULT),MULT)}
RCC1 CC1 0 1
VLC1 LC1 0 {LCl(FS,PI,X,MULT)}
RLCl LC1 0 1
VLC2 LC2 0 {LC2(LC1(FS,PI,X,MULT),MULT)}
RLC2 LC2 0 1
VCC2 CC2 0 {CC2(FS,PI,X,MULT)}
RCC2 CC2 0 1
***RECTIFIER*************************
VR1 M1 M11 0
XL6 M11 DUOUT LCHOKE PARAMS: L={Lp} QL=150 FQ={FS} RDC=0.01 IC=0
XC6 M11 DUOUT CQS PARAMS: C={Cp} QC=988.65 FQ={FS} IC=0
LD1 M11 M12 2n
D11 M12 OUT Dmbrs260t3
VR2 M2 M22 0
XC7 M22 DUOUT CQS PARAMS: C={Cp} QC=988.65 FQ={FS} IC=0
XL7 M22 DUOUT LCHOKE PARAMS: L={Lp} QL=150 FQ={FS} RDC=0.01 IC=0
LD2 M22 M23 2n
D21 M23 OUT Dmbrs260t3
.MODEL Dmbrs260t3 d IS=0.000119966 RS=0.0624233 N=1.7518 EG=0.652121 XTI=0.5
+ BV=60 IBV=1e-05 CJO=2.19068e-10 VJ=0.4 M=0.436049 FC=0.5 TT=0 KF=0 AF=1
VOUT OUT DUOUT {VOUTDC}
*** SPECIALIZED MEASURMENT CIRCUITS
***
.FUNC LORC(FS) {100/(2*PI*FS)} ;FUNCTION THAT PLACES THE FILTER
;COMPONENT OF THE MEASURMENT
;CIRCUITS TWO DECADES BEFORE THE
;SWITCHING FREQUENCY
*CONVERTER TOTAL OUTPUT POWER MEASUREMENT
EPOUT P101 0 VALUE = {I(VOUT)*V(OUT)}
LP1 P101 POUT-TOTAL {LORC(FS)}
CP1 POUTTOTAL 0 {LORC(FS)}
RP1 POUTTOTAL 0 1
**CONVERTER TOTAL INPUT POWER MEASUREMENT
EPIN P101A 0 VALUE = {I(VDUM)*V(Z)}
LP1N P101A PIN {LORC(FS)}
CPIN PIN 0 {LORC(FS)}
RPIN PIN 0 1
*Compression network input voltage fundamental
EVC VRC21 0 VALUE={V(Z)}
LVC VRC21 VRC22 {LORC(FS)}
CVC VRC22 VCINFUND {0.0001*LORC(FS)}
RVC VCINFUND 0 1
*Rectifier the fundermanteal input voltage measure
EVR1 VR11 0 VALUE={V(Ml)}
LVR1 VR11 VR12 {LORC(FS)}
CVRl VR12 VRIN1 {0.0001*LORC(FS)}
-
134
-
A.10
Simulations of Compression Network and Rectifier Together
RVR1 VRIN1 0 1
*Rectifier the fundermanteal input current measure
EIR1 IR11 0 VALUE={I(VR1)}
LIR1 IR11 IR12 {LORC(FS)}
CIR1 IR12 IRINI {0.0001*LORC(FS)}
RIR1 IRIN1 0 1
*Rectifier the input power
EPR1 PIR1 0 VALUE=V(M)*(I(VR1))}
LPR1 PIR1 PINR1 {LORC(FS)}
CPRI PINR1 0
{LORC(FS)}
RPR1 PINR1 0
1
;INPUT POWER
*Rectifier the fundermanteal input voltage measure
EVR2 VR21 0 VALUE={V(M2)}
LVR2 VR21 VR22 {LORC(FS)}
CVR2 VR22 VRIN2 {O.0001*LORC(FS)}
RVR2 VRIN2 0 1
*Rectifier: fundamental of the input current
EIR2 IR21 0 VALUE={I(VR2)}
LIR2 IR21 IR22 {LORC(FS)}
CIR2 IR22 IRIN2 {0.0001*LORC(FS)}
RIR2 IRIN2 0 1
*Rectifier input power
EPR2 PIR2 0 VALUE={V(M2)*(I(VR2))}
LPR2 PIR2 PINR2 {LORC(FS)}
{LORC(FS)}
CPR2 PINR2 0
;INPUT POWER
1
RPR2 PINR2 0
*EFFICIENCY MEASUREMENT
EEF EFF 0 VALUE={IF(V(PIN)<=1,O,V(POUT-TOTAL)/V(PIN))}
REF EFF 0 1 ;EFFICIENCY MEASURMENT
.PRINT TRAN V([CC1J) V([LC1]) V([LC2J) V([CC2]) V([PINR1J) V([PINR2]) V([EFFJ)
.tran 0.05N 3U OU 0.05N
TO MEASURE BALANCE BETWEEN RECTIFIER POWERS, OBSERVE
THE QUANTITIES PINR1 AND PINR2
.PROBE
.END
- 135
-
Appendix B
LDMOS and VDMOS Search Results
Selected pages of Freescale MRF373ALSR1 datasheet are shown below. This device was
ultimately selected for use in this design. Also shown here are tables of information from
RF MOSFET datasheets. The first three tables shown below contain all of the LDMOS
devices that were considered for use in this design. The fourth table contain VDMOS
device information as a basis for the comparisons made in chapter 3.3.1. Selected pages of
the Freescale MRF373ALSR1 datasheet are also included here.
-
137
-
Freescale Semiconductor, Inc.
MOTOROLA
The RF MOSFET Line
Freescale Semiconductor, Inc.
Order this document
by MRF373A/D
SEMICONDUCTOR TECHNICAL DATA
ELECTRICAL CHARACTERISTICS (Tc
Characteretle
=25'C unless otherwise
MRF373ALRI
N-Channel Enhancement- Mode Lateral MOSFETs
MRF373ALSRI
Designed for broadband commercial and industrial applications with frequencips from 470 to 860 MHz. The high gain and broadband performance of these
devices make them ideal for large-signal, common source amplifier applications in 28/32 volt transmitter equipment.
" Typical CW Performance at 860 MHz, 32 Volts. Narrowband Fixture
Output Power -75 Watts
Power Gain - 18.2 dB
Efficiency - 60%
" 100% Tested for Load Mismatch Stress at Ail Phase Angles
with 10:1 VSWR @ 32 Vdc, 860 MHz, 75 Watts CW
" Integrated ESD Protection
- Excellent Thermal Stability
- Characterized with Series Equivalent Large-Signal
Impedance ParametersaAE30.5
" In Tape and Reel. R1 = 500 units per 32 mm, 13 inch Reel.
- Low Gold Plating Thickness on Leads.
L Suffix Indicates 40 t Nominal.
Dran-Source Brekdown5 Voltage
V(BR)OsS
70
-Vd
Zero Gate Volage Drain Current
(Vos - 32 VdO, Von = 0 Vdo)
loss
-
-
1
Gate-Source Leakage Current
0 Vd_)
(Vs - 5 Vd, Vo
IGss
-
-
1
IMAd
Vonsth)
2
2.9
4
Vdn
VGS(Q)
2.5
3.3
4.5
Vdc
0
0.45
Vdc
z
-t
________
CASE
Threshold Voltage
(Vos - 10 V, ID -200 pA)
Gate Quiescent Voltage
(Vos - 32 V, lo - 100 mA)
Gate
DYNAMIC CHARACTERISTICS
Input Capacitance
(VoS - 32 V. VoS - 0, f - 1 MHz)
s0-s, STYLE 1
TL
NI-3A
Output Capacitance
(VoS - 32 V, V0S - 0, t -1M MHz)
Reverse Transfer Capacitance
(Vos - 32 V. Vos - 0, 1 - MHz)
1
36C-05, STYLE 1
0
0-
Efficiency
(VoD = 32 V. P0o - 75 W CW, too - 200 mA, I
Symbol
Rating
Volage
VoSS
Gate -Source Voltage
VGS
MRF373ALRI
25"C
THERMAL CHARACTERISTICS
Characteristio
Thermal Resistance, Junction to Case
ESD PROTECTION CHARACTERISTICS
Teat Conditione
Machine Model
REV
.
(9 Moloole. Ira 0038
Vdo
Watts
wf'C
Wats,
W("C
T,
Tj
65 to +150
200
"C
C
Max
0.8
"C/W
R-
So
-
0.41
Ce
-
08.5
-
pF
Cp
-
49
-
PF
C_
-
2
-
pF
-
880 MHZ)
Load Mismatch
(VoD - 32 V, PotA - 75 W CW Io - 200 mA, I - 880 MHz.
Load VSWR at 10:1 at Al Phase Angles)
Gp.
16.5
182
-
dB
TI
50
80
-
%
No Degradation in Output Power
U0
Unit
0.j
Close
(Minium)
M2 (Minimum)
M1 (Minimum)
MRF373ALRI
MRF373ALSR1
NOTE - CAUTION - MOS devices are susceptible to damage from electrostatic
packaging MOS devices should be observed.
Vdo
+15
197
1.12
278
1.50
1
Human Body Model
70
P0
Symbol
MRF373ALR1
MRF373ALSRI
Unit
-0.5
MRF373ALSR1
Storage Temperature Range
Operating Junction Temperature
Value
Vonsler
C13
FUNCTIONAL CHARACTERISTICS (50 ohm system)
Conmon Source Power Gain
(Voo - 32 V, Pu - 75 W CW, too - 200 mAI = 80 MHz)
Drain
MAXIMUM RATINGS
Adc
ON CHARACTERISTICS
Drain-Source On-Voltage
A)
(VGs - 10 V, - 3SA
NI-360S
MRF373ALSRI
Tc -
Unit
Typ
NonS - 0 Vdc. lo -1 PA
470 - 150 MHz, 75 W, 32 V
ANNEL
BLATERAL N
ROADBAND
RIF POWER MOSFETa
CASE
Total Device Dissipation @
Derate above 25"C
Max
Min
OFF CHARACTERISTICS
RF Power Field Effect Transistors
Drain-Source
soted)
Symbol
charge,
Reasonable precautions
**U"!*,^
For More Information On This Product,
Go to: www.freescale.com
i
handling
and
*
digitaldna-
MRF373ALRI MRF373ALSR1
2
MOTOROLA RF DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
55('3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
TYPICAL CHARACTERISTICS
20
ainGe
NOW&
I
G
S-
* 11iiLT
--
0 0 0w7
0
.
10
Af
P, UTPUTPOWER
frFigure 2.
-APower
00
-A-
bbT
A
C
@11101
A @I
1* -c@1T
I
Y
lil
-a
2x K
SD
$*
12
1.INTERPRET DIMENSIM AND TOLERANCES
PERASKY14SM-1904.
2 C0NTTMxLX COMMON: MOL
OR"ON H
0.03D ft= AM
FROM PAC= MEAMPRED
BODY
aaaOTAO@BO
$0
E-
F
C
NS
0.1a
0,210
119MM4
MIR BSC
K10
ITI A 40@ 1
$M
(WATTS)CW
Output Power
Gain versus
I Am
-9
ILM
-JL
-jL
-JL
T
SM FU
-@T
0
1M
A
ISULATO
I5
-
30
z
V-
-
25
-
10
-
ORAIN
WE
SOURCE
CASE 360B-05
A
A ---
62
.
STYLE I
A @111 j
ISSUE F
NI-360
MRF373ALR1
0
1)6
IN
\
R
SA
511
-m
0
0
$Do st 840
s60
$11
900
Kllb
2*
Figure 3. Porformsance
In
PERWD191-14
WEW 8NEM0D008
2.3ACONTOLLIG
OA@jIBI@
920
.F
IT
N
7 E:
200
L
Lie
co (llI
H
A Q0 180
.
PIN
...--.
3
10
$bSIIOTAOBO
C-
0
0
IC
V0 s,
20
DRAIN
_
30
40
so
5v
KEna
R
00111LIVOR
CASE 36OC-05
ISSUE D
NI-360S
MRF373ALSR1
30M1m
n
SOURCE VOLTAGE (VOLTS)
Figure 4. Capacitance versus Voltage
MRF373ALR1 MRF373ALSR1
4
DECE DATA
For More Information On This ProduceOTOROLA RF
Go to: www.froeescai.com
i
9
f
10
.*
EL
150
-U
A
Narrowband Circuit
MOTOROLA RF DEVICE DATA For More Information On This
Product,
Go to: www.froescale.com
MRF373ALR1 MRF373ALSR1
MEF
LDMOS and VDMOS Search Results
Table of datasheet information for LDMOS devices, 1st of 3 tables.
ND indicates No Data, and italics indicate that a typical value is being used in a column specified as a maximum value
Specified Coss
Specified
Part
Number
Package
Number
Vdsmax
[VI
MRF373ALSR1
360C-05
70
PD55003
PD55003L
PD55008
PD55008L
PD55015
PD55025
PD55035
PD57002
PD57018
PD57006
PD57030
PD57045
PD57060
PD57070
PowerSO-10RF
PowerFlat
PowerSO-10RF
PowerFlat
PowerSO-1ORF
PowerSO-10RF
PowerSO-10RF
PowerSO-10RF
PowerSO-10RF
PowerSO-10RF
PowerSO-10RF
PowerSO-1ORF
PowerSO-10RF
PowerSO-1ORF
M243 Flanged
M250 Unflanged
M243 Flanged
M250 Unflanged
M250 Unflanged
M113
M113
M113
M113
M174
M174
M174
PowerSO-1ORF
PowerFlat
PowerSO-10RF
PowerFlat
40
40
40
40
40
40
40
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
125
125
125
125
25
25
25
25
SD57030
SD57030-01
SD57045
SD57045-01
SD57060-01
SD2900
SD2902
SD2904
SD2918
SD2921-10
SD2931
SD2931-10
PD54003
PD54003L
PD54008
PD54008L
Vgsmax
Vdson
[V]
Max [V}
FREESCALE
pm15m.5
0.45
ST
0.36
prn 20
p15, m 0.5
0.36
pm 20
0.67
0.14
P15, m 0.5
pm 20
0.8
pm 20
0.8
pm 20
0.95
pm 20
0.9
pm20
0.9
pm 20
0.9
pm20
1.3
pm 20
0.9
pm 20
0.8
pm 20
0.95
pm 20
1.3
20
p
m?
1.3
pm 20
0.9
pm 20
0.9
pm 20
0.9
pm 20
1.6
pm 20
1.6
pm 20
1.6
pm 20
5
pm 20
3
pm 20
3
pm 20
3
pm 20
1.3
p 15, m 0.5
0.16
pm 20
0.6
p15,m.5
0.9
Vgs
[V]
Rdson
Id
Rdson
[A]
[Ohms]
at 1 MHz, Vgs=0
Vds
Coss
[V]
[pF]
RdsonCoss
10
3
0.15
32
49
7.35
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
0.5
0.5
1.5
0.5
2.5
3
3
0.125
1.25
0.5
3
3
3
3
3
3
3
3
3
0.5
0.5
3
2.5
10
10
10
1
0.5
2
0.72
0.72
0.45
0.28
0.32
0.27
0.32
7.2
0.72
1.8
0.43
0.3
0.27
0.32
0.43
0.43
0.3
0.3
0.3
3.2
3.2
0.53
2
0.3
0.3
0.3
1.3
0.32
0.3
1.8
12.5
12.5
12.5
12.5
12.5
12.5
12.5
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
50
50
50
50
7.5
7.5
7.5
7.5
24
23
38
38
60
76
73
5.8
21
14
30
47
58
58
34
34
40
40
44
7.8
18
35
35.5
198
190
190
43
43
68
60
17.28
16.56
16.97
10.64
19.2
20.27
23.12
41.76
15.12
25.2
13
14.1
15.47
18.37
14.73
14.73
12
12
13.2
24.96
57.6
18.67
71
59.4
57
57
55.9
13.76
20.4
108
10
10
10
10
10
10
10
10
10
10
10
10
10
0.1
1
1
1
1
1
1
1
1
1
1
1
1
3
0.2
ND
26
26
26
26
26
26
ND
ND
ND
28
28
28
ND
32
46
98
32.5
65
32
ND
ND
ND
32.5
65
98
ND
6.4
9.2
19.6
6.5
13
10.24
ND
ND
ND
6.5
26
ND
0.5
M/A-COM
MAPLST0810-002PP
MAPLST0810-030CF
MAPLST0810-045CF
MAPLST0810-090CF
MAPLST1900-030CF
MAPLST1900-060CF
MAPLST1820-030CF
MAPLST1820-060CF
MAPLST1 820-090CF
MAPLST2122-015CF
MAPLST2122-030CF
MAPLST2122-060CF
MAPLST2122-090CF
Same as part #
P-239
P-239
P-238
Same as part #
Same as part #
P-237
P-238
P-240
Same as part #
Same as part #
Same as part #
Same as part #
65
65
65
65
65
65
65
65
65
65
65
65
65
pm 20
p 20 m ?
p 20 m ?
p 20 m ?
p20m?
p 20 m ?
p 20 m ?
pm 20
pm 20
p 20 m ?
p20 m ?
p20 m?
p 20 m ?
0.3
0.2
0.2
0.2
0.2
0.2
0.32
0.4
0.1
0.2
0.2
0.4
ND
0.2
0.2
0.
0.2
0.32
0.4
0.1
0.2
0.2
0.4
ND
Table B.1: Selected datasheet information for all LDMOS devices considered for use in this
design, table 1 of 3.
-
140
-
Table of datasheet information for LDMOS devices, continued 2 of 3
ND indicates No Data, and italics indicate that a typical value is being used in a column specified as a maximum value
Specified Coss
Specified Rdson
at 1MHz, Vgs=
Part
Package
Vdsmax
Vgsmax
Vdson
Vgs
Id
Rdson
Vds
Coss
Number
Number
[V]
[VI
Max [V]
[V]
[A]
[Ohms]
[V]
[pF]
RdsonCoss
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
1
5
1
1
1
2
1
1
1
1
1
1
1
1
2
2
2
0.2
1
1
1
2
1
1
1
1
1
1
1
1
0.9
0.28
0.062
0.16
0.18
0.19
0.05
0.12
0.14
0.15
0.12
0.9
0.21
0.15
0.28
0.075
0.95
0.125
0.9
0.28
0.3
0.15
0.055
0.15
0.12
0.9
0.31
0.18
26
26
26
28
26
27
26
27
26
13
27
26
26
26
26
26
26
26
26
26
8.5
28
31
ND
40
57
86
95
52
ND
185
8.5
10
ND
26
350
6.3
7.9
ND
26
26
335
26
26
26
28
26
28
28
28
28
28
365
ND
30
ND
8.5
ND
ND
ND
ND
352
7.65
7.84
1.922
ND
7.2
10.83
4.3
11.4
7.28
ND
22.2
7.65
2.1
ND
7.28
26.25
5.985
0.9875
ND
7.28
100.5
54.75
ND
4.5
ND
7.65
ND
ND
ND
ND
116.16
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2.5
8
2.5
8
2.5
8
12
2.5
2
8
13
16
16
5
16
8
2.5
3
8
2
8
3
8
3
8
12
3
16
8
8
0.9
0.65
0.9
0.28
0.9
0.65
0.45
0.9
0.5
0.28
0.2
0.2
0.25
0.5
0.17
0.65
0.9
0.6
0.4
0.6
0.4
0.6
28
28
28
28
28
28
28
28
28
28
28
12.5
28
28
28
28
28
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
7.5
7.5
15
30
15
50
15
30
60
15
30
50
100
100
90
30
100
30
15
24
40
24
40
24
60
24
40
80
24
120
40
40
13.5
19.5
13.5
14
13.5
19.5
27
13.5
15
14
20
20
22.5
15
17
19.5
13.5
14.4
16
14.4
16
14.4
16.8
14.4
16
24
14.4
24
16
16
CREE
UPF1010
UPF1030
UGF09030
UGF09045
UPF1060
UGF09060
UGF09085
UGF09180
UPF14060
UPF16060
UGF16085
UPF2010
UPF2012
UPF18030
UPF18030-095
UGF18060
UGF2005
UGF2008
UGF2016
UPF2030
UGF19030
UGF19060
UGF19085
UGF19090
UGF19125
UPF21010
UGF21030
UGF21060
UGF21090
UGF21125
UGF27025
440095 and 440109
440134
440134
440134
440134
440134
410133
440138
440171
440171
440171
440095 and 440109
440095 and 440109
440162 and 440161
440095
440171 and 440172
440095 and 440109
440095 and 440109
440095
440095 and 440134
440162 and 440161
440171 and 440133
440171 and 440133
440174 and 440175
440174 and 440175
440095 and 440134
440162 and 440161
440171 and 440133
440174 and 440175
440174 and 440175
440159
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
L125
L2701
L2801
LC401
LC801
LP701
LP702
LP801
LP802
LX401
LX501
LX521
LX703
LX802
LZ402
L8701P
L8801P
L225
L2721
L2821
L8721P
L8821P
LC421
LC821
LP721
LP722
LP821
LX723
L2711
L8711P
S08-1
S02
S02
AC
AC
AP
AP
AP
AP
LX2
LX2
LX2
LX2
LX2
LZ
SO8 P
SO8 P
S08-1
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
36
36
36
36
36
36
36
36
36
36
36
36
36
S02
S02
SO8 P
S08 P
AC
AC
AP
AP
AP
LX2
S02
SO8 P
pm 20
0.9
0.28
pm 20
0.31
p 15, m 0.5
p 15, m 0.5
0.16
pm 20
0.18
p15, m 0.5
0.19
p15, m 0.5
0.1
p 15, m 0.5
0.12
p 15, m 0.5
0.14
0.15
15, m 0.5
0.12
p 15, m 0.5
pm 20
0.9
0.21
pm 20
p 15, m 0.5
0.15
p 15, m 0.5
0.28
0.15
p 15, m 0.5
p 15, m 0.5
1.9
0.25
p 15, m 0.5
pm 20
0.18
pm 20
0.28
p15, m 0.5
0.3
p 15, m 0.5
0.15
0.11
p 15, m 0.5
0.15
p15, m 0.5
p15, m 0.5
0.12
p15, m 0.5
0.9
0.31
p15, m 0.5
p 15, m 0.5
0.18
0.13
15, m 0.5
0.075
p15, m 0.5
p15, m 0.51
0.33
POLYFET
20 m ?
2.25
p 20 m ?
5.2
2.25
p 20 m ?
2.24
p 20 m ?
p 20 m ?
2.25
5.2
20 m ?
p 20 m ?
5.4
p 20 m ?
2.25
20 m ?
1
p 20 m ?
2.24
p 20 m ?
2.6
p 20 m ?
3.2
p 20 m ?
4
p 20 m ?
2.5
20 m ?
2.72
p 20 m ?
5.2
p 20 m ?
2.25
p 20 m ?
1.8
p 20 m ?
3.2
p 20 m ?
1.2
p 20 m ?
3.2
p 20 m ?
1.8
p 20 m ?
2.24
p 20 m ?
1.8
p 20 m ?
3.2
20 m ?
3.6
p 20 m ?
1.8
p 20 m ?
3.2
p 20 m ?
3.2
p 20 m ?
3.2
0.13
0.075
0.33
0.28
0.6
0.4
0.3
0.6
0.2
0.4
0.4
Table B.2: Selected datasheet informatioff4A1ll-LDMOS devices considered for use in this
design, table 2 of 3.
LDMOS and VDMOS Search Results
Table of datasheet information for LDMOS devices, continued 3 of 3.
ND indicates No Data, and italics indicate that a typical value is being used in a column specified as a maximum value
Part
Number
Package
Number
Vdsmax
[V]
Vgsmax
[V]
AGRA1OE
AGRA10GM
AGRB1OE
AGRO9030E
AGRO9030GUM
AGRO9045E
AGRO9045GUM
AGRO906OG
AGRO9060GUM
AGR09070EF
AGRO9085E
AGRO9090EF
AGRO9130E
AGRO918OEF
AGR18060E
AGR18090E
AGR19030EF
AGR19045EF
AGR19060E
AGR19125E
AGR19180EF
AGR21030EF
AGR21045EF
AGR21090E
AGR21125E
AGR26045EF
AGR26125E
AGR26180EF
Same as part #
Same as part #
Same as part#
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as part #
Same as art #
Same as part #
Same as part #
Same as part #
Same as part #
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
65
p 15 m 0.5
p 15 m 0.5
p 15 m 0.5
p 15 m 0.5
p15 m 0.5
p 15 m 0.5
p 15 m 0.5
p 15 m 0.5
p 15 m 0.5
p15 m 0.5
p 15 m 0.5
p15 m 0.5
p 15 m 0.5
p15 m 0.5
15 m 0.5
p15 m 0.5
p15 m 0.5
p15 m 0.5
p15 m 0.5
p 15 m 0.5
p 15 m 0.5
p 15 m 0.5
p 15 m 0.5
p15 m 0.5
p15 m 0.5
p15 m 0.5
p 15 m 0.5
p 15 m 0.5
Specified Rdson
Vgs
Id
Rdson
[V]
[A
[Ohms]
Vdson
Max [V]
AGERE
0.28
0.28
0.28
0.35
0.25
0.25
0.25
0.17
0.25
0.12
0.12
0.12
0.08
0.06
0.08
0.11
0.3
0.3
0.08
0.08
0.08
0.3
0.22
0.11
0.08
0.22
0.08
0.08
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
0.5
0.5
0.5
1
1
1
1
1
1
1
1
1
1
1
0.45
1
0.4
0.4
0.45
1
1
0.4
0.5
1
1
0.56
0.56
0.56
0.35
0.25
0.25
0.25
0.17
0.25
0.12
0.12
0.12
0.08
0.06
0.177
0.11
0.75
0.75
0.177
0.08
0.08
0.75
0.44
0.11
0.08
0.5
0.44
1
1
0.08
0.08
Specified Coss
at 1 MHz, V s=0
Vds
Coss
[)l
[pF]
RdsonCoss
28
26
28
28
28
28
28
28
28
26
28
26
28
28
ND
26
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
5.15
5.15
5.15
15.7
15.7
23
23
36
31.5
48
48
48
72
46
ND
48
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
2.884
2.884
2.884
5.495
3.925
5.75
5.75
6.12
7.875
5.76
5.76
5.76
5.76
2.76
ND
5.28
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
Table of datasheet information for VDMOS devices.
Specified Rdson
Part
Number
Package
Number
SD3932
SD3933
S8201
S8202
SP201
SP202
SP203
SP204
SA701
SA702
SC701
SM401
SM703
SM704
SM705
SV401
Vgsmax
[V]
Vdson
Max [V]
Vgs
[V]
Id
[A]
Rdson
[Ohms]
10
10
10
5
5
10
1
1
0.5
100
100
100
134
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
0.5
1
0.5
1
1.5
2
2.5
5
2.5
15
75
10
125
15
2.5
5
10
15
4
2
4
2
1.3
1
0.85
0.5
0.85
0.16
0.35
0.25
0.2
0.16
0.85
0.5
0.25
0.16
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
6
12
6
12
18
24
32
RdsonCoss
ST
SD3931-10
SM706
SP701
SP702
ST704
Vdsmax
[V]
Specified Coss
at 1 MHz, Vgs=0O
Vds
Coss
[V]
[pF]
I
M174
M224
M177
250
250
250
pm 20
S08
S08
AP
AP
AP
AP
AA
AA
AC
AM
AM
AM
AM
AM
AP
AP
AT
AV
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
p 20 m ?
p20rm?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 20 m ?
p 2Omn?
p 20m ?
p 2Omn?
p 20m ?
p20m?
5
pm 20
pm 20
5
5
POLYFET
2
2
2
2
1.95
2
2.125
2.5
2.125
2.4
2.625
2.5
2.5
2.4
2.125
2.5
2.5
2.4
134
390
24
32
200
96
128
160
192
32
64
128
200
134
134
195
24
24
24
24
23.4
24
27.2
32
27.2
32
33.6
32
32
30.72
27.2
32
32
32
Table B.3: Selected datasheet information for all LDMOS devices considered for use in this
design, table 3 of 3, and a table of selected datasheet information for some VDMOS devices.
Notice that most of the VDMOS devices have higher RDSONCOSS products than most of
the LDMOS devices.
-
142
-
Appendix C
Power Schottky Diode Search Results
Table C.1 shows all of the power Schottky diodes found in the initial device search, as
discussed in chapter 6.3. Table C.2 shows all of the 60V power Schottky diodes found
in the second device search, also discussed in chapter 6.3. The datasheet of the diode
that was ultimately selected, the MBRS260T3, is reproduced here with the permission of
OnSemiconductor.
-
143
-
MBRS260T3
MBRS260T3
Qs
Characteristic
Schottky Power Rectifier
4
Rx
Ra
24
80
Maximum Instantaneous Forward Votage (Note 3)
Tj
.F
( SA)
-: 2.0 A)
ON4 6"16011u1110
... employing the Schottky Barrier principle in a metal-to-silicon
power rectifier. Features epitaxial construction with oxide passivation
and metal overlay contact. Ideally suited for low voltage, high
frequency switching power supplies; free wheeling diodes and
polarity protection diodes.
4
Value
http://onsemi.com
Maximum Instantaneous Reverse Current (Note 3)
o
(V=-60V)
RECTIFIER
60 VOLTS
75*C
25*C
VRRM
60
V
VFwtM
VR
i0
Average Rectified Forward Current
(At Rated V0, TL - 95*C)
Non-Repetitive Peak Surge Current
(Surge Applied at Rated Load
irsm
A
60
A
CASE 403A
PLASTIC
. .
MARKING DIAGRAM
2-*C
-55
to +150
*C
.
.
.
.
.
.
.1
itjoaT
~
0.3 0.4 0.5
0.1 0.2
ORDERING INFORMATION
MBRS2rOT3
Package
SMB
2500/Tap-
A R-el-
25*C
1 MHz-
f=
Tj
-55 to +125
dv/dt
10,050
- 5-C
a:
a luc5n
l0E
1.I
-
--
-C-
E-05
0
10
20
40
50
30
V0 , REVERSE VOLTAGE (VOLTS)
Figure 3. Typical Reverse Current
60
0
C
V/ps
(Rated Vt, Tj = 25'C)
0 s*me1-dWW C-0-nft llneal.,
January, 2M0 - Rev. I
uLC,
2003
1
Publication Order Number:
MBRS260T3/D
0.1
100
cc1.OE-04
Shipping
0.7
0.6
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 2. Maximum Forward Voltage
1.OE-02
B26 - Device Code
Ternperature
Operating Junction Temperature
Voltage Rate of Change
-
lb
Vr, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
Figure 1. Typical Forward Vollage
1.0E-07
TC
ctA
- 25C75C
0.1a
60
Te,
mA
'
sMB
Conditions Halfwave, Single
Phase, Hz)
Storage/Operating Case
Tj 125C
10
S
Device
2.0
Tj . 25C
0.2
-
1.OE-03
Unit
vos
15
MAXIMUM RATINGS
Value
Tj .125C
0.475
0.55
1.-
125*C
Symbol
25'C
0.51
0.63
2.0 AMPERES
Mechanical Characteristics:
" Case: Molded Epoxy
* Epoxy Meets UL94. VO at 1/8"
* Weight: 95 mg (approximately)
" Cathode Polarity Band
" Lead and Mounting Surface Temperature for Soldering Purposes:
260*C Max. for 10 Seconds
" Available in 12 nun Tape. 2500 Units per 13" Reel, Add "T3" Suffix
to Part Number
* Finish: All External Surfaces Corrosion Resistant and Terminal
Leads are Readily Solderable
" ESD Ratings: Machine Model = C
Human Body Model = 3B
* Marking: B26
Peak Repetitive Reverse Voltage
Working Peak Reverse Voltage
DC Blocking Voltage
8
with minimsam recommended pad size, PC Board FR4.
2. Mounsted
inch square pad size (1 00.5 inch for each lead)on FR4 board.
3. Pulse Test: Pulse Wldth! 250 ss, Duty Cycles 2.0%.
SCHOTTKY BARRIER
Compact Package with J-Bend Leads Ideal for Automated Handling
Highly Stable Oxide Passivated Junction
Guardring for Over-Voltage Protection
Low Forward Voltage Drop
Rating
Unit
C/W
ELECTRICAL CHARACTERISTICS
SMB Power Surface Mount Package
I-i
Symbol
Thermal Resistance - Junction-to-Lead (Note 1)
Thermal Resistance - Junction-to-Ambient (Note 2)
Surface Mount
"
*
*
*
t
THERMAL CHARACTERISTICS
hftp://onsomi.com
10
20
30
40
VR, REVERSE VOLTAGE (VOLTS)
Figure 4. Typical Capacitance
50
60
MBRS260T3
MBRS260T3
PACKAGE DIMENSIONS
2
3
Q
dc
-
-
1.6
-
2.5
1.8
SMB
dc
d
1.4
02
PLASTIC PACKAGE
CASE 403A-03
1.2
2
SQUARE WAVE
2
2
0
Uj
1
*1
0.5-
60
0.6
80
90
100
110
120
13
TL, LEAD TEMPERATURE (*C)
Figure 5. Current Dereting - Junction to Lead
0.4
0
-
1.DIMENSIOING
AM TOLEACM PE ANS
Y4..5M IND.
2.
cODMIRUUM3DIMENSION: NCH.
3. 0DIMENHUMN SHAMSE MEASURED WIHIN
orMEMSION P.
-
-
t 0.2
4
70
ISSUE D
A
SQUARE WAVE
B
4EE 1ru
a
C
0
0.5
1
1.5
2
2.5
10, AVERAGE FORWARD CURRENT (AMPS)
Figure 6. Forward Power Dissipation
1
K a
mo
P
-
.
UMrf
.1
F
C
K2 -l
q1.UE+.U
IIIII
01.0E-01
MINIMUM SOLDER PAD SIZES
I
261
L1.0E-02
.0%
I~6
A
j!1.0E-03
551.0E0
0.106
Nil0) -RqirMt)
CI'
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
('')
1000
2.159
I. TIME (s)
Figure 7. Thermal Response - Junction to Case
11.0E+o
ON s.elosddutr Ad are gs.d
rademark of Seamlooductt Components Industries. LLC (SCILLOI
CILLC reserves aw dght to make
de wO
u IAwh nokto producU henrs SCLLC mis no waranly. eprsenation of Wsamsan egdaig the sUabty Of its Products for noy
particular pupos, nor dos SCLLC assume any Nabity aising oUtat the appication or use of any podtow circult. and specifcaly disclaims any nd al
labilly,
din w Int Itator special. consequetal or Incidenli dmaiges.
parameters idh may be provided inSCILLC data shees ani/or
-peais
can and do vary indifleetpplicatios and actual perorman e nay very over ine. AN opsatng parameters, including Typials"must be
sildtdfor each custoer apliien by customer's tednical expets. SCt.LC doesnot cowney ay ikense
Its patent
ts the
nor
of oters.
SCILLC produwis are" deoIgned, ended. or alhodzed for use as components insystems Iaended for surga implantnto th bodysrothar appiations
ttended to support or sulainge or for any other q
Otnkn
inwhich lhe
falure of to SCILC dI could create a situation where personal inury or deadt
may occur Should uyetr purctase or use SCILLC products for any su Unintended or usathodt ed applicadon. Buyer shal Indemnity and hold SCLLC
andoiollows. employees. subiiries, afilates, and distribuors harmless against al claims. costs. damages, and expenses, and reasonable attomey fees
adet Wut
of, drecy or innreciy. any claim of personal " or daO associated with such Unintended or unauthitzed Use, ever it such claim aleges tat
SCILLC was ne nt regardintit design or martacture of te part. SCLLC is an Equal Opportunity/Airmative Acion Employer.
S21.OE-01
"Typicl
nder
D1.0E-02
-c
111111111
-1.0E-03
021.0E-04
0.00001
0.0001
0.001
111111111
111111111
0.01
0.1
, TIME
111111
1.0
(s)
Figure S. Thermal Response - Junction to Ambient
10
100
1000
PUBLICATION ORDERING INFORMATION
ULerlurn Fuiment:
Literature Distibusot Center ot ON Seticondtoit
http://onsmLcom
3
JAPAN: ON Semiconductor. Japan Customer Focus Contsr
2-9-1 Kamineguro, Msguro-ku, Tokyo, Japan 153-001
P.O. Box 5163, Denver. Colorado 0217 USA
Phone: 81-3-773-3850
Phon : 303-675-2175 or 800-344-3060 Toll Free USA/Canada
Eml: r4525@onsooLcom
4
Fax: 303-675-2176 sor 800-344-3667Toll Foss USAlCatoooelstsloNknElotniso
Senalconuclor Webefte:
4-3ku
Es: OM
nona ntion
o
N. ArawleinTechnical Support: 800-282-9&%0 Tol Free USACanada
4@h
7 TtON
dgts
hpj/onsoom.com
ont
MBRS260T3/D
Power Schottky Diode Search Results
NOTE: All specs are at 25 degrees C
Bold=direct spec number (not read off graph)
Italic=Maximum value
Non-Bold=Read off of spec sheet graph
Comparison of power Schottky diodes
Manufacturer
ON Semi
ON Semi
ON
Sem
iR.
ST
Part #
lo
Fw1
MBRS1540T3
Curr
[A]
1.5
SS22
2
I
SS24
Z S2000
1OMQ040N
2.1
2
ST
ST
40
20
40
1
ISTPS2L40U
2
STPS2L60
2
2
STPS21-100
ST
2
ST
I STPS2H100A i
I STP2150 1 2__
S
I3,
ST
1N5820
1 N5820
1 3
IR
Dodes InI N5820-1N582 l. 3
1 3 1
I
1N5820
MCC
3
1N5821
MCC
1N5822
3 1
MCC
1
ST
T 1N5821
3
31N5822
ST
5T1 STPS3L25S525
T
ST
I STPS
15
ST
STPS15L25
Fairchild
ES3A-ES3D
0 10Ol 5
Fairchild
1N5821
3
30
Fairchild
FaichIld
SS22-SS24
3
40
2
20, 34
.ishy
L2_
3
.__
2 00
42
?? 170
170
?? 0
200
320
3040
0N5820-1N5822
20,30
Cd
Cd
VR=10v
at VR=25v
at 1MHz
[pFj
78
5
85
I5
51
50
23
90
90
110
49
1
1
1
33
?? 120
?? 120
?? 120
50
1
215
[VI
4
0.
35
0.435
0.385
[Vj
44
0.5
0.4
065
0.45
0.39
0.45
0.43
0.5
I
Package
It=
at
V]
0.48
_
SMB
SMB
0.45
SMB
0.545
0.615
0.5
0.5
0.415
0.395
Vt
Vf
atlt=2
0.285
0.32
0.48
0
1
0.456
J
0.6951
0.6
100
0.39
500
0.285
SMA
DO-41
1 SMA &SMB
~SMA
DO-201AD
Unnamed axial
_O-201AD_
DO-201 AD
SMC
SMC
TO220, D2PAK
TO220, D2PAK
0365
003
0.42
~
0~.~
0535
0.45
0.325
DO-201AD
DO-201AD
DO-201AD
DO-201AD
I
0.38 0.4571
04150.51
0.34
S0T23-6
SMA
SMB
SMA
SMB
0.82
09
0.783 _0.86
22 _
0.83
40
1 0.72 t 0.79 1
30
~0.75 ~0.780.82~
0.87
0.475
120
0.355
0.38
0.365 1 0.385
0.41 0.475
N/A
80__ _03
0.4 I 0.48
0.38 0.475
110
1 0.325 1 0.355
0.46 0.5
2110
.38
0.435
0.45
0.5150.5550.525
110
~~2005
0.38
0.5
042
0.525
8
0.37
0.46
0.49
90
0.42
85
0.425
0.5
0.465
.39
0.
520
0.36
0.375
0.36
920
0.34
24
t0
0.875
0.925
?? 73
? 73
?? 73
1100
__ 1900
Vt
atlf=1
at 1MHz
[pF]
125
180
125
1 180
180
j 230
73
60
105
33
44_
100
82
1
61
100
61
_
43
150__
I280
200
20
20
350 1 230
20,30,40
150 __120
1 250 1 170
20
170
250
30
1 250
170
40
0
201200
110
40
170
120
180
'
180
120
25
1100
.
810
1250
2000
25
33
1 N5822
at
52_____
4
25
30
40
1N5820
Fairchild
Cd
at VR=5v
at 1MHz
[pFl
100
1
100
[V}
2
2
STPS2L25U
Vr
Reverse
Voltage
SMC
DO-201AD
DO-201AD
75 0.525
_
048
0.355
DO-201AD
~
DO-201AD
SMC
Package information: SMA, SMB, SMC are 2-lead surface mount packages, in order of increasing size.
The SOT23-6 is a 6-lead surface mount package
The DO-41, DO-201 AD, T0220 are through-hole packages
MCC stands for Micro Commercial Components
Table C.1: Results of a search for power Schottky diodes rated for I0 ;> 1.5A. Some of the
components listed are clearly unacceptable because of high VF or CD, but are shown for
reference.
-
146
-
NOTE: All specs are at 25 degrees C
Bold=direct spec number (not read off of spec. graph)
Non-Bold=Read off of spec sheet graph
Comparison of 60 volt power Schottky diodes
l
Vr
1 Cd I
0i
lForw. Reverse IatVR=10vI
Part #
Manufacturer
MBRS260T3
OnSemiconductor
.MBRS6T3
ST
SS26T3
3
12
2
60
I
s
r
T21
7iT~F
CT
t-3-t
Vf
MAX
at
[V1
If=3
If=3
i
0.565
0.645
0.55
0.565
0.645
07-
120 1
i9OT
607-
Package
Vf
TYP
at
If2
0.725
- -T
1
Vf
TYP
at
[
.674
7
0.74
0.63
0.725
..-j 0.6 1 0.695
105j 0.555 1 0.62
0.47
23
0.473 _
900
0.375
0.4
i~sTT
Fr2i60
""S356
I
8
60_
S TPS2L60O
160j
60.1
STPS3L60U I
STPS560
5
60 J
STPS41L6OCG 20 1 60
""
Vt
MAX
at If=2
!Curr.Voltage
at1MHz
[Al
[V_
[pF_ _ [
521 0.63
2
60
0.61
-
-1
-
-
-
i1-
T
-
SMB
SMB
SMB
SMA
SMB
Do27trouhhoi
T0220 Dual Common Cath.
-
0.7
079-
SMB
- SMC
SMB
-
-=
--------
Note: The only apparent difference between the OnSemiconductor MBRS26OT3 and the OnSemiconductor SS26T3 is 60A vs. 40A
non-repetitive current
Table C.2: Results of a search for power Schottky diodes rated for VRRM = 60V and for
I > 1.5A. Some of the components listed are clearly unacceptable because of high CD,
but are shown for reference.
-
147
-
Appendix D
Measured LDMOS Device Data
D.1
Introduction
This appendix contains measured data for M/A-COM MAPLST0810-030CF and the Freescale
MRF373ALSR1, the two devices characterized for this design. The characterization allows
more accurate PSPICE modelling of the devices to facilitate a final device choice, as explained in chapter 3. AC and dc measurements are given, along with information about the
experimental setups.
D.2
AC Measurements
Table D.1 contains impedance analyzer measurements of Coss, CIss, and the ESR and
ESL of each capacitance for the two devices. Tables D.2 and D.3 describe the process of
calculating the parameters Cio, M and V of equation 3.5. The following MATLAB file,
called lookzero.m, is referred to in tables D.2 and D.3, and is used to solve for M and Vj.
% MATLAB file lookzero.m used for finding the parameters M and VJ in the
% equation for Coss) using measured values of Coss at two values of Vds,
%plus Cjo, the value of Coss at VDS=OV.
% This file uses the built-in function fzero, which finds the zero
% crossing of a function. Note that the measurements must be provided
% twice identically, once in the function and once outside of the function.
X Created by Juan Rivas and David Jackson
function lookzero()
format long;
%clear the console (optional)
cdc;
cjo=161.13E-12;
Xcjo = Coss at vds=O from measurement
%%%% Measurement point 1:
vdsl=8;
% voltage at which measurement 1 is made
cossl=70.897e-12;
% measurement 1
%%%% Measurement point 2:
vds2=22;
% voltage at which measurement 2 is made
coss2=51.934e-12;
% measurement 2
m=fzero(Ogoal,1)
% find the zero crossing of the function
% named "goal" with initial guess of 1
X Goal is defined below.
% This line also prints M to the console
var1=(cjo/coss1)^(1/m);
Vj=vdsl/(varl-1)
% Calculate and display Vj
-
149
-
Measured LDMOS Device Data
%%X Begin function defintion for "goal"
function [result]=goal(m)
cjo=161.13E-12;
%cjo = Coss at vds=O from measurement
%% Measurement point 1
vdsi=8;
% voltage at which measurement 1 is made
cossl=70.897e-12;
% measurement 1
%%% Measurement point 2:
vds2=22;
% voltage at which measurement 2 is made
coss2=51.934e-12;
. measurement 2
vari=cjo/cossi;
var2=cjo/coss2;
funI=vdsi/(1-(var1^(1/m)));
fun2=vds2/(i-(var2^(i/m)));
result=funi-fun2;
% return the difference of the two functions
% End function defintion for "goal"
D.3
DC Measurements
The measurements of RDS vs. VDS are shown below for the M/A-COM MAPLST0810030CF (Table D.4) and the Freescale MRF373ALSR1 (Table D.5).
-
150
-
D.3
DC Measurements
Measurements of the M/A-COM MAPLST0810-030CF (part number 2) made on 10/28/04 by David Jackson
Freauency (MHz)
Equivalent Model for Coss
Coss (pF)
1 10 1 20 1 100 1 160
Vda
Vds
1
Coss
ESR
ESL
0.00
85.915 J 86.711
87.030
96.451
117.990
DC volts
pF
mOhm
nH
2.00
58.453
61.835
57.903 I 57.767
0.00
69.842
79.720
98.265
3.108
49.402
49.370
49.455
52.540
58.188
4.00
0.00
75.958
- 1 3 1 .5 7 0 , 3.062
6.00
45.391
45.329
45.371
47.871
52.524
2.00
57.076 205.140 3.039
8.00
42.956
42.889
42.944 I 45.211
49.299
2.00
54.161 1-204.800
3.053
10.00
40.430
40.367
40.372
42.399
45.951
4.00
49950
219.420
3.062
12.00
38.870
38.821
38.828
40.700
44.000
4.00
47.559 j-223.250
3.182
14.00
37.560
37.538
37.572
39.332
42.402
16.00
36.773 1 36.715
36.720
38.394 1 41.285
18.00
35.913
35.880
35.918
37.484
40.250
20.0
35.397
35.306
35.336
36.882
39.487
22.0
34.458
34.485
34.491
35.960
38.494
24.0
33.906
33.882
33.918
35.347
37.797
Equivalent Model for Ciss
Vds
Ciss
26.0
33.488
33.451
33.459
34.847
37.227
ESR
ESL
Cls (2F
(
I
(MHz)
Coss
nH
Frequency (MHz)
mOhm I
pFI
No
DC
bias
62.262
Vds
1-315.980
3.152
1
1
1
10
1
20
1100
160
No DC bias I62.676 j-310.230J 3.132
No DC bias 1 62.494 1 62.534 I 62.700 1 68.001 I 78.462
]
Measurements of the Freescale MRF37
Coss (pF) Freq (MHz)
Vds
1
159.57
0.00
161.13
2.01
101.8
101.91
4.10
85.896
85.955
6.08
77.149
77.174
8.00
70.897
70.9
85.674
10.0265.679
61.499
61.487
12.00
14.03
58.061
58.033
15.97
55.49
55.526
18.05
53.736 53.687
20.0
52 714T 52.666
22.0
51.934
51.881
24.0
51.255
51.302
26.0
50.762 I 50.707
28.0
50.332 ' 50.274
49.894
30.0
49.956
Freq (MHz)
Vgs
1
10
0.00
109.67
109.89
|10
t
t
Model
D
E
D
E
D
E
Model
E
E
i (part number I of 5)
made 11/16/04
Equivalenf Model for Coss
Vds
Coss
ESR
ESL
1 Model
DC volts
pF
mOhm
nH
.
0.00
157.05
300.81
2.8381
D
0.00
156.66
304.13
2.8451
E
1.99
101.38 J290.59
2.8566
D
1.99
101.12 1 295.581
2.8629
E
Based upon the above measurements, estimate
package inductance from drain to source as
LQ=ESL=2.84nH, and RSCOSS=ESR=0.3 ohms.
Based upon the data below, estimate
RGATE=ESR=0.3ohms. Gate inductance
measurment is high. Use 1 nH in simulation instead.
Equivalent Model for Ciss
Model
Ciss
ESR
ESL
Vgs
pF
m0hm
nH
0.00
296.06
3.4912
0D101.66
0.00
100.76 1 312.84
3.5163
E
Equipment: Agilent 4395A. Agilent 43961A RF impedance test adapter. Agilent 16092A spring clip fixture. DC power supply: CircuitSpecialists.com
HY3002D-3 connected by aligator-to-BNC coaxial cable to analyzer. Analyzer compensation done w/ DC source connected, set to OV.
Environment: Measurements not made in cleanroom. DUT and analyzer contacts cleaned with lab wipes.
Analyzer settings: Impedance Analyzer Mode. Sweep from 500kHz to 500MHz with intermediate frequency of 30Hz. Averaging factor = 4.
DUT Setup: To measure Coss, solder short from Gate to Source, measure Drain to Source capacitance. To measure Ciss, solder short circuit from Drain
to Source, measure Gate to Source capacitance. Ciss and Coss measured using series capacitance measurement setting. Equivalent Model measured
using impedance magnitude measurement setting. Model D: series RLC. Model E: series RLC in parallel w/ an additional capacitor (value not listed)
Accuracy: Vds is accurate to within +/- 0.01v for VDS=0 to 20V, and to within +/- 0.1v for VDS>20V. Voltages measured using handheld voltmeter.
Units: Vds and Vgs have units DC volts. All capacitance values are in pF.
Table D.1: Impedance analyzer measurements of the Freescale MRF373ALSR1 and the
M/A-COM MAPLST0810-030CF.
- 151
-
Measured LDMOS Device Data
M/A-COM MAPLST0810-030CF Coss analysis
Goal: Determine the parameters Qjo, M, and VI in the equation Coss = jo*(1 (1+VdsNj))M
Method: Use the Coss data measured at 1MHz and shown in the previous table. Cjo is Coss at
VDS=OV. Using Matlab script lookzero.m, solve for m and Vj given Coss at any two non-zero points.
The resulting Vj and m are:
Using Coss at VDS=: 2V and 16V 4V and 26V 6V and 24V 8V and 22V 1OV and 16V
resultant Vj: 0.532765
0.332008
0.333514
0.377116
0.264199
resultant m: 0.247042
0.215433
0.216733
0.223556
0.205969
Calculate Coss from VDS=2V to 16V using Coss = Cjo*(1/(1+Vds/Vj))^M. Find the
minimum of the mean square error (MMSE) between the measured and calculated Coss:
Vds
2.00
Measured Coss
58.453
4.0
9.02
6.0 45.391
8.00
42.956
10.00
40.430
12.00
38.870
14.00
37.560
16.00
36.773
MSE:
--
2V and 16V
58.453000
50.624690
46.253908
43.300542
41.105571
39.377477
37.963194
36.773000
0.404348
Calculated Coss using VDS = :
4V and 26V 6V and 24V 8V and 22V
56.453029
56.357591
56.927089
49.402000
49.28192' 4.664468
45.522899
45.391000
45.657128
42.90902
42.769958
42.956000
40.965618
40.821757
40.948415
39.433351
39.286038
39.366379
38.176988
38.027082
38.069977
37.117575
36.965656
36.977455
0.640393
0.627699
0.410643
10V and 16V
55.195498
48426
44.758514
42.275659
40.430000
38.974402
37.780373
36.773000
1.555413
Conclusions: The best parameters in an MMSE sense are those found by solving the Coss
equation at VDS=2V and 16V. These parameters (Cjo=85.915, Vj=0.532765 and M=0.247042) are
used in the PSpice simulations of the MAPLST0810-030CF.
Table D.2: Solution to the non-linear Coss equation for the M/A-COM MAPLST0810030CF.
Freescale MRF373ALSR1 Coss analysis:
Goal: Determine the parameters Cjo, M, and Vj in the equation Coss = Co*(1/(1+Vds/Vj))AM
Method: Use the Coss data measured at 1 MHz and shown in the previous table. Clo is Coss at
VDS=OV. Using Matlab script lookzero.m, solve for m and Vj given Coss at any two non-zero points.
The resulting Vj and m are:
Using Coss at VDS = :
2,16
4, 26
6,24
8,22
10,16
resultant Vj:
0.67341
0.55836
0.64504
0.69152
1.13615
resultant m:
0.33216
0.3031
0.31416
0.32434
0.39286
Calculate Coss from VDS=2V to 16V using Coss = Cjo*(1/(1+VdsNj))M. Find the
minimum of the mean square error (MMSE) between the measured and calculated Coss:
Calculated Coss using VDS = :
Vds
2.01
4.10
6.08
8.00
10.02
12.00
Measured Coss
101.8
85.896
77.149
70.897
65.679
61.499
2V and 16V
101.799363
84.073280
74.920962
68.945924
64.314145
60.785591
4V and 26V
101.461068
84.708052
76.085080
70.446360
66.064010
62.716175
6V and 24V
103.307055
86.081263
77.148507
71.295386
66.743880
63.266950
8V and 22V
103.569261
86.003072
76.876557
70.897736
66.251661
62.705418
1OV and 16V
107.993407
88.406415
77.940098
71.041059
65.679280
61.596139
14.03
15.97
58.061
55.526
57.858632
55.525170
59.931586
57.705963
60.375897
58.066203
59.759219
57.407384
58.215171
55.526291
1.813236
1.592772
2.316906
1.427864
5.667533
MSE:
-
Conclusions: The best parameters in an MMSE sense are those found by solving the Coss
equation at VDS=8V and 22V. These parameters (Cjo=161.13, Vj=0.69152 and M=0.32434) are
used in the PSpice simulations of the MRF373ALSR1
Table D.3: Solution to the non-linear Coss equation for the Freescale MRF373ALSR1.
- 152
-
D. 3
DC Measurements
Measurements of Rds vs Vgs for M/A-COM MAPLST0810-030CF (part number 2)
0.000
Rds meth. 1
Opencir
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.800
9.1OE+07
3.64E+07
1.13E+07
3.25E+06
1.88E+05
4.76E+04
3.08E+04
1.900
1.83E+04
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
5.62E+03
2.88E+03
1.73E+03
Vas
Open cir.
Rds meth. 2 Rds norm
_ pencir.
_
0pn cir.
9.1OE+07
3.64E+07
1.13E+07
3.25E+06
1.88E+05
4.76E+04
3.08E+04
1.83E+04
5.62E+03
2.88E+03
1.73E+03
1.47E+03 1.47E+03
1.39E+03
7.77E+02
5.18E+02
3.74E+02
2.82E+02
241
241
4.900
3.100
140.66
140.43
.3.200
106.00
105.77
3.300
3.400
77.28
53.15
77.05
52.92
5.000
5.201
5.400
5.601
5.800
6.000
6.500
7.000
7.500
8.000
8.500
9.000
9.501
10.000
11.000
3.500
3.600
3.700
34.36
21.00
12.48
34.13
20.77
12.25
12.000
13.000
14.000
1.39E+03
777
518
374
282
3.000
183.6
Rds meth. 2
3.15
2.26
1.72
1.40
1.19
1.02
0.91
0.80
0.75
0.71
0.67
0.61
0.57
0.59
0.57
0.57
0.55
0.53
0.50
0.50
0.49
0.50
0.48
0.49
Vgs
4.000
4.100
4.200
4.300
4.400
4.501
4.600
4.700
4.800
183.4
Rds meth. 3
0.50
0.45
0.45
0.44
0.44
0.43
0.42
0.41
0.42
0.41
0.38
Rds norm Rds norm
method 2 method 3
2.92
2.03
1.49
1.17
0.96
0.79
0.68
0.57
0.52
0.48
0.44
0.38
0.34
0.36
0.34
0.34
0.38
0.32
0.33
0.30
0.27
0.27
0.33
0.26
0.32
0.27
0.25
0.26
0.32
0.31
0.30
0.29
0.30
0.29
7.26
15.000
7.49
3.800
0.26
1
4.47
16.000
4.70
3.900
Notes:
"meth. #"indicates that the column of measurements was made using method #.
"Rds norm" column contains Rds normalized (i.e. with test setup resistance subtracted out)
RDSON is specified by M/A-COM as 0.2ohms at 1 OV. For all PSpice simulations RDSON=0.29ohms is used
based upon these measurements.
Method 1: DC voltage supplied by Hewlett Packard 33120A 15MHz function generator set to DC
DC voltage verified with a Hewlett Packard 34401A multimeter
Rds measured with a second Hewlett Packard 34401A muhtimeter, set to ohmmeter (2W)
The built in resistance of this setup is not important, since it was only used to measure high resistances
Method 2: DC voltage supplied by Hewlett Packard 33120A 15MHz function generator set to DC
DC voltage verified with a Hewlett Packard 34401A multimeter
Rds measured with a Tektronix TX3 True RMS multimeter
The built in resistance of this setup is between 0.20 ohms and 0.25 ohms. For Rds norm calculation, we use 0.23
Method 3: DC voltage supplied by a Tektronix PS2520 programmable power supply
DC voltage verified with a Hewlett Packard 34401A multimeter
Rds measured with a Tektronix TX3 True RMS multimeter
The built in resistance of this setup is between 0.10 ohms and 0.13 ohms. For Rds norm calculation, we use 0.12
Table D.4:
RDS
vs. VDS measurements for the M/A-COM MAPLST0810-030CF.
Measuremernts of Rds vs
Vgs for Freescale
RIDS Norm
RIDS
<6_Meg_ _ < 6 Meg
_.6 Meg_ .6 Me.
6_.28 Meg_ _68_M
5.15 Meg
5.15 Meg
3.16 Meg
3.16 Meg
98.8 k
98.8 k
16.39k
16.39 k
1.038 k
1.038 k
87.35
87.23
__6.01
5.89
1.08
1.20
04
0.6
0.29
1
4.0 041
4.250F
0.35
0.3
VGS
0.0009
1.007
1.502
1.750
2.005
2.250
2.500
2.750
3.000
3.250
3.500
3.750
MRF373ALSR1 part 1
VGS
4.500
4.750
5.000
5.250
5.504
5.750
6.000
7.000
8.001
9.000
10.000
100
12.000
AD
0.30
0.30
0.31
0.32
0.30
0.30
0.29
0.29
0.28
0.28
0.28
027
0.25
RDS Norm
0.18
0.18
0.19
0.20
0.18
0.18
0.17
0.17
0.16
0.16
0.16
0.15
01
<-RDSON value
4______
"RDS Norm" column contains Rds normalized (i.e. with test setup resistance subtracted out)
"RDSON value" indicates the voltage at which Freescale measures RDSON, 1bV
This value (0.16) is used for all PSpice simulation of the Freescale MRF373ALSR1
Measurement Setup: DC voltage supplied by a Tektronix PS2520 programmable power supply
DC voltage verified with a Hewlett Packard 34401 A multimeter
Rds measured with a Tektronix TX3 True RMS multimeter
The built in resistance of this setup is measured as 0.08 to 0.13 ohms before measurement,
0.09 to 0.11 ohms after the measurements. For 0.12 ohms is used for RDS Norm. calculation
Table D.5:
RDS Vs- VDS
measurements for the Freescale MRF373ALSR1.
- 153
-
Appendix E
Derivation of Multi-resonant Topology
Equations
This appendix contains a derivation of Eqs. 3.5, which govern the relationships between the
various components of the multi-resonant circuit shown in Fig. 3.11 and repeated here for
reference. This derivation is reproduced from [34} with permission.
The impedance of the parallel part of this circuit, labelled Zp, is
Zs = sL 3 +
1 1+s
2
=
SC3
L 3 C3
(E.1)
sC 3
The impedance of the series part of this circuit, labelled Zs, is
Zp =
iC
sC1
sLi
_C___
sL1
+
1+s
C1
2
1
LiC
sLj
+ s 2LC
(E.2)
1
(
The parallel combination of these two impedance is
ZI9 = Zs|Z=(sLi)(1
S 1Z
2
+ s2 L3 C3 )
0I3 1+sTLiCi
3C____)_______________
1 + s 2 (L 1C1 + L3 C3 + LiC 3) + s4 L 1 C 1 L 3 C 3
sL
2
1+s L3C 3
sC3
1+s LiCi
(E.3)
We are concerned with the magnitude of this impedance, which is
(wLi)(1 - w 2 L 3 C 3)
I - w (L 3 C3 + L 1C1 + L1 C 3)+ W4 (L1C1L3 C3 )
2
ZP
ZS
LMR2
CMR1
LMR1j
CMR2
ZMR
Figure E.1: Idealized MR topology for controlling the first three harmonics, same as
Fig. 3.11.
- 155
-
Derivation of Multi-resonant Topology Equations
IZIN I peaks when:
1-w
2
1
--1
+
[122
1]
+
i
wJ
+
U41
;4-
1
0
0
(E.5)
where we define wil as the resonant frequency between LMR1 and CMR1, w12 as the resonant
frequency between LMR1 and CMR2, W22 as the resonant frequency between LMR2 and
CMR2. Solving Eq. E.5 gives
[1
[iU)2
1
+
1 ]=
,
(E.6)
2± +~ 2
Wil
W12 J
][ -±-±-1
]
-3
which leads to
[2
+W2 +
(E.8)
= W 22
1 1W2 2
1
WllW22
We want W22 = 2ws. Therefore wil =
10w2
1;
1
[1
w12
W11
WE 2
(E.7)
(E.9)
3ws
=
ws
Now putting these values in Eq. E.8:
4
9
1
1i2
1
1 [10
WS
9
1
1
10
+ 42
2
9L2
_ 1
4
[
9J
12
40--9-16
36
2
_WS
S
2
W12
(E.10)
12w2
(E.11)
(E.12)
To get the resonance at first and third we need:
Wil =
-
3
156
S
-
(E.13)
W22
(E.14)
= 2wS
(E.15)
W1 2 = V
In terms of component values given C1 and harmonic frequencies, these equations become:
1-
-
Wi
9
4
Li =
1
LC3 .'. C3-
-22wS
12
4
4
=
(4
9CiWS
9C1 (47r2 fS
_
LiC1 .-. L,
1
9C,17r2
(E.16)
(E.17)
f
45
48
5
5
12L 1 w2
12
--- 7
9Ciow
8
8
45
C3 -= -- C4
(E.19)
48
1
W22
1
-
1
1
-
Sw
L 3 C3
3
4C30S
3
45C17r2 fS
-157-
(E.18)
4
[4-C 1]
1
15C 1 7r 2 fS
wg
12
^ 45Cjw 2
(E.20)
(E.21)
Appendix F
for Compensating
Impedance Analyzer Measurements
MATLAB Code
The following code is used to compensate an impedance analyzer measurement for the
series inductance of the measurement leads. This is useful only if all other parasitics (such
as parallel capacitance) are negligible. The file contains instructions for use.
XMatlab code for making differential measurements using an Agilent 4395A impedance
%analyzer.
%In order to cancel the inductance of the leads used in
7.measuring impedance for the multiresonant gate driver
7.we subtract the measurements done on a test pcb board
%with the same leads used for the real measurement
%We must make sure that the only contribution of the leads
Xis series inductance. This requires us to minimize the possible capacitance
Xthat results from having the ground plane of the circuit on top of the
Xground plane of the test fixture of the impedance analyzer.
%To use this file, the analyzer should be set with only "Data" turned on in the
X"Define Save Data" menu under the "Save" menu. The user should then do a "Save Data"
%in ASCII format. The data saved by the impedance analyzer is only the reflection
Xcoefficients vs. frequency, which is why the conversion done below to an
Ximpedance measurement is necessary
XCode written by Juan Rivas, modified by David Jackson
cdc;
clear all;
ZO=50; X[Ohms]Characteristic impedance of the spectrum analyzer
XXXRead the data for the reference measurement
FILENAMEREF='IMPO14.TXT';
GLREF=dlmread(FILENAMEREF, '\t' ,14,0);
XX/Obtain frequency and complex reflection coefficient vectors
FREQREF=GLREF(: ,1);
%Reference Frequency
GLREF=complex(GLREF(:,2),GLREF(:,3)); %Reference Reflection Coefficient
XXXCalculate complex impedance vector
ZREF=ZO.*(1+GLREF)./(1-GLREF);
XReference
Impedance
%%%Plot the reference magnitude impedance, phase and inductance
fl=figure
Xfla=figure;
subplot(2,2,1)
magZREF=20.*logiO(abs(ZREF));
a=semilogx(FREQREFmagZ-REF);
axis([min(FREQ-REF) max(FREQREF) min(magZ-REF)-5 max(magZREF)+5);
grid on;
- 159
-
MATLAB
Code for Compensating Impedance Analyzer Measurements
ai=xlabel('Frequency [Hz)');
a2=ylabel('Magnitude Impedance (dB \Omega)');
a3=title('Magnitude Impedance vs. Frequency');
set(a,'linewidthl,2);
%Plot the phase in degrees
%fib=figure;
subplot(2,2,2)
phaseZREF=angle(Z.REF)*180/pi;
a=semilogx(FREQREF,phase_Z_REF);
axis([min(FREQREF) max(FREQREF) 89 91]);
grid on;
ai=xlabel('Frequency [Hz)');
a2=ylabel('Phase Impedance (degs)');
a3=title('Phase Impedance vs. Frequency');
set(a,'linewidth',2);
%Plot the series inductance (nH)
LZREF-nH=le9.*imag(Z-REF)./(2*pi.*FREQREF);
'fic=figure;
subplot(2,2,3)
a=semilogx(FREQREF,L_Z_REFnH);
axis([min(FREQ-REF) max(FREQREF) min(LZREFnH) max(LZREF-nH)]);
grid on;
ai=xlabel('Frequency [Hz)');
a2=ylabel('Inductance [nH');
a3=title('Inductance vs. Frequency');
set(a,'linewidth',2);
%%Read the data for the reference measurement
FILENAMEM='IMP045.TXT';
GL.M=DLMREAD(FILENAMEM,'\t',14,O);
XX'Obtain frequency and complex reflection coefficient vectors
FREQ_M=GLM(:,i); %Frequency vector for the measurement
GL_M=complex(GLM(:,2),GL.M(:,3)); X.Meas Complex Reflection Coefficient
ZM=ZO.*(1+GLM)./(I-GLM); %Measured Impedance Column vector
%%%Plot the reference magnitude impedance, phase and inductance
XPlot
the impedance magnitude in dB Ohms
f2=figure
Xf2a=figure;
subplot(2,2,I)
mag-ZM=20.*logIO(abs(ZM));
a=semilogx(FREQ-M,magZ-M);
axis([min(FREQM) max(FREQM) min(magZM)-5 max(magZM)+5));
grid on;
ai=xlabel('Frequency [Hz)');
a2=ylabel('Magnitude Impedance (dB \Omega)');
a3=title('Magnitude Impedance vs. Frequency');
set(a,'linewidth',2);
'Plot the phase in degrees
Xf2b=figure;
subplot(2,2,2)
phaseZM=angle(ZM)*180/pi;
a=semilogx(FREQM,phase-ZM);
axis([min(FREQM) max(FREQM) -100 100));
grid on;
ai=xlabel('Frequency [Hz)');
a2=ylabel('Phase Impedance (degs)');
a3=title('Phase Impedance vs. Frequency');
-160
-
set(a,'linewidth',2);
%Compensate the measurement by subtracting the reference measurement
Xfrom the measuremnt of interest:
Z-comp=ZM-Z-REF;
XPlot the magnitude of the compensated vs. the uncompensated
magZ-comp=20.*logIO(abs(Z-comp));
Xf3=figure
f3a=figure;
subplot(2,2,1)
a=semilogx(FREQM,magZM,FREQ_M,magZ.comp);
axis([min(FREQM) max(FREQ-M) min(magZM)-5 max(mag-ZM)+5]);
grid on;
al=xlabel('Frequency [Hz]');
a2=ylabel('Magnitude Impedance (dB \Omega)');
a3=title('Magnitude Impedance vs. Frequency');
a4=legend('Raw Measurement', 'Compensated',3);
set(a,'linewidth',2);
XPlot the angle:
phaseZ-comp=angle(Z-comp)*180/pi;
%figure;
%f3b=figure;
subplot(2,2,2)
a=semilogx(FREQM,phase_Z_comp);
Xaxis([min(FREQM) max(FREQM) -90 -88]);
axis([min(FREQ-M) max(FREQM) min(phaseZ-comp)-5 max(phaseZ-comp)+5); %ADDED BY D. JACKSON
grid on;
al=xlabel('Frequency [Hz]');
a2=ylabel('Phase Impedance (degs)');
a3=title('Phase Impedance vs. Frequency');
set(a,'linewidth',2);
XPlot the equivalent capacitance
CZ-comp-pF=-1e12./(2*pi.*FREQM.*imag(Z-comp));
Xfigure;
subplot(2,2,3)
a=semilogx(FREQM,CZ-comppF);
axis([min(FREQM) max(FREQM) 100 170));
grid on;
al=xlabel('Frequency [Hz]');
a2=ylabel('Capacitance [pF]');
a3=title('Capacitance vs. Frequency');
set(a,'linewidth',2);
XXBEGIN added by D.Jackson 4/9/05
XPlot the Magnitude of only the compensated
magZ-comp=20.*logl0(abs(Z.comp));
Xf3=figure
f4a=figure;
Xsubplot(2,2,1)
a=semilogx(FREQM,magZcomp);
grid on;
al=xlabel('Frequency [Hz]');
a2=ylabel('Magnitude Impedance (dB \Omega)');
a3=title('Compensated Impedance');
set(a,'linewidth',2);
%peak and null detection
-- 161 --
MATLAB
Code for Compensating Impedance Analyzer Measurements
pkfreq=[];
pkmag= [];
pkindex=[);
nulfreq=[];
nulmag=[];
nulindex=[ ;
for ind=i:(length(FREQM)-2),
current=magZ-comp(ind);
nextmag-Z.comp(ind+i);
nextnext=magZ-comp(ind+2);
if (next>current & nextnext<next)
pkfreq='[pkfreq FREQM(ind+)];
pkmag=[pkmag magZ-comp(ind+)];
pkindex=[pkindex ind+1);
elseif (next<current & nextnext>next)
nulfreq=[nulfreq FREQM(ind+1)];
nulmag=[nulmag magZ-comp(ind+i)];
nulindex=[nulindex ind+1]
end;
end;
pkfreq
pkmag
nulfreq
nulmag
Xmeasure
the Q of the n'th null
n=1;
Xspecify the number of the null that you want to find the Q of
nulmag-n=nulmag(n);
nulfreq-n=nulfreq(n);
nulindex-n=nulindex(n);
up3db=nulmag-n+3;
Xgo
3dB up from this null
for ind=nulindex-n:length(FREQM+1),
current=mag-Z-comp(ind);
next=mag-Z-comp(ind+1);
if ((up3db>current & up3db<next)I(up3db==current))
upper3dbfreq=FREQ-M(ind);
break;
end;
end;
for ind=1:nulindex-n,
current=mag-Z-comp(ind);
next=magZ-comp(ind+1);
if ((up3db<current & up3db>next)I(up3db==current))
lower3dbfreq=FREQM(ind);
break;
end;
end;
Q=nulfreq-n/(upper3dbfreq-lower3dbfreq)
%Plot the PSpice data together with the impedance analyzer data, compensated
psp=load('Psp085b.txt');
invmagpsp=psp(:,2);
freqpsp=psp(:,1);
magpsp=20*logiO(I./invmagpsp);
figure(f4a);
hold on;
b=semilogx(freqpsp, magpsp,'r');
a4=legend('Compensated','PSpice',4);
axis([min(FREQM) max(FREQM) min(mag-Z-comp)-5 max(mag-Z-comp)+5]);
%axis([8e7 1e8 10 20]);
break;
%Plot the angle:
phase-Z-comp=angle(Z-comp)*180/pi;
subplot(2,2,2)
- 162
-
a=semilogx(FREQM,phase-Z-comp);
axis([min(FREQM) max(FREQM) -90 -88]);
axis([min(FREQM) max(FREQM) min(phaseZcomp)-5 max(phase_Z_comp)+5]); %ADDED BY D. JACKSON 4/9/05.
grid on;
al=xlabel('Frequency [Hz)');
a2=ylabel('Phase Impedance (degs)');
a3=title('Compensated Impedance');
set(a,'linewidth',2);
XPlot the equivalent capacitance:
CZ-comp-pF=-1e12./(2*pi.*FREQM.*imag(Z-comp));
subplot(2,2,3)
a=semilogx(FREQM,CZ-comp-pF);
axis([min(FREQM) max(FREQM) 100 170));
grid on;
al=xlabel('Frequency [Hz)');
a2=ylabel('Capacitance [pF]');
a3=title('Compensated Impedance');
set(a,'linewidth',2);
XXEND added by D.Jackson 4/9/05
-
163
-
Appendix G
Passive Component Datasheets
Shown below are the datasheets for many of the passive components used in the converter,
beginning with air core inductors (reproduced with the permission of Coilcraft) and followed
by mica chip capacitors (reproduced with the permission of Cornell Dubilier Electronics).
Refer to Tables 10.1, 10.3, and 10.4 for information about which parts are used.
- 165
-
Mini Spring- Air Core Inductors
Mini Spring Air Core Inductors
amE me"s
oaatONONWSIEOR C
Typical L vs Frequency
0e
-n
These surface mount air core "spring" inductors provide
extremelyhigh overawidefrequencyrange.
They're jacketed with a high temperature material that
ensures mechanical stability and very tight tolerance. It
also forms aflat top, making them suitable for automatic
placementand refloworvaporphaseprocessing. Solder
coatedleadsensurereliablesoldering.
FI
I
40
Coilcraft Designer's Kit C102 contains samples of all
5% inductance tolerance parts. Kits with 2% tolerance
are also available. To order, contact Coilcraft or visit
http://0rder.colleraft.com.
Part
number'
AOiT_
AO2T_
A03T_
A04T_
A05T_
B06T_
Bo7T.
BOBTB09T
B1OT_
1.
Men
Turns
1
2
3
4
5
6
7
8
9
10
Inductance2
(nH)
2.5
5.0
8.0
min
145
140
140
137
132
100
102
105
112
106
5,2
12.5
18.5
17.5
22.0
28.0
35.5
43.0
oring. pleane specify lowrnce
Q4
Percent4
tolerance
10
10,5,2
5,2
5,2
5,2
5,2
5,2
5,2
(MHz)
150
150
150
150
150
150
150
150
150
150
min
(GHz)
12.5
6.5
5.0
3.3
2.5
2.2
2.1
1.8
1.5
1.2
Irm'
(A)
4
4
4
4
4
4
4
4
4
4
MH
15
200
400
Frequency (MHZ)
IOD
600
4M0
no0
1oo
s0w
low
Frequency (MHz)
Qvs Frequency
ypical
20
DCR'
max
(mOhm)
1.1
1.8
2.6
3.4
3.9
4.5
5.2
6.0
.8
7.9
17.5
20
2' M
100
-
(Ms
135
Weight
(mg)
31
42
52
65
78
100
110
118
133
147
I
0
a
12.5
e5
M
150
code:
200
4110
FrOquOnM (MHZ)
100
"
A-
I
Encapoulant
D-
o
60
Recommended Land Patterns
31ZE0
SIZEA
E
0=ernc:
2% J.5% K.10%
AgeniHP 4288 with Cdi5cra SMD-A loxur and correlation.
2. Inducance
3. Tolenrse in bold am stocked for imrnsdate shiqont
4. 0 measussd using Agksnl/HP 4291A with Aglint/HP 16193A test itu
5. SRF tested on he Ageint/HP 8720D and the Soc-S test Sixturs.
6.OCR tested on to Cambridgo Tednoiogy Mods/510 Mtiro-ohmmeter.
7. Average curmnt for a 15"C rise above 25C ambientOperaing temperature range -40'C to .125"C.
o Eectrial specications at 25".
See Ouaelication Standards section fm nviraonental and test data
Io
rqu20n)
400
Frequency (MHz)
asured using
I-
Si
B --
4
0 .10
s
C 4
0 .124
2S
0x
i
A
A 1
sex
155
3,94
0.
0.'175
318
0.270
6.86
0.175
0.124
0.25
0.125 *0.010
2.92 .0.25
B
4.45
3.15
3.1600.25
5.84 .0.38
4.45
3.15
0.125 *0.010
1
E
0.115 *o.010
0.230.0o.015
max
Fn
0.029
0,74
0.029
0.165
0.74
.8
Strip Length
Tapiandedl:
700/rr- 1
Feopagong data ses Tape
T...... *.: TINed-e
6o&4aItL
Specifications
Pleass
check
1102 Stvor Lake Road
subject to change without notice.
our website for latest information.
Cery ioleO6013
E-maill
Docurent 107-1
Phone a47/e30-6400
Infoecoicraftcom
Web
Revised 01/30/03
Pox
847/539-1469
hop:/swcolcraftcom
&eoiead
and
Specifications sub10 10 change Without notio.
Please check Our elbifte for latest Iinaaton.
1102 Silver Lake
Roed Cry, noile80013
E-mall
500rir.4
/10lrer
R"
opper
Spedficae
Docunent
107-2
Phone 947/639-6400
lnroecollcrafLcom
2200f rre
se=
Revised
t*
t
25"
Fqn
5
Mini SpringTM inductos are availablein standard
EIA tape and reel packaging: 12 mm for size A, and
16 mm for size Bparts.
SRF
ma
30-
Coilcraft
Test
freq.
s n -- -
55
03/14/05
Fax 847/36g-1469
Web http://ww.collcraftcom
134-2
SDocument
Document 184-1
S-Purunmiw fur
Midi Spring' Air Core Inductors
Midi Spring-Air Core Inductors
Typical Qvs Frequency
Typical L vs Frequency
250
This family of surface mount Midi Springs inductors is
designed for highercurrent applications (up to 3.5 Amps)
than our smaller series. It also provides higher Q factors
at lower frequencies.
Like all Coilcraft "spring" inductors, these parts provide
the advantages of an air core inductor in a package
optimized for auto placement. The top of the coil is
capped with acrylic, forming a flat surface and assuring
mechanical stability. The leads are solder coated for
reliable soldering.
Coilcraft Designer's Kit C118 contains samples of all
5% inductance tolerance parts. Kits with 2% tolerance
are also available. To order, contact Coilcraft or visit
http:/lorder.coilcraft.com.
200
S120 nH
150
=10 S T T II
50
-
a-150
968 nH
8
39 nH
-
22 nH'
I
0 1000
e10
1 (00
Frequency (MHz)
5
Inductance2 Percent
Part
toterance3
(nH)
number
5.2
22
1812SMS-22N_
5,2
27
1812SMS-27N
5,2
33
1812SMS-33N5,2
39
1812SMS-39N_
47
1812SMS-47N5,2
56
1812SMS-56N_
5,2
68
1812SMS-68N.
82
1812SMS-82N
5,2
100
1812SMS-R1O
5,2
120
1812SMS-R12_
5,2
5,2
02
typ
min
135
135
130
135
135
125
120
120
115
125
100
100
100
100
100
100
100
100
100
100
39nH'
12 nH
100DO
so
1
10
100
1000
10000
Frequency (MHz)
5
DCR
Irma
Test SRF'
max max
min
freq.
(MHz) (GHz) (mOhm) (A)
3.0
3.2
4.2
150
4.0
3.5
2.7
150
4.8
3.0
2.5
150
3.0
4.4
2.1
150
3.0
5.6
150
2.1
3.0
6.2
1.5
150
2.5
8.2
150
1.5
2.5
9.4
1.3
150
1.7
1.2
12.3
150
1.5
17.3
150
1.1
1.hendomarngpsaient/el
2.
rit/
andteslodwdtoen
kokeker
correlaion.
HP 4nlAdedrah.AwertiIPO2Stdarde
3TolseanesinboldFretloCkedlor'
Wedl
SRADD ed lduS
5. OCR
8
518
leam
Tehog
Aragecurrentfora 15crieeabome 25-c
mbiend.
8
7.0pWrdintWmpWrluern-4-Cl
a.
Bcidp
iateiaio ni'25-C.
See oudratinlndedssetonor
envkronmental and test dea
Recommended
Land Pattern
E
--- -
max
A
0.195
4,95
8 max
0.250
6,35
j
F1r
mmx
C
0.165
4,20
D
0.140 *0.010
3,56 0,25
E
0.170o0.015
4,32 *0,38
Length
Sti
max
F
0.030
0.76
2.Sn
0228
SAC
0.10-0.168
weight:
T-m1tr.m: TWeed over copper
Tap. and eel: 507" reel; 2000113" reel 12 r tape Wih
For pakng dela see Tape and Redt Speficaiors seiodn.
0ec
Specifications subject to change without notice.
Please check our weboite for latest information.
.5
012
o'min
*A
Document
184-1
Revised 12/17/104
847/639-149
1102 Silver Lake Road Cary, ttmoisS 013 Phone 847/639-6400
E-maHl infolcoilcraft.com Web htp://www.coitcraftcom
Fax
4
Specifications subject to change without notice.
Please check our website for latest information.
Document
184-2 Revised 03/06/03
1102 Silver Lake Road Cary, Illinois 60013 Phone 847/639-6400 Fax 847/639-1469
E-mal ino@coilcraft.com Web http://vww.colicrat.com
Types MC and MCN Surface-Mount Mica Chip Capacitors
Types MC and MCN Surface-Mount Mica Chip Capacitors
High-Frequency, High-Stability Chips for RF Amplifiers, Transmitters and CATV
Typical Performance Curves
New Type MCN Nonmagnetic Chips for Ultra-High Frequency and MRI Applications.
With self-resonant frequencies typically above one gigahertz for
popular RF capacitance values and with a Q above 2,000, Type
MC capacitors are the answer for high-frequency public-service
radio communication, flight radio and cable television. The natural
mica dielectric retains its high-Q to many megahertz, so higher and
higher frequency applications are limited by the circuit inductance,
not the Type MC capacitor. Now new nonmagnetic Type MCN
chips are available for MRI and other ultra-high frequency
applications that use more expensive porcelain ceramic chips.
Highlights
Specifications
00
Ratings
Part Nomber
O5
MCOMCAORSD
MC08CA010D
Type
(pF)
68
75
0805
50
MCO8FA60J
MCM8FA750J
MCO8FA820J
MCO8FA910J
MC08FA10IJ
MC12FA470J
MC12FA500J
51
56
62
68
75
MC12FA510J
MC12FA560J
MC12FA620J
MC12FA680J
MC12FA750J
1210
1210
1210
1210
1210
360
390
430
250
270
300
330
360
390
82
91
100
110
120
130
150
1210
1210
1210
1210
1210
1210
1210
1210
1210
1210
1210
100 Vdc
MC08CA020D
0805
82
MC08CA030D
MC08CA040D
0805
0805
91
MC08CA0550
MCOBCA060D
0805
0805
0805
47
5.0
6.0
7.0
8.0
9.0
10'a
MCo8CA070D
MC08CAD800
MC08CA090D
MC08CAIOOD
12.0
15.0
180
20.0
220
24.0
27.0
30.0
33,0
360
MCO8EA12DJ
MC08EAI5OJ
MCO8EA180J
MC08EA200J
MC08EA220J
MC08EA240J
MC08EA270J
MC08EA30W
MC08FA330J
MC08FA360J
39.0
MC08FA390J
43.0
47.0
50.0
51.0
MCO8FA430J
MC8FA470J
MCO8FA500J
MCW8FA51J
MC08FA560J
MC08FA620J
560
620
Cornell Dubilier - 1605 E. Rodney
0805
0805
0805
0805
0805
0805
0805
100
0805
160
0805
0805
0805
0805
0805
0805
180
200
MC12FA82GJ
MC12FA910J
MC12FA101J
MC12FAIIJ
MC12FA12IJ
MC12FA131J
MC12FA151J
MC12FA161J
MC12FA11J
MC12FA20IJ
220
240
250
270
300
330
MC12FA221J
MC12FA241J
MC12FA251J
MC12FA271J
MC12FA301J
MC12FA33IJ
0805
0805
0805
0805
08'5
0805
French
Frequency (MHz)
Capacitance (pF)
RF Communication
0805
3.0
1000
1
.
000
too
CATV
Type
2.0
4.0
CA
0
Transmitters
Part Number
0W5
Q
Amplifiers
(pF)
100 Vdc
1'0
*
.
Voltages: 100 Vdc, 500 Vdc, and 1000 Vdc
Capacitance Range: 0.5 pF to 2,200 pF
Capacitance lolerance: ±0.25% to ±5%
Temperature Range: -55 *C to +125 *C
n , 12 ,0112 , and 2223n
Q 1es: 080
r, ase Si
case
catalog
catalog
case
cap
Cap
catalog
cap
(pF)
CA
Applications
MRI coils
Tuned circuits
RF Instruments
New, great-value, nonmagnetic MCN chips
- Low ESR/ESL to > I GHz. Q > 2000
- Exact-values ±0.25% 100 pF, V up to 1000 V
- Free from thermal cracking, 270 *C OK
- High RF current - dV/dt 20,0(X) V/ps
- Withstands 200% rated voltage
- Rock stable; No change with time, V & f
-
Capacitance vs. Frequency
Q vs. Capacitance
0805
0805
0806
0805
1210
1210
1210
1210
1210
Part Normber
100 Vdc
MC12FA361IJ
Q vs. Frequency
10.2bZ
10000
+0.1
Type
MC12FA431J
MC18FA251J
MC18FA271J
MC18FA301J
MC18FA331J
MC18FA361J
MCI8FA391J
430
MC18FA431J
1812
470
500
510
560
620
580
750
820
910
1000
1100
1200
1500
1800
2000
2200
MC18FA47IJ
MC18FA501J
MC18FA511J
MC18FA561J
MC18FA62IJ
MC18FA88IJ
MC18FA75IJ
MC18FA821J
MC22FA91IJ
MC22FA102J
MC22FA112J
MC22FA122J
MC22FA152J
MC22FA182J
MC22FA202J
MC22FA222J
1812
1812
1812
1812
1812
2-0
U -0A1
1000
DO Ia
e,-0.51 ___-0.3__
1
10
Frequency (MHz)
1210
1000
100
-5
125 C
25*C
Resonant Frequency vs. Capacitance
10
100 a
k'Cz
10
C
Temperature
Impedance vs. Frequency
1812
1812
1812
2220
2220
2220
2220
2220
2220
2220
2220
0
o1
Case
1210
1210
1210
1812
1812
1812
1812
1812
1812
MC12FA391J
% Capacitance Change vs. Temperature
L
'
-
l
t
A
1
.
CL
10
100 MHz
0.1
1
10 GHz
1G
Frequency
100 GHz
10
100
1000
Capacitance (pF)
1210
Blvd. - New Bedford, MA 02744 - Phone: (508)996-8564 * Fax: (508)996-3830 - www.cde.com
Comell Dubilier - 1605 E. Rodney French Blvd. * New Bedford, MA 02744 . Phone: (508)996-8564 - Fax: (508)996-3830. www.cde.coo
Bibliography
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[22] J. Phinney, J. Lang, and D. Perreault. Mulit-resonant microfabricated inductors and
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[23] F. Terman. Radio Engineering, page 23. Electrical and Electronic Engineering Series.
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