Jaehan Koh (jkoh@buffalo.edu)
Ph.D. Candidate
CSE Dept., SUNY at Buffalo
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Introduction
Verilog Programming on Windows
Verilog Programming on Linux
Example 1: Swap Values
Example 2: 4-Bit Binary Up-Counter
Summary
X-Win32 2010 Installation Guide
References
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Verilog
o A commonly used hardware description language (HDL)
o Organizes hardware designs into modules
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Icarus Verilog
o An open-source compiler/simulator/synthesis tool
• Available for both Windows and linux
o Operates as a compiler
• Compiling source code written in Verilog (IEEE-1364) into some target format
o For batch simulation, the compiler can generate an intermediate form called vvp
assembly
• Executed by the command, “vvp”
o For synthesis, the compiler generates netlists in the desired format
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Other Tools
o Xilinx’s WebPack & ModelSim
o Altera’s Quartus
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Verilog Programming on Windows
o Use Icarus Verilog
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Verilog Programming on Linux
o Remotely have access to CSE system
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Downloading and Installing Software
o Icarus Verilog for Windows
• Download Site: http://bleyer.org/icarus/
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Edit source code using a text editor
o Notepad, Notepad++, etc
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Compiling Verilog code
o Type “iverilog –o xxx_out.vvp xxx.v xxx_tb.v”
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Running the simulation
o Type “vvp xxx_out.vvp”
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Viewing the output
o Type “gtkwave xxx_out.vcd”
o An output waveform waveform file xxx_out.vcd (“value change
dump”) can be viewed by gtkwave under Linux/Windows.
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Icarus Verilog under CSE Systems
o Have access to [timberlake] remotely using
• [X-Win 2010] software
• [Cygwin] software
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How to check if the required software is
installed
• Type “where iverilog”
• Type “where vvp”
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Edit source code using a text editor
o Vim, emacs, etc.
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Compiling Verilog code
o Type “iverilog –o xxx_out.vvp xxx.v
xxx_tb.v”
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Running the simulation
o Type “vvp xxx_out.vvp”
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Swapping inputs
o Swap the first bit with the second, the third with the fourth.
o E.g., 0101  1010
4
IN
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4
0
0
1
1
2
2
3
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OUT
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Code
module swapvals(IN, OUT);
input [3:0] IN;
output [3:0] OUT;
module swapvals_tb;
reg [3:0] IN = 4'b0101;
wire [3:0] OUT;
// swap the input bits
assign OUT ={IN[2],IN[3],IN[0],IN[1]};
endmodule
initial
begin
$dumpfile("swapvals.vcd");
$dumpvars(0, s);
$monitor("IN=[%b], OUT=[%b].",IN,OUT);
#100 IN = 4'b0011;
#100 $finish;
end
swapvals s(IN, OUT);
endmodule
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How to compile code
o iverilog -o swapvals.vvp swapvals.v swapvals_tb.v
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How to run the simulation
o vvp simple.vvp
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How to view the output using GTKWave program
o gtkwave swapvals.vcd
C:\iverilog\bin>vvp swapvals.vvp
VCD info: dumpfile swapvals.vcd opened for output.
IN=[0101], OUT=[1010].
IN=[0011], OUT=[0011].
C:\iverilog\bin>gtkwave swapvals.vcd
GTKWave Analyzer v3.3.0 (w)1999-2009 BSI
[0] start time.
[200] end time.
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4-bit binary up counter
o The desired pattern sequence is as follows
• 0000  0001  …  1111  0000  …
o No external input is required.
4
0
OUT
1
2
3
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Code
module fourbit_up_counter(clk,q,reset);
input clk;
input reset;
output reg [3:0] q;
initial
begin
q=4'b0000;
end
always@(posedge clk)
begin
if (reset==1'b1)
q=4'b0000;
else
q=q+1;
end
endmodule
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`timescale 1ns/1ns
module fourbit_up_counter_tb;
reg clk;
reg reset;
wire [3:0] q;
fourbit_up_counter
instance0(.clk(clk),.q(q),.reset(reset));
initial
begin
clk = 1'b0;
reset = 1'b1;
#10 reset = 1'b0;
#1000 ;
$finish;
end
initial
begin
forever #20 clk = ~clk;
end
initial
begin
$monitor("Time = [%t]ns, Q = [%b]",$time,q);
end
endmodule
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How to compile code
C:\iverilog\bin>vvp fourbit_up_counter.vvp
Time = [
0]ns, Q = [0000]
Time = [
20]ns, Q = [0001]
Time = [
60]ns, Q = [0010]
Time = [
100]ns, Q = [0011]
Time = [
140]ns, Q = [0100]
Time = [
180]ns, Q = [0101]
Time = [
220]ns, Q = [0110]
Time = [
260]ns, Q = [0111]
Time = [
300]ns, Q = [1000]
Time = [
340]ns, Q = [1001]
Time = [
380]ns, Q = [1010]
Time = [
420]ns, Q = [1011]
Time = [
460]ns, Q = [1100]
Time = [
500]ns, Q = [1101]
Time = [
540]ns, Q = [1110]
Time = [
580]ns, Q = [1111]
Time = [
620]ns, Q = [0000]
Time = [
660]ns, Q = [0001]
Time = [
700]ns, Q = [0010]
Time = [
740]ns, Q = [0011]
Time = [
780]ns, Q = [0100]
Time = [
820]ns, Q = [0101]
Time = [
860]ns, Q = [0110]
Time = [
900]ns, Q = [0111]
Time = [
940]ns, Q = [1000]
Time
=
[
980]ns, Q = [1001]
(c) 2012 Jaehan Koh
o C:\iverilog\bin>iverilog -o
fourbit_up_counter.vvp
fourbit_up_counter.v
fourbit_
o up_counter_tb.v
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How to run the simulation
o vvp simple.vvp
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Icarus Verilog is a Verilog simulation and synthesis tool
You can download and run it under different platforms
You can perform simulation by using Xilinx WebPack
software
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Download the Software
o Visit http://ubit.buffalo.edu/software/
o Go to [Windows software]  [Software downloads].
o Download the file [win_xwin32-2010_xxxx.exe].
o You will be asked to log in for downloading.
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How to remotely have access to [timberlake] system.
o Run [X-Config].
o Choose [CSE-timberlake] and click on [Launch].
o Log in.
Log in to CSE system.
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You will see a prompt.
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Icarus Verilog, http://iverilog.icarus.com/.
Matt Zucker, “Icarus Verilog,” Swarthmore College,
http://www.swarthmore.edu/NatSci/mzucker1/e15/iverilo
g-instructions.html.
Wikipedia, “Icarus Verilog,”
http://en.wikipedia.org/wiki/Icarus_Verilog.
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