Multi-Layer Three-Dimensional Silicon Electronics Enabled by Wafer
Bonding
by
Chuan Seng Tan
B.Eng. (Hons) in Electrical Engineering, University of Malaya, Malaysia, 1999
M.Eng. in Advanced Materials for Micro- and Nano-Systems, Singapore-MIT Alliance,
National University of Singapore, Singapore, 2001
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
at the
MASSACHUSMTT
INRMTUR
OF TECHNOLOGY
Massachusetts Institute of Technology
June 2006
NOVR 2 2006
@ 2006 Massachusetts Institute of Technology
All rights reserved.
LIBRARIES
Author .........................
.........................
........
Department of Electrical Engineering and Computer Science
March 3, 2006
Certified by ...............................................................
Re..
SL. Rafae Reif
Provost and Maseeh Professor of Emerging Technology
Thesis SuDervisor
Certified by .............................................................
......... .... ........
Anantha P. Chandrakasan
gineering
upervisor
Accepted by ..............
C. Smith
Chairman, Department Committee on Graduate Studies
BARKER
2
Multi-Layer Three-Dimensional Silicon Electronics Enabled by Wafer
Bonding
by
Chuan Seng Tan
Submitted to the Department of Electrical Engineering and Computer Science
on March 3, 2006 in Partial Fulfillment of the Requirements for the Degree of
Doctor of Philosophy in Electrical Engineering and Computer Science
ABSTRACT
Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several
interconnected device layers, have many performance, form factor, and integration
advantages. The main objective of this work is to develop reliable process technology to
enable the fabrication of a vertically interconnected silicon multi-layer stack.
Low temperature wafer bonding processes, both copper thermo-compression
bonding and silicon dioxide fusion bonding, are studied extensively as key enabling
technology. Cu thermo-compression bonding is studied for its feasibility as a permanent
bond between active layers in a multi-layer stack. It is found that pre-bonding anneal in
forming gas can remove surface oxide on Cu wafers and reduce the oxygen content in the
bonded layer. The quality of bonded Cu layer is adversely degraded by the formation of
interfacial voids. Void nucleation and growth are studied and counter-measures for void
suppression are proposed and implemented. Silicon dioxide wafer bonding, on the other
hand, is used as a temporary bond to attach a donor wafer to a handle wafer during donor
wafer thinning and subsequent layer transfer. Sufficiently high bond strength is obtained
with careful surface preparation and activation prior to bonding.
Silicon layer can be stacked either in a "face down" or "face up" orientation.
Using a combination of wafer bonding and thinning, double-layer stacks in both
orientations are fabricated. By repeating these steps on two "face down" double-layer
stacks, a four-layer stack is successful demonstrated. A vertically interconnected active
layers stack is demonstrated by fabricating poly-silicon resistor chains. Poly-silicon
resistors in two layers are electrically connected with interlayer vias. Temperature
measurement of metal lines suggests that Cu bonding medium can remove heat from top
active layer of a double-layer stack more effectively than oxide bonding medium.
Thermal stress induced in a multi-layer stack can pose a serious reliability
concern. Analytical and numerical evaluation of thin film stresses of a multi-layer stack
is performed. Stresses of interest include normal stress in thin films, and shear and peel
stresses at the interfaces. It is found that the Cu bonding layer is under substantial tensile
stress that increases with bonding temperature. High stress level in the Cu bonding layer
provides a strong driving force for the formation of interfacial voids.
3
Thesis Supervisor: L. Rafael Reif
Title: Provost and Maseeh Professor of Emerging Technology
Thesis Supervisor: Anantha P. Chandrakasan
Title: Keithley Professor of Electrical Engineering
4
Acknowledgements
As I wrap up an undertaking that has occupied me for the better part of the past four years, I take
great joy in acknowledging the many people that have enabled me to reach this point.
Professor Rafael Reif, my research advisor, deserves a lot of credits for his dedication
and trust in me. Even when he was completely tied up with administrative matters as the head of
department and later as the Provost of MIT, he always spent time with me to ensure that I get all
the supports and resources in order to perform my work. It was a great honor to be able to
represent him at many conferences and invited talks. For that, I thank him for his trust and
confidence. He has made graduate student life a very pleasant one for me.
Professor Anantha Chandrakasan is another important person that I must thank. His role,
especially during the later stage of my doctoral program, has been very essential and instrumental
to the success of this thesis. He is always friendly and supportive of what I do. I thank him for his
willingness to assist in many administrative matters and to give me valuable advice. This thesis
would not be in its present form without many valuable inputs and suggestions from my thesis
readers, Professors Clifton Fonstad and Duane Boning. I thank them for their interest in my thesis
and for providing constructive feedback.
Another group of people that have spent a good amount of time with me are the
superstars in the research group, past and present. Susan took care of almost all administrative
matters in the research group, from scheduling meetings to dinners. She came to my thesis
defense and stayed even though she was lost after the first slide! I have the opportunity to share
an office with Shamik and Nisha. Shamik was very focused on his work and he took care of all
matters related to computers in the group. It has been quite an experience to work with Nisha on
the SRC project. I believe a lot of good things came out from this interaction. I especially owe
Andy a big thank you - he initiated this project and laid down many fundamental works that
saved me a lot of hard works. Always cheerful and helpful, he is one good person that I am so
blessed to be associated with. To Kuan-Neng, I remember fondly his help in setting up copper
wafer bonding experiment and the opportunity to co-author a number of articles with him. I am
glad that Ajay will continue to work on oxide wafer bonding and I am sure he will take the
project to another level of excitement. While I did not work with Tan Mau directly, he has always
provided energy to the group. For Ritwik, I want to thank him for helping me to settle in when I
first came and to stay in touch with the group.
MTL staff members deserve kudos for their assistant in running my experiments and for
making sure that all equipments are up and running. They are a group of highly skilled and
capable specialists in their own right. I want to mention Paul Tierney, Bob, Eric, Bernard, Kurt,
Paul McGrath, Dennis, Tim, Dan, Paudely, Brian, Joe and Vicky. Special thanks also go to Dee
and Acia for taking care of the funding accounts and for ensuring that all invoices are paid
promptly.
This project is generously funded by a number of agencies including MARCO
Interconnect Focus Center, SRC with custom finding from TI, DARPA with a subcontract from
IBM, and a graduate fellowship from Applied Materials. I have the opportunity to interact with
many industry collaborators includes Scott Pozder and David Theodore of Freescale, Patrick
Thompson and J.D. Luttmer of TI, and Albert Young of IBM. Special thanks to Mauro Kobrinsky
and Scott List for having me as an intern at Intel Corporation in Hillsboro, Oregon.
5
I am very grateful to a group of friends that have provided me social support and comfort
in weal and woe. It was always nice and warm to hang out over dinners, movies, shopping,
outings, or cookouts! Irving is one such great friend that I truly missed. He is the most colorful
friend I ever had. I can't forget the many trips to Watertown to make merits and to spend them all
the same day! Zulina is another person I came to treasure a lot despite that she changed her mind
as quickly as Boston's weather. George was a regular guest and host in Tang Hall. I enjoyed
working out in the gym with him. Jin Hock has been very sweet and accommodating. He is such a
selfless person and I see great success lies ahead for him. For Cheng Hau, even though he was
initially shy and maintained a distance, he has become a significant part in my social circle.
Thanks for the supply of music and movies, and for checking on me from time to time. Michelle
knew my kitchen very well as she was a regular self-invited guest! Thanks for being so sweet and
lovely. Wee Liang was a great companion come to good food and I am sure he will find his
dream job soon. Shien Jin was one of the first friends I have at MIT and I enjoyed having many
constructive discussions with him. Joel and Ari are expecting their first son as I am writing this
page and I am so happy for them as their family grows!
Many friends in Malaysia, Singapore, and England have constantly showed their care and
support throughout these years. In particular, I must mention Sean Pin, Poo Choo and David,
Yuan Chiat, Vino, Sirirat, Boon Cheng, Chee Lip, Lee Wee, Eric, and you know who you are.
For Lee Peng, thanks for your constant understanding, care, and patience. Your e-mails, phone
calls, and MSN messages are always very sweet to me.
To the uveitis support group members, you guys were great support when I was battling
with my health problems and at the lowest point of my life. I came to Boston with a chronic
condition in my left eye and was under severe pain. Dr. Foster at the Massachusetts Eye and Ear
Infirmary skillfully treated my eye and provided peace of mind for me to concentrate on my
studies. I will always remember him. I must also thank Liz, Mike, and all other support group
members that come together to share and care.
It was a rare opportunity to meet and learn from Tenzin Priyadarshi, he is one talented
and compassionate teacher as well as friend I have. Thanks to the MIT Buddhist Community, I
have become very close to Linda. She is forever motherly and I am going to miss her Italian
salsa! I am also very glad to know Melvyn and his family better in the past years.
I am sure I have unintentionally missed out quite a number of significant people, but I
want to let you know that I cherish your friendships and am glad to have the opportunity to know
you. I hope our paths will cross again in the future.
The real highlight of this acknowledgement goes to the Tan family. They are a group of
hardworking and dedicated people that have supported me in many ways. Dad and Mom never
stop giving me their unconditional love and support. I wouldn't have come this far without them.
I pray that they will remain strong and witness the next chapter in my life. To all my brothers,
thanks for taking care of the family and giving me this privilege to further my studies. For Auntie
Catherine, you are awesome and great! I dedicate this dissertation to my parents and to the loving
memory of my sister for their years of devoted support and selfless love. I bow to them.
May you all be well and happy always!
Chuan Seng
Cambrige, Mvfassachusetts, Spring 2006
6
Table of Contents
List of Figures
11
List of Tables
17
Chapter 1: Introduction, Motivations, and Objectives
19
1.1 Background and Introduction .................................................
1.2 Motivations for Research in Three-Dimensional (3-D) ICs ..............
1.2.1 Interconnect Bottleneck .............................................
1.2.2 Chip Form Factor ....................................................
1.2.3 Heterogeneous Integration .........................................
1.2.4 Hybrid CMOS ........................................................
1.3 Objectives and Thesis Organization .........................................
Chapter 2: Wafer Level Integration of Integrated Circuits
2.1 Three-Dimensional Integrated Circuits ......................................
2.2 Bottom-Up Approach ..........................................................
2.2.1 Laser Beam Recrystallization ......................................
2.2.2 Seeding ................................................................
2.2.3 Selective Epitaxial Growth .........................................
2.3 Assembly Approach ............................................................
2.3.1 D ielectric B ond ......................................................
2.3.2 M etallic B ond .........................................................
2.4 3-D Integration Enabled by Cu thermo-compression Bonding ..........
Chapter 3: Copper Thermo-Compression Bonding
3.1 Blanket Copper Wafer Bonding ..............................................
3.1.1 Thermo-Compression Bonding of Cu .............................
3.1.1.1 Wafer Preparation and Bonding Procedures ..........
3.1.1.2 Bonding Mechanism .....................................
3.1.1.3 Surface Roughness .......................................
3.1.1.4 Choice of Cu ..............................................
3.1.1.5 Surface Oxide .............................................
3.1.1.6 Copper Out-diffusion ....................................
3.1.2 Process Parameters ...................................................
3.1.2.1 Bonding Duration .........................................
3.1.2.2 Bonding Temperature ....................................
3.1.2.3 Contact Force .............................................
3.2 Reliability of Bonded Copper Layer .........................................
3.2.1 Observation of Interfacial Voids ..................................
3.2.1.1 Nucleation and Growth ..................................
3.2.1.2 Counter Measures ..........................................
7
19
20
21
22
22
23
24
25
25
26
27
28
29
29
30
31
33
37
37
38
38
39
42
44
46
55
56
56
59
60
62
63
63
67
3.2.2 Thin Films Mechanical Integrity ...................................
3.3 Sum m ary ........................................................................
Chapter 4: Silicon Dioxide Fusion Bonding
4.1 Low Temperature Oxide Wafer Bonding ...................................
4.1.1 Wafer Preparation ..................................................
4.1.2 Results and Discussions ............................................
4.1.2.1 Wafer Preparation ........................................
4.1.2.2 Pre-Bonding Densification ...............................
4.1.2.3 Chemical Mechanical Polishing .........................
4.1.2.4 Post-Bonding Anneal ....................................
4.1.2.5 Choice of CVD Oxides ..................................
4.1.2.6 Activation Methods ......................................
4.2 Thin Film Handling and Reliability .........................................
4.2.1 Mechanical Grinding ................................................
4.2.2 TMAH Etch ..........................................................
4.2.3 Interfacial Properties ................................................
4.3 Sum m ary ........................................................................
Chapter 5: Face-to-Face Silicon Layer Stacking
5.1 Face-to-Face Silicon Bi-layer Stack .........................................
5.1.1 Wafer Preparation ...................................................
5.1.2 Cu-to-Cu Bonding ...................................................
5.1.3 SOI Donor Wafer Etch Back .......................................
5.1.3.1 Grinding and TMAH .....................................
5.1.3.2 Hydrogen Induced Wafers Splitting ...................
5.2 Silicon Multi-layer Stack ......................................................
5.2.1 Process Flow .........................................................
5.2.2 Demonstration of Quadruple-layer Stack ........................
5.3 Sum mary ........................................................................
Chapter 6: Back-to-Face Silicon Layer Stacking
6.1 Silicon Bi-layer Stack .........................................................
6.1.1 Wafer Preparation ...................................................
6.1.2 Oxide Wafer Bonding ...............................................
6.1.3 Donor Wafer Etch Back .............................................
6.1.4 Cu Wafer Bonding ...................................................
6.1.5 Handle Wafer Release ...............................................
6.1.5.1 Grinding and TMAH .....................................
6.1.5.2 Hydrogen Induced Wafer Splitting .....................
6.2 Thin Film Reliability ...........................................................
6.3 Summ ary ........................................................................
8
69
71
73
73
75
77
77
79
80
85
87
88
92
93
94
96
99
101
101
102
103
103
104
108
111
111
112
113
115
115
115
117
118
118
119
119
120
124
125
Chapter 7: Demonstration of Vertically Interconnected Active Layers
7.1 Thermal Management .........................................................
7.1.1 Test Structures Fabrication .........................................
7.1.2 Temperature Measurement .........................................
7.2 Cu Lines Bonding ..............................................................
7.3 Vertically Interconnected Active Layers ....................................
7.3.1 Fabrication ............................................................
7.3.2 Results and Discussions .............................................
7.4 Sum m ary ........................................................................
127
127
128
129
132
134
135
136
139
141
Chapter 8: Thermal Stress Analysis
8.1 T herm al Stress ..................................................................
8.2 Thermal Stress Models .........................................................
8.2.1 3-D Structures ........................................................
8.2.2 Stress Electrical Equivalent Model ................................
8.2.3 Suhir's Thermal Stress Model ......................................
8.2.4 Finite Element Analysis .............................................
8.3 Thermal Stress Analysis .......................................................
8.3.1 Bonding Temperature ...............................................
8.3.2 Cu Layer Thickness .................................................
8.3.3 Choice of Interlayer Dielectric .....................................
8.4 Sum m ary ........................................................................
141
143
143
145
147
149
150
150
155
157
160
161
Chapter 9: Summary and Conclusion
Summ ary ........................................................................
9.1.1 Experimental Work ..................................................
9.1.2 Theoretical Work ....................................................
9.2 Future W ork .....................................................................
9.1
16 1
161
166
166
169
Bibliography
9
10
List of Figures
1.1
A conceptual multi-layer three-dimensional integrated circuit. ...................
21
1.2
3-D integration can replace long global and semi-global wires with shorter
vertical interconnects. ..................................................................
22
2.1
Process flow for 3-D integration scheme using Cu wafer bonding. ...............
34
3.1
Sample preparation: Direct Cu to Cu thermo-compression bonding and wafer
thin b ack . .................................................................................
39
3.2
Plan view of as-deposited copper on oxide wafer. ..................................
40
3.3
AFM scan of as-deposited Cu on oxide wafer prior to bonding. The surface
roughness of the Cu layer is estimated to be 1.99 nm. ..............................
40
3.4
SEM image of bonded Cu layer sandwiched between oxide layers. Cu-coated
wafers were bonded at 300 0C for 1 hour followed by an anneal at 400 0C for
41
I h ou r. .....................................................................................
3.5
(a) TEM image of bonded Cu layer. Note that the bonding Cu layers merge
and a homogeneous Cu layer is obtained after bonding and anneal. (b) Closeup view of the microstructures of bonded Cu layers. Grain structures that
extend across the original bonding interface are observed. Dislocation lines
42
(marked with arrows) are clearly seen in the grains. ................................
3.6
AFM scan of as-deposited Cu on poly-Si prior to bonding. The surface
roughness of the Cu layer is estimated to be 8.59 nm. ..............................
43
3.7
SEM image of bonded Cu layer sandwiched between poly-Si layers. Cucoated wafers were bonded at 300 0C for 1 hour followed by an anneal at 400
0C for 1 hour. ............................................................................
44
3.8
Close-up view of the microstructures of bonded Cu layers. Grains structures
that extend across the original bonding interface are observed. Dislocation
lines (marked with arrows) are clearly seen in the grains. .........................
45
3.9
EDS profile of the bonded Cu layer. No appreciable contaminant is found. ....
46
3.10
Thermo-compression of electro-plated Cu. (a) As-deposited Cu, and (b)
46
bonded C u layer. ........................................................................
3.11
XPS spectra of Cu-covered wafers after 12 hours and 12 days storage in the
clean room. Signals of Cu 2 pl/2 and 2 P3/2 from CuO become stronger after 12
days of storage. ...........................................................................
11
48
3.12
Auger Electron Spectroscopy (AES) signals of various elements in sample 2
50
as a function of sputter etch time. ....................................................
3.13
SIMS profiles of the oxygen content in the bonded Cu layers with different
pre-bonding exposure to the air. ......................................................
51
SEM micrographs of bonded Cu layers from Cu wafers with different
exposure to the air prior to thermo-compression bonding. ........................
53
3.15
SIMS profile of Cu in area adjacent to the bonded Cu layer. .....................
55
3.16
SEM images of grain structures in bonded Cu layer: (a) bonded at 300 0C for
57
5 min, and (b) annealed at 300 0C for 1 hour after bonding. .......................
3.17
SEM images of grain structures in bonded Cu layer: (a) bonded at 300 0C for
57
10 min, and (b) annealed at 300 0C for 1 hour after bonding. .....................
3.18
SEM images of grain structures in bonded Cu layer: (a) bonded at 300 0C for
30 min, and (b) annealed at 300 0C for 1 hour after bonding. .....................
57
SEM images of grain structures in bonded Cu layer: (a) bonded at 300 0C for
30 min, and (b) annealed at 300 C for 1 hour after bonding. .....................
58
3.14
3.19
3.20
SEM images of grain structures in bonded Cu layer: (a) bonded at 300 0C for
58
1h, and (b) annealed at 300 0C for 1 hour after bonding. ...........................
3.21
SEM images of grain structures in Cu layer bonded for 1 hour at: (a) 200 0C,
(b) 300 0C , and (c) 200 C . .............................................................
60
SEM images of grain structures in Cu layer bonded at 300 0C with contact
force: (a) 2 kN, (b) 4 kN, (c) 6 kN, (d) 8 kN, and (e) 10 kN. ......................
61
3.22
3.23
Images of bonded wafer pairs after etch-back. These wafers are bonded under
62
contact force of (a) 2 kN, and (b) 4 kN. ..............................................
3.24
Observation of voids in the bonded Cu layer. This layer is bonded at 300 0C
.. 64
for 1 hour. ..............................................................................
3.25
Interfacial void growth during Cu thermo-compression bonding at 300 0C for
(a) 10 min, (b) 30 min, and (c) 60 min. ...............................................
65
Variation of interfacial void sizes in Cu layers bonded at various conditions:
(a) 300 0C / 1 hour, (b) 400 0C / 1 hour, (c) 300 0C / 1 hour with poly-Si caps,
and (d) 300 0C / 1 hour with 100 0C / 30 min pre-bonding anneal. ...............
66
3.26
3.27
SEM of Cu layer afters different pre-bonding anneal: (a) no anneal, (b) 100
12
C for 30 min, and (c) 150 C for 30 min. ............................................
68
Photographs of bonded wafer pairs after bonding and etch-back. The wafer
bow for the pairing wafers are (a) 5-10 pm, and (b) 30-40 m. ...................
70
3.29
SEM image across the boundary where thin film delaminated. ...................
71
4.1
Schematic shows the bonding of CVD oxide on an SOI structure to thermal
oxide on a handle w afer. ...............................................................
76
3.28
4.2
Infra-red images of bonded oxide wafer: (a) no interfacial voids, and (b)
78
interfacial voids due to surface particles. ............................................
4.3
Wafer bows for LTO, PE-TEOS, PE-Silane, and handle wafers prior to
bonding. Wafer bow of unprocessed bare silicon wafer is included for
79
com parison . ..............................................................................
4.4
The effect of post-bonding annealing on bonding interface for: (a)-(b) wafer
pair without densification on PE-Silane oxide, and (c)-(d) wafer pair with
densification on PE-Silane oxide. (a) and (c) are IR images before annealing,
and (b) and (d) are IR images after annealing. .......................................
80
AFM scans for (a) as-deposited LTO oxide, and (b) densified and polished
LT O oxide. ...............................................................................
82
AFM scans for (a) as-deposited PE-Silane oxide, and (b) densified and
polished PE-Silane oxide...............................................................
82
AFM scans for (a) as-deposited PE-TEOS oxide, and (b) densified and
polished PE-TEOS oxide. ..............................................................
83
4.5
4.6
4.7
4.8
RMS roughness of PE-TEOS oxide as a function of CMP duration. Note that
the roughness falls below 1.0 nm and does not change significantly beyond 1
84
..
m inute. ...............................................................................
4.9
Bond strength as a function of CMP duration. .......................................
4.10 The variation of bonding strength of PE-TEOS oxide bonded to thermal oxide
as a function of annealing duration at different annealing temperatures. ........
85
86
4.11
Bonding strength of different CVD oxides bonded to thermal oxide as a
87
function of post-bond annealing duration at 300 C. ...............................
4.12
Bond strength of bonded wafer pairs treated with different chemical cleans
and annealed at 300 C for 3 hours. ...................................................
13
88
4.13
Bond strength of bonded wafer pairs annealed at different temperatures. .......
4.14 Schematic shows the etch-back of the SOI wafer after bonding to a handle
wafer. The etch-back stops on the BOX layer. .....................................
4.15
Infrared (IR) transmission images of piranha treated and bonded wafer pairs
before and after grinding. Bonded pairs were annealed for 3 hours at: (a)-(b)
100 C and (c)-(d) 200 C respectively. (a) and (c) are images before grinding
and (b) and (d) are images after grinding. ............................................
990
92
94
4.16 Cross-sectional SEM micrograph showing thin films (from donor wafer) are
bonded to a handle wafer after SOI donor wafer etch-back. The wafers were
treated with oxygen plasma and no post-bonding anneal was done. .............
95
4.17
Cross-sectional TEM micrograph showing that thin films (from donor wafer)
are bonded seamlessly to a handle wafer after SOI donor wafer etch-back. .... 96
4.18
High resolution TEM micrograph showing the bonding interface of PE-TEOS
and thermal oxides. The bonding interface is smooth with no interfacial voids.
A transitional area at the bonding interface approximately 2.2 nm thick is
97
ob served . .................................................................................
4.19 EDX profiles of various regions close to the PE-TEOS and thermal oxides
bonding interface: (a) PE-TEOS, (b) bonding interface, and (c) thermal oxide.
5.1
Face-to-face silicon layer transfer and stacking based on Cu thermocompression and wafer etch-back. .....................................................
98
102
5.2
SEM shows a silicon bi-layer stack obtained after donor wafer thin-back. ..... 105
5.3
Cu grain structure in the bonded layer. Note that the original Cu layers have
merged and a homogeneous layer is obtained. .......................................
105
SEM image shows a silicon bi-layer stack with the insertion of low
temperature oxide (LTO) between the SOI and the Cu layers. ....................
106
Cu grain structure in the bonded layer. Note that the original Cu layers have
merged and a homogeneous layer is obtained. .......................................
107
Image of transferred thin films on the substrate wafer after donor wafer etchback. Delamination is observed at the edge of the wafer. ..........................
107
5.7
Simulated hydrogen profile using TRIM program. ..................................
108
5.8
FIB image shows a silicon bi-layer stack. The substrate of top donor wafer
was separated using hydrogen induced wafer splitting. .............................
109
5.4
5.5
5.6
14
Cu grain structures in the bonded layer. Note that the original Cu layers have
merged and a homogeneous layer is obtained. .......................................
110
Schematic shows a possible way to fabricate a silicon quadruple-layer stack
by stacking two silicon bi-layer stacks. ...............................................
111
FIB image shows a silicon quadruple-layer stack achieved by stacking two
silicon bi-layer stacks in Figure 2. This paves a promising path to multi-layer
and multi-functionality silicon stacks. ................................................
112
Schematics of back-to-face silicon layer transfer and stacking for threedimensional integration. ................................................................
116
6.2
SEM image of thin films attached to the handle wafer after etch back. ..........
119
6.3
SEM shows back-to-face silicon layers stack obtained after handle wafer
grinding and TM AH strip. ..............................................................
120
SIMS profile of implanted hydrogen into the handle wafer. The hydrogen
peak is situated about 300 nm from the oxide-silicon interface into the silicon
handle w afer. .............................................................................
12 1
6.5
The hydrogen profile simulated using TRIM. ................................................
121
6.6
SEM shows the silicon layers stack obtained after handle wafer release.
Handle wafer is released at the peak of the implanted hydrogen profile. ........
122
5.9
5.10
5.11
6.1
6.4
6.7
Hydrogen-implanted handle wafer surface under optical microscope for (a)
as-implanted wafer, and (b) after wafer underwent 400 0C anneal for 1 hour. .. 123
6.8
Thin film delamination due to the presence of surface particles at the bonding
interface: (a) IR image reveals large void at the oxide bonding interface due to
surface particles, (b) photo of thin films on the handle wafer after etch-back,
and (c) photo of final thin film stack after handle wafer release. ..................
124
7.1
Kelvin test structure for resistance measurement. ...................................
127
7.2
SEM images of temperature sensor structure on oxide layers bonded using (a)
C u, and (b) oxide. ........................................................................
128
Resistance of gold line measured in temperature range 25-200 0C on substrate
bonded using (a) Cu, and (b) oxide. ...................................................
131
7.4
Calibrated gold line temperature at different current density. .....................
132
7.5
Cross sectional SEM image shows bonded Cu lines that are spaced at 5.3 m.
133
7.3
15
7.6
Bonded Cu lines with various widths: (a) 2.0 ptm, (b) 4.1 tm, and (c) 9.2 gm.
134
7.7
Poly-silicon resistor and via chain fabricated using a bi-layer stack in a faceto-face fashion . ...........................................................................
135
(a) and (b) Interlayer vertical vias without and with doped poly-silicon fill. (c)
A double-layer poly-Si resistor chain with bonded vertical via. ..................
136
Optical microscope images of poly-silicon resistor chain before and after
stackin g . ...................................................................................
137
7.10
Resistance of individual poly-Si resistors having different width. ...............
138
7.11
Resistance of 3-D poly-Si resistors chain. ............................................
138
8.1
Types of thermal stresses, including normal stress (a), shear stress (Z), and
peel stress (p). ............................................................................
14 1
8.2
Thin film stack used in thermal stress analysis. .....................................
143
8.3
Electrical equivalent circuit of a mechanical component. ..........................
146
8.4
Stress profile in each thin film layer based on FEMLAB estimation. ............
151
8.5
Thin film stress in a bi-layer stack bonded at 400 0C. Note that the bonded Cu
layer is under high tensile stress. ......................................................
152
8.6
Tensile stress in Cu layer bonded at different temperature. ........................
153
8.7
Shear stress in Cu layer bonded at different temperature. ..........................
154
8.8
Peel stress in Cu layer bonded at different temperature. ...........................
154
8.9
Normal stress in Cu layer with different thickness. .................................
155
8.10
Shear stress in Cu layer with different thickness. ...................................
156
8.11
Peel stress in Cu layer with different thickness. .....................................
156
8.12 Normal stress in Cu layer with different dielectric. .................................
158
Shear stress in Cu layer with different dielectric. ...................................
159
8.14 Peel stress in Cu layer with different dielectric. .....................................
159
7.8
7.9
8.13
16
List of Tables
2.1
Characteristic features of 3-D packaging and 3-D integration. ....................
25
4.1
Root-mean-square (RMS) roughness of various as-deposited oxides and
improvement achieved with CMP. ....................................................
81
4.2
RMS roughness of oxide wafers with and without oxygen plasma exposure. ... 91
4.3
Summary of various bonded pairs endurance to mechanical grinding and
TM A H etch. ..............................................................................
93
Mechanical and thermal properties of materials used in thermal stress
analysis. ...................................................................
144
Mechanical parameters for stress analysis and their electrical equivalent. ......
146
8.1
8.2
17
18
Chapter 1
Introduction, Motivations, and Objectives
1.1 Background and Introduction
For the past 40 years, higher computing power was achieved primarily through transistor
performance enhancement as a result of continuously scaling down the device
dimensions as described by Moore's Law. Integrated circuits (ICs) have essentially
remained a planar platform throughout this period of rigorous scaling. As performance
enhancement through device scaling becomes more challenging and demand for higher
functionality increases, there is tremendous potential to explore the third dimension, i.e.,
the vertical dimension of the integrated circuits. This was rightly envisioned and pointed
out by Richard Fenyman, physicist and Nobel Laureate, when he delivered a talk on
'Computing Machines in the Future' in Japan in 1985 and his original text reads
"Another direction of improvement (of computing power) is to make physical machines
three dimensional instead of all on a surface of a chip. That can be done in stages instead
of all at once - you can have several layers and then add many more layers as time goes
on" [1].
While dimensional scaling has consistently improved device performance in
terms of gate switching delay, it has a reverse effect on global interconnect latency [2].
The global interconnect RC delay has increasingly become the circuit performance
limiting factor especially in the deep sub-micron regime. Even though Cu/low-K material
systems have been introduced to improve interconnect RC delay, they are not a long-term
solution. This is because the diffusion barrier material used in Cu metallization has a
19
finite thickness that is not readily scaled and has higher resistivity than Cu resulting in a
higher effective resistivity in Cu wires than in bulk Cu. The surface electron scattering
effect and high operating temperature make the resistivity even worse as the wire
dimensions scale down, and hence the RC delay suffers [3].
When chip size continues to increase to accommodate more functionality, the
total interconnect length increases at the same time. This causes a tremendous amount of
power to be dissipated unnecessarily in the interconnect. On-chip signals also require
more clock cycles to travel across the entire chip as a result of increasing chip size and
operating frequency. Implementation of system-on-chip (SoC) using a planar IC process
will result in larger chip size, longer interconnects, and longer process time as each
functional block is fabricated sequentially using separate sets of technology. We are also
constrained to use a similar substrate which might not have the required material
properties for certain applications and signal cross-talk among blocks is inevitable. It is
clear that as demand for functionalities continues to grow, conventional planar integrated
circuits will not be able to accommodate such mounting demand without compromising
performance, process complexity, and cost.
1.2
Motivations for Research in Three-Dimensional (3-D) ICs
Recently, there has been research interest in advanced three-dimensional integrated
circuits (3-D ICs) in the form of a stack of interconnected active layers which has many
performance, integration and cost advantages [4]. Three-dimensional integrated circuits
can be defined as a stack of several device layers (with interconnects) that are electrically
interconnected by vertical interlayer vias. Figure 1.1 schematically shows the concept of
20
4-
Layer 4
Device/Interconnect layer
Interlayer vertical via
Layer 3
Substrate
Layer 2
Layer 1
Figure 1.1. A conceptual multi-layer three-dimensional integrated circuit.
multi-layer 3-D ICs. In principal one can stack as many device layers as the technology
and the economics allow. Advantages offered by 3-D integration will be discussed and
potential applications will be highlighted in this section.
1.2.1 Interconnect Bottleneck
Today as the device dimension continues to shrink and the chip area continues to
increase, the circuit performance has shifted from being device dominated to interconnect
dominated. As a result of scaling, global interconnects become slower due to increased
resistance and capacitance. Total interconnect length also increases as the complexity of
the chip increases. As a result, interconnect latency and power consumption increase.
One solution to the interconnect problem is to partition a large chip into smaller
blocks followed by thinning, stacking, and interconnecting them with vertical vias on a
common substrate as shown in Figure 1.2. Instead of having to travel across the entire
chip, inter-block communication is now through vertical vias which are much shorter.
21
Logic
< <L
Memory
W
t,
<W
W
d
3-D
2-D
Figure 1.2. 3-D integration can replace long global and semi-global wires with shorter
vertical interconnects.
With a 3-D implementation, one ends up with shorter global and semi-global
interconnects (for clock, power, etc). This will directly translate into lower propagation
delay and power consumption. This in turn will have a positive effect on overall system
performance. To seek a long-term solution to the interconnect bottleneck, the
International Technology Roadmap for Semiconductors (ITRS) has outlined 3-D
interconnects as one of the promising options [5].
1.2.2 Chip Form Factor
By stacking a few device layers in a vertical fashion, more compact integrated circuits
can be realized. Packing density, in terms of number of devices or functionalities per unit
chip area will increase and this might have a cost advantage in applications where silicon
area is a primary consideration.
1.2.3 Heterogeneous Integration
System-on-a-chip (SoC) is a potential solution to the mounting demand for multiple
22
functionalities on a single chip. There are several challenges associated with planar
implementation of system-on-a-chip (SoC) on a single substrate. Each functional block
has to be built in sequence, and it is challenging to optimize each functional block on the
same substrate. Substrate coupling might cause signal corruption between functional
blocks [6]. 3-D integration is an attractive choice for SoC implementation as it allows
integration of various functional blocks in a vertical fashion. In this way, each block can
be optimized independently and stacked to form a 3-D system. Since there is no common
substrate in this type of implementation, noise between blocks is expected to improve
compared to a planar implementation.
1.2.4 Hybrid CMOS
Another attractive advantage to the stacking of active device layers in a vertical fashion is
the implementation of hybrid CMOS. While the n-MOSFETs and p-MOSFETs in CMOS
inverters have remained largely identical in terms of materials selection in the past,
MOSFETs in state-of-the-art CMOS inverters have increasingly diverged. For example, a
tensile strained channel is required for n-MOS while a compressive strained channel is
required for p-MOS [7], and the <100> orientation sees higher electron mobility while
the <110> orientation sees higher hole mobility [8]. As CMOS becomes "hybrid," a
single substrate implementation and processing can be highly complex. There is
opportunity for 3-D vertical integration in this area: one can build and optimize n-MOS
and p-MOS on two different substrates, bond, and thin back to form stacked CMOS.
23
1.3 Objectives and Thesis Organization
The main objective of this doctoral work is to develop process technology to assist the
fabrication of three-dimensional integrated circuits (3-D ICs) in the form of a silicon
multi-layer stack.
Chapter 2 is a brief survey of existence technology options for 3-D ICs fabrication
reported in the literature. Each technology option is briefly described and examples are
given.
In Chapter 3 and 4, low temperature wafer bonding approaches, both copper (Cu)
thermo-compression bonding and silicon dioxide fusion bonding, are studied extensively
as key enabling process steps. Wafer surface preparation, bonding mechanism, and
bonding reliability are discussed.
Building on results on wafer bonding, silicon layer stacking forms the next two
chapter of this thesis. Silicon layer stacking can be arranged either in a face-to-face or
back-to-face fashion. Face-to-face stacking is covered in Chapter 5, while back-to-face
stacking is described in Chapter 6. Structural integrity and reliability of the multi-layer
stack will be examined.
Vertically interconnected active layers will be demonstrated in Chapter 7. A
double-layer consists of poly-silicon resistor chains is fabricated.
In Chapter 8, thermal stress in a silicon multi-layer stack is addressed. Analytical
and numerical evaluation of thin film stresses of the stacked layers will be performed.
Chapter 9 concludes this thesis with salient contributions of this work and
suggested future work.
24
Chapter 2
Wafer Level Integration of Integrated Circuits
This chapter reviews a number of technology options for wafer level integration of
integrated circuits utilizing silicon process technology. Both methods, i.e., 'bottom-up'
method based on solid phase crystallization and 'assembly' method based on wafer
bonding are discussed. Examples drawn from the literature will be given. A process flow
based on Cu thermo-compression and oxide fusion bonding is proposed.
2.1 Three-Dimensional Integrated Circuits
"Three-dimensional integrated circuits (3-D ICs)" is a broad term that covers a number of
technology options to arrange integrated circuits in a vertical stack. It is possible to stack
ICs in a vertical fashion at various stages of processing, including during back-end
metallization or after passivation. ICs can be stacked in various forms, i.e., chip-to-chip,
chip-to-wafer, or wafer-to-wafer. Active layers can be vertically interconnected using
Table 2.1. Characteristic features of 3-D packaging and 3-D integration.
3-D Packaging
3-D Integration
Infrastructure
Packaging
Foundry
3-D Interconnect
Bond wires, through
wafer hole
Interlayer via
Active layer
thickness (pm)
> 50
~10
I/O Density (cm 2)
1o4
25
- 10
lob - 101
bond wire, through wafer holes, or interlayer vias. Each technology option varies in terms
of vertical interconnect density. Generally, vertical stacking of ICs can be achieved either
using packaging or foundry facilities. Since there is substantial overlap between the two,
classification of 3-D ICs technology is often not straight forward. Table 2.1 is an attempt
to list a few characteristic features of both platforms [9], [10].
This chapter intends to present an overview of wafer scale 3-D integration of ICs
utilizing silicon foundry technology. This serves as background information to understand
the work developed in this thesis. A good reference for 3-D packaging of ICs can be
found in [11]. In general, there are two primary fabrication schemes for wafer scale
integration of integrated circuits. To form a stack of active device layers, one can build it
sequentially using a "bottom-up" approach or in parallel and assemble the finished device
layer using an "assembly" method. Both approaches are described and examples will be
given based on reports in the literature. Comments on each technology will be given
where appropriate.
2.2 Bottom-Up Approach
In the bottom-up approach, devices in each active layer are processed sequentially starting
from the bottom-most layer. Devices are built on a substrate wafer by mainstream process
technology. After proper isolation, a second device layer is formed and devices are
processed by conventional means on the second layer. This sequence of isolation, layer
formation, and device processing can be repeated to build a multi-layer structure.
The key technology in this approach is forming a high quality active layer isolated
from the bottom substrate. A number of techniques will be discussed in the subsections.
26
This bottom-up approach has the advantage that precision alignment between layers can
be accomplished. However, it suffers from a number of drawbacks. The crystallinity of
upper layers is usually low and imperfect. As a result, high performance devices cannot
be built in the upper layers. Thermal cycling during upper layer crystallization and device
processing can degrade underlying devices and therefore a tight thermal budget must be
imposed. Due to the sequential nature of this method, manufacturing throughput is low.
Despite all the challenges mentioned above, a 3-D stacked memory cell has been in
production [12].
2.2.1 Laser Beam Recrystallization
Kawamura et al. [13] demonstrated a 3-D CMOS having an n-channel transistor in a
recrytallized silicon layer and a p-channel transistor in the silicon substrate. After bottom
p-channel transistors were built, a silicon nitride (Si 3N4 ) insulating layer and a chemicalvapor deposition (CVD) poly-silicon layer were deposited. The poly-silicon film was
recrystallized using an Ar laser. A 3.8 pim n-channel transistor built in the top
recrystallized layer exhibits surface mobility of 240 cm2/Vs while the p-channel transistor
mobility is 210 cm 2 /Vs. A seven-stage ring oscillator fabricated in this 3-D structure has a
propagation delay of 8.2 ns.
Subsequently, Kunio et al. [14] used an Ar laser beam to recrystallize a 0.5 jtm
thick layer of poly-Si deposited by low pressure chemical-vapor deposition (LPCVD) on
the planarised vertical isolation layer formed by LPCVD oxide. SiN stripe lines acted as
an anti-reflection layer for the laser beam. Grains having an average size of 600 jim in
length and 15 ptm in width, and with random orientations are obtainable. Mobilities of n-
27
MOS and p-MOS transistors are 493 and 166 cm 2/Vs respectively for devices with 4 Im
gate length. A four-layer stack consists of CMOS programmable logic array (PLA) and
SRAM was successfully fabricated.
2.2.2 Seeding
In order to have control over grain location during recrystallization of silicon grains from
amorphous silicon, seeding agents such as germanium and nickel can be used.
Subramanian et al. [15] reported 100-nm thin-film transistor (TFT) devices
having on-off current ratio >106 and subthreshold slope of 107 mV/dec using Ge-seeded
lateral recrystallization of amorphous silicon. Amorphous silicon was deposited on an
oxidized wafer and patterned into active islands. Low temperature oxide was
subsequently deposited and seeding windows were etched over the drain regions of the
devices. Germanium was selectively deposited in the seed windows and the amorphous
silicon films were crystallized at 550 0C. This method is suitable for use in vertically
integrated 3-D circuits.
Chan et al. [16] used recrystallization of amorphous silicon by metal-inducedlateral-crystallization (MILC) to nucleate poly-silicon grains. After bottom layer device
fabrication was completed on an SOI wafer, a layer of low temperature oxide (LTO) was
deposited for isolation. Amorphous silicon film was then deposited and covered with
LTO. The LTO layer was patterned and nickel was deposited as a seeding agent. Lateral
recrystallization was carried out at 560 0C. A 3-D ring oscillator was formed by p-channel
devices in the recrystallized layer and n-channel device in the SOI substrate. Lower
propagation delay and load capacitance are reported for a 3-D circuit compared to a 2-D
28
circuit using this technology.
2.2.3 Selective Epitaxial Growth
Selective epitaxial growth (SEG) is another recrystallization method that can be used to
obtain a poly-silicon layer isolated from a silicon substrate [17]. Pae et al. reported
multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective
epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO). This method begins by
forming an oxide well on a thick oxide layer. Adjacent to the wells, an SEG seed window
is etched in the thick oxide. Then SEG/ELO is grown out of the seed window and
laterally over the thick oxide until the wells are completely filled with ELO. The excess
SEG/ELO is removed by CMP. P-MOEFETs fabricated in this layer exhibited low
subthreshold leakage of below 0.2 pA/pm, and a subthreshold swing of 76 mV/dec.
2.3 Assembly Approach
While the recrystallization technique finds specific applications in memory devices, it is
not suitable for applications where high performance devices are required. This has
opened up opportunity for an alternative "assembly" method. This method allows one to
fabricate individual 2-D circuits using conventional planar fabrication technology; these
2-D circuits can then be tested and assembled to form 3-D circuits. While it is possible to
stack high performance devices, new challenges exist for this method. Precision
alignment between layers can impose a limit on the density of vertical interconnects. Low
temperature layer transfer techniques are also needed, and recent progress in low
temperature wafer bonding has been very encouraging [18]. Since device layers can be
29
fabricated in parallel and optimized using their respective technologies prior to layer
stacking, higher throughput can be expected. This is attractive to realize true
heterogeneous integration of materials and functionalities.
Thin device layers can be added to a substrate to form a vertical stack of device
layers in two orientations, i.e., "face down" or "face up." The face down orientation adds
a device layer face-to-face with the substrate wafer. In this method, a donor wafer is
permanently bonded to a substrate and thinned back to the desired thickness. On the other
hand, the face up orientation adds a device layer back-to-face with the substrate wafer. In
this method, a donor wafer must first be temporarily bonded to a handle wafer, thinned
back to the desired thickness, and permanently bonded to the substrate wafer. The transfer
is completed by removing the handle wafer. A permanent bond between active layers can
be formed either by insulating or conducting materials. Examples for each of these
bonding approaches are given below.
2.3.1
Dielectric Bond
When the bonding medium between active layers is insulating, a "via last" sequence is
followed. Device layers are first bonded and vertical vias are etched through the bonding
interface. Therefore, high aspect ratio vertical vias are needed. Examples of such bonding
media include polyimide adhesive, polymeric adhesive, and silicon oxide.
Ramm et al. [19] pioneered what is termed the "Vertically Integrated Circuit
(VIC)" by stacking thinned processed device wafers using an aligned bonding process
with polyimide adhesive and vertical interconnects. In this method, deep vias were
formed in the top wafer into the silicon substrate before it was attached to a handle wafer.
30
The substrate was thinned to expose the vias at the back. A thinned top donor wafer was
then bonded to the substrate wafer using polyimide glue. After handle wafer release, the
vias were further opened down to the top level metal on the bottom circuit and filled with
CVD TiN and W after careful wall isolation. Contact resistance for the deep interchip
vias was measured as 2 Q for a 2 pm x 2 pm via. Lu et al. [20] used a face down
approach, hence avoiding the use of a handle wafer. Wafers were bonded using polymeric
glues such as Benzocyclobutene (BCB).
Warner et al. [21] demonstrated two-layer SOI CMOS circuits with operational
ring oscillators. When circuit fabrication has been completed, SOI wafers are coated with
low temperature oxide (LTO). The LTO layers are polished to the required surface
smoothness and then activated. Wafers are bonded face-to-face using the hydrophilic
bond of oxide layers, and the bonded pair is annealed at 300 0C. The substrate of top
wafer is removed by a wet chemical etch which stops on the buried oxide layer. Interlayer connection are formed by etching vias through the oxide bonding interface and
filled with CVD tungsten. A functional 65-stage ring oscillator was fabricated in 0.8 tm
CMOS technology. Guarini et al. [22] designed a back-to-face donor layer transfer to
substrate wafer using oxide fusion bonding. A glass handle wafer was used to assist in
wafer alignment, and bonding between donor wafer and glass handle was done using
polymeric glue. It was shown that the intrinsic electrical characteristics of the thinned
layer were preserved.
2.3.2
Metallic Bond
Device layers can also be bonded with a conductive metallic layer. This is an attractive
31
choice because it allows a "via first" approach for fabricating 3-D ICs. When metal is
used as the bonding medium, vias can be formed in both pairing device layers prior to
bonding, hence the requirement for interlayer via aspect ratio can be relaxed. Vias are
electrically connected by bonding landing pads at the end of the vias. Dummy pads are
bonded to provide mechanical strength to the stack. Since metal is a conductive medium,
bonding of a continuous film is not possible, and proper dielectric filling between metal
pads is needed for a reliable bond. Thermo-compression of metals such as Cu [23] and
Au [24] have been demonstrated.
Using a similar flow to that described in [19], Ramm et al. [25] replaced the bond
between active layers with a metallic bond formed by Solid-Liquid interdiffusion of Cu
and tin (Sn). Cu pads were formed on both top and bottom wafers, and Sn was deposited
on the top Cu pads. Under a pressure of 5 bar and temperature of 260-300 C, Sn starts to
melt and intermixing of Sn and Cu will take place. A stable eutectic alloy, Cu 3Sn, forms
between the remaining Cu layers. This is an attractive choice because the alloy is stable
up to 600 C, hence providing a temperature window to stack additional layers on the
stack using similar technique.
Tan et al. [26] stacked ultra-thin silicon layers in a face-to-face fashion having Cu
as the bonding medium. A double-layer stack was demonstrated and by repeating the
stacking with two double-layer stacks, a four-layer stack was successfully built. A doublelayer stack arranged in back-to-face fashion bonded by Cu was also demonstrated [27],
[28].
32
2.4 3-D Integration Enabled by Cu thermo-compression Bonding
This section will describe a proposed 3-D integration process based on work on Cu
thermo-compression and oxide fusion bonding. The bulk of this thesis is related to this
process flow. In this scheme, two front-end-of-line (FEOL) active device wafers are
stacked in a back-to-face fashion and bonded by means of low temperature Cu-to-Cu
thermo compression. Interlayer vertical vias electrically interconnect the device layers.
Low temperature wafer bonding is necessary since the pre-bonding device layers already
have Al metal interconnect lines. This is an attractive scheme because it allows lower
aspect ratio interlayer vertical vias and a thinner bonding layer. The process sequence in
this proposed 3-D integration scheme is illustrated in Figure 2.1 (a)-(f).
Handle Wafer Attachment
Figure 2.1 (a)-(f) depicts the process sequence to fabricate a 3-D CMOS inverter. The
bottom device layer is an n-MOS device fabricated on bulk Si, while the top device layer
is a p-MOS device fabricated on an SOI wafer independently prior to stacking. To start
with, the front side of the top layer is attached to a handle wafer as shown in Figure 2.1
(b) to provide mechanical support for ease of wafer handling. Therefore, the bonding has
to be strong enough to hold the SOI wafer during subsequent processes. Note that this
bonding is a temporary one, as the handle wafer will be released from the final 3-D stack.
This dictates the need for ease of handle wafer release at the end. Low temperature oxide
wafer bonding [29] is used in this thesis.
33
Temporary
mechanical
bond
(a) Two (almost) fully processed
wafer's.
(b) SOl wafer is attached to a
handle wafer.
(C) SOI wafer backside thinning.
Permanent
electrical
bond
(d) Cu vias and pads are created.
(e) Cu-to-Cu wafer bonding.
(f)
Handle wafer release.
Figure 2.1. Process flow for 3-D integration scheme using Cu wafer bonding.
SOI Thin Back
In Figure 2.1 (c), the SOI substrate is thinned back after bonding to a handle wafer. A
combination of mechanical grinding, plasma dry etch and chemical wet etch can be used
for this thinning step. In order to achieve good etch stop behavior, it is typical to etch the
final 50 to 100 gm of Si using a wet chemical etch. The buried oxide (BOX) serves as the
etch stop layer, as there is an excellent selectivity between Si and oxide in wet etchant.
The handle wafer has to be protected against chemical attack by SiO 2 coating.
34
Backside Vias and Bonding Pads Formation
Backside interlayer vertical vias and Cu pads are created on the thinned SOI wafer. Note
that in this 3-D integration scheme, the requirement for via aspect ratio is relaxed, as vias
are formed on both wafers and connected. There are two sets of Cu pads. The first set is
the via landing pads to form the electrical connection between both device layers, and the
second set is the dummy pads to increase the bonding area and hence increase the
bonding strength. This is schematically shown in Figure 2.1 (d).
Cu Thermo-compressionBonding
Figure 2.1 (e) shows that the top device layer is aligned to the bottom device layer,
presumably with Cu pads already created on it, and bonded at low temperature with a
constant down force in an inert ambient. A final post-bonding annealing step allows interdiffusion at the Cu-Cu interface and promotes grain growth.
Handle Wafer Release
The top donor wafer is bonded to the silicon handle wafer using oxide fusion bonding.
The handle wafer can be removed from the final 3-D stack by a combination of
mechanical grinding and wet etch. Alternatively, a less abusive method such as hydrogen
induced wafer splitting can be used. Hydrogen is implanted into the handle wafer prior to
bonding. The handle wafer can be released by annealing at a temperature higher than the
temperature used during Cu thermo-compression bonding to form the permanent bond.
Using metal as the bonding interface between active layers is an attractive choice
because metal is a good heat conductor and this will help circumvent the heat dissipation
35
problem encountered in 3-D ICs. At the same time, a metal interface allows additional
wiring and routing. Cu is the metal of choice because it is a mainstream CMOS material,
and it has good electrical (pcu =1.7 mQcm vs. PAl =2.65 mQcm) and thermal (Kcu = 400
W m- 1 K-1 vs. KAl = 235 W m-1 K-1 ) conductivities and longer electro-migration lifetime.
Another advantage offered by the metal bonding interface is that the metal layer can act
as a ground shield if properly grounded, hence achieving better noise isolation between
device layers on the stack. Note that we have used a back-to-face bonding approach. In
this back-to-face bonding approach, the SOI wafer is thinned and bonded to the substrate
wafer, hence eliminating the potential damage from the SOI thinning step to the whole 3D stack.
The above flow is completed with two bonding steps: (a) a temporary bond
between donor and handle wafers using oxide fusion bonding, and (b) a permanent bond
between donor layer and substrate wafer using Cu thermo-compression bonding. Both
types of wafer bonding are studied in the next chapters in terms of bonding mechanism
and reliability. Silicon layer stacks bonded by Cu are also demonstrated based on the
above flow.
36
Chapter 3
Copper Thermo-Compression Bonding
In this chapter, low temperature (400 0C and below) thermo-compression of coppercoated wafers is studied. Careful surface preparation is used to ensure that a reliable bond
is achieved. Copper grain microstructure evolution during bonding and annealing is also
monitored. Reliability issues related to the bonded Cu layer, such as voids at the bonding
interface, are examined. Finally, counter-measures to control voids formation are
proposed and implemented.
3.1 Blanket Copper Wafer Bonding
Copper (Cu) thermo-compression is studied to achieve a permanent bond to hold active
device layers together in a multi-layer three-dimensional (3-D) silicon layer stack.
Metallic Cu wafer bonding is an attractive choice because the same bonding medium acts
as an electrical bond to establish a conductive path between active layers in a 3-D IC, and
as a mechanical bond to hold the active layers together reliably. Metallic bonding also
allows a "via-first" approach for vertical integration, and hence relaxes the aspect ratio
requirement on interlayer via. Higher via density is also possible since less silicon area is
consumed to form the interlayer via.
37
3.1.1 Thermo-Compression Bonding of Cu
3.1.1.1
Wafer Preparationand Bonding Procedures
In this section, wafer bonding by Cu thermo-compression is demonstrated and
characterized on blank Si wafers. All wafers used in this experiment were p-type 150 mm
Si(100) wafers of 10-20 Q-cm resistivity. Thermal oxide (5000A) was grown on the
wafers. All wafers received a 10 min piranha (H 2 0 2 :H2 SO 4
=
1:3 by volume) solution
clean followed by deionized water rinse and spin-dry prior to metallization. The next step
was the deposition of Tantalum (50 nm) and Copper (300 nm) in an e-beam deposition
system. Chamber pressure during metal deposition was 1
x
10-6 Torr. Cu and Ta pellet
purities were 99.999% and 99.95 % respectively.
A pair of wafers was aligned face-to-face in an Electronic Vision EV620 Aligner
and clamped together on a bonding chuck. Three separation metal flaps each 30 gm thick
were inserted between the wafers at the edges and loaded into an EV501 bonder. Three
cycles of N2 purge ware done, and the chamber was evacuated to 1 x 10-3 Torr. At this
point, a down force was applied on the wafer pair while the flaps were being pulled out.
The temperatures of the chuck and top electrode were ramped up to 300
0C
and
maintained at that temperature. The contact force was 4000 N when the wafer pair was in
full contact at 300 0 C, and the bonding step lasted for 1 hour. After bonding, the bonded
wafers were annealed in atmospheric N2 ambient for 1 hour at 400 0 C. In order to prepare
the bonded wafers for cross sectional examination of the bonded Cu layer, one side of the
bonded wafers has to be thinned back to the buried oxide layer. Wafer thinning was
achieved using a combination of mechanical grinding and selective tetra-methylammonium-hydroxide (TMAH) etch. Approximately 600 out of 675 pm of one wafer
38
(b)
(a)
Si substrate
Si substrate
50
Ta rr).
.. .. .S0G2 (5MC nrr ......
Te (50 nrT)
TOs
Te (5C nrr)
25(5(X nr
...
. . . . . . . ..
---nr
Ts~~~~
~O
(50C
-
---
Si substrate
Si substrate
Cu-tc-Cu thermocompression bonding
Top Si substrate thin back
Figure 3.1. Sample preparation: Direct Cu to Cu thermo-compression bonding and wafer
thin back.
was removed using mechanical grinding and the remaining 75 gm of silicon was stripped
in 12.5% TMAH at 85 *C for 100 min. Since TMAH is highly selective to Si0 2, etching
stopped on the oxide layer. Cross-sectional study can then be performed. The above steps
are schematically summarized in Figure 3.1.
3.1.1.2 Bonding Mechanism
Figure 3.2 shows a plan view of as-deposited Cu on oxide wafer. Small grains on the
order of 20-100 nm are clearly seen from the SEM image. The root-mean-square (RMS)
surface roughness of this Cu layer is estimated from an atomic force microscopy (AFM)
surface scan using tapping mode. Figure 3.3 is a 5 gm x 5 gm AFM image of the Cu layer
and its surface roughness is estimated to be about 1.99 nm. Figure 3.4 (a) shows a cross
section of as-deposited Cu layer on oxide wafer prior to bonding. The cross section of the
39
..............................
.. . .....
Figure 3.2. Plan view of as-deposited copper on oxide wafer.
bonded Cu layer sandwiched within two oxide layers is shown in Figure 3.4 (b). Note
that the two Cu bonding layers merge and a homogeneous bonded layer is obtained. In
order to understand the microstructures of the bonded Cu layer, transmission electron
microscopy (TEM) analysis is performed on this sample. Two TEM images with
different magnification are shown in Figure 3.5. As can be seen from these images, large
5.00
2.50
0
20.
0
nmn
10.
0
nmn
0.0
nm
0
5.00
2.50
Figure 3.3. AFM scan of as-deposited Cu on oxide wafer prior to bonding. The
surface roughness of the Cu layer is estimated to be 1.99 nm.
40
(a)
(b)
Figure 3.4. SEM image of bonded Cu layer sandwiched between oxide layers. Cu-coated
0
wafers were bonded at 300 C for 1 hour followed by an anneal at 400 C for 1 hour.
Cu grains, which often extend beyond the original bonding interface, are obtained after
bonding and annealing. Dislocation lines are also found in the Cu grains.
A possible bonding mechanism that gives rise to the above grain structures will be
grain
proposed in this section. From the TEM images, it is evident that there is substantial
intergrowth during bonding and annealing. The jagged Cu-Cu interface suggests that
diffusion between two Cu layers has taken place. During bonding and subsequent
annealing, Cu layers are in intimate contact under the applied pressure. At the bonding
temperature, Cu atoms acquire sufficient energy to diffuse rapidly, and Cu grains begin to
grow. At the bonding interface, diffusion can happen across the bonding interface and
grains growth can progress across the interface. After sufficiently long duration, large Cu
grains on the order of 300-500 nm are obtained, and a homogeneous bonded Cu layer is
formed.
41
(a)
0
pm
100
nm
(b)
Figure 3.5. (a) TEM image of bonded Cu layer. Note that the bonding Cu layers merge
and a homogeneous Cu layer is obtained after bonding and anneal. (b) Close-up view of
the microstructures of bonded Cu layers. Grain structures that extend across the original
bonding interface are observed. Dislocation lines (marked with arrows) are clearly seen
in the grains.
3.1.1.3 Surface Roughness
One of the key requirements for successful wafer bonding is low wafer surface microroughness. Rough surfaces will reduce the amount of contact area and hence degrade the
42
50.0 nm
5.00
25.0 nm
2.50
0.0
nm
0
0
5.00
2.50
Figure 3.6. AFM scan of as-deposited Cu on poly-Si prior to bonding. The surface
roughness of the Cu layer is estimated to be 8.59 nm.
quality of the final bond. The above experiment was repeated using wafers having higher
surface roughness. To achieve this, poly-Si was deposited on wafers having 5000
A of
thermal oxide prior to metallization. The thickness of the poly-Si layer is 4000
Tantalum (500
A)
and Copper (3000
A)
A.
were then deposited as before. Bonding and
annealing were repeated on these wafers with poly-Si as the capping layers.
The surface roughness of the as-deposited Cu layer on poly-Si is estimated from
AFM, and the surface scan is shown in Figure 3.6. The RMS roughness is markedly
increased to 8.59 nm. It is found that bonding can be achieved despite significant increase
in the surface roughness as evidenced from Figure 3.7. Figure 3.7 shows cross-sectional
SEM images of the as-deposited Cu layer on poly-Si, and the bonded Cu layer. The
wiggling surface of the poly-Si layer is clearly seen. A close-up view of the Cu grains in
the bonded layer is shown in the TEM image in Figure 3.8. As with the case of bonded
Cu having oxide as capping layers, large Cu grains, which often extend beyond the
43
original bonding interface are obtained. Despite significant increase in the surface
roughness when poly-Si is used as capping layers, a seamless and continuous bonded
0
layer is obtained. This is direct evidence that with the applied temperature (300-400 C)
and contact force (4000 N) during bonding and annealing, atom diffusion and grain
growth can overcome surface irregularities to form a homogeneous Cu layer. Electron
Dispersion Spectroscopy (EDS) analysis of the bonded Cu layer in Figure 3.9 shows that
apart from Cu, no appreciable foreign contaminant is found in the bonded layer.
3.1.1.4 Choice of Cu
In the above experiment, metals are deposited in an e-beam deposition system. Since ebeam deposition is not used in typical manufacturing environments for metallization, the
(a)
(b)
Figure 3.7. SEM image of bonded Cu layer sandwiched between poly-Si layers. Cu0
coated wafers were bonded at 300 0C for 1 hour followed by an anneal at 400 C for 1
hour.
44
0
O'k),OW IIM
Figure 3.8. Close-up view of the microstructures of bonded Cu layers. Grains structures
that extend across the original bonding interface are observed. Dislocation lines (marked
with arrows) are clearly seen in the grains.
above demonstration of Cu thermo-compression is repeated using Cu deposited by
electro-chemical means. Tantalum diffusion barrier and Cu seed layers were deposited in
an e-beam system for 500 A each. The wafers were then plated with an additional 2000
A
of Cu. Wafer bonding and anneal were repeated using the same process parameters as
before.
Figure 3.10 (a) shows the cross-sectional view of the as-deposited Cu layer, and
Figure 3.10 (b) shows the bonded Cu layer. Note that the plated Cu layers merge and a
homogeneous bonded Cu layer with grains that extend beyond the original bonding
interface is obtained. Grain boundaries are marked with arrows. This experiment proves
that Cu thermo-compression bonding can also be achieved using electroplated Cu.
45
Cu
600-
400Cu
0
0
200-
PU
0
5
10
15
Energy (keV)
Figure 3.9. EDS profile of the bonded Cu layer. No appreciable contaminant is found.
3.1.1.5 Surface Oxide
Low temperature (400 *C and below) direct Cu to Cu thermo-compression bonding is
demonstrated above. Since the mechanism for Cu thermo-compression bonding is based
on Cu inter-diffusion and grain growth, surface contaminants such as oxide are
detrimental to successful bonding especially at very low temperature. However, there is
(b)
(a)
Cu /plating ~ 200 nmn
Cu /e-beamn ~ 50 nmn
S0,
Figure 3.10. Thermo-compression of electro-plated Cu. (a) As-deposited Cu, and (b)
bonded Cu layer. (Sample credit: Joyce Wu)
46
more often than not a time lag between Cu deposition and bonding, and therefore the
formation of surface oxide is inevitable. Excessive oxygen incorporation into the bonded
Cu layer might also increase the resistivity of the Cu layers and hence degrade the
electrical performance of Cu interconnects. Techniques that can be used to reduce the
surface oxide prior to bonding include the use of a chemical clean such as HCl [23] and
glacial acetic acid followed by a forming gas purge in the bonding chamber [30] prior to
bonding. In this section, forming gas anneal is performed on Cu wafers prior to bonding
and experimental evidence of the reduction of oxygen content in the bonded Cu layer is
presented.
All wafers used in this experiment were n-type 150 mm Si-(100) blanket wafers.
5000A of thermal oxide is grown as a buried oxide (BOX) on silicon wafers, followed by
the deposition of 4000 A of undoped poly-silicon at 620C. Pairing wafers are bonded
using Cu as the bonding medium. Prior to bonding, 50 nm of tantalum (Ta) and 300 nm
of Cu were deposited on the donor and the substrate wafers in an e-beam deposition
system. Wafers with Cu layer on top are denoted as Cu wafers in the remainder of the
text. Ta acted as a diffusion barrier [31] to prevent Cu diffusion into the device layer
which might degrade the electrical integrity of the device layer in an actual process. After
metal deposition, all wafers were split into two groups and were stored in the clean room
for 12 hours and 12 days, respectively, to allow different amount of surface oxide to form
prior to thermo-compression bonding. They are denoted as sample 1 and 2 in the
following text. The relative humidity and the temperature in the clean room were about
40% and 20 0C.
47
5000
4500-
2p, 2(Cu)
400035002p,,(Cu)
/_ 3000
2p.(CuO)
2(CuO)
-
2500
-12 days
S2000 -
1500.12 hours
1000500
I
I
I
I
I
970
960
950
940
930
Binding Energy (eV)
Figure 3.11. XPS spectra of Cu-covered wafers after 12 hours and 12 days storage in the
clean room. Signals of Cu 2 p12 and 2 p3/2 from CuO become stronger after 12 days of
storage.
After the specified time lag, a donor wafer (sample 1) was aligned to a pairing
substrate wafer (also from sample 1) in a face-to-face fashion in an EV Group aligner.
The wafer pair was clamped together on a bond chuck and separated by three 30 pim thick
metal flaps and was transferred to the bonding chamber. After three cycles of nitrogen
0
(N 2 ) purge and pump-down, thermo-compression bonding was performed at 300 C under
a contact force of 6 kN for 1 hr in vacuum. We repeated the above steps for wafers from
sample 2. In addition, one pair of Cu wafers similar to sample 2 were annealed in forming
0
gas (95% N 2: 5% H 2 , by volume) ambient in the bonding chamber at 150 C for 15 min
prior to bonding. This pair of wafers will be denoted as sample 3. Note that sample 1 and
48
2 were annealed in inert N2 ambient at 150 0C for 15 min before bonding to ensure the
same amount of thermal budget in all samples. All bonded pairs were then annealed in
atmospheric N2 ambient at 400 C for 1 hr to allow Cu inter-diffusion and grain growth to
achieve higher bonding strength. The substrate of one of the bonded wafers was thinned
back using a combination of mechanical grinding and tetramethyl-ammonium hydroxide
(TMAH) strip.
Copper-covered
wafers
were
examined
for surface
oxide
using X-ray
photoelectron spectroscopy (XPS) after 12 hours and 12 days storage before wafer
bonding. Figure 3.11 shows XPS spectra of sample 1 and 2 obtained using an Al K"
(1486.6 eV) source. Both spectra are aligned with respect to the Cis peak at 285 eV. Since
sample 2 was stored longer in air than sample 1, one can expect more surface oxide on
sample 2. This is reflected by the stronger Cu
2
p1/2
(953.7 ev) and
2
P3/2
(934.2 eV) peaks
from cupric oxide (CuO) in the spectrum of sample 2. In order to estimate the oxide
thickness, sample 2 was subjected to sputter etch, and the concentration of oxygen (0)
was monitored using Auger Electron Spectroscopy (AES). The sample surface was
sputtered with Ar' ions at 3 keV for a duration of 5 s and the concentration of oxygen
was analyzed. These steps were repeated until oxygen diminished. Figure 3.12 is a plot
that shows 0 concentration at different stages during etching. Note that the 0 signal
diminishes completely after 75 s of sputter etch. Since the etch rate of copper oxide under
this etch condition is not well calibrated, the copper oxide thickness can be expressed in
terms of other well-known materials such as silicon dioxide. Given that silicon dioxide
etch rate is 0.47 A/s under this condition, the copper oxide thickness on sample 2 is
approximately 35.3 A of SiO 2 equivalent.
49
100-
80 -
_
60
.
C
A-Cu
0
o
-u-
-C.,U
40-
20-
I
0
20
40
60
-
-,
80
Etch time (s)
Figure 3.12. Auger Electron Spectroscopy (AES) signals of various elements in sample 2
as a function of sputter etch time.
In order to quantify the oxygen content in the bonded Cu layers, we performed
secondary ion mass spectrometry (SIMS) analysis on the bonded Cu layers. The top
buried oxide layer was stripped in hydrofluoric (HF) solution to facilitate the analysis.
SIMS analysis was performed using Cs+ as primary ions at 15 keV. Figure 3.13 shows
the oxygen profiles in poly-Si, Ta and bonded Cu layers from all three samples described
above. In the SIMS profiles, the quantification is only valid for the oxygen in the Cu
layers, and the oxygen peaks at poly-Si/Ta and Ta/Cu interfaces are likely due to ion
yield effect in different material matrixes. The Cu profile is included to assist in
identifying different layers. Since a Cu sputter rate is used for the entire profile, the Cu
thickness is approximately correct but the other thicknesses will not be correct due to
50
1E22
+-
e
-A.- I
E
02
E
12 hours
12 days
Original bonding interface
12 days with forming
gas anneal
lCl
0 1E21
C
1 E7
-
C
0
C
0
C
0
C
0
C
0
U
1E20 -
0
1000 a0.
,AAAAAAAAAAAAAAAAAAAAAAAAAAA&AAA
S.
0
*0OS0SSO*00O@*OS@SO@SSOS4040
0
1E19-
--
9
0.0
Ta
Tq
Poly-Si
i
:
PI
SiCO
0.2
0.6
0.4
Cu-Cu
CU C
0.8
0.1
1.0
Depth (gm)
Figure 3.13. SIMS profiles of the oxygen content in the bonded Cu layers with different
pre-bonding exposure to the air.
their different sputter rate relative to Cu. In addition, since there is significant roughness
in the unpolished poly-Si layer, the depth resolution of all layers will be limited.
From Figure 3.13, there is detectable oxygen concentration in the bonded Cu layer
when the Cu wafers were exposed to the air for 12 hrs prior to bonding. Due to the
presence of surface oxide, the oxygen concentration is higher at the original bonding
interface. Oxygen atoms diffuse from the bonding interface into the Cu layer during
bonding and annealing. The oxygen content at the original Cu bonding interface is
estimated to be 0.08 atomic %. Since the Cu source is 99.995% pure and the e-beam
deposition was performed at a base pressure of 10~6 Torr, the additional oxygen in the Cu
layer is likely to originate from the deposition chamber and from the air during the 12
hours time lag between Cu deposition and bonding. The oxygen peak value increases to
51
2.96 atomic % (-37 X) in sample 2. Since the Cu wafers from sample 2 were kept for 12
days in the clean room, the surface oxide was thicker (compared to sample 1) prior to
bonding. Upon bonding and annealing, oxygen atoms from the oxide layer at the
interface diffuse into the Cu layers and resulted in higher oxygen content in the bonded
layer.
However, if the pairing Cu wafers were annealed in forming gas in the bonding
chamber prior to bonding at 150 0C for 15 min (sample 3), the oxygen concentration
close to the original bonding interface drops to 0.52 atomic %. In order to explain this
observation, we can begin by looking at the oxidation of Cu and reduction of copper
oxide. Cu can be oxidized readily in the atmosphere and the growth of Cu oxide is not a
self-limiting process. During oxidation, cuprous oxide (Cu 2 0, also known as red oxide)
forms initially followed by cupric oxide (CuO, also known as black oxide) [32]. When
Cu wafers with a surface oxide layer are annealed in forming gas, hydrogen can act as a
reducing agent to convert the surface oxide back to elemental Cu. These reactions are
exothermic and can be described by the following [33], [34]:
CuO + H 2 -- Cu + H 20 (AH = - 87.1 kJ/mol at 650K)
Cu 2O
+
H 2 -. 2Cu + H 20 (AH = - 91.0 kJ/mol at 673K)
52
[1]
[2]
(a)
Sample 1
(b)
Sample 2
(C)
Sample 3
Figure 3.14. SEM micrographs of bonded Cu layers from Cu wafers with different
exposure to the air prior to thermo-compression bonding.
In Figure 3.13, since the oxygen content is higher in sample 3 than in sample 1,
we can conclude that the reduction of surface oxide to elemental Cu is not complete in
sample 3 under the bonding and annealing conditions used in this experiment. Since the
reduction reaction starts from the top of the wafers, the bonding interface is free from
surface oxide but there is a layer of buried copper oxide in the Cu wafers. During
bonding and annealing, oxygen atoms from the buried copper oxide layer out-diffuse and
are redistributed across the bonded Cu layer. Since the surface is free from oxide before
53
bonding, the oxygen concentration at the interface is expected to be lower than at the
location where buried oxide remains. This explains the dip (instead of a peak as in sample
1 and 2) in the SIMS profile of sample 3. Further reduction of oxygen content in the
bonded layer might be achievable with forming gas anneal at higher temperature or
longer anneal duration. In an actual process, however, longer anneal duration is more
favorable than higher anneal temperature to prevent unwanted damage to the device
layers. Since forming gas anneal is widely used in semiconductor processing to enhance
both interface and oxide trap generation at poly-Si/SiO2 interface [35], the use of forming
gas anneal during Cu wafers bonding is compatible with mainstream processes.
It is also interesting to investigate the effect of surface oxide on the grain growth
during bonding and annealing. Figures 3.14 (a)-(c) show close-up SEM images of all the
bonded Cu layers from samples 1, 2, and 3. Substantial inter-diffusion and grain growth
in all bonded Cu layers can be observed in the close-up SEM images, as evidenced by Cu
grains that extend from one end to the other. The original bonding interfaces disappear
and homogeneous bonded Cu layers are obtained. Note that despite the presence of
surface oxide in samples 1 and 2, these Cu wafers can be bonded successfully and
significant grain growth can be observed at bonding temperature of 300 0C and annealing
temperature of 400 0C. Therefore, it can be concluded that Cu wafers can be kept for up
to at least 12 days without affecting their ability to bond at these temperatures. The effect
of surface oxide on grain growth during bonding and annealing at temperature below 300
0C
is under investigation.
54
i. . _!
..
........
160
100000
30Si
U)Q
co
10000
65Cu
0
Cn
0
C
100
0
10
SiO 2
0
100
200
300
400
Ta
500
Cu-Cu
600
700
Depth (nm)
Figure 3.15. SIMS profile of Cu in area adjacent to the bonded Cu layer.
3.1.1.6 Copper Out-diffusion
Cu diffusion in silicon and silicon dioxide is a known problem and the diffusion is
enhanced at high temperature. During Cu thermo-compression bonding, temperature in
the range of 300-400 0C is applied. It is hence important to ensure that Cu does not
diffuse into the surrounding oxide layers during bonding and annealing. In this
experiment, Ta is used as a diffusion barrier. The extent of Cu out-diffusion during
bonding and annealing is studied from SIMS analysis. Figure 3.15 is a SIMS profile that
shows Cu trace in the area adjacent to the bonded Cu layer. Note that Cu concentration
drops sharply in the Ta and Si0 2 layer. This is encouraging, as it shows that Cu does not
out-diffuse into surrounding oxide layer under 300 C / 1 h of bonding and 400 C / 1 h of
annealing, hence confirming the role of Ta as an effective diffusion barrier.
55
___
--
-
3.1.2 Process Parameters
There are a number of important process parameters that directly determine the quality of
the final bond during Cu thermo-compression bonding. In this section, three important
bonding parameters, i.e., temperature, duration and contact pressure, will be studied by
examining the grain structure in the bonded Cu layer.
In the bonding procedures described in Section 3.1.1, thermo-compression
bonding of Cu is accomplished in two steps, i.e., an initial bonding step to establish bond
between pairing wafers and a post-bonding anneal to enhance the bond. Since the
bonding step is a single wafer pair step, long bonding duration will decrease through-put
in a manufacturing environment. However, annealing can be accomplished in an
atmospheric furnace and it is possible to process batches of wafers during annealing.
Therefore, a better way to achieve high through-put Cu wafer bonding is to initiate a
preliminary bond with a short bonding step and to enhance the bonding strength with a
post-bonding anneal.
3.1.2.1 Bonding Duration
Cu wafers were bonded using oxide as the capping layers. Bonding was done at 300 0C
under a contact force of 4000 N for 5, 10, 15, 30, and 60 min. A second group of wafers
bonded for each of these durations is further annealed for 1 hour at 300 0C. The grain
structure of the bonded Cu layer is examined with cross-sectional SEM.
Figures 3.16-3.20 are SEM images showing Cu grain structures in the bonded
layer for various durations, with and without post-bonding anneal. As shown in Figure
3.16 (a), a bonding interface can clearly be seen after 5 min of bonding. Inter-diffusion of
56
Cu atoms across the bonding interface is limited. However, lateral grain growth has taken
place and Cu grains begin to emerge. The grain boundary arising from the bonding
interface begins to migrate with 10 min of bonding, and a zigzag interface appears in
(a)
(b)
Figure 3.16. SEM images of grain structures in bonded Cu layer: (a) bonded at 300 *C for
5 min, and (b) annealed at 300 C for 1 hour after bonding.
(b)
(a)
Figure 3.17. SEM images of grain structures in bonded Cu layer: (a) bonded at 300 C for
10 min, and (b) annealed at 300 *C for 1 hour after bonding.
(b)
(a)
0
Figure 3.18. SEM images of grain structures in bonded Cu layer: (a) bonded at 300 C for
30 min, and (b) annealed at 300 C for 1 hour after bonding.
57
Figure 3.17 (a). Lateral grains on the order of 0.2-0.3 gm can be seen clearly. Since the
extent of grain growth in the direction perpendicular to the bonding interface is still
limited, Cu grains are largely confined in their original layers. As bonding duration
increases to 15 min and 30 min, substantial grain growth can be seen in both directions.
Large Cu grains on the order of 0.5 pm that extend beyond the original bonding interface
are observed in both Figures 3.18 (a) and 3.19 (a). Cu grains that extend from one end to
the other end are achievable with 1 hour of bonding as evidenced from the SEM image in
Figure 3.20 (a).
(a)
(b)
Figure 3.19. SEM images of grain structures in bonded Cu layer: (a) bonded at 300 0 C for
30 min, and (b) annealed at 300 C for 1 hour after bonding.
(a)
(b)
Figure 3.20. SEM images of grain structures in bonded Cu layer: (a) bonded at 300 C for
lh, and (b) annealed at 300 0 C for 1 hour after bonding.
58
Since the bonded layer will be used to conduct current in real applications, large
Cu grains can reduce the number of grain boundaries, hence providing a high
conductivity path in the bonded layer. While it is possible to achieve large Cu grains with
bonding alone as described above, long bonding duration (30 min and above) will reduce
the final through-put in a manufacturing environment since bonding is a single wafer pair
step. In Figure 3.16 (b), large grains are observed in Cu bonded at 300 0C for 5 min with
a post-bonding anneal at 300 C for 1 hour. This is a promising observation since one can
process multiple bonded wafer pairs during post-bonding anneal in an atmospheric
furnace after bonding for higher through-put.
3.1.2.2 Bonding Temperature
Thermo-compression of Cu is studied for possible integration into mainstream processes
to fabricate multi-layer 3-D ICs. Since this involves bonding device wafers that have
completed front-end and some back-end steps, low temperature bonding is highly
desired. This is essential to prevent damage to the devices and to be compatible with lowK
dielectrics. Low temperature bonding is also important to reduce thermal stress due to
thermal mismatch of different materials.
Cu wafers were bonded using poly-Si as the capping layers. Bonding is done for 1
hour under a contact force of 4000 N at 200, 300, and 400 0 C. No post-bonding anneal is
performed on these bonded wafer pairs. The grain structure of the bonded Cu layer is
examined with cross-sectional SEM.
Figure 3.21 (a)-(c) is a summary of cross-sectional SEM images showing grain
structures in Cu layers bonded at 200, 300, and 400 C, respectively. All bonded Cu
59
(a)
200 OC
(a)
300 OC
400 OC
Figure 3.21. SEM images of grain structures in Cu layer bonded for 1 hour at: (a) 200 0 C,
(b) 300 0C, and (c) 200 C.
layers exhibit large grains that extend beyond the original bonding interface. The result
from Cu layers bonded at 200 C is particularly encouraging since thermal budget can be
reduced significantly for wafers bonded at this temperature.
3.1.2.3
Contact Force
Cu layers can be bonded based on high temperature Cu atom diffusion across the bonding
interface and grain growth. Therefore, a determining factor to achieve wafer bonding is to
have intimate contact between pairing wafers at the atomic level. During thermocompression bonding, down force is applied on the wafer pair that is clamped on the
60
(a)
(b)
(c)
(d)
(e)
Figure 3.22. SEM images of grain structures in Cu layer bonded at 300 C with contact
force: (a) 2 kN, (b) 4 kN, (c) 6 kN, (d) 8 kN, and (e) 10 kN.
bonding chuck. The uniformity of the applied contact force is affected by surface
irregularity due to wafer bow and contaminants. At high temperature, the wafer can
deform more easily, hence the uniformity can be enhanced. This section examines grain
structures in bonded Cu layers as well as bonding uniformity under various contact force.
Cu wafers were bonded using poly-Si as the capping layers. Bonding was done
for 1 hour at 300 0C under contact forces of 2, 4, 6, 8, and 10 kN. Since 150 mm wafers
were used in this experiment, the corresponding bonding pressures were 113, 226, 340,
453, and 566 kPa, respectively. All pairing wafers exhibit wafer bow lower than 20 tim.
61
Figure 3.23. Images of bonded wafer pairs after etch-back. These wafers are bonded
under contact force of (a) 2 kN, and (b) 4 kN.
No post-bonding anneal was performed on these bonded wafer pairs. The grain structure
of the bonded Cu layer was examined with cross-sectional SEM.
Figures 3.22 (a)-(e) is a summary of cross-sectional SEM images showing grain
structures in Cu layers bonded using the above pressures. All bonded Cu layers exhibit
large grains that extend beyond the original bonding interface. As can be seen from
images of bonded wafer pairs after etch-back in Figure 3.23, a highly uniform bond is
achieved under contact force of 2 kN. A uniform bond is achieved across the entire wafer
except at the wafer edge and flat, because no Cu is deposited approximately 1-2 mm from
the edges and laser scribe marks are present at the flat area. With the integration of
porous low-K dielectrics having lower mechanical strength, it is more advantageous to
lower the contact force to maintain structural integrity of these materials.
3.2 Reliability of Bonded Copper Layer
In order for the bonded Cu layer to act as a reliable electrical or mechanical bond, a
defect-free and uniformly bonded Cu layer is desired. In this section, the observation of
62
interfacial voids within the bonded Cu layer and debonding of bonded thin film are
studied. These observations point to the need for careful attention during Cu thermocompression bonding.
3.2.1 Observation of Interfacial Voids
Oxide wafers coated with Cu were bonded at 300 0C for 1 hour under a contact force of 4
kN. One of the pairing wafers was thinned back to the buried oxide layer, and crosssectional SEM analysis was performed. Careful examination by SEM analysis across a
length of 20 pm reveals large voids in the bonded Cu layers as shown in Figure 3.24.
These voids are located at and near the location of the original bonding interface. These
voids can provide nucleation sites for electromigration failure and can lead to open circuit
failures. When the void density is too high, the voids can also cause thin film
delamination. Therefore, this observation requires careful understanding of the origin of
these voids so that counter-measures can be implemented.
3.2.1.1 Nucleation and Growth
Interfacial void nucleation and growth are discussed in this section. Figure 3.25 is a
collection of SEM images showing void density and size at various stages during Cu
wafer bonding at 300 0C. These images can be used to describe the formation and growth
of the interfacial voids.
63
Figure 3.24. Observation of voids in the bonded Cu layer. This layer is bonded at 300 *C
for 1 hour.
Voids can nucleate at local interfacial irregularities arising from surface
contamination (e.g., hydrocarbons or native oxide on the pre-bonded Cu surface) and
surface roughness. When pairing wafers are brought into contact, these surface
irregularities prevent intimate contact between two Cu surfaces at the atomic level. When
the temperature is ramped to the desired bonding temperature and maintained at that
temperature, Cu atoms diffuse across the bonding interface via the contacted areas. As
grain growth across the interface continues, micro-voids are formed at the bonding
interface. This can be clearly seen in Figure 3.25 (a) for Cu layer bonded for 10 min.
These micro-voids are highly mobile. As bonding is prolonged and as Cu grains become
larger, these micro-voids will diffuse along grain boundaries defined by the original
bonding interface. As these micro-voids diffuse, they coalesce to form bigger voids as
shown in Figure 3.25 (b) for 30 min of bonding. At the triple points, the movement of the
void is impeded, and the void will grow in size at the expense of smaller voids as shown
in Figure 3.26 (c) when the bonding continues for 60 min. The size of the void is about
64
0.3 pm in this SEM image. Therefore it can be concluded that voids nucleate at a much
smaller size and then grow in size as smaller voids coalesce.
Another factor that contributes to void growth is vacancy coalescence during
bonding. Since Cu is deposited on oxide wafers at low temperature, one begins with a
high density of vacancies in the Cu layer. The wafer temperature during Cu deposition in
the e-bam system is estimated to be about 68
C. Since the bonded Cu layer is
constrained between the wafers, there are no free surfaces for excess vacancies to diffuse
to and to self-annihilate. During bonding, these vacancies are absorbed at the grain
boundaries. As the grain size continues to increase during annealing, fewer grain
(a)
(b)
10 min
(C)
0
Figure 3.25. Interfacial void growth during Cu thermo-compression bonding at 300 C for
(a) 10 min, (b) 30 min, and (c) 60 min.
65
(a)
(b)
(c)
(d)
Figure 3.26. Variation of interfacial void sizes in Cu layers bonded at various conditions:
(a) 300 'C / 1 hour, (b) 400 *C / 1 hour, (c) 300 'C / 1 hour with poly-Si caps, and (d) 300
'C / 1 hour with 100 *C / 30 min pre-bonding anneal.
boundaries are available to absorb these vacancies. As a result, increased void nucleation
and growth at triple points and along interfaces can be expected.
When the bonded wafer pair is cooled from the bonding temperature down to
room temperature, high tensile stress builds up in the Cu layer due to mismatch in
thermal expansion between the Cu and adjacent layers. Thermal stress analysis will be
presented in Chapter 8. Under such stress conditions, the bonded Cu layer could
potentially deform and result in interfacial voids. Therefore, interfacial void formation in
the bonded Cu layer could be a likely avenue to accommodate the high tensile stress
resulting from thermal mismatch.
66
Figure 3.26 shows a number of SEM images of Cu layers bonded under different
conditions. By comparing Figures 3.26 (a) and 3.26 (b), it is noticed that the size of the
void is larger when the bonding temperature is increased from 300 0 C to 400 0C. During
bonding, dislocations can climb and emit or absorb point-defects. In the presence of
tensile stress, dislocation climb occurs in directions that enable absorption of interstitials
or emission of vacancies. Vacancies emitted during such dislocation climb can migrate
and coalesce to help relieve some of the tensile stress. Given a higher bonding
temperature, the thermal-mismatch-induced calculated tensile-strain is higher, providing
a driving force for greater vacancy generation. The higher resulting concentration of
available vacancies can then contribute to the growth of larger voids in the case of the
higher temperature bonding.
Voids have been observed previously in Cu-based dual-damascene interconnects
under vias that connect to a wide metal lead [36]. The presence of interfacial voids in the
bonded Cu layer can lead to degraded reliability both electrically and mechanically.
3.2.1.2
Counter Measures
Based on understanding of interfacial voids formation earlier, a few counter measures are
proposed and shown in this section. Since a high bonding temperature provides greater
driving force for void generation, bonding should be designed at lower temperature.
67
(a)
(b)
100 *C /30 min
(C)
M76Ir
6..
150 *C /30 min
Figure 3.27. SEM of Cu layer afters different pre-bonding anneal: (a) no anneal, (b) 100
0C for 30 min, and (c) 150 0C for 30 min.
Figure 3.26 (c) shows SEM images of bonded Cu layers with poly-Si as capping
layer. As discussed earlier, the RMS roughness of Cu layers deposited on a poly-Si
surface is 8.59 nm as compared to 1.99 nm on an oxide surface. Higher surface roughness
presents severe surface irregularities for bonding and as a result larger voids are formed.
It is therefore essential to keep the wafer RMS roughness at a level lower than
-
2 nm.
Since processed wafers often have a rough surface, methods such as chemical-mechanical
polishing (CMP) can be used to achieve the required surface roughness prior to bonding.
As pointed out above, vacancy diffusion and coalescence can contribute to void
growth. One potential solution is to anneal the Cu layer prior to bonding. Annealing can
68
promote grain growth, and drive vacancies to the free surface where they become selfannihilated. This method is proven effective in reducing the size of voids as shown in
Figure 3.26 (d). In this sample, the Cu layers are annealed at 100 0 C for 30 min in N2
ambient in the bonding chamber prior to applying contact force to initiate the bonding
step.
Figure 3.27 shows grain structure evolution in the as -deposited Cu layer during
pre-bonding annealing. Grain growth can be observed with 100 0C anneal for 30 min. In
principle, one can reduce the number and size of voids in the bonded Cu further by
performing pre-bonding anneal at higher temperature. This attempt is not successful, as
the Cu layer begins to show signs of oxidation with 150 0 C anneal for 30 min. This is due
to the fact that the bonding chamber is not completely depleted of oxygen. The reachable
pressure is only 1 x 10-3 Torr before nitrogen is purged. Residual oxygen in the chamber
reacts with Cu drastically when the temperature is higher than 100 0C. The presence of a
thick surface oxide will impede successful bonding. One also needs to be careful in
controlling the extent of grain growth during pre-bonding anneal. Large grains in the Cu
layers might result in slower bonding, due to limited grain growth of large grains in the
Cu layers.
3.2.2
Thin Film Mechanical Integrity
Another important reliability issue in Cu wafer bonding is bonding uniformity. Bonding
uniformity will directly determine the final yield. In applications where Cu wafer
bonding is used to form 3-D structures, one of the bonded wafers is thinned down to the
required thickness. Therefore, an important aspect of bond uniformity is the ability of the
69
bond to hold transferred thin films onto the substrate reliably. The uniformity of strong
bond can be examined by thinning one of the bonded wafers down to the buried oxide
layer. At areas where bonding is not complete or weak, the thin film will delaminate from
the substrate.
Bonding uniformity is directly related to wafer bow. Cu wafers were bonded
using oxide as the capping layers. Bonding was done for 1 h under a contact force of
4000 N at 300 C. No post-bonding anneal was performed on the bonded wafer pairs.
Figure 3.28 compares two bonded and etched back wafer pairs having very different
wafer bow. When the wafer bow is in the range of 5-10 pm, strong bond is achieved
across the entire wafer as shown in Figure 3.28 (a). However, bonding uniformity is
degraded for wafers having bow in the range of 30-40 pm as shown in Figure 3.28 (b).
Severe thin film delamination is found in areas close to the wafer edge.
(a)
(b)
Figure 3.28. Photographs of bonded wafer pairs after bonding and etch-back. The wafer
bow for the pairing wafers are (a) 5-10 gm, and (b) 30-40 pm.
70
Figure 3.29. SEM image across the boundary where thin film delaminated.
To understand the cause of thin film delamination, a cross-sectional study is
performed at the boundary where the thin film is delaminated and it is shown in Figure
3.29. As can be seen in this figure, the oxide film delaminates at areas where no Cu to Cu
bond is established. Due to wafer bow, Cu layers are not in intimate contact in this area
during bonding. As a result of poor vacuum (1 x 10- Torr) in the bonding chamber,
oxygen residuals oxidize the exposed Cu. As the wafer is thinned back to the buried
oxide layer, stress causes the thin film to break and detach from the substrate.
3.3 Summary
In this chapter, thermo-compression bonding of Cu is discussed by presenting
experimental results. Blanket Cu films deposited on two oxide wafers are found to merge
and form a homogeneous layer under suitable bonding conditions, i.e., at a temperature
71
range of 300-400 C and contact pressure ~ 226 kPa. Cu grains that often extend beyond
the original bonding interface are observed in the bonded Cu layers based on cross
sectional SEM and TEM studies. Pre-bonding forming gas anneal on the Cu layers is
found to reduce the oxygen content in the final bonded layer significantly. The grain
structure in the bonded layers is also examined for various bonding conditions such as
bonding duration, temperature, and contact pressure.
The reliability of the bonded layer is seriously degraded by the formation of
interfacial void. The nucleation and growth of interfacial void are proposed and counter
measures for void suppression are implemented. Bonding uniformity across the entire
wafer is directly related to the wafer bow and in severe cases thin film delamination is
observed.
72
Chapter 4
Silicon Dioxide Fusion Bonding
Direct bonding of various chemical vapor deposition (CVD) oxides to thermal oxide is
studied. Prior to bonding, CVD oxide wafers are subjected to careful surface preparation
including densification and chemical-mechanical polishing (CMP). Oxide wafers are
bonded following surface activation, and post-bonding anneal is performed to achieve
higher bond strength. Bond strengths with respect to surface preparation and process
parameters are compared. The reliability of the bonding interface in terms of sustaining
wafer etch-back and thin film handling is examined.
4.1 Low Temperature Oxide Wafer Bonding
A silicon multi-layer stack can be fabricated either in a front-to-front [26] or back-to-front
[28] fashion. These two approaches will be elaborated in Chapters 5 and 6, respectively. In
the latter method, a silicon-on-insulator (SOI) donor wafer is first bonded to a handle wafer
to assist in SOI wafer handling in subsequent processes. The substrate of the SOI wafer is
then etched back to the buried oxide (BOX) layer. Wafer etch-back is usually completed
using a combination of mechanical grinding and chemical etch. The SOI and BOX layers
are then transferred to a substrate device wafer by a second bonding step, followed by
handle wafer release. Note that the bonding between the SOI wafer and the handle wafer is
a temporary bond, as the handle wafer will be released from the final 3-D stack. The
second bond, however, is a permanent bond that holds the thin films to the substrate.
Therefore, there are two bonding steps involved in the thin film transfer method described
73
above. Bonding media that have been investigated as the temporary bond include Cu [37],
epoxy [38], and various adhesives [22], [39]. However, these materials usually present
integration constraints such as thermal budget, endurance to chemical attack during etchback, and CMOS compatibility. We have avoided process complexity which would arise
from the use of new materials, and resorted to direct low temperature oxide-to-oxide wafer
bonding which is a natural and CMOS friendly choice in terms of materials selection.
Oxide wafer bonding has been studied and applied extensively for applications in
silicon-on-insulator (SOI) wafers [40],
[41] and micro-electro-mechanical
systems
(MEMS) [42] fabrication. Most works have concentrated on bonding thermal oxide wafers
and silicon wafers that have suitable properties for bonding. In the silicon layer stacking
flow described above, the SOI donor wafer already has devices and interconnects built on
it. Therefore thermal oxide is not available on the wafer surface, and any subsequent high
temperature step is prohibited. In this case, one can resort to oxides prepared at low
temperature (400 0C and below) by means of chemical vapor deposition (CVD) which are
used as an interlayer dielectric (ILD). However, CVD oxides prepared at low temperature
do not possess properties favorable for wafer bonding. Unlike an SOI donor wafer, the
handle wafer does not carry any devices or interconnects, hence it can endure a high
temperature oxidation step prior to bonding. In this work, we investigate the necessary
surface preparations needed for successful bonding of CVD oxide wafers (deposited at low
temperature) to thermal oxide wafers grown at high temperature for the above applications.
Bonding strength of the bonded wafer pairs with regard to surface preparation, CVD oxide
types, activation methods, annealing temperature, and annealing duration are estimated.
74
The ability of the bond to hold thin films to the handle wafer during mechanical grinding
and chemical etch are studied.
4.1.1
Wafer Preparation
A proof-of-concept study of SOI donor wafer bonding to a handle wafer using direct CVD
oxide (on SOI donor wafer) to thermal oxide (on handle wafer) wafer bonding is explored.
The choice of two different oxides will be explained below. To minimize process
complexity, all wafers used in this experiment were n-type 150 mm blanket Si(100) wafers.
Two sets of wafers were prepared: one group was the handle wafers and the other was the
dummy SOI wafers. The handle wafers were covered with 5000
A of
thermal oxide for
protection against chemical attack during SOI wafer etch-back. Wet silicon etchants such
as KOH and TMAH are known to have excellent selectivity towards thermal oxide [43].
SOI wafers are an attractive choice as starting wafers to obtain an ultra-thin silicon layer,
because the BOX layer serves as excellent etch stop layer during substrate thinning. Since
manufacturing grade SOI wafers are prohibitively expensive, SOI dummy wafers were
prepared. SOI dummy structures were prepared by growing 5000
buried oxide (BOX), followed by the deposition of 4000
A
A of thermal
oxide as
of undoped polysilicon at
6200 C. The SOI wafers were then coated with 1 pm of various CVD oxides at low
temperature. Three different CVD oxides were prepared: (a) silane source low pressure
chemical vapor deposition (LPCVD) oxide at 400 0 C, (b) silane source plasma enhanced
chemical vapor deposition (PECVD) oxide at 4000 C, and (c) tetraethyl-orthosilicate
(TEOS) source PECVD oxide at 350 0C. These oxides will be denoted as low temperature
oxide (LTO), PE-Silane, and PE-TEOS, respectively, throughout this chapter. In actual
75
....
....
...
Protective oxide (500 nm)
wafer
Si handle
CVD oxide (1 prr)
SOl (400 nm)
BOX
(500
nr)
Si substrate
Figure 4.1. Schematic shows the bonding of CVD oxide on an SOI structure to thermal
oxide on a handle wafer.
device wafers with metal interconnects, CVD oxides are an attractive choice for interlayer
dielectrics (ILD) because of their high deposition rate and low temperature process. Since
all SOI wafers already have devices and interconnects fabricated on them in an actual
process, process temperatures in all subsequent steps were kept at 400 C or below.
While CVD oxides have the advantage of a low thermal budget, they are relatively
porous and have rough surfaces that are unsuitable for successful wafer bonding. Due to the
non-equilibrium nature of the CVD process, byproducts or gas molecules may be
incorporated into the deposited film [44] and this might result in out-gassing during
subsequent processing that can debond the bonded wafer pair. Therefore, CVD oxides on
SOI dummy wafers were densified in atmospheric N2 ambient at 350 C for 5 hours to
drive away all trapped gas molecules. Since as-deposited CVD oxides exhibit relatively
high surface roughness, direct bonding using such wafers is often unsuccessful. Therefore,
76
the SOI wafers were chemical-mechanically polished after densification to increase both
the surface smoothness and the bonding yield.
To ensure that this bonding method is applicable in real device wafers, a low
temperature process is essential to avoid undesired thermal damages. Hence, a hydrophilic
bonding was chosen because this type of bonding can give reasonable bond strength even
with relatively low temperature anneal (400 0C and below). All handle wafers and SOI
dummy wafers received a 10 min piranha (H 2 0 2 : H 2 SO 4
=
1:3) solution clean followed by
deionized water rinse and spin-dry. This cleaning was necessary to clean the polished
wafers and to terminate the wafer surfaces with hydroxyl (OH) groups to initiate wafer
bonding. The pairing wafers were then bonded at room temperature as shown in Figure 4.1.
After bonding, the wafer pairs were annealed at various temperatures up to 300 0C in
atmospheric N2 ambient to enhance the bonding strength.
4.1.2 Results and Discussions
4.1.2.1 Wafer Preparation
During wafer bonding, trapped surface particles can cause undesired interface voids which
would affect the quality of the bonding interface. Infrared (IR) imaging is a convenient and
common way to examine macroscopic interfacial voids of the bonded wafer pairs. Since
both silicon (Eg = 1.12 eV) and SiO 2 (Eg = 8.0 eV) are transparent to infrared, interfacial
voids can be viewed by transmitting infrared light through one side of the bonded wafer
pair. An infrared camera can then be used to detect the interface void at the other side of
the bonded wafer pair. Besides infrared imaging, scanning acoustic microscopy and X-ray
topography can also be used to examine interfacial voids. In Figure 4.2, IR images of two
77
(a)(b
Figure 4.2. Infra-red images of bonded oxide wafer: (a) no interfacial voids, and (b)
interfacial voids due to surface particles.
bonded wafer pairs prior to annealing are shown. The SOI dummy wafers are coated with
PE-Silane oxide. Figure 4.2 (a) shows an wafer pair with a seamless bonding interface as
observed under IR camera. In Figure 4.2 (b), however, interfacial voids are observed. The
voids are caused by surface particles that are incorporated during wafer handling. Surface
particles prevent intimate contact and bonding is not achieved in the surrounding areas.
These voids can result in thin film delamination during wafer etch-back and we will discuss
this in chapter 6 on back-to-front silicon layers stacking. Therefore, it is extremely
important to have particle free surfaces during wafer bonding in order to achieve high
quality bonding.
Apart from surface cleanliness, another important requirement that affects the bonding
quality is the wafer bow [45]. It is generally agreed that a wafer bow below 25 gm is
required for 150 mm wafers [46]. Wafer bows of various wafers were measured using a
KLA-Tencor thin film stress measurement system prior to bonding and the results are
summarized in Figure 4.3. Wafer bow of an unprocessed bare silicon wafer is included for
comparison. All processed wafers exhibit acceptable wafer bow. PE-TEOS and PE-Silane
oxide wafers have higher wafer bow than LTO oxide wafer. This is possibly because LTO
78
25
20-
----
500nm SiO/Si
---
LTO
PE-Silane
PE-TEOS
Siicon
,A-
oL_
C.)
-V---
15-
00
20
40
60
80
100
120
140
Wafer Length (mm)
Figure 4.3. Wafer bows for LTO, PE-TEOS, PE-Silane, and handle wafers prior to bonding.
Wafer bow of unprocessed bare silicon wafer is included for comparison.
oxide film was deposited on both top and bottom surfaces of S0I dummy wafers, and
wafer bow due to thin film stress are therefore minimized.
4.1.2.2 Pre-bondingDensification
Figure 4.4 shows IR images from the bonded wafer pairs before and after post-bonding
anneal. All S0I dummy wafers were coated with PE-Silane oxide. Densification was done
0
at 3500 C for 5 hours while post-bonding annealing was done at 300 C for 3 hours. Figures
4.4 (a) and 4.4 (b) are IR images for a wafer pair without pre-bonding densification before
and after post-bonding anneal. It is evident that voids form in this wafer pair after anneal.
Voids are formed possibly due to out-gassing of trapped molecules from undensified PE-
79
(a)(b
Undensified, post-anneal
Undensified, pre-anneal
(d)
(c)
Densified, post-anneal
Densified, pre-anneal
Figure 4.4. The effect of post-bonding annealing on bonding interface for: (a)-(b) wafer
pair without densification on PE-Silane oxide, and (c)-(d) wafer pair with densification
on PE-Silane oxide. (a) and (c) are IR images before annealing, and (b) and (d) are IR
images after annealing.
Silane oxide during post-bonding anneal. However, a wafer pair with densified PE-Silane
oxide bonds very well and no observable void is found from the IR images. The IR images
for this wafer pair before and after post-bonding anneal are shown in Figs. 4.4(c) and 4.4(d)
respectively. This suggests the importance of densification for reliable bonding when CVD
oxide is used for wafer bonding.
4.1.2.3 Chemical Mechanical Polishing
When two wafers are brought into contact at room temperature, hydrogen bonds between
hydroxyl (OH) groups are established across the gap between the wafers. The strength of
80
the hydrogen bonds will decrease sharply as the distance between the OH groups increases.
Since there is less intimate contact area when the wafer surface is rough, the number of
strong bonds will be limited and the bond strength will decrease. CMP can be used to
achieve the required surface roughness prior to wafer bonding, and its effectiveness is
evaluated in this section.
To achieve high quality bonding, the root-mean-square (RMS) roughness of the
wafer surfaces has to be kept below 1.0 nm [66]. Atomic force microscopy (AFM) is a
powerful tool to scan the surface profile and to measure the roughness of different
materials. We have performed AFM surface scans on various CVD oxide wafers in tapping
mode on a D3000 unit from Digital Instruments. Table 4.1 lists the root-mean-square
(RMS) roughness of CVD oxide wafers before and after densification and CMP. RMS
roughness of as-deposited LTO, PE-TEOS, and PE-Silane oxides on SOI dummy wafers
are 13.35, 8.53, and 9.63 nm respectively. These values are too high for reliable wafer
bonding. However, it is promising to notice that 3 min of CMP on densified CVD oxides
improves the RMS roughness values to 0.53, 0.48 and 0.51 nm respectively, below the
RMS roughness requirement of 1.0 nm for successful wafer bonding. On the other hand,
Table 4.1. Root-mean-square (RMS) roughness of various as-deposited oxides and
improvement achieved with CMP.
Surface
preparation
As deposited
LTO
Densified and CMP
As deposited
PE-TEOS
Densified and CMP
As deposited
PE-Silane
Densified and CMP
Oxide
81
RMS Roughness
(nm)
13.35
0.53
8.53
0.48
9.63
0.51
100.0
300
(a)
5.0
3,00
(b)
2.5
50.0
-2.00
2.00
i
0
1.00
1.00
I.0
VUu
z U.u
3.00
;0
-
Figure 4.5. AFM scans for (a) as-deposited LTO oxide, and (b) densified and polished
LTO oxide.
handle wafers with a layer of 5000
A thermal
oxide exhibit an RMS roughness of 0.27 nm,
and this value is acceptable for reliable bonding. Hence handle wafers do not require
additional surface polishing. For purpose of comparison, RMS surface roughness of a
cleaned bare silicon wafer is estimated to be about 0.14 nm.
Figure 4.5 compares the 3gm x 3pm surface profiles of the as-deposited LTO oxide
and LTO oxide that has undergone 5 hours of N2 anneal at 350'C and 3 min of CMP. Note
the obvious difference between the two wafers in terms of their surface profiles. The
uneven surface profile of the as-deposited oxide film will limit the amount of surface area
(b)00
(a)00
ii;
I0.0
1.00
1.00
1.00
2.00
1.00
3.00
2.00
0.00
Figure 4.6. AFM scans for (a) as-deposited PE-Silane oxide, and (b) densified and
polished PE-Silane oxide.
82
(a)
7
(b)
[9
Figure 4.7. AFM scans for (a) as-deposited PE-TEOS oxide, and (b) densified and polished
PE-TEOS oxide.
that can be in intimate contact with its pairing wafer, which in turn will degrade the quality
of the bond. The densified and polished wafer, on the other hand, is much more even and
will promote better wafer bonding. Figures 4.6 and 4.7 show the AFM surface profiles of
PE-Silane and PE-TEOS oxides respectively. Therefore, CMP is an effective tool to
achieve reasonable surface smoothness for CVD oxide wafer bonding.
Figure 4.8 shows the RMS roughness values of the PE-TEOS oxide as a function of
chemical-mechanical-polishing (CMP) duration. Note that CMP has improved the surface
roughness tremendously to a value below 1.0 nm after one minute of polishing, and the
roughness does not improve significantly beyond one minute. It is interesting to investigate
the effect of surface roughness on the final bond strength of the bonded wafer pairs. To do
this, we have used Maszara crack opening method to quantify the bond strength. In this
method, a razor blade of thickness 2y is inserted into the edge of the bonded wafer pair, and
the crack length L is measured from the infrared (IR) image. The bonding strength, given
by the average surface energy of the bonded pair y in J/m2, can be estimated from the
following relation [48]:
83
3Et3 y
2
81=
8eL
(1)
where E = 166 GPa, the modulus of elasticity for Si(100), 2y and L are the crack separation
and length, respectively, and t is the thickness of the wafer. Note that we have neglected the
presence of oxide due to its much smaller thickness compared to the wafer thickness. We
have performed the crack opening experiment at a temperature of 23 0 C and relative
humidity of 40%.
SOI dummy wafers coated with PE-TEOS oxides that have undergone CMP
durations as specified in Figure 4.8 were bonded to thermal oxide coated handle wafers.
The bonded pairs were annealed at 300 0C for 3 hours and were kept in the clean room for
24 hours prior to bond strength measurement. Figure 4.9 summarizes the bond strength as a
function of CMP duration. There is no significant bond strength difference for wafers
polished from 1 to 3 minutes. This is related to the fact that all PE-TEOS wafers polished
10-
8-
6-
C
Cr
0
4-
1 n
2-
1nm
0 1
I
I
0
1
2
3
CMP Duration (min)
Figure 4.8. RMS roughness of PE-TEOS oxide as a function of CMP duration. Note that
the roughness falls below 1.0 nm and does not change significantly beyond 1 minute.
84
for 1 minute or beyond exhibit similar RMS roughness. Without CMP, however, the wafer
failed to bond and separated immediately after the contact force was removed. Longer
duration of CMP can potentially result in increased wafer bow which are detrimental to
high quality bonding. Therefore, an optimum CMP duration is reached once the RMS
roughness is below 1.0 nm, because beyond that there is no gain in terms of bond strength
and it could potentially degrade the wafer surface quality for bonding.
4.1.2.4 Post-BondingAnneal
Since hydrogen bonds between the bonded wafer pair are relatively weak, a heat treatment
can be used to strengthen the bond. In this section, the effect of post-bonding anneal on the
bonding strength is studied. For the purpose of our application, we have limited the anneal
1
n
0.9-
_E
0)
-----------------
0.8-
0.7-
.C
0
C:
0.6
-
U.
-I------
0.0
0.5
1.0
2.0
1.5
2.5
3.0
3.5
CMP Duration (min)
Figure 4.9. Bond strength as a function of CMP duration.
85
1000-
3000C
N
A
A
800-
E
A/
600 -
E
250-C
400 -
CO
200*C
200
400
0
0
0
2
6
4
8
10
Post-bond annealing time (h)
Figure 4.10. The variation of bonding strength of PE-TEOS oxide bonded to thermal
oxide as a function of annealing duration at different annealing temperatures.
temperature to 300
C. This temperature is lower than the pre-bonding densification
temperature, i.e. 350 *C, to prevent any possibility of out-gassing of residual molecules.
Figure 4.10 shows the variation of bonding strength of PE-TEOS oxide bonded to
thermal oxide as a function of annealing duration at different annealing temperatures. The
bonding strength does not increase tremendously and saturates beyond 2 hours of annealing
at a given temperature. The bonding strength achieved with 10 hours of post-bond
annealing at 200, 250 and 3OT are 250, 500, and 850 mJ/m2 respectively. As expected,
higher bonding strength is obtained at higher annealing temperature. At higher temperature,
the OH groups gain more surface mobility and more hydrogen bonds develop across the
gap. The reaction of surface silanol (Si-OH) groups is also enhanced as follows,
Si-OH + OH-Si
->
(2)
Si-O-Si + H20
86
The water molecules gain more surface mobility and diffuse out of the bonding interface.
As a result, strong siloxane (Si-O-Si) bonds are formed. The Maszara crack opening
method is very sensitive to ambient relative humidity, temperature and experimental error.
An error of ± 23-86 mJ/m2 is estimated in all bonding strength values plotted in Figures
4.10 and 4.11.
4.1.2.5 Choice of CVD Oxides
Figure 4.11 shows the bonding strength of different CVD oxides to thermal oxide as a
0
function of post-bonding anneal duration at 300 C. Note that all oxides show increased
bonding strength after annealing and the bonding strength does not increase significantly
beyond 2 hours of heat treatment. Both LTO and PE-TEOS oxide exhibit comparable bond
strength
(~
850 mJ/m 2) beyond 2 hours of heat treatment. This value is stronger than that
1000800-
600
D)
C
400-
C
LTO
0--
PE-Silane
--
PE-TEOS
A
0
i
0
I'I
2
I
*I
4
6
*
8
1
I
10
Post-bond annealing time (h)
Figure 4.11. Bonding strength of different CVD oxides bonded to thermal oxide as a
0
function of post-bond annealing duration at 300 C.
87
achieved by PE-Silane oxide (- 600 mJ/m 2 ). The reason for this discrepancy is unclear, but
it could be due to the quality of the PE-Silane oxide film such as porosity and moisture
resistance.
4.1.2.6 Activation Methods
In Figure 4.12, bond strengths of bonded wafer pairs treated with different chemical cleans
prior to bonding are compared. PE-TEOS oxide was chosen for this comparison. The
bonded pairs were annealed at 300 0C for 3 hours after room temperature bonding. All
wafer pairs were stored in the clean room for 24 hours after annealing before bond strength
measurement. It is observed that wafer pairs treated with RCA-1 are stronger than those
treated with piranha. This is because an RCA-1 treated surface has a smaller contact angle
1100
T
1000-
900
1
800.
0)
C
700-
Piranha
RCA
NH4OH
Activation method
Figure 4.12. Bond strength of bonded wafer pairs treated with different chemical cleans and
annealed at 300 0C for 3 hours.
88
than that treated with piranha [49]. Smaller contact angle corresponds to higher
hydrophilicity of a surface, hence higher density of hydroxyl (OH) groups for hydrogen
bond formation during bonding. During chemical clean, oxide surfaces treated with piranha
or RCA-1 are terminated with OH groups. When two wafers are brought into contact at
room temperature, hydrogen bonds between OH groups are established across the gap
between the wafers. The bonding strength will increase if the number of OH groups
available to establish hydrogen bonds increases. Since the RCA-1 treated oxide surface has
more bonding sites, one would expect that the final bond strength is higher in a wafer pair
treated with RCA-1 than that treated with piranha.
During annealing, the reaction of surface silanol (Si-OH) groups according to
reaction (2) is enhanced. Water molecules from the reaction gain surface mobility and
diffuse out of the bonding interface. As a result, strong siloxane (Si-O-Si) bonds are
formed. Since reaction (2) is reversible, water molecules can rupture the siloxane bonds if
they remain at the bonding interface. Therefore, the important mechanism for high bond
strength is the complete removal of water molecules from the bonding interface leaving
behind strong siloxane bonds. This explains the need of post-bonding anneal. When wafers
are treated with ammonia hydroxide, however, bonding surfaces are terminated by amine
(NH 2) and hydroxyl (OH) groups. Upon annealing, the following reaction takes place:
(3)
Si-NH 2 + Si-OH -> Si-O-Si + NH 3
In the above reaction, ammonia (NH 3 ) is the reaction product instead of water as in the
usual bonding mechanisms for hydrophilized wafers, such as those treated with piranha or
89
--
2500
~ Oxygen Plasma
No Oxygen Plasma
-2000
E
1500-
)1000
0
500-
0
50
100
150
200
250
300
Anneal Temperature CC)
Figure 4.13. Bond strength of bonded wafer pairs annealed at different temperatures.
RCA-1. Unlike water, ammonia (NH 3) in reaction (3) has less possibility to rupture the
already formed siloxana bonds [50]. Thus, NH40H treated wafers should have a stronger
bond than RCA-I or piranha treated wafers.
Figure 4.13 compares the bond strength of bonded wafer pairs annealed at different
temperatures. PE-TEOS oxide wafers were used and all wafers were cleaned with piranha.
In addition to wet chemical clean, one group of wafers was exposed to oxygen plasma at
200 W for 20 s before piranha clean. As predicted, bond strength increases as anneal
temperature increases. Similar findings were reported previously [29], [51]. The oxygen
plasma exposure enhances the bond strength significantly. For example, with oxygen
2
2
plasma activation, bond strength is increased from 819 mJ/m to 2314 mJ/m when post-
bonding anneal is performed at 300 C for 3 hours. The increase of bond strength in wafers
treated with oxygen plasma has been widely studied; bond strength improvement results
from increased water removal from the bonding interface, allowing strong covalent bonds
90
Table 4.2. RMS roughness of oxide wafers with and without oxygen plasma exposure.
Wafer
RMS Roughness (nm)
As prepared Oxygen plasma
exposure
0.20
0.23
Si02/ Si
PE-TEOS / poly-Si /
0.36
0.32
SiO 2 / Si
I
to be formed [52], [53]. It has been speculated that oxygen plasma exposure can create a
thin layer (a few nanometers) of porous structure on the wafer surface. As a result, water
molecules from reaction (2) can diffuse from the bonding interface and are trapped in the
porous layer, leaving behind strong siloxane covalent bonds. This mechanism happens even
at room temperature if bonded wafers are stored sufficiently long.
We have also performed atomic force microscopy (AFM) surface scans on oxide
wafers in the tapping mode on a D3000 unit from Digital Instruments. Table 4.2 lists the
root-mean-square (RMS) roughness of all wafers with and without oxygen plasma
exposure. Note that oxygen plasma exposure has a smoothing effect on the oxide wafers.
The surface roughness of the carrier wafer (i.e., SiO 2 ) is improved from 0.23 nm to 0.20
nm, while the surface roughness of the donor wafer (i.e., PE-TEOS) is improved from 0.36
nm to 0.32 nm. Improved surface roughness increases the intimacy of pairing wafers when
they are brought in contact. The strength of the hydrogen bonds will increase sharply as the
distance between the OH groups decreases and hence the number of strong initial bonds
also increases.
91
4.2 Thin Film Handling and Reliability
After the donor SOI wafer is successfully bonded to the handle wafer, the donor wafer
needs to be thinned back to the BOX layer as shown in Figure 4.14, to obtain a thin silicon
layer. The substrate of the donor wafer can be thinned back using a combination of
mechanical grinding and tetraethyl-ammonium hydroxide (TMAH) selective strip. Since
mechanical grinding has no selectivity between silicon and oxide, grind-back is stopped at
about 75 gm away from the BOX layer. This remaining 75 gm thick of silicon layer can be
stripped easily using 12.5 wt % of TMAH solution at 85 C for about 100 min. Since
TMAH has excellent (more than three orders of magnitude) selectivity towards oxide at
these etching conditions, the etching stops on the BOX layer.
In order to be useful in actual process, wafer pairs bonded using CVD and thermal
oxides described above have to withstand mechanical force and chemical corrosion during
subsequent steps. The most abusive steps are during etch-back that consists of mechanical
grinding and TMAH etch. Therefore, it is essential to identify the requirements of bond
Si handle wafer
PETEOS (1 pm)
SOl (400 nm)
BOX (500 nm)
Si substrate
I t ftt
Si substrate mechanical grinding
and TMAH selective strip.
Figure 4.14. Schematic shows the etch-back of the SOI wafer after bonding to a handle
wafer. The etch-back stops on the BOX layer.
92
strength for the bonded pairs to sustain etch-back. In this section, we will study the bond
strength requirement to sustain these thinning steps. All wafer pairs tested in Figure 4.13
were subjected to mechanical grinding and TMAH etch. Table 4.3 is a summary of the
endurance of bonded pairs during mechanical grinding and TMAH etch.
4.2.1 Mechanical Grinding
As shown in Table III, all bonded pairs treated with oxygen plasma in addition to piranha
clean prior to bonding maintain their bonding interface integrity after mechanical grinding,
regardless of post-bonding anneal temperatures. However, wafers treated with piranha
alone require annealing at 200 0C for 3 hours to withstand the grinding without the creation
of new interfacial voids. In Figure 4.15, infrared (IR) transmission images of piranha
treated and bonded wafer pairs before and after grinding are compared. These wafer pairs
are annealed at 100 C and 200 0C, respectively, for 3 hours. As shown in Figures 4.15 (a)
and (b), mechanical grinding creates additional interfacial voids at the bonding interface
when the bonded pair is annealed at 100 0C. The voids are created because the bond
Table 4.3. Summary of various bonded pairs endurance to mechanical grinding and TMAH
etch.
Grinding
TMAH
Voids
Voids
Successful
Delamination
Delamination
Delamination
300 OC / 3h
No
Successful
Successful
Delamination
Successful
Yes
100
0C
/ 3h
Successful
Successful
Yes
Yes
200
300
0C
/ 3h
0C / 3h
Successful
Successful
Successful
Successful
Bonding Procedures
Post-bonding
Oxygen
anneal
Plasma
No
No
100 C / 3h
No
No
200 C / 3h
No
Yes
93
(b)f
100*C/3h anneal: post-grinding
100*C/3h anneal: pre-grinding
(d)
(c)
200*C/3h anneal: post-grinding
200*C/3h anneal: pre-grinding
Figure 4.15. Infrared (IR) transmission images of piranha treated and bonded wafer pairs
before and after grinding. Bonded pairs were annealed for 3 hours at: (a)-(b) 100 'C and
(c)-(d) 200 0C respectively. (a) and (c) are images before grinding and (b) and (d) are
images after grinding.
strength is not sufficient to withstand applied shear force during grinding. However, no
additional void is created when the bonded pair is annealed at 200 'C as evidenced from
Figures 4.15(c) and (d). All wafers treated with oxygen plasma exposure survive the
mechanical grinding with no additional interfacial voids. Therefore, a bonding strength
0
to be
higher than 338 mJ/m2 (from 100 C/3 h anneal) is required for mechanical grinding
reliable.
4.2.2
TMAH Etch
All bonded pairs are further subjected to 12.5 wt % TMAH etch at 85 'C for 100 minutes.
Complete film delamination at the bonding interface is observed when pairing wafers are
94
Figure 4.16. Cross-sectional SEM micrograph showing thin films (from donor wafer) are
bonded to a handle wafer after SOI donor wafer etch-back. The wafers were treated with
oxygen plasma and no post-bonding anneal was done.
not treated with oxygen plasma. However, all wafers that are exposed to oxygen plasma
survive the TMAH etch. The cross-sectional SEM image in Figure 4.16 shows that the thin
film stack (i.e., BOX/poly-Si/PE-TEOS from donor wafer) is bonded to the oxide handle
wafer after TMAH etch. This bonded pair was not annealed after bonding at room
temperature. The SEM image shows good structural integrity of the thin film stack with no
interfacial voids. This is very encouraging as the required bond strength to sustain etchback can be achieved without post-bonding anneal. Hence, thermal budget and thin film
stresses due to thermal mismatch are greatly reduced in this case. Therefore, it can be
2
concluded that bonded pairs require a bond strength higher than 819 mJ/m (from 300*C/3h
anneal without oxygen plasma activation) to sustain both mechanical grinding and TMAH
etch.
95
Figure 4.17. Cross-sectional TEM micrograph showing that thin films (from donor wafer)
are bonded seamlessly to a handle wafer after SOI donor wafer etch-back.
4.2.3 Interfacial Properties
In this section, the bonding interface of CVD oxide to thermal oxide is examined with high
resolution transmission electron microscopy (HR-TEM) and energy dispersive X-ray
(EDX) analysis. The chosen sample is from bonded wafer pairs composed of PE-TEOS and
thermal oxides. These wafers are exposed to oxygen plasma, cleaned, bonded, and
annealed at 300 'C for 3 hours. The SOI donor wafer is then thinned back to the BOX
layer. While thin films are bonded to the handle wafer after etch back, it is also necessary
to examine the bonding interface thoroughly for possibility of micro-voids and
96
Figure 4.18. High resolution TEM micrograph showing the bonding interface of PE-TEOS
and thermal oxides. The bonding interface is smooth with no interfacial voids. A
transitional area at the bonding interface approximately 2.2 nm thick is observed.
contaminants. The TEM image in Figures 4.17 shows that the thin films stack from SOI
donor wafer are attached to the handle wafer after etch back. A close-up view of the
bonding interface is shown in Figure 4.18. The bonding interface appears to be smooth and
no micro-void is observed. A transitional region (lighter tone) of about 2.2 nm thick is also
observed. This region consists of mostly Si-O-Si bonds that bridge the oxide surfaces
together.
Unintentional surface contamination is examined using energy dispersive X-ray
(EDX) analysis. Three regions are analyzed and the results are shown in Figure 4.19. No
foreign contaminant is observed in the bulk regions of PE-TEOS and thermal oxides, as
97
(a)
150(
0100(
I_
)
0
500
0
2
4
6
10
8
Energy (keV)
(b)
1500
'10000
0
500
Energy (keV)
(C)
1500
01000
0
0
LI
Energy (ke)
8
Figure 4.19. EDX profiles of various regions close to the PE-TEOS and thermal oxides
bonding interface: (a) PE-TEOS, (b) bonding interface, and (c) thermal oxid e.
shown in the EDX profiles from these areas in Figure 4.19 (a) and (c). The electron beam is
focused on areas circled (solid line) in the TEM images to the left. Traces of silicon (Si)
and oxygen (0) that formed the oxides are detected. Copper (Cu) trace levels are also
detected, and are attributed to the sample support grid. At the bonding interface, however,
trace levels of fluorine (F) are also observed, apart from Si, 0, and Cu. F is most likely
incorporated on the oxides surface from F residuals in the chamber used for oxygen plasma
activation. F containing agents such as halocarbon-13 (CF 4) and halocarbon-23 (CHF 3 ) are
used in the same chamber for other applications. A chamber clean prior to oxygen plasma
exposure is necessary to get rid of the F.
98
As shown in the TEM image in Figure 4.19(c), the bonding interface is damaged
after being bombarded with the high energy (- 200 keV) electron beam during EDX
analysis. However, bulk PE-TEOS and thermal oxides survive the electron beam. This
suggests that the transitional area at the bonding interface is weaker than the bulk materials.
However, it is sufficiently strong for the purpose of holding thin films during layer transfer.
4.3 Summary
In this Chapter, low temperature bonding of CVD oxide to thermal oxide is discussed. It is
demonstrated that CVD oxide wafer, with proper surface preparations including
densifiction and CMP, can be bonded to thermal oxide wafer. A short exposure to oxygen
plasma prior to bonding increases the bond strength significantly in the bonded wafer pair.
Oxygen plasma treated wafer pair can bond at room temperature and withstand subsequent
mechanical grinding and TMAH etch without post-bonding anneal.
99
100
Chapter 5
Face-to-Face Silicon Layer Stacking
In this chapter, silicon layer stacking in a face-to-face fashion is demonstrated. Stacking
is accomplished by means of direct Cu-to-Cu thermo-compression bonding and silicon
substrate thinning. The advantages of this orientation include the absence of an extra
handle wafer, thus a much simpler and straight forward process. A silicon bi-layer stack
is successfully fabricated and a progression to a quadruple-layer stack is shown. This
opens up the opportunity for vertical integration of ultra-thin silicon device layers.
5.1 Face-to-Face Silicon Bi-layer Stack
One approach to stack thin silicon device layers is by wafer bonding and etch-back. Thin
layers can be arranged either in a face-to-face or back-to-face fashion. In this section, a
face-to-face silicon layer stacking approach that is enabled by low temperature copper
thermo-compression bonding is described. This stacking method is the most direct way to
stack thin layers. We will discuss back-to-face stacking in Chapter 6. In the face-to-face
stacking method developed in this chapter, a silicon-on-insulator (S0I) donor wafer is
bonded to a substrate wafer in a face-to-face manner using Cu as the bonding medium
and is etched back to the buried oxide (BOX) layer. A silicon bi-layer stack, with SOI
layers that are as thin as 400 nm, is demonstrated.
101
(a)
(b)
Donor wafer
-
Donor wafer
SO (400 nmn
Ta (50 nm,-
SO
Ta (5C nrm
Ta (5C nm:
Ta (50 nm,
(400 nm
.
SO (400 nm,
SO (400 nm,
Si substrate
Si substrate
Cu-tc-Cu thermocompression bonding
Top Si substrate mechanical grinding
and TMAH selective etci
Figure 5.1. Face-to-face silicon layer transfer and stacking based on Cu thermocompression and wafer etch-back.
5.1.1 Wafer Preparation
The process flow to fabricate a silicon bi-layer stack in a face-to-face arrangement is
shown in Figure 5.1. The experiment was performed on blanket silicon wafers. All wafers
used in this experiment were n-type 150 mm Si(100) wafers. SOI wafers are an attractive
choice because the BOX layer serves as an excellent etch stop layer during substrate
thinning in silicon etchants such as tetraethyl-ammonium hydroxide (TMAH) as
previously shown in earlier chapters. Since manufacturing grade SOI wafers are
prohibitively expensive, SOI dummy wafers were prepared and used as both donor and
substrate wafers in our experiment. SOI dummy structures were prepared by growing
5000A of thermal oxide as a buried oxide (BOX) on silicon wafers, followed by the
deposition of 4000
A of undoped poly-silicon
at 620'C. Since the donor wafers already
have devices and interconnect fabricated on them in an actual process, process
102
temperatures in all subsequent steps were kept at 400 C or below to be compatible with
back-end-of-line (BEOL) processes.
5.1.2 Cu-to-Cu Bonding
All donor and substrate wafers were cleaned in piranha (H2 0 2 : H2 SO 4 = 1:3, by volume)
followed by metal deposition. Fifty nm of Ta and 300 nm of Cu were deposited on the
donor and the substrate wafers in an e-beam system. Ta was used as a diffusion barrier to
prevent Cu diffusion into the device layer which might degrade the electrical integrity of
the device layer in an actual process. The donor wafer was then aligned to the substrate
wafer in an EV Group aligner and the pair was clamped on a bonding chuck. Wafers
were separated by three metal flaps each about 30 pm thick at the edge. Aligned wafers
were transferred to an EV Group bonding chamber. After three cycles of N2 purge and
pump down, the metals flaps were pulled out and thermo-compression bonding was
performed at 400 0C under a contact force of 4 kN for 1 hr in vacuum. This is
schematically shown in Figure 5.1 (a). The bonded pair was then annealed in atmospheric
N2 ambient at 400 0C for 1 hr to allow Cu inter-diffusion and grain growth to achieve
higher bonding strength.
5.1.3 SOI Donor Wafer Etch Back
The next step in the flow is donor wafer thin-back as schematically shown in Figure 5.1
(b). Two methods will be described in the following.
103
5.1.3.1 Grinding and TMAH
The substrate of the bonded donor wafer can be thinned back using a combination of
mechanical grinding and TMAH strip. This is a destructive method since the substrate of
the donor wafer will be completely ground and etched away. Mechanical grinding was
outsourced to a vendor. This is a two-step grinding process. There is a coarse grind where
most of the removal is done, followed by a fine grind that removes the last 15-20 microns
and removes any damage. When the grinding is finished using a 2000 grit type grind
wheel, the finished wafer surface exhibits a roughness of 0.13 ptm. In addition, DI water
is used for process cooling and cleaning; no chemicals or slurries are used during
grinding. Since mechanical grinding has no selectivity between silicon and oxide, the
grind-back was stopped at about 75 tm away from the BOX layer. This remaining 75 pim
thick silicon layer was stripped easily using 12.5 wt % TMAH solution at 85 C for about
100 min. Since TMAH has excellent (more than three orders of magnitude) selectivity
towards oxide, the etching stopped on the BOX layer.
Figure 5.2 is a cross-sectional SEM image showing the final silicon bi-layer stack
after donor wafer substrate removal. Note that all thin film layers are held together
reliably by the bonded Cu layer. This SEM micrograph therefore confirms the layer
stacking method described above. The resulting wiggling interface between the poly-Si
layers and the Ta layers was due to the surface roughness of the unpolished poly-Si
layers.
Figure 5.3 shows the close-up view of grain microstructure in the bonded Cu
layer. Substantial inter-diffusion and grain growth in the bonded Cu layer can be
observed in the close-up SEM image, as evidenced by Cu grains that extend beyond the
104
Figure 5.2. SEM shows a silicon bi-layer stack obtained after donor wafer thin-back.
original bonding interface. The original Cu layers have merged and a homogeneous
bonded Cu layer is obtained. Grain boundaries of the Cu grains are marked with arrows.
In a production process, devices in the SOI layer are interconnected by metal
wires and interconnects are embedded in the interlayer dielectric (ILD). To make the
Figure 5.3. Cu grain structure in the bonded layer. Note that the original Cu layers have
merged and a homogeneous layer is obtained.
105
MORIMP.
-IM-1013MV.
Figure 5.4. SEM image shows a silicon bi-layer stack with the insertion of low
temperature oxide (LTO) between the SOI and the Cu layers.
above stacking process as close to a real process as possible, the donor and the substrate
wafers were coated with 0.5 pm of low temperature oxide (LTO) from a silane source at
400 0C. LTO oxide is an attractive choice for interlayer dielectric (ILD) and passivation
layers because of its high deposition rate and low process temperature. We repeated the
stacking process described in Figure 5.1. Figure 5.4 is the SEM image of the silicon bilayer stack with the insertion of LTO layers between the SOI and Cu layers. All layers
are held together with good integrity by the bonded Cu layer. Microstructure of Cu grains
in the bonded Cu layer is shown in the close-up view in Figure 5.5.
In the above process, SOI dummy structures are used as both donor and substrate
wafers. Note that the substrate wafer can be either an SOI wafer or a bulk Si wafer for
this layer stacking experiment. The selection of substrate wafer depends on specific
application need.
106
MPMMMMMPM===
----
-
--
-
Figure 5.5. Cu grain structure in the bonded layer. Note that the original Cu layers have
merged and a homogeneous layer is obtained.
In wafer level silicon layer stacking, bonding uniformity across the wafer is
essential to obtain high yield of the final transferred films. It is therefore important to
Figure 5.6. Image of transferred thin films on the substrate wafer after donor wafer etchback. Delamination is observed at the edge of the wafer.
107
MINEWWROF=
Q '
1
&
.
11.......
evaluate the uniformity of the transferred thin films on the substrate wafer. Shown in
Figure 5.6 is an image of transferred thin films on the substrate wafer after donor wafer
etch-back. Except at the wafer edge, complete thin film transfer is obtained across the
whole wafer. Thin films delaminate at the wafer edge due to wafer thickness nonuniformity and possibly the presence of particles due to wafer handling.
5.1.3.2 Hydrogen Induced Wafers Splitting
To minimize potential process damage to the bonded Cu layer arising from mechanical
grinding, hydrogen induced wafer splitting [54] can be used to release the substrate of the
donor wafer. H2' ions at a dose of 5 x 1016 cm- 2 were implanted at an energy of 150 keV
into the donor wafer prior to wafer bonding. To estimate the hydrogen ion penetration
depth, the Transport of Ions in Matter (TRIM) program is used [55]. Since TRIM does
not allow molecular ions as the doping species, hydrogen ions (Hi) were used at energy
ION RANGES
Ion Range
=
7025 A
6XO4
5X10 4
-
4x10
-3x10
3r10
0A
4
0I
I
a.
L-
4
aL___.
(A
(A_1_
.- J
- Target Depth -
0~o
1.9 Um
Figure 5.7. Simulated hydrogen profile using TRIM program.
108
Figure 5.8. FIB image shows a silicon bi-layer stack. The substrate of top donor wafer
was separated using hydrogen induced wafer splitting.
of 150 keV. A total of 10,000 ions were simulated. The simulated hydrogen profile is
shown in Figure 5.7. A penetration depth of 7025
A is estimated.
Upon heating at the appropriate temperature after Cu thermo-compression
bonding of donor wafer to substrate wafer, lateral microcracks induced by hydrogen will
release the substrate of the donor wafer at the peak of hydrogen implant. Since this
process is temperature dependent, all heat treatments prior to layer splitting ware kept at
0
300 *C or below. Therefore, Cu wafer bonding was done at 300 C instead of 400 C to
prevent premature wafer de-bonding. All other bonding parameters were unchanged.
After donor wafer was bonded to the substrate wafer, a final annealing step was
performed at 400 C for 1 hr to initiate wafer splitting and to further enhance Cu layer
109
Figure 5.9. Cu grain structures in the bonded layer. Note that the original Cu layers have
merged and a homogeneous layer is obtained.
bonding strength. Fig. 5.8 is the focus ion beam (FIB) image of the silicon bi-layer stack
after wafer separation. Note that the oxide surface contains surface blisters as a result of
microcracks created by hydrogen ion cut. The two wafers separated close to the interface
of the BOX layer and silicon substrate of the donor wafer. A homogeneous Cu layer with
grains that extend from one end to the other end can be observed in the close-up view of
the bonded Cu layer in Figure 5.9. This suggests that significant grain growth has taken
place even though the thermal budget was reduced to provide a temperature window for
Cu wafer bonding and hydrogen induced layer splitting.
110
5.2 Silicon Multi-Layer Stack
5.2.1 Process Flow
In applications such as system-on-a-chip (SoC) or high density memory where a higher
level of integration and device density is required, a silicon multi-layer stack is of great
promise. It is possible to expand the silicon layer stacking developed above beyond a bilayer stack. In this section, we will demonstrate a quadruple-layer stack by stacking two
bi-layer stacks as obtained in Figure 5.2. Except for the starting wafers, all process steps
remained the same. Fifty nm of Ta and 300 nm of Cu were deposited on two bi-layer
stacks as shown in Figure 5.10 in an e-beam system. The two wafers each composed of a
silicon bi-layer stack were aligned and transferred to the bonding chamber. Thermocompression bonding was done at 400 C under the contact force of 4 kN for 1 hr in
0
vacuum. The bonded pair was then annealed in atmospheric N2 ambient at 400 C for 1 hr
to allow inter-diffusion and grain growth in the Cu layer for higher bonding strength. The
Cu-Cu thermocompression bonding
-
I_
Ta - 50 nm
Ta - 50 nm
Ta -50 nm
Ta - 50 nm
Ta - 50 nm
Ta - 50 nm
SOI - 400 nm
SOI - 400 nm
Si substrate
Si substrate
Figure 5.10. Schematic shows a possible way to fabricate a silicon quadruple-layer stack
by stacking two silicon bi-layer stacks.
111
Figure 5.11. FIB image shows a silicon quadruple-layer stack achieved by stacking two
silicon bi-layer stacks in Figure 2. This paves a promising path to multi-layer and multifunctionality silicon stacks.
top silicon substrate was subsequently thinned back using a combination of mechanical
grinding and TMAH strip as before.
5.2.2 Demonstration of Quadruple-layer Stack
Figure 5.11 is an FIB image of a silicon quadruple-layer stack obtained by stacking two
bi-layer stacks together. It clearly shows that all layers are bonded and stacked
accordingly. All three bonded Cu layers show stable grain structure after substantial Cu
inter-diffusion and grain growth as evidenced from Cu grains that extend from one end to
112
the other in the homogeneous layers. The same steps can be repeated to build a silicon
multi-layer stack.
5.3 Summary
A face-to-face ultra-thin silicon layer stacking method based on low temperature Cu
wafer bonding and etch-back is described in this Chapter. A silicon quadruple-layer stack
can be fabricated by stacking two silicon bi-layer stacks together hence paving the path to
a true multi-layer silicon stack.
113
114
Chapter 6
Back-to-Face Silicon Layers Stacking
In Chapter 5, face-to-face arrangement of thin silicon layers is described. Silicon layers
can also be stacked in a back-to-face fashion. In back-to-face silicon layer stacking, a
donor wafer is bonded to a temporary handle wafer for mechanical support and etched
back to the required thickness. Stacking is completed by bonding the thinned silicon
device layer (that is attached to the handle wafer) to a substrate wafer in a back-to-face
manner and followed by handle wafer release. In this chapter, we describe a back-to-face
silicon layer stacking method using a combination of low temperature oxide wafer
bonding (as a temporary bond between the donor wafer and the handle wafer) and Cu
wafer bonding (as a permanent bond between the thinned silicon layer and the substrate
wafer). The process flow is summarized in Figure 6.1.
6.1 Silicon Bi-layer Stack
6.1.1
Wafer Preparation
The experiment was performed on blanket silicon wafers. All wafers used in this
experiment were n-type 150 mm Si-(100) wafers. Two sets of wafers were prepared: one
group was the handle wafers and the other was the SOI dummy wafers (as donor and
substrate wafers). The handle wafers were covered with 5000 A of thermal oxide for
protection against chemical attack during donor wafer etch-back. Wet silicon etchants
such as tetra-ethyl-ammonium-hydroxide
(TMAH) are known to have excellent
115
(b)
(a)
Si handle wafer
Si handle wafer
CVD oxide (1 pry)
SO (40C
CVD oxide(' prr)
nrT)
BOX (50C mT)
SO (40C nrr)
BOX (500 nm)
Donor wafer
Donor wafer
t t t t
Mechanical grinding and TMAHselective strip of donor wafer
substrate
Top wafer is bonded to handle wafer (CV to-thermal oxides bonding).
(d)
(c)
Si handle wafer
SihIand/ar
h no/
Wfer
CVD oxide (1 pm)
SOI (400 nm)
CVD oxide (1 pm)
BOX (500 nn)
nrn)(5
Ta
SO (40C nm)
Ta (5C nm)
Ta (50 nm)
Ta (50 nm)
- . -. - . . .
. .
-
-
-
---
Ta (SC nm)
.
-----
SOI (400 nm)
BOX (500 nmn)
BOX (50C Im)
SO (40C nmn)
BOX
(50C nm)
Substrate wafer
Substrate wafer
Cu-to-Cu thermocompression bonding.
Handle wafer release
Figure 6.1. Schematics of back-to-face silicon layer transfer and stacking for threedimensional integration.
selectivity towards thermal oxide. SOI dummy structures were prepared by growing
5000A of thermal oxide as a buried oxide (BOX) on silicon wafers, followed by the
deposition of 4000
A of undoped poly-silicon
at 620 0C. Since the donor and substrate
wafers already have devices and interconnects fabricated on them in an actual process, all
subsequent process temperatures were limited to 400 C and below, as in the approaches
described in previous chapters. The donor wafers were coated with 1 gm of tetraethylorthosilicate (TEOS) source plasma enhanced chemical vapor deposition (PECVD) oxide
116
at 350 C. PE-TEOS oxide is an attractive choice for interlayer dielectric (ILD) and
passivation layers because of its high deposition rate and low process temperature.
6.1.2 Oxide Wafer Bonding
To begin the silicon layer transfer and stacking process, the donor wafers were bonded to
the handle wafers for mechanical support and ease of wafer handling. While epoxy [38]
or adhesive material [39] can be used for this type of bonding, we have avoided process
complexity which could arise from the use of new materials, and focused on direct oxide
to oxide wafer bonding which is more CMOS friendly. While the protective thermal
oxide on the handle wafers possesses suitable properties for wafer bonding, PE-TEOS
oxide on the SOI dummy wafers prepared at low temperature requires additional surface
preparation before wafer bonding can be initiated. PE-TEOS oxide on SOI dummy
wafers was densified in atmospheric N2 ambient at 350 0C for 5 hours to drive away all
trapped gas molecules. This step allowed degassing from the porous SiO 2 , which was
detrimental to the bonding, to take place prior to bonding. Surface smoothness is a critical
factor that determines successful wafer bonding. It is well known that PE-TEOS oxide
has a rough surface. To reduce the surface roughness, the wafers were chemicalmechanically polished (CMP) for 3 min after densification. The surface roughness
improved from 8.53 nm to 0.48 nm. All handle wafers and donor wafers were activated
by oxygen plasma followed by a 10 min piranha (H 2 0 2 :H2 SO 4
=
1:3) clean. This cleaning
was necessary to terminate the wafer surfaces with hydroxyl (OH) groups to initiate
hydrogen bonds during wafer bonding. Activated handle wafers were aligned to donor
wafers in an EV Group aligner and the pairs were bonded as schematically shown in
117
Figure 6.1(a). Bonding was performed at room temperature under a contact force of 1 kN
for 2 min. After bonding, the bonded wafer pairs were annealed at 300 0C in atmospheric
N2 ambient for 3 hours to enhance the bonding strength. The bonding strength is
estimated to be about 1400 mJ/m2 using Maszara crack opening method.
6.1.3 Donor Wafer Etch Back
The next step in the flow was donor wafer thin-back as described in Figure 6.1(b). The
substrate of the bonded donor wafer can be thinned back using a combination of
mechanical grinding and TMAH strip. Since mechanical grinding has no selectivity
between silicon and oxide, the grind back was stopped at about 75 tm away from the
BOX layer. The remaining 75 pm thick silicon layer can be stripped easily using 12.5 wt
% TMAH at 85 0C for about 100 min. Since TMAH has excellent selectivity towards
oxide, the etching stops on the BOX layer. Therefore SOI wafers are an attractive choice
in this type of silicon layer stacking as the BOX layer serves as an excellent etch stop
layer. Figure 6.2 shows an SEM image of thin films attached to the handle wafer after
etch back.
6.1.4
Cu Wafer Bonding
The thinned silicon layer on the handle wafer was then bonded to a substrate wafer using
Cu as the bonding medium as shown in Figure 6.1 (c). Fifty nm of Ta and 300 nm of Cu
were deposited on the thinned layer and the substrate wafer in an e-beam system. Ta
acted as a diffusion barrier. Thermo-compression bonding was done at 400 C under a
contact force of 4 kN for 1 hr in vacuum. The bonded pair was then annealed in
118
Figure 6.2. SEM image of thin films attached to the handle wafer after etch back.
atmospheric N2 ambient at 400 *C for 1 hr to promote Cu inter-diffusion and grain
growth for higher bonding strength.
6.1.5 Handle Wafer Release
Figure 6.1 (d) shows the final step in the flow, i.e., the handle wafer release. This can be
done in the following two ways: grinding and TMAH, and hydrogen induced wafer
splitting.
6.1.5.1 Grinding and TMAH
The most direct way to remove the handle wafer is by mechanical grinding and TMAH
strip. The handle wafer was ground to about 75 ptm from the bonding interface. The
remaining 75 jim of silicon layer was stripped in 12.5 wt % TMAH solution that stopped
119
5X
Figure 6.3. SEM shows back-to-face silicon layers stack obtained after handle wafer
grinding and TMAH strip.
on the protective oxide layer. Figure 6.3 is a cross-sectional SEM image showing all final
layers on the stack. The close-up views of the bonding interfaces are also shown. This
SEM image confirms the layer stacking described above. The resulting wiggling interface
between the bottom poly-Si and the Ta layer was due to the surface roughness of the
unpolished poly-Si layer. No interfacial void is observed at the bonding interface between
the PE-TEOS and thermal oxides. Substantial inter-diffusion and grain growth in the Cu
can be observed in the close-up SEM image at the bottom right. Note that the original Cu
bonding interface has disappeared and a homogeneous bonded Cu layer is obtained.
6.1.5.2 Hydrogen Induced Wafer Splitting
To minimize process damage to the Cu bonding interface as a result of mechanical
grinding, hydrogen induced wafer splitting can be used to release the handle wafer. H2 '
120
1022
H 2'
Oxygen
5e16cm at 150 keV
101
0
C)
Cn
10,1-CD
-
E
0
CD
102g
C
Hydrogen
10
0
C
10
Si handle wafer
SO2
0.0
I
I
I
0.2
0.4
0.6
I
I
0.8
1.0
100
1
1.2
Depth (jim)
Figure 6.4. SIMS profile of implanted hydrogen into the handle wafer. The hydrogen
peak is situated about 300 nm from the oxide-silicon interface into the silicon handle
wafer.
ions at a dose of 5 x 1016 cm-2 were implanted at an energy of 150 keV into the handle
wafer prior to wafer bonding. Upon heating at the appropriate temperature, lateral micro-
ION RANGES
Ion Range
=
6910 A
7T10 4
W1 4
5x10 4
4x10 4
--
A Target Depth
x10 4
1%10 4
0
urn
Figure 6.5. The hydrogen profile simulated using TRIM.
121
Figure 6.6. SEM shows the silicon layers stack obtained after handle wafer release.
Handle wafer is released at the peak of the implanted hydrogen profile.
cracks induced by hydrogen will release the handle wafer at the location around the peak
of hydrogen implant profile. Figure 6.4 is the SIMS profile of the implanted hydrogen
with a peak about 300 nm into the silicon handle wafer from the oxide-silicon interface.
The hydrogen profile simulated using the TRIM program is also shown in Figure 6.5.
To ensure successful bonding, it is important to ensure that hydrogen implant
does not increase the surface roughness of the oxide handle wafer excessively. The
surface roughness of the oxide handle wafer is estimated with AFM to be 0.27 nm as
mentioned in Chapter 4. This value increases to 0.34 nm upon hydrogen implantation.
Note that this value is below the roughness requirement of 1.0 nm and hence CMP is not
required for oxide handle wafers with hydrogen implant for successful wafer bonding.
Since this process is temperature sensitive, all heat treatments prior to layer
splitting were kept at 300 C or below. Therefore, Cu wafer bonding was done at 300 *C
122
(b)
(a)
Annealed at 400 OC for 1 h
As implanted
Figure 6.7. Hydrogen-implanted handle wafer surface under optical microscope for (a)
as-implanted wafer, and (b) after wafer underwent 400 0C anneal for 1 hour.
for 1 hr to prevent premature wafer de-bonding. Hydrogen induced wafer splitting was
achieved with an anneal at 400 0C for 1 hour. This step also enhanced the Cu layer
bonding strength. Figure 6.6 is an SEM image of the stack after the handle wafer
separation. We have used a substrate wafer with 1 pm of PE-TEOS oxide on top. The
remaining 300 nm of Si left over by the handle wafer on the top of the stack can be
stripped using a short TMAH dip. The close-up view shows a homogeneous Cu layer
with grains that extend from one end to the other end, suggesting that significant grain
growth has taken place even though the thermal budget was reduced to provide a
temperature window for Cu wafer bonding and hydrogen induced layer splitting.
Figure 6.7 shows optical microscope images of hydrogen implanted wafer before
and after anneal at 400 C for 1 h. Note that surface blisters form on oxide wafers after
anneal. These blisters originate from microcracks caused by gathering of hydrogen
molecules; the resulting force pushes upward to the free surface to form blisters. In the
case of a well bonded wafer pair, the force will cause lateral propagation of the cracks
and thus release the wafer close to the location of the implanted hydrogen peak.
123
(a) As bonded
(b) Etch-back
(c) Handle wafer release
F4
Figure 6.8. Thin film delamination due to the presence of surface particles at the bonding
interface: (a) IR image reveals large void at the oxide bonding interface due to surface
particles, (b) photo of thin films on the handle wafer after etch-back, and (c) photo of
final thin film stack after handle wafer release.
6.2 Thin Film Reliability
Surface cleanliness is an essential requirement to obtain reliable wafer bonding. The
presence of surface particles at the bonding interface of protective thermal oxide on the
handle wafer and the PE-TEOS oxide on the SOI donor wafer can have detrimental
consequence on the final thin film integrity. This is highlighted in Figure 6.8. IR image in
Figure 6.8 (a) reveals large voids at the bonding interface of an oxide wafer pair due to
unwanted surface particles that are incorporated during wafer handling. These particles
prevent bonding at areas surrounding the particles. As a result, thin films detach from the
handle wafer in these areas, as shown in Figure 6.8 (b), because there is no mechanical
support to hold them to the handle wafer. The same delamination is also observed after
the handle wafer is released from the thin film stack in Figure 6.8 (c) and this will
degrade the final yield. Except at the wafer edge, thin films are transferred reliably onto
the substrate wafer at locations where no interfacial voids were observed at the oxide
bonding interface. Therefore, surface particle control during wafer bonding is an
124
important aspect to achieve high yield in thin film transfer.
6.3 Summary
Ultra-thin silicon layer is successful attached to an oxide handle wafer in a two-step
process consists of low temperature oxide wafer bonding and silicon substrate thin-back.
The silicon layer is subsequently transferred to a substrate wafer by Cu thermocompression bonding followed by handle wafer release to form a double-layer stack.
125
126
Chapter 7
Demonstration of Vertically Interconnected Active Layers
Building on the demonstration of silicon multi-layer stacking in Chapters 5 and 6, this
chapter focuses on the demonstration of a stack of interconnected active layers. The role
of Cu bonding medium as a heat conduit is assessed. A vertically interconnected active
layer stack having poly-Si resistor chains is then demonstrated.
7.1 Thermal Management
One of the advantages offered by stacking active device layers on a vertical stack is the
ability to integrate higher number of devices in a given chip area. However, such an
architecture suffers from higher power density that will adversely affect the performance
R = (V, -
V2)/'
Figure 7.1. Kelvin test structure for resistance measurement.
127
(b)
(a)
Cr
SiO2
Si substrate
n
5000
S1S ubstrate
-
- nm-
Figure 7.2. SEM images of temperature sensor structure on oxide layers bonded using
(a) Cu, and (b) oxide.
and reliability of a 3-D IC [56]. Integrated microchannels for cooling have been proposed
as a potential solution to thermal issues in 3-D ICs [57]. In this section, the ability of the
Cu bonding medium to mitigate the heating issue is demonstrated experimentally.
7.1.1 Test Structures Fabrication
The purpose of this experiment is to compare heating problems in double layer stacks
bonded using Cu and oxide. Temperature of a sensor built in the top layer is measured
and compared for both cases. Temperature of device layers under certain operating
conditions has previously been measured using various temperature sensors, including pn diode [Nakamura 2002] and gate poly [Su, 1994]. In this work, temperature sensors are
formed from patterned gold (Au) lines on a substrate. By monitoring changes in the
resistance value of the Au lines, temperature of the Au lines can be estimated.
128
Temperature sensors were formed on two sets of processed substrates. In the first
substrate, two oxide wafers were bonded by Cu and etched back to the buried oxide layer
as previously shown in Figure 3.4. In the second set of substrates, 500 nm of CVD oxide
was deposited on a wafer coated with 500 nm of thermal oxide. After proper surface
preparation and activation, this wafer was bonded to a top wafer having 500 nm of
thermal oxide. The top wafer was etched back to the buried oxide layer. All wafer
bonding was completed in a face-to-face fashion. Temperature sensors, in the form of
Kelvin structures, were patterned on these two sets of substrates as shown in Figure 7.1.
The thickness of the gold layer is about 200 nm with 50 nm of chrome (Cr) as an
adhesion layer. These structures are shown in Figure 7.2.
7.1.2 Temperature Measurement
It is well known that the conductivity of metals such as Au is temperature dependent.
Therefore is it possible to estimate the temperature in an Au line by measuring its
resistance. The resistance of Au lines was measured in a temperature range of 25-200 0C.
These Au lines are 10 tm wide and 400 pm long. By applying a small amount of test
current through the Au lines and by measuring voltage drop across the two ends of the Au
lines, resistance can be estimated from:
R = (V -V 2)/I
(7.1)
The test current must be carefully chosen to avoid unwanted heating that might increase
the actual temperature of the lines. The test current in this measurement was chosen to be
129
10 mA. When a 5 mA of current is applied, no significant change in resistance was
measured. Hence it is confirmed that 10 mA of test current does not generate excessive
heat that will affect the measured resistance value. The variation of line resistance at
various substrate temperatures is plotted in Figure 7.3 for substrates with Cu and oxide as
bonding mediums. A linear approximation of resistance changes as a function of
temperature can be made as follow:
(7.2)
R(T) = R(T ) + S(T -T,)
where R(T) is the resistance at temperature of interest, T, and R(TO) is the resistance at
reference temperature, To, which is 25 0C in this experiment. S is the slope of linear
approximation of the measured resistance values at various temperatures.
The Au lines are then subjected to stressing current ranging from 5 mA to 100
mA and the corresponding lines resistance is measured. During current stressing, the
substrate temperature is maintained at 25 0C. By calibrating the resistance values to the
temperature values based on Figure 7.3, it is possible to estimate Au line temperatures
under various stressing currents. The results are plotted in Figure 7.4 for both Cu and
oxide bonding mediums.
As current density in the Au lines is increased, temperature of the lines increases
since more heat is generated from enhanced collision between electrons and Au atoms.
However, this increase is smaller for substrate bonded by Cu. For example, at a current
density of 5 MA/cm2, temperature of Au line on Cu bonded substrate is 45 C while
130
(a)
6.8
6.6 -
Measurement
Linear Fit
6.46.2-
I
6.0
2
5.8
E 5.6U)
-
5.4-
5.2
5.0
4.8100
50
0
150
200
150
200
Temperature (0C)
(b) 7.2
U
7.0
Measurement
Linear Fit
6.86.6
6.4-
2
6.26.0-
-
5.85.65.4
5.2
5.0-
I
0
50
100
Temperature (0C)
Figure 7.3. Resistance of gold line measured in temperature range 25-200 0C on substrate
bonded using (a) Cu, and (b) oxide.
oxide bonded substrate exhibits a higher temperature of 54 0C. This difference becomes
more significant at higher current density.
At a given current density in the Au lines, lower temperature is measured when
Cu is used as the bonding medium as compared to the case when oxide is used as the
131
Oxide
8070 -
060 Cu
50 -
E
(D 40-A
A A-
30-A
0
202
1
2
3
4
5
6
7
Current Density (MA/cm2)
Figure 7.4. Calibrated gold line temperature at different current density.
bonding medium. Since Au lines are conducting current at lower temperature (hence
lower resistance) in the case of Cu, power consumption is lower. This difference can be
explained in terms of thermal conductivity of both mediums. Since Cu has a thermal
conductivity of 394 W/Km which is higher than 14 W/Km in the case of oxide, substrate
prepared by Cu bonding can remove heat more effectively from the Au lines and this
results in a lower temperature. Therefore, it can be concluded that bonded Cu layer has a
positive effect in removing heat in a 3-D stack.
7.2 Cu Lines Bonding
Since Cu is a conductive medium, a continuous Cu bonding layer between active layers is
of no practical application. In an actual multi-layer 3-D ICs implementation having Cu as
the bonding medium, Cu bonding should be done in the forms of pad-to-pad or line-toline bonding with proper electrical isolation. Two sets of pads are required: (a) electrical
132
pads, with dimension higher than alignment tolerance, to form electrical connections
between active layers, and (b) mechanical pads, which cover area between active layers
without vertical via, to provide mechanical support between active layers.
For the purpose of demonstration, Cu lines with various widths were patterned on
LTO/poly-Si/oxide wafers using a lift-off method. Two wafers, with Cu patterns that are
mirror image of each other, were then aligned and bonded face-to-face at 400 *C for 1
hour. One side of the bonded wafer pair was then thinned back to the oxide layer so that
cross sectional SEM analysis can be performed. Figure 7.5 shows a cross section of Cu
lines that are successfully bonded. The spacing between bonded lines is 5.3 gm and it is
filled with air. Figures 7.6 (a)-(c) are SEM images of bonded Cu lines having various
widths of 2.0, 4.1, and 9.2 gm, respectively. Based on these images, it can be concluded
that a misalignment below 0.5 gm is attainable with the current set-up. However,
interfacial voids are observed in the bonded lines and they can lead to serious reliability
concern. The bonding process should be optimized to minimize the formation of void.
Another reliability concern is the empty space between the bonded lines that might
reduce mechanical support between the active layers. Moisture in the empty space can
Figure 7.5. Cross sectional SEM image shows bonded Cu lines that are spaced at 5.3 gm.
133
I--
.
.
-
-
... 1.
__
5---
-
,
-- , -,
-- .., , __ , __ -
M;;NM
(a)
(b)
(c)
9.2 pm
(400 OC /1 h)
Figure 7.6. Bonded Cu lines with various widths: (a) 2.0 gm, (b) 4.1 gm, and (c) 9.2 gm.
also potentially corrode the bonded Cu lines. One solution is to form damascene Cu lines
and to perform parallel bonding of Cu and dielectric such as oxide.
7.3 Vertically Interconnected Active Layers
A stack consists of two vertically interconnected active layers is fabricated using copper
thermo-compression bonding and wafer thinning developed in Chapter 5. A double-layer
face-to-face stack is chosen. Each layer contains poly-Si resistors that are vertically
connected at both ends to resistors in the adjacent layer to form a 3-D resistor chains.
Poly-Si resistor chains are electrically connected by inter-layer vertical vias.
134
7.3.1 Fabrication
Figure 7.7 shows a schematic of the proposed poly-silicon resistors chain. The doublelayer stack is fabricated by bonding an SOI donor wafer to a substrate wafer in a face-toface manner using Cu as the bonding medium. The substrate of the donor wafer is then
etched back to the buried oxide layer. The fabrication began by growing 400 nm of
thermal oxide on 150 mm Si(100) wafers followed by deposition of n-doped poly-silicon.
Poly-silicon lines were etched to form resistors. Low temperature oxide (500 nm) was
deposited and vias were etched to poly-silicon lines at both ends. Vias were filled with ndoped poly-silicon and polished after high temperature activation of dopant in the polysilicon. Dopant activation was done at 1000 0C for 20 min. CMP was performed to obtain
flat and smooth surface for bonding as well as to remove excessive poly-Si during via
filling. Then, Cu bond pads were formed and pairing wafers were bonded face-to-face to
form resistor and via chains. Bonding was done at 400 C for 1 hour under contact force
Ta
Si substrate
Figure 7.7. Poly-silicon resistor and via chain fabricated using a bi-layer stack in a faceto-face fashion.
135
of 4 kN in vacuum. Ta was used as diffusion barrier below the Cu pads. The top wafer
was ground back until it was 75 gm away from the oxide layer. TMAH was used to strip
the remaining silicon. Finally contact holes were opened and probe pads were formed.
7.3.2
Results and Discussions
Interlayer vertical via is an important component that provide electrical connection
between active layers in a 3-D ICs. In this experiment, via with aspect ration smaller than
one is fabricated. The vias can be filled with doped poly-silicon. Figures 7.8 (a) and (b)
(a)
(b)
(c)
Figure 7.8. (a) and (b) Interlayer vertical vias without and with doped poly-silicon fill. (c)
A double-layer poly-Si resistor chain with bonded vertical via.
136
are SEM micrographs of a 1 pm via with and without poly-Si fill. Conformal filling is
obtained as can be seen in Figure 7.8 (b). Excessive poly-Si on top of the LTO layer is
removed during CMP. Shown in Figure 7.8 (c) is a double-layer stack consists of poly-Si
resistor chains that are connected with bonded vertical vias. In Figure 7.9, optical
microscope images of single layer and bi-layer of poly-silicon resistor chains are shown.
The bonding pads are 40 pm x 40 ptm in the design. The top layer is successfully bonded
to the bottom layer and thinned back to form a continuous 3-D poly-Si resistor chains.
The current-voltage (I-V) characteristic of individual poly-Si resistors prior to
layer transfer is measured. All poly resistors are 50 pm long with various widths of 1, 2,
and 5 gm, respectively. As shown in Figure 7.10, all poly-Si lines exhibit ohmic behavior
when probing is done directly on the poly lines. Figure 7.11 lists the resistance value of
individual poly-Si resistors. Based on this plot, the resistivity of the activated poly-Si is
0
estimated to be about 1.56 mcm. The dopant activation was done at 950 C for 30 min.
Cu bond pad
Double Layer
Single Layer
Figure 7.9. Optical microscope images of poly-silicon resistor chain before and after
stacking.
137
16-
*
*
14-
1 m
2 m
5 m
A
1210-
E
8-
64-
0
0
2
4
6
8
10
Voltage (V)
Figure 7.10. I-V characteristic of individual poly-Si resistors having different widths.
4000
,
35003000-
.0
2500 2000 -
U)
(D,
a:
150010005001
2
3
4
5
Drawn Line Width (jim)
Figure 7.11. Resistance of individual poly-Si resistors having different width.
138
7.4 Summary
Temperature measurement of metal lines suggests that Cu bonding medium can remove
heat from top active layer of a double layer stack more effectively than oxide bonding
medium. A vertically interconnected active layers stack is demonstrated by fabricating
poly-silicon resistor chains that are connected with interlayer via.
139
140
Chapter 8
Thermal Stress Analysis
Thermal stress analysis is performed on a bi-layer silicon structure fabricated using Cu
wafer bonding. Stresses of interest include normal stress in the thin films, and interfacial
(shear and peel) stress at the interfaces. A stress-electrical equivalent model is used.
Analytical results are compared with results obtained from finite element analysis. It is
found that Cu bonding layer is under high tensile and interfacial stresses.
8.1 Thermal Stress
In microelectronics fabrication, thin films are added to a substrate at temperatures higher
than room temperature. Since most thin films have different thermal expansion than that
of the substrate, they are always under stresses when the stack is cooled down to room
temperature. Stresses develop because materials try to change their length with
temperature, but are restrained by structural boundaries. This type of thin film stresses is
known as thermal stresses. Common types of thermal stresses include normal stress
P(x)
I
t
(X)
Figure 8.1. Types of thermal stresses, including normal stress (u), shear stress (),
peel stress (p).
141
and
(tensile or compressive) in the thin films, and interfacial shear and peel stresses at the
interfaces [60], [61]. Thermal stresses in thin films are shown in Figure 8.1.
Thermal stress can cause serious reliability concerns in the thin film stack [62].
For example, thermal stress has been found to cause open circuit failure in a multilevel
interconnect structure [63]. Peel stress is experimentally shown to be an important factor
for delamination in thermally mismatched bimaterial assembly [64]. Understanding the
nature of thermal stresses in such electronic systems plays an important role in achieving
higher reliability. In the 3-D structure described in previous chapters, multi-layer thin
films with different thermal and mechanical properties are added to the substrate and it is
very important to analyze the thermal stresses in each layer so that a more reliable 3-D
process can be designed.
This chapter presents results from thermal stress analysis on a face-to-face bilayer stack demonstrated in Chapter 5. Normal stress in each thin film will be estimated
numerically using FEMLAB, commercial finite element method software [65]. The
results are compared with analytical results obtained from a stress-electrical equivalent
method [66] and a thin film thermal stress model proposed by Suhir [67]. Shear and peel
stresses at each interfaces will also be estimated using the Suhir model. The dependence
of thermal stresses on process parameters such as Cu thermo-compression bonding
temperature and bonded Cu layer thickness is also investigated.
142
}Thin films
(a)
(a)stc
Si Substrate
50 pm
100 pm
(b)
SiO 2 (500 nm)
Poly-Si (400 nm)
TEOS (500 nm)
Ta (50 nm)
Cu-Cu (600 nm)
Ta (50 nm)
TEOS (500 nm)
Poly-Si (400 nm)
Si0
2
(500 nm)
Si (50 pm)
Figure 8.2. Thin film stack used in thermal stress analysis.
8.2 Thermal Stress Models
8.2.1 3-D Structures
The 3-D structure used in this analysis is shown in Figure 2. These are the schematic
from FEMLAB after meshing. The stack consists of nine layers of thin films on a thick
substrate (50 pm). The thin films are buried oxide (BOX), poly-Si, TEOS, Ta, bonded
143
Cu, Ta, TEOS, poly-Si and buried oxide. The length of each layer in the stack is chosen
to be 100 pm and thickness of each layer is shown in the figure.
To simplify the analysis, we have excluded buried interconnects from the stack.
Each layer is assumed to be a continuous layer and the interfaces are perfectly bonded.
They are assumed to be stress free at the temperatures they are added to the stack. All
buried oxides films are grown and hence assumed to be stress free at 1000 0 C. The copper
layer is formed as a result of thermo-compression bonding of two copper layers on the
top of substrate wafer and the back of thinned SOI wafer. During thermo-compression
bonding of Cu-to-Cu, inter-diffusion takes place and the Cu layers merge and become
one homogeneous layer. Therefore, we assumed that the bonded Cu layer is stress free at
the bonding temperature. Since the thickness of each thin film is much smaller than the
thickness of the substrate, they do not experience bending stress and are stress free in the
Table 8.1. Mechanical and thermal properties of materials used in thermal stress analysis.
Layer
Thickness
aRef
b Ref
e Ref
Coefficient of
ratio
thermal expansion
0.5
0.4
0.05
0.6
50
0.20
0.223
0.342
0.343
0.278
0.5
2.7
6.3
16.5
2.6
0.5
0.5
58.5
2.45
0.24
0.35
1
66
[68], [69]
[70], [711
' Ref [72]
dRef
Poisson's
Modulus
(GPa)
72
162.8
185.7
129.8
127.0
(pm)
SiO2a
Poly-Sib
Ta0
Cu-CuC
Si(1 00)
substrated
TEOSe
SiLK_
Elastic
[73], [74]
[75]
' Ref [76]
144
(10~6/*C)
direction normal the thin film plane. As a result, each film experiences in-plane biaxial
stress, either tensile or compressive. Table 8.1 lists mechanical and thermal properties of
materials on the 3-D stack used in this analysis.
In this section, induced thermal stresses as a result of uniform cooling from
respective process temperatures to room temperature (25 C) in each thin film layer in the
double-layer stack and interfaces are calculated analytically and numerically. This
analysis provides an estimation of the level of thermal stresses in the chosen 3-D
structure. No prediction on failure will be given in this analysis. A stress-electrical
equivalent model developed by Riemer [66] is used to evaluate the normal stress in the
thin films using an equivalent SPICE model to represent the elastic behavior of thin
films. In-plane and interfacial stresses are estimated using an analysis proposed by Suhir
[67] for stresses in multi-layered elastic thin films on a thick substrate. Finally, finiteelement analysis is used to simulate the thermal stresses using commercial software,
FEMLAB [65].
8.2.2 Stress Electrical Equivalent Model
This model is explained in [66] and will be briefly described in this section. In analytical
and finite element analyses, thermal stresses are derived directly from dimensions and
materials properties. Riemer introduced an electrical equivalent method for thermal
stresses analysis in which physical dimensions and materials properties are converted into
performance parameters (e.g., impedance) hence elaborate descriptions of geometry and
materials are avoided. In this method, capacitance is chosen as the electrical equivalent of
the spring constant, k of material because spring and capacitor store energy, and both
145
Table 8.2. Mechanical parameters for stress analysis and their electrical equivalent.
Mechanical Parameters
Spring constant, k=F/AL
F is the force in Newton
AL is the deformation in meter
Mechanical impedance,
Ze=A L/F= 1/k
Electrical Equivalent
Capacitance, C=Q/V
Q is the charge in Coulomb
V is the voltage in volt
Electrical impedance,
Z= V/I=1/coC
follow the same equations for series or parallel connections. Table 8.2 summarizes
important mechanical parameters for stress analysis and their electrical equivalents. By
conveniently setting the angular frequency, w=- we can establish current I as the
equivalent of force, F. The thermal stress behavior of each layer is represented by
impedance, Ze.
The unrestrained or "inherent" thermal expansion, AL, of a material is aAT.L,
where a is the thermal expansion coefficient, AL is the temperature change, and L is the
length of the part. The inherent thermal expansion (source voltage) is the driver for a
thermal force (current), which flows through the impedance, Ze into any load (boundary
conditions) connected to the terminations. This causes an elastic thermal deformation ALf
(voltage drop) of the element. The voltage measured at the terminal of the equivalent
circuit represents the actual elongation AL of the element under the restraint of the
71
V=aAT.L
1
Ze = k
Figure 8.3. Electrical equivalent circuit of a mechanical component.
146
boundary conditions.
In a stack of thin films, each layer is represented by an electrical equivalent circuit
as shown in Figure 8.3 and the terminations are connected together. This represents the
mechanical bonding of two surfaces. Circuit analysis can then be used to derive thermal
deformations and thermal forces as node voltages and loop currents.
8.2.3 Suhir's Thermal Stress Model
Consider a multi-layered structure consists of a stack of thin films on a thick substrate.
The length of the stack is 2L and the thickness of each layer is denoted as hi (i=O, 1, 2,
...m). In his model [67], all thin film materials are assumed to be linear elastic. When the
above structure is subjected to uniform cooling, stresses develop in the thin films and at
the interfaces. The first group of thermal stress is the in-plane biaxial stress acting in the
thin film and they are responsible for the strength of the materials. The second group of
thermal stress is the interfacial shear and peel stresses. Interfacial stresses are responsible
for film blistering and peeling at the interfaces. Important equations are presented here
and a complete derivation can be found in the original reference.
(1) In-plane biaxial stress
For a multi-layered thin film stack on a thick substrate,
m
ho >>
hi
147
ho is substrate thickness and hi is the thickness of the i-th layer. The stresses in the film
layers, -i = EiJAajAtj where Ei" = Ej /(1 - vi), Ei0 is the biaxial modulus, Et is the Young
modulus, and vi is the Poisson's ratio. Aai = o - o is the thermal expansion mismatch
between the i-th layer and the substrate. Ati is the difference between the temperature i-th
layer is applied and temperature of interest.
(2) InterfacialStress
(i) Shear Stress
Shear stress acting in the i-th interface, i.e., in the interface between the i-th and the
(i+1)-st layers is distributed along the interface and can be calculated from,
zi (x) = -kT sinh(kx)
cosh(kL)
where k 2
i-O
4 "m
with A-
1
Eoh
i-O
and T = 11-yhj, i=0,1,2, ... , m-1
j=i
The maximum value of zi(x) occurs at x=L, and since calculation shows that for the
structures in question the k value is large,
m
1
i,M
~ -ka
-A
j=i
148
(ii) Peel Stress
Peel stress, also known as transverse normal stress, arises from the constraint that forces
the assembled components to bend jointly and have the same curvature at all sections
despite differences in their flexural rigidities [77] Shear stress acting in the i-th interface,
i.e., in the interface between the i-th and the (i+1)-st layers is distributed along the
interface and can be calculated from,
pi(x) =
2
k 2T cosh(kx) M hi
cosh(kL)
__
1
pi (x) is maximum when x=L. Therefore,
pi'max (x
- 12kIC 111
j=i
MX
Yh
j=i+1
= 2 kri'max
Z
Y
hi
j=i+1
8.2.4 Finite Element Analysis
A thermal stress model in FEMLAB is used to estimate thermal stress in the bi-layer
stack described above. This model considers only thermal load and a linear elastic
material model is used. The stress-strain relation or constitutive equation for linear
conditions including initial stress and strain and thermal effects reads,
u = DEel + q = D(E - Eth - E) + U
where D is the 6 x 6 elasticity matrix. The strain can be decomposed into thermal (eth),
initial (E, ), and elastic strains (Eel).
E=
Eel +
Eth +
E
And,
149
E
E,
Eth
I
= avec(T - Tef
YXY
Yyz
-Yxz th
where a is the stress vector, D is the elasticity matrix, e and y are the strain components,
vec is the thermal expansion coefficients, T is the actual temperature and Tref is the
reference temperature.
8.3 Thermal Stress Analysis
8.3.1 Bonding Temperature
Stress analysis is performed on a bi-layer stack having 0.6 pm Cu and bonded at 400 0C
using FEMLAB. Stress profile in each thin film layer based on FEMLAB estimation is
shown in Figure 8.4(a). A close-up view of the stress profile is shown in Figure 8.4(b).
For better visualization, the stress profile is plotted along x=O and it is shown in Figure
8.5. It is very obvious that when the bonded structure is cooled down to room
temperature (taken as 25 0C), the bonded Cu layer suffers from high tensile stress at a
value of 1140 MPa based on FEMLAB estimation. This value is higher than the yield
stress of Cu thin film (262 MPa) [78] and it imposes serious structural reliability issue of
the bonded Cu layer. In reality, this value of stress is too high and relaxation take place to
accommodate such high stress in the form of deformation such as the interfacial voids
observed in Chapter 3.
150
One important process parameter that has direct impact on the value of thermal
stress is the process temperature. Normal stress in each layer is also estimated using the
Riemer's stress-electrical equivalent and Suhir's thermal stress analysis for different
bonding temperature. The results are compared with numerical results obtained from
GPa
(a)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
(b)
5
.4
.3
.2
-1
0
1
2
3
4
5
(pm)
Figure 8.4. Stress profile in each thin film layer based on FEMLAB estimation.
151
1200-
Bonding Temperature: 400 OC
Cu thickness: 0.6 rn
Cu-Cu
1000-
-C 800 a) 600 (n
(0 400 -
Poly-Si
Sio
2
Poly-Si
TEOS
SiC 2
TEOS
Ta
Ta
-200 49
50
51
52
53
Distance (im)
Figure 8.5. Thin film stress in a bi-layer stack bonded at 400 C. Note that the bonded Cu
layer is under high tensile stress.
finite element analysis using FEMLAB and are summarized in Figure 8.6. At 400 0C, the
Cu bonding layer is expected to suffer from high tensile stress between 665-1140 MPa.
As mentioned above, high tensile stress raise serious reliability concerns of the
mechanical integrity of the bonded Cu layer. One possible solution to circumvent such
high stress level is to lower down the bonding temperature as clearly shown in Figure 8.6.
For example, by lowering the bonding temperature to 200 0C, one can lower the stress
level to between 310-517 MPa assuming that a successful Cu-Cu bond can be achieved at
this temperature.
Interfacial stresses at room temperature are calculated using the analysis method
proposed by Suhir. We have calculated the variation of interfacial stress level for a range
of temperatures from 200 - 400 0C. It is assumed that direct Cu-to-Cu bonding can be
achieved in this temperature range and the bonded Cu layer is stress free at its bonding
temperature. The total thickness of the bonded Cu layer is chosen to be 0.6 gim. Figures
152
...
........
1200-
1100-
-
1000
-A-
--
Femlab
Riemer
Suhir
9008009D
700 S600-
z
00
500-
Cu: 0.6 jim
TEOS
400
300
*
I
200
I
II
250
300
I
350
400
Bonding Temperature CC)
Figure 8.6. Tensile stress in Cu layer bonded at different temperature.
8.7 and 8.8 show the value of shear and peel stresses in the Cu layer bonded at various
temperatures. The interface between the lower Ta capping layer and Cu is denoted as
"Ta/Cu" while the interface between the top Ta capping layer and Cu is denoted as
"Cu/Ta" in the figures.
It is clear from Figures 8.7 and 8.8 that interfacial stresses are sensitive to the
temperature at which the Cu layer is bonded. For example, shear stress at the Ta/Cu
interface increases from -149 MPa when the Cu layer is bonded at 200 C to - 413 MPa
when the Cu layer is bonded at 400 0C. Similarly, the peel stress at the Ta/Cu interface
0
increases from -122 MPa when the Cu layer is bonded at 200 C to -340 MPa when the
Cu layer is bonded at 400 0C. Therefore, lower bonding temperature has a favorable
effect on the room temperature interfacial stresses of the Cu layer.
153
0-
-100-
200 0C
U) -200-
300 *C
CO
C -300
Ta/Cu
-
---
Cu/Ta
Cu thickness: 0.6 pm
-400
400 *C
TEOS
50
45
40
Distance (jim)
Figure 8.7. Shear stress in Cu layer bonded at different temperature.
0 -r-w-w-w
.50
-50
0
-200
*C
-100-
2 -150 -
2-200CD-250-
-300-
300 0C
CL
-u-Ta/Cu
-v--Cu/Ta
400 *C
Cu thickness: 0.6 sm
TEOS
-3500.40
0.50
0.45
Distance (pim)
Figure 8.8. Peel stress in Cu layer bonded at different temperature.
154
8.3.2 Cu Layer Thickness
Another important parameter in Cu wafer bonding is the total thickness of the bonded Cu
layer. We have simulated the variation of stress level for for a range of Cu layer thickness
from 0.2 - 1.0 gm at 400 C and the results are plotted in Figure 8.9. FEMLAB predicts a
small of 73 MPa in stress level from 1176 MPa to 1103 MPa as the Cu thickness is
increased from 0.2 gm to 1.0 pm. Riemer on the other hand predicts an even small
decrease (21 MPa) in the stress level from 674 MPa to 653 MPa as the Cu thickness is
increased from 0.2 gm to 1.0 gm. Suhir, however, does not predict any dependency of
stress on Cu layer thickness.
1200
1000
CO
C
A
-
A
-
A
A
A
8000)-
600-
"
0
400-
z
200A
0.0
Femlab
---0-
Riemner
ir
-A-uhirTEOS
0.2
0.4
Bonding Temperature: 400 0C
0.6
0.8
1.0
Cu thickness (gm)
Figure 8.9. Normal stress in Cu layer with different thickness.
155
100 .
U -W-W-W-W-V
W
0.2 gm
-100-
-200-
0.4 gm
-300 (D
-400-
.c
-500-
0.6 gm
-M-
-V-
6)
TaI/Cu
C u/Ta
0.8 gm
-600-700-
Bonding Temperature: 4000C
TEOS
1.0 gm
UUU
0.45
0.40
0.50
Distance (jim)
Figure 8.10. Shear stress in Cu layer with different thickness.
100
-100----
-200-
CD
-300-
---A-
Ta/Cu 0.2 jim
Cu/Ta 0.2 m
Ta/Cu 0.4gm
-v-
Cu/Ta 0.4gm
Ta/Cu 0.6 m
-4- Cu/Ta 0.6 m
4-
-4000,
CD
---
-500 -
+
-*-
-600-700-
--
Ta/Cu 0.8 m
Cu/Ta 0.8 m
Ta/Cu 1.0jm
Cu/Ta 1.Ojm
Bonding Temperature: 400 C
TEOS
0.40
0.45
0.50
Distance (Jim)
Figure 8.11. Peel stress in Cu layer with different thickness.
From Figures 8.10 and 8.11, interfacial stresses are sensitive to the thickness of the
bonded Cu layer as predicted by the Suhir's model. For example, shear stress at the
156
Ta/Cu interface increases from -86 MPa when the Cu layer thickness is 0.2 pm to - 736
MPa when the Cu layer thickness is 1.0 tm. Similarly, the peel stress at the Ta/Cu
interface increases from -59 MPa when the Cu layer thickness is 0.2 jim to -716 MPa
when the Cu layer thickness is 1.0 jim. It is clear that interfacial stress has strong
dependent on bonded Cu layer thickness. Thicker Cu layer will result in higher interfacial
stress.
8.3.3 Choice of Interlayer Dielectric
As interconnect RC delay increases quickly as scaling continues, dielectric materials with
low permittivity is sought after to replace conventional silicon dioxide as interlayer
dielectric
(ILD). Low-k dielectric
can potentially reduce
capacitance between
interconnects lines and hence improve the interconnect latency. Low-k materials will be
integrated into CMOS processing as projected by the ITRS roadmap. Therefore, it is
important to understand the impact of integration of low-k materials on the stress level of
a multi-layer stack achieved using copper wafer bonding.
While Si0
2
met the performance demands for past ILD, lower-k dielectrics are
required for current and future technology needs. Lower-k dielectrics in use today are
commonly grouped as either ultralow-k (k<2.2-2.4) or low-k (2.4<k<3.5). These
materials can be deposited either by a spin-on route (spin-on dielectrics or SODs) or by a
chemical vapor deposition (CVD) or plasm-enhanced (PE) CVD. The SODs are primarily
polymer or organically modified Si0
2
(OSG or organosilicate glasses), and recent
candidates include SiLK [79]. For the 45 nm node (2010), the effective dielectric
constants become 2.3-2.6, as predicted by the ITRS roadmap, update version in 2004.
157
9U
Femlab
850
800 -
Suhir
oL
700650
600-
CO 550-
zo
500
0Riemrer
450 Bonding Temperature: 300 'C
Cu thickness: 0.6 pn
400
1
350-
SILK
TEOS
Dielectric Materials
Figure 8.12. Normal stress in Cu layer with different dielectric.
Two classes of dielectrics are investigated in this analysis. Inorganic dielectric of
choice is TEOS oxide, while organic dielectric of choice is SiLK. TEOS oxide is
prepared using plasma-enhanced chemical-vapor-deposition (PE-CVD)
and has a
dielectric constant of about 3.8. SiLK is a trade name of a class of organic dielectric from
Dow Chemical. It is a solution of a low-molecular-weight aromatic thermosetting
polymer. Thin films are applied by conventional spin-coating equipment and cured at
400*C or higher. Cured films have a dielectric constant of 2.62. The properties of TEOS
and SiLK can be found in Table 8.1.
158
...
.....
....
. ....
U -W-W-W-w-100-
2
-200-
TEOS
Cz
-300-
---
Ta/Cu
-v-- CurTa
-400 -
-500 -
SILK
Bonding Temperatu re: 300 *C
m
Cu Thickness: 0.6 sA
I
-U----,...
0 .45
0.40
I
0.50
Distance (p m)
Figure 8.13. Shear stress in Cu layer with different dielectric.
0- -100-
TEOS
-200-
a-300-
2
CO
-400-
-u-Ta/Cu
-v- Cu/Ta
SiLK
D -500-600-
Bonding Temperature: 300 *C
Cu Thickness: 0.6 pm
-7000.40
0.50
0.45
Distance
Figure 8.14. Peel stress in Cu layer with different dielectric.
In 8.12, the normal stress in the bonded Cu layer with different surrounding
dielectric is compared. Both FEMLAB and Riemer predict a small drop in tensile stress
159
as TEOS is replaced by SiLK. By switching SiLK from TEOS, FEMLAB predicts a
small decrease of tensile stress from 828 MPa to 807 MPa.
However, interfacial is affected more by the properties of the dielectric. In Figures
8.13 and 8.14, Suhir predicts a significant change in interfacial stress as one moves from
TEOS to SiLK. It is predicted in Figure 8.13 that shear stress at the Ta/Cu interface
increase from -281 MPa to -494 MPa. In Figure 8.14, peel stress is predicted to increase
from -231 MPa to -676 MPa as a result of switching to SiLK from TEOS. This points to
careful attention on the stress level in bonded Cu layer as organic low-k dielectric is
employed as ILD materials.
In Figures 8.7, 8.8, 8.10, 8.11, 8.13, and 8.14, interfacial shear and peel stresses are
calculated from the center of the stack (x=O) to the edge (x=5 mm). It is observed from
these figures that both shear and peel stresses are extremely small across the entire length
and increases rapidly closer to the edge of the stack. Interfacial shear and peel stresses are
concentrated at the edge of the stack.
8.4 Summary
Analytical and numerical evaluation of thin film stresses of a multi-layer stack due to
thermal mismatch is performed. Stresses of interest include normal stress in thin films,
and shear and peel stresses at the interfaces. It is found that the Cu bonding layer is under
substantial tensile stress that increases with bonding temperature. Integration of low-ED
materials is found to change the thin film stress levels.
160
Chapter 9
Summary and Conclusion
The main objective of this work is to develop reliable process technology to enable the
fabrication of a vertically interconnected silicon multi-layer stack. Using a combination
of wafer bonding and thinning, ultra-thin silicon layer stacks are successfully
demonstrated. This chapter summarizes salient contributions in the areas of low
temperature wafer bonding, silicon substrate thinning, and inter-layer via formation. Thin
film thermal stress in a silicon multi-layer stack is also analyzed. Building on a number of
interesting results, promising future work is proposed.
9.1 Summary
This thesis consists of experimental and theoretical works that focus on silicon multilayer stack. Experimental work that forms the bulk of this thesis includes low temperature
wafer bonding and its reliability, silicon substrate thinning, formation of vertical interlayer via, ultra-thin silicon layer stacking, and demonstration of vertically interconnected
active layer stack. Thermal stress analysis forms a full chapter of theoretical work. All
important contributions will be described in this section.
9.1.1 Experimental Work
The main objective of this thesis is to develop enabling process technology to fabricate
three-dimensional integrated circuits (3-D ICs). An important element of the process
technology is low temperature wafer bonding. Building on fundamental understanding of
161
reliable wafer bonding, ultra-thin silicon layer stacks are fabricated in both 'face up' and
'face down' orientations. The highlight of experimental work is the demonstration of a
vertically interconnected double-layer stack consists of poly-Si resistor chains. The
following is a summary of work on wafer bonding, silicon layer stacking, and
interconnected active layers stack.
(1) Wafer Bonding
Wafer bonding is studied as a key enabling technology for 3-D IC fabrication. Two types
of low temperature (400 C and below) wafer bonding, i.e., thermo-compression bonding
of metallic copper and fusion bonding of silicon dioxide, are investigated. Bond strength
enhancement techniques as well as reliability issues of the bonded wafer pairs are also
included.
(a) Copper thermo-compression bonding
Thermo-compression bonding of Cu to form a permanent bonding medium between
active layers is studied and demonstrated. Bonded Cu layer can form electrical
connections and provide mechanical support between active layers. Fundamental
understanding of the mechanism during wafer bonding and of reliability issues is
gathered. It is observed that Cu thin films can be bonded to form a homogeneous layer
under suitable conditions, i.e., at a temperature range of 300-400 0 C and contact pressure
-
226 kPa. No observable Cu out-diffusion into adjacent layers is found during bonding
and annealing by using Ta as a diffusion barrier layer. Cu grains that often extend beyond
the original bonding interface are observed in the bonded Cu layers based on cross
162
sectional SEM and TEM studies. The evolution of grain structure in the bonded layers is
also examined for various bonding durations, temperatures, and contact pressures.
Surface oxide on Cu thin film can prevent the formation of a reliable bond. The
effectiveness of pre-bonding forming gas anneal as a method to remove surface oxide on
copper-coated wafers prior to bonding is examined. It is found that pre-bonding forming
gas anneal on the Cu layers can reduce the oxygen content in the final bonded Cu layer
significantly.
The reliability of the bonded Cu layer is severely degraded by the formation of
interfacial void. The void nucleation and growth mechanisms are proposed and counter
measures for void suppression are implemented. Void size and density are found to
increase with bonding temperature and surface roughness. It is found that a pre-bonding
anneal in inert N2 ambient can suppress the formation of void in the final bonded layer.
Bond uniformity across the wafer is directly related to the wafer bow and in severe cases
thin film delamination is observed.
(b) Silicon dioxide fusion bonding
Silicon dioxide fusion bonding is explored to serve as a temporary bond between a
donor wafer and a handle wafer for thin film handling in back-to-face silicon layer
stacking. Specifically, low temperature bonding of CVD oxide to thermal oxide is
discussed. It is demonstrated that CVD oxide wafer, with proper surface preparations
such as densifiction and CMP, can be bonded to thermal oxide wafer. Bond strength
as a function of annealing temperature, annealing duration, and activation method are
compared.
163
The requirement of bond strength to withstand process damage is determined.
A short exposure to oxygen plasma prior to bonding increases the bond strength of
the bonded wafer pair significantly. Oxygen plasma treated wafer pair can be bonded
at room temperature and withstand subsequent mechanical grinding and TMAH
selective etch without the need for post-bonding anneal. An SOI donor wafer bonded
to a handle wafer is successfully thinned back to the buried oxide layer. An ultra-thin
silicon layer originally from the donor wafer is held reliably by the oxide bonding
interface onto the handle wafer for subsequent layer transfer.
(2) Silicon Layers Stacking
By combining wafer bonding and thinning, ultra-thin silicon layers are stacked to form
multi-layer stacks. Silicon layers can be arranged in face-to-face or back-to-face
orientation.
(a) Face-to-face stacking
The most direct way to stack silicon layer is by bonding a donor wafer facing down to a
substrate wafer. The donor wafer is then thinned back to the required thickness. Using
copper wafer bonding and silicon wafer thinning, a bi-layer silicon stack has been
successfully demonstrated. Wafer substrate thinning can be achieved either using a
combination of mechanical grinding and TMAH selective etch, or hydrogen induced
wafer splitting. Both wafer thinning methods are demonstrated.
A silicon four-layer stack is subsequently fabricated by stacking two silicon bilayer stacks together hence paving the path to a true multi-layer silicon stack.
164
(b) Back-to-face stacking
Silicon layer can also be added to a substrate wafer in a facing up fashion. Using oxide
bonding as a temporary bond between a donor wafer and a handle wafer, donor wafer is
thinned back to the buried oxide layer. Silicon layer from the donor wafer (now attached
to the handle wafer) is successfully transferred to a substrate wafer using Cu as the
bonding medium followed by handle wafer release. The handle wafer can be released
either using a combination of mechanical grinding and TMAH selective etch, or
hydrogen induced wafer splitting. Both types of release methods are demonstrated to
fabricate silicon bi-layer stacks.
(3) InterconnectedActive Layers
Since Cu is a better heat conductor than oxide, a Cu bonding medium can potentially
assist in heat removal from top layers of a multi-layer stack to the substrate. By
measuring resistance of metal lines at various current densities and calibrating it with a
resistance vs. temperature measurement, temperature of metal lines at a particular current
density can be estimated. This measurement suggests that metal lines on a double-layer
stack bonded with Cu is 9 C cooler than those lines on a stack bonded with oxide at a
2
current density of 5 MA/cm.
Since Cu conducts current, bonding of patterned line or pad is required in an
actual application. Cu lines, patterned with a lift-off technique, are successfully bonded.
The smallest line is ~ 2 tm in width. Building on results accumulated from silicon layer
stacking and Cu line bonding, a vertically interconnected double-layer stack is fabricated.
165
The double-layer stack, arranged in a face-to-face fashion, consists of poly-silicon
resistor chains. Electrical connectivity between layers is achieved by inter-layer vertical
vias.
9.1.2 Theoretical Work
Analytical and numerical evaluation of thin film stresses of a multi-layer stack due to
thermal mismatch is performed. This analysis considers normal stress in thin film (tensile
or compressive) and interfacial stress (shear and peel). Analytical analysis is performed
using models such as stress-electrical equivalent model and multi-layer thin film stress
model. Numerical analysis is performed using FEMLAB, a commercially available finite
element analysis software.
Comprehensive analysis is performed to understand the dependence of thermal
stress on process parameters such as bonding temperature, design parameters such as Cu
bonding layer thickness, and materials selection such as the integration of low-[]
dielectric. Both analytical and numerical results indicate that the Cu bonding layer is
under substantial tensile stress that increases with bonding temperature. High stress level
in the Cu bonding layer provides a strong driving force for the formation of interfacial
voids described earlier. Integration of low-D dielectric such as SiLK is found to change
the thin film stress levels.
9.2 Future Work
Building on fundamental understanding of wafer bonding and silicon layer stacking
developed in this work, the following deserve further investigation:
166
(a) Reliability of bonded Cu layer is severely degraded by formation of voids. The
formation of void must be understood thoroughly so that effective counter
measures can be carefully implemented.
(b) The handle wafer release techniques developed in this thesis, i.e., mechanical
grinding followed by selective wet etch and hydrogen induced wafer splitting, can
introduce undesired damage and increase manufacturing cost. Another possibility
is to create undercut in the oxide bonding interface to release the handle wafer.
This can be achieved by creating continuous trenches in the handle wafer to allow
HF encroachment and oxide removal.
(c) Reliable and low resistance vertical vias are needed to establish electrical
connections between active layers in a 3-D IC. Silicon area consumption should
also be minimized during via formation. Improvement in alignment tolerance can
increase via density hence higher connectivity between active layers.
(d) The effectiveness of Cu bonding layer in terms of heat removal is observed. A
comprehensive study can be done by including more complicated test structures
to represent hot spots in an actual circuit. Modeling of heat removal with the
insertion of Cu bonding layer in a multi-layer stack can also be included.
(e) In order to achieve a seamless bonding interface free from moisture and to
provide a higher mechanical support, Cu lines patterned using a damascene
method can be used. Parallel bonding of metallic copper and silicon dioxide might
be needed.
167
168
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