Two-dimensional Materials for Ubiquitous Electronics Yu

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Two-dimensional Materials for Ubiquitous Electronics
by
Lili Yu
B.S., Physics
Peking University (2011)
Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment
of the requirements for the degree of
ARCHNES
Master of Science
MASSACHUSETTS INSTRfE
OF TECHNOLOGY
At the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
JUL 0 8 2013
June 2013
0 Lili Yu, All rights reserved.
LIBRARIES
The author hereby grants to MIT permission to reproduce and distribute publicly paper and
electronic copies of this thesis document in whole or in part.
Signature of Author.............
...................................................
Department of Electrical Engineering and Computer Science
May 28, 2013
.........................
Certified by .................
-.-------Tom~s Palacios
Professor of Electrical Engineering and Computer Science
Thesis Supervisor
Accepted by...........................
....
-o---... -. .
sie A...........
Leslie A. Kolodziejski
Chair, Department Committee on Graduate Students
Two-dimensional Materials for Ubiquitous Electronics
By
Lili Yu
Submitted to the Department of Electrical Engineering and Computer Science
June, 2013, in partial fulfillment of the
requirements for the degree of
Master of Science
Abstract
Ubiquitous electronics will be a very important component of future electronics. However, today's
approaches to large area, low cost, potentially ubiquitous electronic devices are currently dominated by
the low mobility of amorphous silicon and organic semiconductor. Two-dimensional materials are good
candidates for ubiquitous electronics because of their excellent properties such as transparency,
flexibility, high mobility and low cost. This thesis focused on the development of the first devices and
circuits based on transition metal dichalcogenides (TMDs), a family of two dimensional
semiconductors. The transport properties of exfoliated few layer flakes MoS 2 and chemical vapor
deposition (CVD) grown single layer large area MoS 2 are systematically studies. Integrated devices and
circuits based on large-scale single-layer MoS 2 grown by CVD are demonstrated for the first time. The
transistors fabricated on this material demonstrate excellent characteristics such as record mobility for
CVD MoS 2, ultra-high on/off current ratio, record current density and GHz RF performance. The
demonstration of both digital and analogue circuits shows the remarkable capability of this singlemolecular-layer thick material for mixed-signal applications, offering scalable new materials that can
combine silicon-like performance with the mechanical flexibility and integration versatility of organic
semiconductors.
Thesis supervisor: Tomis Palacios
Tile: Associate Professor of Electrical Engineering and Computer Science
3
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4
Table of Contents
Chapter 1 Introduction
.........................................................
12
1.1 Ubiquitous Electronics ..............................................................................................................................................
1.1.1 Opportunities Enabled by Ubiquitous Electronics
1.1.2 Challenges for Ubiquitous Electronics
................................
.......................................
12
12
14
1.2 2D C rystals: L ayered Materials..............................................................................................................................15
1.2.1 2D Material: Excellent Platform for Ubiquitous Electronics
.........................
15
1.3 Transition Metal Dichaeolgenides: Properties and Application.................................................................
23
1.3.1 Layer-dependent Properties.............................................................................................................................23
1.3 .2 Electronic P roperties.........................................................................................................................................24
1.3.3 P hotonic P roperties............................................................................................................................................26
1.4 Th esis O utlin e .............................................................................................................................................................
31
1.4.1
Synthesis of MoS 2 : Exfoliation and CVD method. .....................................................................
32
1.4.2
D evice Technology for M oS 2 ..................................................................................................................
32
1.4.3
Depletion Mode and Enhancement Mode FET on MoS 2
32
1.4.4
Develop a Chip Scale Fabrication Technology for Large Scale CVD Grown Single Layer
33
MoS 2 .
.. .... ... .... ... .... ....
1.4.5
Heterogeneous Integration of CVD Single Layer Graphene and MoS 2 for Flexible Electronic
Ap p licatio n .....................................................................................................................................................................
33
Chapter 2 Fabrication of MoS 2 flake-based Field Effect Transistors (FETs)...................................................
35
2.1 M oS 2 Flake Sample Preparation .............................................................................................................................
35
2.1.1 Exfoliation Of MoS 2 Few Layer Flakes .........................................................................................................
35
2.1.2 Chemical Vapor Deposition Growth of MoS 2 ....................................................
39
.... ... ... .... ... ... .... ... .... . . .
2.2 Fabrication Process for MoS 2 Based Devices and Integrated Circuits. ....................................................
43
2.2.1 Electron Beam Lithography and Dose Optimization ...........................................................................
43
2.2.2 Fabrication Process for MoS 2 Few Layer Flakes
45
Chapter 3. MoS 2 Field Effect Transistors (FET)
................................
........................................
3.1 Device Structure and Measuring Method .......................................................................................................
48
48
3 .1. 1 D evice Structure .................................................................................................................................................
48
3.1.2 Hysteresis in MoS 2 FETs
49
................................................
3.2 Field Effect Transistors (FET) on Few Layer MoS2 Flakes. .....................................................................
3.2.1 Direct-coupled FET Logic (DCFL) Technology
.................................
3.2 .2 D evice P erformance..........................................................................................................................................53
5
50
51
3.3 FET on Single Layer MoS 2 by CVD Grow n. ................................................................................................
55
3.3.1 Im pact of the O hmic M etal on the FET Performance............................................................................
55
3.3.2 The Schottky Barrier Between MoS 2 and Different Metal Contact...................................................
61
3.3.3 M obility of CV D MoS 2 .....................................................................................................................................
65
3.3.4 The H igh-K D ielectric for high m obility MoS 2 ...........................................................................................
68
3.3.5 Top-gated D C and RF D evices.......................................................................................................................75
Chapter 4. D igital and Mixed-signal Circuits on MoS 2 ......................................................
... ... ... ... ... .. ... .... ... .... ... . .
79
4.1 Logic Circuits U sing DFTL Technology on M oS 2 Flakes. .......................................................................
79
4.1.1 Basic Logic U nit: Inverter and N AN D Gate.........................................................................................
79
4.1.2 SRAM............................................................81
4.1.3 Ring O scillator....................................................................................................................................................82
4.2 Circuits Based on Large Scale CV D Samples...............................................................................................
4.2.1 Integrated Logic Circuits Based on Single-Layer MoS 2 ..........................................
4.2.2 Integrated M ix-Signal Circuits Based on Single-Layer MoS 2 ...................................
84
.. ... ... ... .. ..... ... ... .. . .
84
.. ... ... ... .... ... ... . . .
87
Chapter 5. Graphene as Electrodes for Flexible Electronics. ...............................................................................
89
5.1 Fabrication of D evices and Circuits.......................................................................................................................89
5.2 Device...........................................................................................................................................................................92
5.2.1 Back G ate Perform ance ....................................................................................................................................
93
5.2.2 Top Gate Perform ance......................................................................................................................................95
5.2.3 Temperature Dependent Measurements of Graphene/MoS 2 Junctions.............................................
96
5.3 Integrated Circuits......................................................................................................................................................97
Chapter 6 Conclusions and Future Plans..........................................................................................................................99
6.1 Conclusion...................................................................................................................................................................99
6.2 Future W ork. .............................................................................................................................................................
6.2.1 Further Optimization of the D evice Technology......................................................................................100
6.2.2 D oping of TMD s..............................................................................................................................................100
6.2.3 Compact Modeling of TM D FET.................................................................................................................100
6.2.4 Integration of 2D Circuits on Flexible Substrates.....................................................................................101
Reference...............................................................................................................................................................................104
6
100
7
List of figures.
Figure 1. Examples of ubiquitous electronics for application in flexible display, human health and human
interaction, energy storage and generation and wireless system...........................................................................13
Figure 2. The relation between time delay per stage of ring oscillator from inverter with electron mobility[5].
....................................................................................................................................................................................................
15
Figure 3.The crystal structures of different two-dimensional materials. (a) Transition Metal Dichalcogenides,
(b) Transition Metal Oxides, (c) V-VI/IV-VI compounds, (d) Graphene, (e) Hexagonal Boron Nitride. ........ 16
Figure 4. (a) 3D sketch of the band structure of graphene near the Dirac cone[69]. (b) The relationship of
electron velocity with electric field for different materials. Graphene shows a higher carrier velocity than
m ost oth er materials[70]. .....................................................................................................................................................
18
Figure 5. Some of the main applications of graphene. (a) Optical and SEM image of graphene RF device. (b)
DNA decorated graphene sensor[80], (c) Graphene based large scale touch screen[87]. (d) A dye-sensitized
solar cell with graphene transparent conducting film [86] ......................................................................................
19
Figure 6. Examples of band gap engineering in graphene. (a)(b)(c) band gap opening in graphene using
graphene nanoribbon[90]-[92]. (d)(e)(f) band gap opening in graphene by applying a strong electric field
perpendicular to bilayer graphene[90], [94], [95] ....................................................................................................
20
Figure 7. The energy band gaps of TMDs. (For single layer MoX 2 and WX 2, there is big difference between
optical energy band gap and electronic bandgap due to the large binding energy of the exciton, which will be
discu ssed in detail later).......................................................................................................................................................2
1
Figure 8. The energy band gaps of TM Os[101]-[103]...........................................................................................
22
Figure 9. The energy band gaps of V-VI/IV-VI compounds[52], [53], [104], [105].........................................22
Figure 10. The energy band diagram of MoS 2 with different layer number[95]................................................24
Figure 11. TMDs based FET. (a)FET on thick WSe 2, showing the ambipolar behavior and high on/off
ratio[1 10], (b)The single layer MoS 2 transistor in dual gate structure[106], (c)The single layer WSe 2 p-FETS
w ith chem ically doped contact[ 107].................................................................................................................................25
Figure 12. Theoretical calculation of the limit performance of single layer MoS 2[108].................................26
Figure 13. Layer dependence of photoluminescence efficiency in MoS2[97]..................................................
27
Figure 14. Energy-level diagram of proposed multi-junction solar cell made of stacked semiconductors of
different bandgaps to absorb different wavelengths from the solar spectrum to reduce thermalization losses.
The blue dashed lines represent the quasi-Fermi levels defining the open-circuit voltage, and yellow dots
represent electrons in the device[ 111]..............................................................................................................................28
Figure 15. The PL intensity of MoS 2 with different thickness and the energy of exciton A (inset)[ 114].........29
Figure 16. The illustration of large excitonic energy in TMDs. The calculated imaginary part of transverse
dielectric constant as function of photon energy for MoX 2 and WX 2 monolayer. The vertical solid line
indicates the energy of exiton A, dashed vertical line indicates the electronic energy band gap and the
binding energy of exciton A are noted in each figure[ 113]. ..................................................................................
30
Figure 17. The vibration of MoS 2 . (a)Different vibration modes of MoS 2 , (b) The characteristic Raman peak
of MoS 2 with different layer numbers. (c) The layer dependent Raman peak of Aig mode, E 12g mode and their
peak space [1 16 ]. ....................................................................................................................................................................
31
Figure 18. The fabrication process for exfoliation of single or few layer MoS 2 ............................ . ... .... ... .... .. . . . 36
Figure 19. AFM image for exfoliated MoS 2 before annealing....................................................................................37
Figure 20. An optical micrograph image of single layer MoS 2............................................... .... ... ... .. .... ... ... .... ... . . 38
8
Figure 21. AFM and Raman for exfoliated MoS 2 flake from 1L to 5L. For each MoS 2 flake, the height
information from AFM and Raman peak shifts between E2g mode and Aig mode are cross-checked to
39
confirm the num ber of layers in the M oS 2 thin film ................................................................................................
Figure 22. (a) Chemical structure of PTAS (right) and schematic picture for the growth process on diverse
41
surfaces (left). (b) Schematic diagram for the growth setup.................................................................................
Figure 23. (a)PL of the single-layer MoS 2 grown by CVD. Inset: the corresponding Raman spectra. (b) AFM
images (inset) and cross-sectional height profiles of the single-layer MoS 2 thin film grown by CVD ............. 42
Figure 24. (a)Low magnification and (b) high resolution TEM image of as-grown MoS 2 . Inset in (a) shows
the corresponding SA ED patterns......................................................................................................................................43
Figure 25. The AFM images of SiO 2 substrate after development. (a) photolithography, EBL with dose
... .... .... . . .
2
45
(b) 1400 uC/cm 2 , (c) 1600 uC/cm 2 , (d) 2000 uC/cm2 , (e) 1500 uC/cm2 , (f) 3000 pC/cm ...............
Figure 26. The fabrication process of MoS 2 integrated devices and circuits......................................................46
Figure 27. Schematic diagram of MoS 2 FET(a)back gate structure. (b)dual gate structure............................49
Figure 28. Hysteresis of MoS 2 FET. Double sweep of voltage is used to investigate this effect....................50
Figure 29 Schematic of the Direct-coupled FET logic (DCFL) Technology. (a) energy diagram of isolated
metal, insulator and n-type semiconductor. (b) energy diagram of enhancement mode and depletion mode
52
MO S stru ctu re ........................................................................................................................................................................
Figure 30 (A) Schematic representation of an E-mode and a D-mode device. (B) Schematic illustration of an
integrated 5-stage ring oscillator circuit on MoS2 thin films, which is constructed by integrating 12 MoS2 FETs.
Three distinct metal layers of the MoS2 IC are represented by M1, M2, and M3. M1 is directly in contact with the
bilayer MoS2 thin film while M2 and M3 are the Pd and Al gate layers, respectively. Via holes are etched through
the HfO2 dielectric layer to allow connections from M2 and M3 to M1. The general aspects of the fabrication
process apply to all the devices and logic circuits presented in this letter. (C) The transfer characteristics of
depletion (D) mode and enhancement (E) mode bilayer MoS2 FETs. (D) The transfer characteristics in
logarithmic scale of depletion (D) mode and enhancement (E) mode bilayer MoS2 FETs. Device dimension:
53
Lg=1 pLm and Lds=1 ptm . The substrate is grounded...................................................................................................
55
Figure 31. The output performance for the E-mode FET.........................................................................................
Figure 32. Transmission line method measurement of contact resistance between MoS 2 and Ti..................57
Figure 33 Basic I-V curves of CVD single layer MoS 2 with different metal contacts. The device length is:
Ag:500 nm, In:400 nm, Mo: 1 pim, Ti: 100 nm. The current scales with the channel length and the Source
drain voltages of devices with different metals scale with the channel length....................................................58
Figure 34. Output performance for MoS 2 FET with different metals. (a) Ag, (b)In, (c)Mo, (d)Ti. The device
59
length is (a) 500 nm , (b)400 nm, (c)1 im , (d)100 nm . ............................................................................................
60
.........................
contacts.
metal
different
with
MoS
layer
single
CVD
for
Mobility
Figure 35. Field Effect
2
Figure 36. Temperature dependent measurement of current for Ni/MoS 2 contact............................................62
Figure 37. Schottky barrier heigh between Ni and MoS 2 at different gate voltage............................................63
Figure 38. Temperature dependent measurement of current for Au/MoS 2 contact..........................................64
64
Figure 39. The Schottky barrier height for Au-M oS 2 contact. ................................................................................
Figure 40 Optical micrograph of a Hall bar structure on MoS 2 . The voltage and current of MoS 2 in white
66
dashed rectangle is used to extract mobility...............................................................................................................
68
............................................................
method.
4-probe
using
measured
Si0
on
Figure 41. Mobility of MoS 2
2
Figure 42. The Charge transport properties of the multilayer MoS2 channel. The open circles are data
measured in ref [138], and the filled circles are data from ref. [143]. From the theoretical transport model,the
electron mobility (dashed line) is limited by impurity scattering (red line) at low temperatures. At room
9
temperature, the mobility is limited by the combined effect of the homopolar (out-of-plane) phonon (green
line) and the polar-optical phonon (blue) scattering[ 138]......................................................................................
69
Figure 43. Mobility of two MoS 2 devices on SiO 2 covered with A120 3 measured using 4 probe methode......71
Figure 44. Mobility of five different MoS 2 devices on SiO 2 covered with HfO2 measured using 4 probe
m eth od ......................................................................................................................................................................................
72
Figure 45. Mobility change in MoS 2 devices as a function of the average dielectric constant of the
en viro nmen t............................................................................................................................................................................73
Figure 46. The relationship of mobility on carrier density. (a)six-Hall bar structure for MoS 2 on a SiO
2
substrate, and (b) on SiO 2 and covered with HfO 2 -............................................................
... ... ... ... ... ... ... ... .... ... ... ... . . 74
Figure 47. The carrier density of MoS 2 (a) on SiO 2 substrate (b) on SiO 2 substrate covered with A12 0 3 ......... 75
Figure 48. . The carrier density of MoS 2 on SiO 2 substrate covered with HfO2 . .......................... ... ... .... ... .... . . . 75
Figure 49. Optical micrograph of the fabricated chip showing arrays of RF transistors, currents sources, and
1-bit and 2-bit analog-to-digital converters (ADC) .................................................................................................
76
Figure 50. Output characteristics of an FET fabricated on CVD single-layer MoS 2. The device shows
excellent current saturation. LG= l pm ..............................................................................................................................
77
Figure 51 Transfer characteristics of the MoS 2 FET with LG=1 pm. (a) linear scale (b) log scale. The on/off
current ratio of the device exceeds 108, making these devices ideal for ultra-low power applications. The
subthreshold sw ing is 110 mV /dec....................................................................................................................................78
Figure 52 First RF characterization of MoS 2 FETs. In this device the LG is 300 nm.fr=900 MHz andfmx=1
GHz. This measurement is done in vacuum (~105 Torr) to reduce hysteresis...................................................78
Figure 53. Demonstration of an integrated logic inverter on bilayer MoS2. (A) Output characteristics (IdsVds) of the E-mode FET and D-mode load for the inverter. (B) Output voltage as a function of the input
voltage, and its mirror reflection, for a bilayer MoS2 logic inverter. The shaded area indicates its noise
margins (NML and NMH) for logic operation. The gain of the inverter is close to 5. (Inset) Schematic of the
electronic circuit diagram of a logic inverter. .................................................................................................................
80
Figure 54 Demonstration of an integrated NAND logic gate and a static random-access memory (SRAM)
cell on bilayer MoS 2. (A) Optical micrograph of the NAND gate and the SRAM fabricated on the same
bilayer MoS 2 thin film. . (B) Output voltage of the flip-flop memory cell (SRAM). (C) Output voltage of the
N AN D gate . ............................................................................................................................................................................
81
Figure 55 A 5-stage ring oscillator based on bilayer MoS 2. (A) Optical micrograph of the ring oscillator
constructed on a bilayer MoS 2 thin film. (B) Schematic of the electronic circuit of the 5-stage ring oscillator.
(C) Output voltage as a function of time for the ring oscillator at Vdd= 2 V. (D) The power spectrum of the
output signal as a function of Vdd.......................................................................................................................................83
Figure 56. Optical micrograph of a fully integrated inverter constructed on single-layer MoS 2........... ... .... . . 84
Figure 57. (a) Input-output characteristics of the inverter as a function of supply voltage Vdd. The inverter
operates on a wide range of Vdd from 0.5 V to 5V. (b) Voltage gain of the inverter. At Vdd=5 V, the peak
voltage gain of the inverter is close to 20.........................................................................................................................85
Figure 58. Optical micrograph of a fully integrated NAND gate constructed on single-layer MoS 2...... .... . . 86
Figure 59. (a) Schematic circuit for the NAND gate. (c) Output voltage of the NAND gate .........................
86
Figure 60. Optical micrograph of a fully integrated 1-bit ADC constructed on single-layer MoS 2 ....... .. ... . . 87
Figure 61 (a) Schematic circuit for the ADC. (b) AC coupled oscilloscope reading of the input and output
signals ( kH z) of the AD C ..................................................................................................................................................
88
Figure 62. Fabrication process of devices or circuits using graphene as ohmic contacts. ..............................
90
10
Figure 63 Optical Microscope image of different steps along fabrication process, using Hall bar structure as
illustration. (a) The Optical Microscope image after ALD lift off, (b) The Optical Microscope image after
transfer of graphene. (c) The Optical Microscope image of the completed device...........................................91
Figure 64. The schematic for the Hall bar structure micrographed in Figure 63 (c).........................................92
93
Figure 65.The top gated MoS 2-graphene transistor. .................................................................................................
94
Figure 66. The output i-v properties of graphene -MoS 2 transistor....................................................................
scales.
(b)
semilog
and
linear,
(a)
FET
in
Figure 67. The transfer characteristics of a typical graphene-MoS 2
95
....................................................................................................................................................................................................
Figure
Figure
Figure
Figure
Figure
68. Field effect mobility calculated from Figure 67 (a).................95
96
69. (a) The output and (b) transfer characteristics of graphene-MoS 2 FETs........................................
96
.....................................................
FET.
70. Temperature dependent measurement of graphene-MoS 2
71. SHB of the M oS2 -graphene contact...............................................................................................................97
72. The optical image and the schematic diagram of a NAND gate of MoS 2 circuits with Graphene as
th e metal co n tacts. .................................................................................................................................................................
98
Figure 73. (a) Input-output characteristics of the inverter at supply voltage Vdd=3V. (b) Voltage gain of the
in ve rter.....................................................................................................................................................................................9
11
8
Chapter 1 Introduction
1.1 Ubiquitous Electronics
1.1.1 Opportunities Enabled by Ubiquitous Electronics
Si technologies have enabled much of the modem world for the last 60 years; however in the
near future, electronics will develop new dimensions with diverse functionalities: represented by
flexible displays, intelligent clothing, smart health diagnostics, autonomous homes and wearable
computing, [1]-[7]. Theses ubiquitous applications of future electronic are mainly based on flexible
systems. Such electronic systems are large-area, low cost and can be placed on to any type of
surfaces, such as cloth, plastic and paper. They can also have novel properties, including low weight,
durability and simple device integration. The electronic circuits will be printed[8]-[12], just like
documents are on the paper in a copy machine. With these advantages, they can be utilized in a
wide range of applications as shown in Figure 1. With flexibility, durability and low weight, the
devices will be wearable, interactive, portable, greatly improving user experiences.
1Z
12
Figure 1. Examples of ubiquitous electronics for application in flexible display, human health
and human interaction, energy storage and generation and wireless system
One key element of future ubiquitous electronics is a flexible display[ 13]-[16], which can be
used in electronic newspaper, rollable TV, invisible cloak etc. Flexibility of such devices is strongly
limited by conventional transparent conductors (TC), dominated by brittle metal-oxide-
semiconductors. Graphene, a two dimensional metal, being the ideal flexible TC[17], [18], is highly
desirable also because of the increasing cost of Indium tin oxide, the industry standard in TC to
date[ 19]. Flexibility in electronic materials is also very attractive for medical and bioengineering.
The biological environment is fragile and geometrically complicated with curvy features. Thus,
electronics with flexibility and an ability to conform to biological surfaces can provide noninvasive
monitoring, control, interaction and integration with living organisms. This will greatly help with
subcutaneous implantation of sensor arrays, home diagnosis, health monitoring, drug delivery and
even facilitating or artificial organ [20]-[22]. Some of these applications are already starting to
reach the market place [23], [24]. These will be a breakthrough in medicine in terms of scientific
study, real-time patient monitoring and quality of life improvement.
To make the whole system truly portable, power management devices such as batteries, solar
cell, fuel cells or wireless power supply receiver should be integrated in the flexible system to
provide on-demand energy supply for devices such as displays, sensors, antennas, motors, and
actuators. Recently, many advances have been made in flexible solar cell[25], [26] optical
rectenna[27], [28], flexible supercapacitor[29]-[32], flexible battery[33]-[35] and wireless
receiver[36]. Wireless data sharing and communication between different devices is important for
portable devices, wearable computers, smart cloth, medical applications and flexible RFID tags [27],
[37], [38]. Devices integrated with intelligent computing using wireless sensors or antenna will
keep everything, everywhere connected thereby providing seamless operation for the users. With
these components, we can build energy harvesters to extract energy from the environment and then
use circuitry to properly store this energy in batteries and capacitors, forming a flexible, wearable
mobile energy harvester. In conclusion, the flexible electronics will be utilized in a wide range of
applications in our daily life.
13
1. 1.2 Challenges for Ubiquitous Electronics.
In spite of the tremendous potential of ubiquitous electronics, there are still many challenges in
the materials, technologies and integration for flexible electronics application. Here, this work
mainly studies new materials and technologies to improve the mobility of flexible electronic, which
determine the inherent performance limitations of the transistors. As an example, the operating
speed of a ring oscillator, one of the most essential building blocks in many systems, is indicated by
the mobility of the materials. The delay time per stage dependence on mobility is shown in Figure 2
for different material systems. The operating speed is in these circuits is typically proportional to
electron mobility. Today's technologies for flexible electronics mainly use amorphous or
polycrystalline silicon, amorphous oxide or organic semiconductors as the active channel
semiconductors. Both amorphous silicon and organic semiconductors suffer from very low mobility
1 4
2
(~4 cm 2V-s' for electrons in amorphous silicon, and -3 cm V- s for holes in organic
semiconductors)[4], [6], due its intrinsically disordered nature and quantum-mechanical-tunneling
based transport, resulting in slow switching and higher driving voltage and power lost. Poly-silicon,
despite its high mobility (-100 cm2 V's), suffers from a complex technology, large leakage current,
poor yield and high cost when processed at the low temperatures required for flexible plastic
substrates[39]. Finally, amorphous oxide (MOx) semiconductors offer better overall performance,
however the controllability and stability is still an issue because of its amorphous nature[40].
14
101
&ama
*1
4)
~1
Organic
44
3-o0
I
10 a
~1
444
@444
CL
Ii
poly-Si
Polymers
10-.7
Il.
44
E 10 .
-=
Figure 2. The relation
I
nc-*..
mc-W
~....
10
*1
1
0
103
I
.
-1
0-2
10
. . ....
I
.
101
.
. . ....
I
.
.
102
103
between time delay per stage of ring oscillator from inverter with electron
mobility[5].
In summary, new materials with better properties of mobility, on/off ratio, transparency,
flexibility, stability, compatibility with low temperature process and low cost are imperative to
boost the development of flexible electronics.
1.2 2D Crystals: Layered Materials.
1.2.1 2D Material: Excellent Platform for Ubiquitous Electronics.
The successful isolation of graphene [41], [42] and its remarkable properties have renewed
interest in inorganic, two-dimensional materials. 2D materials have a layered lattice structure,
which has strong covalent bonds within each layer but only weak Van Der Waals' forces between
the layers. This unique property makes possible the creation of atomically smooth material sheets
and the precise control on the number of layers, hence the thickness of the material, at the atomic
level. In addition to graphene, other two dimensional materials include transition metal
15
dichalcogenides (TMDs, MX 2)[43]-[48], transition metal oxides (TMOs)[49], [50], and V-VI/IVVI compounds[5 1]-[55] and the graphene analogue of hexagonal Boron Nitride[56]-[58]. The
lattice structures are shown in Figure 3.
(d)
TMDs (Transition Metal Dichalcogenides)
MoS 2,WS 2,NbSe 2 (MX 2)
(b) IW>bI
0
14
AAAI
I
RIn1
Graphene
P# *
6-
6-
1
4
4
TMOs (Transition Metal Oxides)
MoO3 , LiCoO2
Hexagonal Boron Nitride
IIl-VI/V-VI Compounds
(Galn)2Se3, B12(Se,Te) 3
Figure 3.The crystal structures of different two-dimensional materials. (a) Transition Metal
Dichalcogenides, (b) Transition Metal Oxides, (c) V-VI/IV-VI compounds, (d) Graphene, (e)
Hexagonal Boron Nitride.
TMDs form layered structure of the form X-M-X. The metal elements (M) come from
group IV (Ti, Zr, Hf and so on), group V (V, Nb or Ta) or group VI (Mo, W and so on) of
the transition metals. The X is a chalcogen element (S, Se, Te), typically forming two
hexagonal planes separated by a plan of metal atoms, as shown in Figure 3. The metal for
TMOs can be any metal element from transition metal group and most V-VI/IV-VI
compounds have the structure of X-M-X-M-X. The 3 or 5 atomic layers are connected
16
with covalent bonds, forming a molecular or quasi-two-dimensional layer. The different
molecular layers are connected by the week Van der Waals' force.
Figure 3 (d) and (e) show the structure of graphene and its analogue of hexagonal
boron nitride respectively. These 2D crystals have in-plane covalent bonds and weak n-t
interactions between different layers. Each one of these layers is only one atom thick and,
therefore, constitutes the thinnest two dimensional crystals.
These materials are mechanically flexible, optically transparent, thermally stable as
well as excellent electronic properties. The large mobility and a wide range of energy
band gap give them the capability to deal with both analog and digital signal to interact
with other electronic systems in the environment[59]-[63]. Hence, the 2D materials are
good candidates for ubiquitous electronics with enormous advantages over organic
semiconductor, poly-silicon or amorphous oxides. In addition, field-effect transistors
(FET) built on the ultra-thin few-layer 2D crystals are effectively the optimal form of
ultra-thin body FETs[64], which can enhance the electrostatic control of the channel
carriers by the gate electrode and suppress the influence of the drain electrode over the
channel carrier at high drain bias. Furthermore, insulating or semiconducting 2D crystals
absent of dangling bonds are also ideal candidates for use as the tunneling barrier in
tunneling FETs or diodes[65], [66].
1.2.2 Graphene for ubiquitous electronics
Among 2D materials, the one that has attracted the most attention is graphene, the
monolayer counterpart of graphite. Graphene has linear energy dispersion near the K
point in momentum space, and charge carriers can be described as massless Dirac
fermions, resulting Fermi velocity around 1/300 of the light, exceeding 106 cm2 ,'V1 S-1 at
2 K[67] and exceeding 105 cm 2
V-1
s-1 at room temperature for devices encapsulated in
BN dielectric layers[68], providing an abundance of new physics and applications in the
fields of electronic, optical, thermal. Here we will highlight its applications for flexible
electronics.
17
5
(25, 0) CNT (ref. 57)
0
GaAs
Si
1
W
0
0
10
20
30
40
50
Electric field (kV cm')
Figure 4. (a) 3D sketch of the band structure of graphene near the Dirac cone[69]. (b) The
relationship of electron velocity with electric field for different materials. Graphene shows a higher
carrier velocity than most other materials[70].
The development of low cost large scale CVD growth and flexible transfer process of
graphene has boosted the applications of graphene[71]-[75]. Thanks to its exceptional
electronic[69] and optical properties[ 17], graphene is ideal flexible transparent
conductive film to replace indium tin oxide. Recently, a graphene-based programmable
touch surfaces with flexible device architecture was recently demonstrated[76]. Graphene
based pH or glucose sensors have demonstrated high resolution and low noise, providing
excellent platform for bioelectronics[77]-[80]. Thanks to its high mobility, graphene
based RF devices have shown intrinsic cutoff frequencies of a few hundred
gigahertz[81]-[83]. They can be integrated on flexible substrates with hexagonal boron
nitride as the dielectric layer, realizing flexible RF devices. In addition, graphene has
already been exploited for a variety of energy applications such as batteries[34], [35],
supercapacitors[30], [32], [80], water splitting[85], and solar cells[86]. In addition,
graphene based supercapacitors have higher energy storage capability than other
materials. Moreover, because its particular electronic, optical, mechanic and thermal
properties, this material could be used for a new generation of energy harvesting
nanodevices, combining all these properties, such as a nano-opto-electro-mechanical
system.
18
(du
Graphene
Figure 5. Some of the main applications of graphene. (a) Optical and SEM image of graphene
RF device. (b) DNA decorated graphene sensor[80], (c) Graphene based large scale touch
screen[87]. (d) A dye-sensitized solar cell with graphene transparent conducting film[86].
In spite of its excellent transport properties, graphene has severe shortcoming for
electronic systems. Because graphene lacks a bandgap, field-effect transistors (FETs)
made from graphene can not be effectively switched off and they show low on/off
switching ratios, which limits its transistor applications only to analogue circuits[82],
[88], [89]. Quantum-mechanical confinement in patterned graphene nanoribbons[90] or
nanoribbons produced by unzipping carbon nanotubes[91]'[92] can lead to bandgaps up
to 400 meV. However, the size of the bandgap is often very sensitive to edge states; the
off-state current can increase due to edge roughness; and the mobility can degrade
exponentially with increasing bandgap (200 cm 2 /V.s for a 150 meV bandgap)[92]'[93].
Bandgaps up to 250 meV can also be induced by applying a strong electric field
perpendicular to bilayer graphene[94]. This approach has limited use for electronic
applications since the bandgap produced is too small for building large-scale logic
circuits. The extra electrode required to apply the transversal electric field also
complicates device design and degrades overall circuit performance. All these methods
add complexity and reduce the mobility of graphene.
19
(a)
(c)
(b)
3
0
100
1
r
10t
10
#101
-1
I
lie
0
-10
-k
(A)W
,
T
4a
a
_
Figure 6. Examples of band gap engineering in graphene. (a)(b)(c) band gap opening in graphene
using graphene nanoribbon[90]-[92]. (d)(e)(f) band gap opening in graphene by applying a strong
electric field perpendicular to bilayer graphene[90], [94], [95].
1.2.3 2D materials with a bandgap
As discussed above, graphene may not be the best two-dimensional material for digital
application. Lots of materials from the group of TMDs, TMOs and V-VI/IV-VI
compounds naturally have a band gap. The energy band gaps of these materials are
shown in Figure 7, Figure 8 and Figure 9. From the Figure 7, the heavier the metal in
TMDs, the larger the band gap, however, the heavier the chalcogen element, the smaller
the energy band gap. Metal from group IV and VI (Ti, Zr, Hf, Mo, W) tend to form
semiconductor materials with S and Se. Metals from group IV (V, Nb, Ta) tend to form
metals with S and Se, among which NbS2 , NbSe 2, TaS 2, TaSe 2 are even superconducting
below a critical temperature. The chalcogen of Te typically forms semi-metals in
combination with different metal elements. The band gap values are shown in Figure 7.
[96]. The bulk of semiconducting TMDs usually have indirect energy band gap. Both the
direct band gap and indirect band gap are shown in Figure 7. As the TMDs are thinned
down, the electronic structure changes with the number of layers. In many TMDs, there is
20
a transition from indirect band gap in the bulk to the direct band gap of in the monolayer
form[46], [97]-[l00]. In addition, the single layer TMDs have large excitonic energy
which cause big difference between the optical energy bandgap and electronic energy
bandgap. All these materials have attracted a great deal of interest after Field Effect
Transistor had been built on single layer MoS 2 flakes.
Semi-metal
Ti
1.95(D1),.3(1B)
1.55(DB),0.15(1B)
Zr
1.68(DB),2.10(IB)
1.20(DB), 1.61(18)
Hf
2.7(D),1.93(IB)
1.77(DB),1.18(IB)
Semi-metal
V
Metal,
Metal
Semi-metal
Nb
Metal,
superconducting
Metal,
superconducting
Metal
Ta
Metal,
superconducting
Metal,
superconducting
Semi-metal
Mo
Bulk: 1.2(8i)
Single layer:
Bulk: 1.1 (IB)
Single layer:
Bulk: semi-metal
Single layer:
1.88(08), 2.82(EB)
1.49(DB), 2A1(EB)
1.13(DB),1.77(EB)
Semi-metal
W
Bulk: 1.35(B)
Bulk: 1.1(IB)
Single layer:
Single layer:
1.77(DS),2.S8(EB)
1.60(DB),242(EB)
DB: direct bandgap, IB: indirect bandgap, EB: Electronic bandgap
Figure 7. The energy band gaps of TMDs. (For single layer MoX 2 and WX 2 , there is big
difference between optical energy band gap and electronic bandgap due to the large binding energy
of the exciton, which will be discussed in detail later)
The metal elements in TMOs can be any transition metal. Their energy band gaps are
shown in Figure 8. Generally, they have wider band gap than TMDs. Some of the TMOs
with large band gap can form an excellent dielectric. HfO 2 , La 2O 3 and ZrO2 have
attracted lot of interest because of their high constant dielectric. LiCoO 2 has been used as
the anode of Lithium battery.
21
CoO
2.4
NiO
4.3
CuO
1.37
Pd
Rh
2.2 2.1-2.A
Ir
Ag
Au
Pt
1.84
Figure 8. The energy band gaps of TMOs[ 101]-[103]
Figure 9 shows the energy band gap of V-VI/IV-VI compounds. Among them, Bi 2 Se 3 ,
Bi 2Te 3 had been widely studied as thermoelectric materials for decades and been found to
be a topological insulator recently[52], [53].
SMetal
I?.,-
--0 _ .-
Ga
2.5
1.9
1.2
In
2.1
1.2
0.9
Ti
1.2
Semi-metal
Semi-metal
As
2.
1.7
1.
Sb
1.7
1.2
0.3
Bi
1.3
0.35
0.15
Figure 9. The energy band gaps of V-VI/IV-VI compounds[52], [53], [104], [105]
These three families of materials are layered inorganic compounds. Except from them,
the analogue of Graphene, hexagonal BN is insulator with large band gap of 6.5eV.
In fact, the large collection of 2D TMD and TMO crystals, together with graphene and
hexagonal boron nitride, establishes an extremely versatile material system that spans
22
metallic conductor, semimetal (graphene), semiconductors, insulators, high-k dielectric,
even superconductors and the topological insulator. These materials provide abundant
platform for both conventional and ubiquitous electronics. Free of dangling bonds, we
can easily build complex heterostructures by just stacking different materials, adding
more functionalities and exploring more device structures.
1.3 Transition Metal Dichacolgenides: Properties and Application
As discussed previously, 2D materials provide us with a full toolbox for both conventional and
flexible electronics. In this thesis, we will focus on the TMDs family, especially on MoS 2 , WS 2 and
WSe 2.
1.3.1 Layer-dependent Properties.
In TMDs, the metal layer is sandwiched by two chalcogen layers. The overall symmetry of
TMDs is hexagonal or rhombohedral and the metal atoms have octahedral or trigonal prismatic
coordination[96]. As the TMDs are thinned down, the electronic structure changes with the number
of layers. In many TMDs, there is a transition from indirect band gap in the bulk to the direct band
gap of in the monolayer form[46], [97]-[100]. The change in the band structure with the number of
layers is due to quantum confinement and the resulting charge in hybridization between pz orbitals
on S atoms and d orbitals on Metal atoms. From the DFT calculation, the conduction band states at
the K point are mainly due to the d orbitals on the Metal atoms, which are mainly confined in the
middle of the X-M-X layer and do not have too much interaction between different layers[46], [97].
The conduction band states at the F point are hybrid states from both the d orbital of the metal and
the pz orbital from the chalcogen atoms with strong interaction between different layers. Thus, when
the layer number decreases, the conduction band at K point does not change while the energy at the
F point increases, making the K point of the conduction band reach the lowest energy, as shown in
Figure 10.
23
b
a
r
M K
Bulk
rr
MK
C
r r
ML
4 layers Bilayer
d
rr
Mt
r
Single layer
Figure 10. The energy band diagram of MoS2 with different layer number[95].
1.3.2 Electronic Properties.
With a band gap between 1eV to 2 eV, TMDs are suitable for digital transistors and circuits. The
single layer MoS 2 with only one molecular layer in thickness, is robust against "short-channel
effects" when scaling down the channel length[ 106]-[108]. Currently, state-of-art microprocessors
have silicon-based metal-oxide-semiconductor field-effect-transistors (MOSFETs) with featured
gate length of 22nm[109]. These Si-based devices are facing very serious short channel effects such
as drain-induced barrier lowering (DIBL), threshold voltage roll-off, and poor sub-threshold slope,
due to the bad vertical electrostatic control of the gate. A channel length 3 times larger than channel
thickness is typically necessary to achieve good vertical electrostatic integration in MOSFETs. Thus,
single layer MoS 2 as the thinnest semiconductor, represents the ultimate limit of MOSFET scaling.
The first transistor from few-layers TMDs was reported in 2004 from a thick WSe 2 flake[1 10],
where the WSe 2 showed ambipolar behavior, mobility up to 500 cm 2 /V.s at room temperature and
on/off ratio larger than 104 at 60K. The first single layer top-gated MoS 2 was reported by EPFL
group with a dual gate structure[106]. The top gate device with 30nm high-K dielectric has shown
the on current of 2.5 pA/pm, on/off ratio higher than 108, transconductance around 1 UKS/L]m and
24
subthreshold swing of 74 meV/dec. Then a p-type FET with an active channel made of a single
monolayer flake of WSe 2 was made with ZrO 2 as the high-k dielectric and NO 2 gas as the p-type
dopant at the access region to reduce the contact resistance. This device showed an on/off ratio of
106 [107]. The subthreshold swing for that device was able to achieve -60 mV per decade, the
theoretical limit of subthreshold swing at room temperature, because of the low interface charge.
These devices based on single layer TMDs show the high performance and immunity of short
channel effect of two dimensional semiconductors.
(a)
1
(c)
P -
ho*
1
cumu"et
vomv
o
..JooMV
accumulation
sub-
i0mv
10-7
0l
\ l: t:So
10 -81
10-
2000
1018
_
-100
-50
0
50
100
4
5=74mvdec0
-
-4
__0
-2
VTop
0
gate voltage
2
V
4
(V)
(
*W *Se
(b)
,e.
0*
NO2
e"
G Pd)
1-L\m~e
1 E-7
P
S
1E-9
SiO2 (270 nm)
1E-11
-1.5
-1.0
-0.5
0.0
va.4(V)
Figure 11.TMDs based FET. (a)FET on thick WSe 2 , showing the ambipolar behavior and high
on/off ratio[l 10], (b)The single layer MoS2 transistor in dual gate structure[106], (c)The single
layer WSe 2 p-FETS with chemically doped contact[ 107].
Theoretical simulations have shown that single-layer MoS 2 transistors with gate lengths of 15
nm could operate in the ballistic regime with on-current as high as 1.6 mA/pm, subthreshold swing
25
0.5
close to 60 mV/dec and current on/off ratio of 1010 [108]. Simulated current-voltage curves for a
single-layer MoS 2 transistor at different operating conditions are shown in Figure 12. The simulated
devices show good current saturation with the source drain driving current and DIBL less than 10
mV/V. These studies have shown that 2D materials are immune to short channel effect. On the
other hand the low subthreshold swing is easy to achieve in this system because there is no dangling
bonds, resulting possible low Vdd for circuits. This demonstrates the high potential for MoS 2 to be
used in low-power electronics.
(a)
90
-10'
85 --
LG = 30 nm
(b
=
,
V =0.V
1.75
*
0.05 V
10
x L. = 500 nm (Experiment)
0
(a)
10
012
~75-'
E
101
700
70
10
650
5
10
15
t
20
(nm)
25
30
35
-0.6
(0
5
00
-0.4
-02
0.2
0
VG
0.4
0.6
0.8
Figure 12. Theoretical calculation of the limit performance of single layer MoS 2 [108].
1.3.3 Photonic Properties.
As discussed above, when TMD flakes become single layer, there is a transition from indirect
bandgap to direct bandgap. This transition results in 104 times increase of the intensity of the
photoluminescence quantum yield from bulk to monolayer MoS 2 , as shown in Figure 13.
26
*
4000
-
monolayer
bilayer
C-
SSi
;
hexalayer
Raman
0
buk
2nd order
SI Raman
b
0a
Wavelength
A. (nm)
Figure 13. Layer dependence of photoluminescence efficiency in MoS 2 [97].
(a) Photoluminescence and Raman spectra of MoS 2 monolayer, bilayer, hexalayer, and bulk
sample. Different Raman peaks can be assigned to the MoS 2 and silicon vibration modes. For MoS2
thin layers, monolayer MoS 2 Raman signal is relatively weak because less material is being excited.
However, photoluminescence is the strongest in monolayer MoS 2 in spite of reduced material
volume. (b) Photoluminescence spectra normalized by Raman intensity for MoS 2 layers with
different thickness, showing a dramatic increase of luminescence efficiency in MoS 2 monolayer[97].
For semiconductors with a direct bandgap, photons with energy greater than the bandgap energy
can be readily absorbed or emitted. For indirect bandgaps, an additional phonon must be absorbed
or emitted to supply the difference in momentum, making the photon absorption or emission
27
process much less efficient. The direct bandgap for single layer TMDs increases its ability to absorb
and emit light, which is greatly desirable for optical application such as lasers, LEDs, solar cells,
photodetectors and displays. Recently, an optimized solar cell structure has been proposed by
utilizing semiconductors of different bandgaps[ 111], as shown in Figure 14. They can absorb
different wavelengths from the solar spectrum to reduce thermalization losses. The wide range of
optical energy band gap of different single layer TMDs make them excellent materials for
photovoltaic applications.
Eg
----V/\,
\AA\
VV\, V\/\
'VV\
V\,
AA
\
'V\
V\
VV1\,
V
'VV\, '*VV\
V\\
\
Figure 14. Energy-level diagram of proposed multi-junction solar cell made of stacked
semiconductors of different bandgaps to absorb different wavelengths from the solar spectrum to
reduce thermalization losses. The blue dashed lines represent the quasi-Fermi levels defining the
open-circuit voltage, and yellow dots represent electrons in the device[ 11].
The TMDs are found to have large exciton energy[97], [112], [113]. The photoluminescence
spectrum of MoS 2 has a dominant peak at 1.9 eV for exciton A and other peaks at higher energy for
exciton B and direct band gap hot luminescence.
28
_
N
- 3.2 rwri
-4.4 nvrn
- 7.6rn
06"0
m
1.t87-
1.86
~
:100
7
Thickness (nm)
80
0
Wavelength (nm)
Figure 15. The PL intensity of MoS 2 with different thickness and the energy of exciton A
(inset)[1 14].
An exciton is a bound state of an electron and an electron hole, which are attracted to each other
by electrostatic Coulomb force. It is an electrically neutral quasiparticle that exists
in insulators, semiconductors and in some liquids. When a photo is absorbed by a semiconductor, it
excites an electron from the valence band into the conduction band. The electron in the conduction
band is then attracted to this localized hole by the Coulomb force. This attraction provides a
stabilizing energy balance. Consequently, the exciton has slightly less energy than the unbound
electron and hole. Thus, we need less energy to excite an electron to the exciton states than to the
conduction band. The two exciton states in MoS 2 come from the energy split of valence band
because of the strong spin orbital coupling (SOC). The energy values (1.8 ev for exciton A and 2.05
eV for exciton B) are well matched with the theoretical calculation[ 113]. At the same time, the
theoretical calculation has shown that exciton binding energies are quite high in MoS 2 because of
the high effective mass and decreased dielectric constants because of the 2D confinement. The
exciton binding energy for exciton A is about 0.897eV for monolayer and 0.424 eV for bilayer. As
comparison, the valence exciton energies for other common semiconductors are very small, such as
14.7meV in Si, 1.5meV for Ge, 5.1meV for GaAs[ 115]. For these materials with small excitonic
29
energy, the PL spectrum consists of a direct band gap hot luminescence peak broadened by the
exciton energy level and PL measurement is a good method to extract the electronic energy band
gap. However, the electronic energy band gap for single layer MoS 2 should be around 2.8 eV and
optical band gap is 1.9eV.
1.03 eV
-MoS 2
0.91 eV
80 Mo~e
1
Mo~e2
1~
1.04 eV
M40
0 90 eV
WSe2
1
1.5
2
2.5
Photon energy (eV)
Figure 16. The illustration of large excitonic energy in TMDs. The calculated imaginary part of
transverse dielectric constant as function of photon energy for MoX 2 and WX 2 monolayer. The
vertical solid line indicates the energy of exiton A, dashed vertical line indicates the electronic
energy band gap and the binding energy of exciton A are noted in each figure[l 13].
30
The phonon dispersion shown as different vibration mode characterized by Raman peak is also
dependent on the layer number of MoS 2 . The main Raman peaks correspond to the in-plane E12g and
Eiu phonon modes, and the out-of-plane Aig mode (Fig 16.a). The E2g mode describes the in-plane
vibration and the Aig mode describes the out of plane vibration. Thus Aig mode is sensitive to the
structure along the vertical direction and is changed by the thickness of MoS 2 . For decreasing layer
thickness, the E2g peak will slightly red shift and the A Ig peak blue shift. The spacing of the peak
for E2g mode and Aig mode changes from 25 cm- to 18 cm 1 when the layer numbers of MoS 2
change from 5 to 1. These peak position shifts allow layer thicknesses to be identified through
Raman spectroscopy.
a
b
c
t
408A1
222
406
.,24,
E0
~~40
51
~
+-
E
p
404
5L
-20-
360
380
400
420
Raman shift (cmW)
0
1
2
3 4 5 6
Thickness (L)
8ulk
Figure 17. The vibration of MoS 2 . (a)Different vibration modes of MoS 2 , (b) The characteristic
Raman peak of MoS 2 with different layer numbers. (c) The layer dependent Raman peak of A Ig
mode, E1 2g mode and their peak space[ 116].
1.4 Thesis Outline
2D materials are excellent material system for ubiquitous electronics. They offer better choice
than current material for flexible electronics, such as organic semiconductor and amorphous silicon.
As discussed above, 2D materials provide us with a full tool box for both conventional and flexible
electronics. In this thesis, we will focus on materials from TMDs family, especially MoS 2, WS 2 and
WSe 2, for logic applications. The synthesis method and device technology will be developed and
the transport properties will be investigated. Both digital and analog circuit applications are
31
demonstrated. In addition, graphene has been integrated into MoS 2 based devices and circuits as
metal contact.
This thesis is divided in the following five topics:
1.4.1
Synthesis of MoS 2 : Exfoliation and CVD method.
MoS 2 has a layered structure, with weak van der Waals force between layers and strong covalent
force between atoms in the same layer. Single or few layer structure of MoS 2 can be obtained by the
top-down methods of micro-mechanism exfoliation, liquid exfoliation or the bottom up methods of
chemical vapor synthesis, physical vapor synthesis. In this thesis, I will use the micro-mechanical
exfoliation to get few layer flakes from bulk crystal. I will also use the chemical vapor deposition
synthesis method developed in Professor Jing Kong's group to get large scale single layer MoS 2.
Then I will develop the whole fabrication process for MoS 2 FET, including electron beam
lithography, atomic layer deposition, source/drain contacts and gate metal optimization.
1.4.2
Device Technology for MoS 2.
The first dual gate transistor based on single layer MoS 2 was fabricated in 2011. There are still
many challenges to achieve high performance MoS 2 transistor. Firstly, the low doping level of
MoS 2 and the Fermi level pinning at the interface between MoS 2 and metal contacts, result in large
contact resistance in MoS 2 devices. Secondly, due to the lack of dangling bonds, it is hard for the
oxide dielectric deposited by atomic layer deposition to nucleate on the surface of MoS 2 , resulting
in a very narrow process window, low yields and poor dielectric quality. In this thesis, the contacts
between MoS 2 and different metals will be characterized. The method to accurately measure the
mobility will be discussed.
1.4.3
Depletion Mode and Enhancement Mode FET on MoS 2 .
Inverters can be implemented using three different structures: the n-type metal-oxidesemiconductor (NMOS) only or p-type metal-oxide-semiconductor (PMOS) only inverter, the static
complementary metal-oxide-semiconductor (CMOS) inverter, or the direct coupled FET logic
(DCFL) circuit. The MoS 2 FET shows p-type characteristics and the first inverter on MoS 2 uses
NMOS only structure with one MoS 2 NMOS as load resistor. The type of inverter is simple but has
32
large power consumption and low processing speed because current flows through the resistor in
one of the two states. There is also mismatching between the input and output voltage, causing
complexity of the circuits. Static CMOS inverter, which requires both NMOS and PMOS devices,
greatly reduces power consumption since one of the transistors is always off in both logic states and
improves the processing speed due to the relatively low resistance compared to the NMOS-only
type devices. However, the native 2D structure makes it hard to dope MoS 2, hence the p-type
transistor is hard to realize on MoS 2. In that case, direct-coupled FET logic technology will be the
second best choice to make multistage circuits for MoS2 transistor. It has simple structure and
relatively high speed with very low power dissipation The threshold voltage in DCFL device is
tuned by using gate metals with different work function to get both positive and negative threshold
voltages, realizing both depletion mode and enhancement mode MOSFET. With this technology,
four different integrated logic circuits are realized: a logic inverter, a NAND gate, a static random
access memory (SRAM) cell, and a 5-stage ring oscillator. This part of this thesis work is done
together with another senior graduate student, Han Wang, in my group. Han designed the
experiment and we did the fabrication, measurement and analysis together.
1.4.4
Develop a Chip Scale Fabrication Technology for Large Scale CVD Grown
Single Layer MoS 2.
Micro exfoliation cleavage can isolate single crystal flakes with high quality. However, the
limited size and uniformity between different flakes prevents these flakes from being useful in
large scale fabrication and real world applications. With the rapid progress in large-scale growth of
MoS 2 by chemical vapor deposition, chip scale fabrication and device design of circuits with more
functions is a must. In this thesis, I will develop the chip scale fabrication on single layer CVD
grown MoS 2 and design, fabricate and characterized DC, RF devices and integrated logic, analog
and mixed-signal circuits. This part of the thesis work was done in collaboration with another senior
graduate student, Han Wang, in our group. Han designed the experiment and we did the fabrication,
measurement and analysis together.
1.4.5
Heterogeneous Integration of CVD Single Layer Graphene and MoS 2 for
Flexible Electronic Application.
33
For the ultimate transparent flexible electronics, all parts of the device should come from 2D
materials. One potential structure for this future transparent electronics would be made of MoS2 as
the active channel, BN as the gate dielectric and graphene as the transparent electrode, all of which
will be integrated on the flexible substrate. In this thesis, I will use graphene as metal contact to
fabricate MoS2 based devices circuits. The device and circuit performance will be investigated and
the heterostructure of two dimensional materials will be studied.
34
Chapter 2 Fabrication of MoS 2 flake-based Field Effect Transistors (FETs)
MoS 2 is the thinnest semiconductor and it is immune to short channel effect and high mobility
choice for flexible electronics. In this thesis devices and circuits based on MoS2 will be designed,
fabricated, characterized and analyzed. This chapter studied how to make FETs from MoS 2 . The
micro-mechanic exfoliated and chemical vapor deposition method are utilized to achieve single
layer MoS 2 . Then the fabrication process is discussed and demonstrated to get MoS2 devices and
circuits.
2.1 MoS2 Flake Sample Preparation
The MoS 2 has layered structure, with week van der Waals force between layers and strong
covalent force between atoms in the same layer.Single or a few layer structures can be fabricated by
the top-down methods of micro-mechanism exfoliation, liquid exfoliation or the bottom up methods
of chemical vapor synthesis, physical vapor synthesis. Our research started with exfoliated high
quality single crystal MoS 2 flakes and then moved to large scale fabrication using CVD synthesized
by chemical vapor deposition.
2.1.1 Exfoliation of MoS, Few Layer Flakes.
The exfoliation of MoS 2, shown in Figure 18, starts with the preparation of substrates with
alignment markers (Figure 18(a),(b)). A 4 inch wafer of 300 nm SiO 2 / p-type heavily doped Si[41]
is patterned by photolithography, followed by 5 minutes Asher at a power of 900 W to clean the
photoresist residue. Then 5nm Cr /50nm Au is deposited on the wafer, followed by liftoff process.
The thickness of the SiO 2 layer is selected to provide the optimal optical contrast for identifying the
number of layers of MoS 2 . The metal combination is chosen to both give enough secondary
electrons to help imaging for alignment during the Electron Beam Lithography (EBL) as well as to
preserve the clean pattern during Piranha cleaning right before exfoliation. After lift-off, the 4 inch
wafers are cut into small pieces (about 1cm X 1cm). After 15 minutes piranha cleaning the pieces
are rinsed with IPA and then blow dried with N 2 . Then we use cleanroom blue scotch tape to
transfer MoS 2 onto the SiO 2 substrate.
35
S
2
Pattern the substrate
by photo lithography
P-type Si
PR
PR
PR NPR
P-type Si
MoS 2 flakes
Cr/Au
Pirahna cleaning
P-type Si
Exfoliation
s
P-type Si
Figure 18. The fabrication process for exfoliation of single or few layer MoS 2 .
Right after exfoliation, there are typically some bubbles between MoS 2 and SiO 2 as well as
residue on the surface of MoS 2 and SiO 2 . All these cause inaccuracy in thickness measurement by
AFM, noise signal during Raman measurement and bad interface between MoS 2 and metal contact,
resulting in large contact resistance. Figure 19 Shows the typical AFM image of MoS 2 flakes right
after exfoliation. The layered structure can be clearly seen in this image. The bubble and the
residues can be easily observed. The residues are then removed by annealing the sample at 350 C*
in Argon 600 sccm/H 2 30 sccm for three hours to clean away the tape residue and relax and flatten
the sample on the substrate. This cleaning step is important to get the AFM profile and clear Raman
signal.
36
0.01
Figure 19. AFM image for exfoliated MoS 2 before annealing.
Under the optical microscope, we can identify single layer MoS 2 flakes, which have a light
purple color, as shown in Figure 20.
37
Figure 20. An optical micrograph image of single layer MoS2
The number of layers can be estimated based on the optical contrast because of the interference
between the MoS
2
layers and the oxide layer of the substrate.
After, identification of thin MoS 2 flakes under optical microscope, the number of MoS 2 layers is
then confirmed by atomic force microscopy (AFM) based on its thickness and by Raman
spectroscopy based on the peak spacing between the
E2g
mode and the Aig mode, respectively. The
height profile for 1-layer (1L) to 5-layer (5L) MoS 2 flakes are shown in Figure 21. They have a
thickness of 0.65nm for each layer, which is consistent with the c lattice constant of the bulk
material. The number of molecular layers can also be confirmed by the peak spacing between the
E2g
mode and Aig modes [116] from Raman signal. The
E2g
mode describes the in-plane vibration
and the AIg mode describes the out of plane vibration. Thus Aig mode is sensitive to the structure
along the vertical direction and is changed by the thickness of MoS 2 . As shown in the right panel of
38
Figure 21, when the layer numbers of MoS 2 decrease, the E2g peak slightly red shifts and the A l g
peak blue shifts. The spacing of the peak for E2g mode and Aig mode changes from 24 cm- 1 to 18
cm-1 when the layer numbers of MoS 2 change from 5 to 1.
E,
IL
IL
6.5A
SI
E2 9 Ag
.04
0
08
0i4
0.2
OG
6
14
2
1
0.8
1.8
2
5
451
350
Lateral Distance [pm]
RamanShift [cnfr]
2L
13 A
2L
10p
0
W S 0 2L0s
25s 0
201
4
20M
Lateral Distance
(pm]
400
ao
E
iao
200
3
0
4 6
0~
oo
S
130
~
400
oo
Lateral Distance [pm]
4L
27A
.2
7 JAM
2.5
A
0o
450
Raman Shift [cm
so
soW
i
m
5L
Z
5 pim
40'
350
Lateral Distance [pm)
5L
T2
0
550
Soo
460
RamanShift [cm-1)
4L
0
s50
3L
pm
t im
500
450
RamanShift [cr]
33 A
0.2
0.4
o.
o8
12
3so
400
Lateral Distance [pm]
450
500
550
Raman Shift [crII
Figure 2 1. AFM and Raman for exfoliated MoS2? flake from IL to 5L. For each MoS2 flake, the
height information from AFM and Raman peak shifts between E2g mode and A Igmode are cross-
checked to confirm the number of layers in the MoS 2 thin film.
2.1.2 Chemical Vapor Deposition Growth of MoS 2 .
In order to apply MoS 2 to real applications, the quality and the scalability of the material are very
important. Thus a method to achieve high-quality large area single layer MoS 2 is highly desirable.
Thanks to the progress on the Chemical vapor deposition (CVD) synthesis method in Professor Jing
Kong's group, high-quality MX 2 (i.e. MoS 2, WS 2, MoSe 2 and WSe 2) monolayers can be directly
synthesized on various surfaces using scalable atmospheric pressure chemical vapor deposition
39
(APCVD) process with the seeding of perylene-3,4,9, 10-tetracarboxylic acid tetrapotassium salt
(PTAS). The method will be described for the case of MoS 2 , as an example.
The growth starts with the coating of the substrate with PTAS. Figure 22(a) shows the chemical
formula of the PTAS used in this work and an schematic picture describing possible growth
mechanisms. The high solubility of PTAS in water enables the seed solution to be uniformly
distributed on the hydrophilic substrate surfaces. Uniform but small crystalline seeds of PTAS are
precipitated on the surfaces after drying the water. The samples are then introduced in a growth
furnace, which schematic set-up is shown in Figure 22(b). The MoO 3 powders (0.03g) and S
powders (0.01g) were placed in different crucibles. The optimized distance of MoO 3 and S crucible
is 18cm. During the growth, the furnace is heated to the growth temperature of 650C and argon
gas is flowed through the furnace at the flow rate of 10sccm. At the growth temperature, the sulfur
vapor is carried by the Argon gas flow to the position of MoO 3 crucible. Then the MoO 3 powders
were reduced by the sulfur vapor to form volatile MO 3-x.The MO 3-xarrives at the substrate surface
and reacts with the sulfur vapor to form MoS 2 . The heterogeneous nucleation is believed to be
initiated at the PTAS sites [117], [118].
40
(a)
K+ K+
000000
0
O0
0
00
Id
0000
K+ K+
Diverse Surfaces
PTAS
(b)
4 substrate
MO3
1
+-6cm.
[email protected]@@W*-
S
L
----
I=Ar
-
Figure 22. (a) Chemical structure of PTAS (right) and schematic picture for the growth process
on diverse surfaces (left). (b) Schematic diagram for the growth setup.
Raman and PL experiments were performed in a confocal spectrometer using a 473 nm
excitation laser. The Raman spectroscopy shown in Figure 23 (a) confirms that single-layer MoS 2
with uniformity greater than 95% can be grown at centimeter-scale, which is only limited by the
size of the reaction furnace. The CVD synthesized MoS 2 can be detected to be single layer from the
distance between the two characteristic Raman peaks: E2g and A Ig (Figure 23 (a) inset). The high
quality of the material is evidenced by the outstanding photoluminescence peaks (Figure 23 (a))
derived from its 1.8 eV direct bandgap. It should be noted here that the PL has higher intensity in
CVD samples than in the exfoliated single layer flake. This is believed to be due to impurity
contamination in the the commercialized MoS 2 crystals. This is different from high-quality
41
exfoliated graphene, since the Kish graphite which people use to exfoliate single layer graphene is
a byproduct of steel-making, and has extremely high purity. It is obtained when carbon crystallizes
from molten steel during the steel manufacturing process. The high temperature purifies and
anneals the material, ensuring the high quality of the crystal. Thus, the CVD sample is not only
necessary for the large scale applications but also provides a better platform for studying the
physics of MoS 2 such as excitons[97], [112], valleytronics[ 119]-[122] and superconductivity[ 123].
AFM data confirms the thickness of the material is about 6.9 A, which is very close to values
reported for single-layer MoS 2 flake (Figure 23 (b)).
1.0
Raman
P
1
0.87
(b)
0.4
All
E
0.2
b
1
0.6
I
'
6.9A
'-0.2
YV
-0.4
1
-0.6
-0.8
450
500
650
600
550
Wavength (nm)
700
750
0.0
0.2
0.4 0.6 0.8 1.0 1.2
Lateral Distance (pm)
1.4
Figure 23. (a)PL of the single-layer MoS2 grown by CVD. Inset: the corresponding Raman
spectra. (b) AFM images (inset) and cross-sectional height profiles of the single-layer MoS 2 thin
film grown by CVD
Seeded by PTAS, the MS 2 favors layer growth and form large-area monolayer. Crystal and edge
structure of the as-grown MS 2 flakes have been studied with TEM. In Figure 24, high resolution
TEM images and corresponding SAED pattern with [001] zone reveal same hexagonal lattice
structure. The spacing of (100) and (110) planes of MoS 2 measured from Figure 24 (b) is 0.27 and
0.16 nm, respectively, which is consistent with the bulk value. The highly ordered lattice structure
and undetectable defects in Figure 24 (b) (b) demonstrate the high quality of the CVD synthesized
MoS 2 .
42
1.6
Figure 24. (a)Low magnification and (b) high resolution TEM image of as-grown MoS 2 . Inset in
(a) shows the corresponding SAED patterns.
2.2 Fabrication Process for MoS 2 Based Devices and Integrated Circuits.
2.2.1 Electron Beam Lithography and Dose Optimization
All the patterns in the MoS 2 device fabricated in this work were created by Electron Beam
Lithography in Elionix 125 system. Studies have shown that 2D material system is very sensitive to
the surface roughness and photoresist residue, which can act as scattering centers[68], [124]. It is
very important to keep the fabrication process clean. Commonly used photo-lithography leaves a
thin film of photoresist residue after development, making the 2D material surface very rough, as
shown in Figure 2.8 (a). Following standard processing procedures results in a surface arithmeticmean roughness (Ra) and a root-mean square roughness (Rq) of 1.16 and 0.92 nm, respectively. In
conventional semiconductor processing, oxygen plasma is commonly used to remove organic
residues; however, there is a weak selectivity between graphene and other organic compounds;
furthermore, CVD graphene contains defects and wrinkles due to growth and transfer, which make
it more reactive than mechanically exfoliated graphene. A common procedure for removing organic
residues is a forming gas anneal. Unfortunately, forming-gas annealing at > 200
43
oC
is incompatible
with the liftoff technology due to the photoresist reflow. Therefore, 2D materials based devices
suffer from high contact resistance if photo-lithography is used. On the other hand, it has been
shown that Ebeam lithography has cleaner surface if the dose and the development are optimized.
Electron Beam Lithography (EBL) can also define smaller features and it is a mask free process to
allow pattern design flexilbility. The EBL process starts by coating the sample with poly(methyl
methacrylate) (950k MW PMMA) at 4000 rpm for 60 seconds. Then the exposure is done with a
current of 5nA and field size of 600um. The actual e-beam dose varied depending on the features
and patterns to be defined. After exposure, the sample was developed in the mixture solvent of
Methyl isobutyl ketone (MIBK) and Isopropanol (IPA) (MIBK:IPA=1:3) for 90 seconds. Next, the
sample was rinsed in IPA for one minute. The AFM image of different doses is shown in Figure 25.
The PMMA resist residue forms isolated islands or dots on the substrates. In the dose range from
1200 uC/cm2 to 3000 uC/cm 2, there is no over exposure even for pattern as narrow as 200nm gap.
With the increase of dose, both the height of the islands and the density of the islands are greatly
reduced. The height of the islands with dose of 1400 uC/cm 2 (Figure 25(b)) can be large than
100nm, while the typical height of the islands with dose of 2500 uC/cm 2 (Figure 25(e)) is 4nm.
EBL with dose of 2500 uC/cm 2 can give pretty clean surface with Ra of 0.20nm and Rq of 0.1 5nm
which is close to the surface roughness of SiO 2 before fabrication. Thus, the dose of 2500 uC/cm2 is
used for the fabrication of MoS 2 FETs.
44
a
a
mm
b
b
c
ampal
d
f
e
mo 1 Hr'Wi
ilko t
4J
Figure 25. The AFM images of SiO 2 substrate after development. (a) photolithography, EBL
with dose (b) 1400 uC/cm 2 , (c) 1600 uC/cm 2 , (d) 2000 uC/cm 2, (e) 1500 uC/cm 2 , (f) 3000 pC/cm 2
2.2.2 Fabrication Process for MoS 2 Few Layer Flakes.
For exfoliated MoS 2 , the marked substrate formed by photolithography helps locate the flake and
align the designed pattern on top of the flake. For CVD samples, the markers are written together
with the source and drain pattern during the first time EBL. After that we evaporated 10 nm Ti! 50
nm Au followed by lift-off to form the source drain metal contacts. For the CVD sample, an extra
step of mesa isolation is conducted to fully isolate different devices. The second EBL is used to
create PMMA etch mask and the single layer MoS 2 is etched for 30s in a Reactive Ion Etcher using
a gas combination of He and 02 at substrate bias of 200V and pressure less than 10 8 Torr. After that,
samples will be put into acetone overnight to remove the PMMA residue and create clean surfaces
for atomic layer deposition (ALD) process. The top gate dielectric of HfO2 or A120 3 was then
deposited as gate dielectric using ALD at 190 *C. It should be noticed that, the ALD process is has
limited temperature process window for 2D material, because there are no dangling bonds out of the
plane of MoS 2 layer. The ALD process in 2D materials is realized by physical absorption instead of
45
chemical reaction. The low temperature helps the precursor form a void-free layer on top of MoS 2 .
The ALD deposition of HfO2 was done on a commercial Savannah ALD system from Cambridge
NanoTech using alternating cycles of H20 and tetrakis(dimethylamido)hafnium (TDMAH) as the
precursors. To fabricate discrete transistors, the last step of the fabrication was to pattern the top
gate electrode by electron-beam lithography, which was then formed by depositing the desired gate
metal. For the construction of DFCL integrated logic circuits, the second and third metal layers (M2:
60 nm Al and M3: 60 nm Pd) need to be connected to the first metal layer (M1) at certain locations
depending on the design. This was achieved by patterning and etching via holes through the HfO 2
dielectric using reactive ion etching (RIE) with BCl 3/Cl 2 gas chemistry. The ratio between the flow
rates of BC13 and Cl2 is 4:1. The etch rate of our low power recipe is around 6 nm/min. This etching
step preceded the definition of the gate metal layers M2 and M3.
Exfoliate MoS 2 on SiO2
I
I
EBL and M3 deposition
EBL and SD (M1) deposition
EBL and M2 deposition
ALD high-k dielectric
Pattern and Via hole etch
Figure 26. The fabrication process of MoS2 integrated devices and circuits.
46
47
Chapter 3. MoS 2 Field Effect Transistors (FET).
This chapter systematically discusses the device technology for MoS 2 FETs. Threshold voltage
tuning, contact metal, mobility measurement and dielectric integration will be discussed in this
chapter. Then top gated DC and RF devices are fabricated on CVD grown single layer MoS 2, and
they demonstrate excellent characteristics such as record mobility for CVD MoS 2, ultra-high on/off
current ratio, record current density and GHz RF performance.
3.1 Device Structure and Measuring Method.
3. 1.1 Device Structure
There are two different basic FET device structures using here as shown in Figure 27. Figure 27
(a) shows the back gate structure using the heavily p-type doped silicon substrate to apply the back
gate voltage. In this device structure, the dielectric oxide is 285nm SiO2 and the gate voltage is
applied on the whole wafer at the same time. Figure 27 (b) shows the dual gate structure after
integrating the dielectric layer and top gate layer based on the back gate structure. In this devices
structure, we can tune the top gate and back gate separately. The back gate is grounded during the
top gate measurement if not specified.
48
(b)
Figure 27. Schematic diagram of MoS2 FET(a)back gate structure. (b)dual gate structure.
3.1.2 Hysteresis in MoS 2 FETs
The dc characterization was done using an Agilent 4155C Semiconductor Parameter Analyzer.
All the measurements in chapter 3 to 5, are conducted in vacuum environment at pressure around 3
x
10~6 torr). This is necessary to get the intrinsic performance of MoS 2 FET because of the
hysteresis in the devices. Figure 28 shows the double sweep of back gate voltage. There is obvious
voltage shift between the different voltage sweep directions indicated by the arrows. The final plot
will use the data indicated by two green arrows to form the complete back gate sweep from -60 V to
60 V. The double sweep relax the device after measurement and can get the relative intrinsic
49
transport properties. The hysteresis may come from the atmospheric adsorbates like oxygen and
water which may not be able to removed completely in vacuum[125]. Similar effects have also been
observed for graphene devices[ 126]. On the other hand, the hysteresis effect is much serious with
negative bias, where there is less current. This might be caused by trapping states in the material or
at the interface of MoS 2 and SiO 2 . Detailed study of hysteresis mechanism is necessary to get
reliable devices performances and in important for real application.
2.5.
___m_._
---
2.0
_-__v_-_a_-_v
1st double sweep
2nd double sweep
1.5
1.0
0.5
0.0
-60
-40 -20
0
20
40
60
Vsub (V)
Figure 28. Hysteresis of MoS 2 FET. Double sweep of voltage is used to investigate this effect.
3.2 Field Effect Transistors (FET) on Few Layer MoS2 Flakes.
The transistors on the MoS 2 show n-type semiconductor properties with negative threshold
voltage[106]. The first inverter on MoS 2 uses two transistors with one of them as load resistor[ 127].
With this structure, the input voltage needs to sweep from negative to positive bias in order to get
the inverter output performance, causing the different voltage level between the input and output
voltage. The native 2D structure makes it hard to dope MoS 2, hence the p-type transistor is hard to
realize on MoS 2. In that case, direct-coupled FET logic technology will be the second best choice to
make multistage circuits for MoS 2 transistor. The threshold voltage is tuned by using gate metals
with different work function to get both positive and negative threshold voltages, realizing both
depletion mode and enhancement mode MOSFET. On the other hand, a low threshold voltage value
is key for low power application.
50
3.2.1 Direct-coupled FET Logic (DCFL) Technology.
To build both depletion-mode and enhancement-mode FETs on the same sheet of MoS 2 , we use
metals with different work function, wM, as the gates to control the threshold voltages of the FETs.
Figure 29 shows the band diagram of FETs with gate metal work function either greater than the
semiconductor work function, i.e. wM > ws, or smaller than the semiconductor work function, i.e.
WM <wS. A low work function metal tends to induce electrons in the channel, tuning the channel to
the charge accumulation regime; while a high work function metal can induce the channel into the
charge depletion regime, all at zero gate bias. The work functions of some commonly used metals
are shown in table 1. In this work, the Al is chosen for depletion mode transistor and Pd for
enhancement mode transistor. For the Al-gate and Pd-gate MoS 2 FETs reported in this work, the
difference in threshold voltage is around 0.76 V, which changes the work function from negative to
positive and allows the fabrication of both enhancement-mode and depletion-mode MoS 2 FETs,
respectively. (Figure 51).
Metal
Al
Ti
Cr
Mo
Ni
Au
Pd
Pt
OM (eV)
4.0
4.3
4.5
4.6
4.7
5.2
5.4
5.6
Table 1. Work function for commonly used metals[128], [129].
The difference between the work functions of two metals in a dielectric is generally different
from that in vacuum. This phenomenon may be characterized quantitatively by the S parameter,
which accounts for dielectric screening and depends on the electronic component of the dielectric
constant. It can be calculated as the ratio between the effective metal work-function differences on a
dielectric to that in vacuum:
0M,eff = DCNL,d
+
S(OMvac - (CNL,d)
where (DM,eff is the effective work function of the metal in a dielectric and
4
M,vac is the work
function of the same metal in vacuum. #CNL,d is the charge neutrality level of the dielectric. The
difference between the effective work functions of two metals can then be related to their difference
in vacuum:
A(M,eff = SAOM,vac
51
Since AcDM,eff and AcDM,vac are about 0.76 and 1.04 eV, respectively, we have S ~ 0.7 for the
metals on HfO 2, which agrees closely with the value reported in ref [130].
(a)
EO
EO
WM
Es
4s
Ed,
ws
EC- --- ]P'-EF
EF -
---
Eg
Metal
EE
Insulator
n-type
Semiconductor
(b)
EO
E0EF
EV
WS> WM
Al: wM= 4.08 eV
Depletion Mode
WM<
wM
Pd: wM= 5.12 eV
Enhancement Mode
Figure 29 Schematic of the Direct-coupled FET logic (DCFL) Technology. (a) energy diagram
of isolated metal, insulator and n-type semiconductor. (b) energy diagram of enhancement mode
and depletion mode MOS structure.
Energy band diagrams (A) for isolated metal, insulator and semiconductor, and (B) after
bringing them in intimate contact and thermal equilibrium is established. Depending on the
different pairing of metal and semiconductor work functions, the metal-oxide-semiconductor
(MOS) structure can induce the channel into either accumulation regime (for depletion mode FET)
52
or depletion regime (for enhancement mode FET).
3.2.2 Device Performance.
The direct-coupled FET logic technology used in this work integrates both negative (D-mode)
and positive (E-mode) threshold voltage n-type transistors on the same chip (Figure 30 A and B).
Figure 30 C and D shows the device characteristics of two MoS 2 FETs with Al (wM = 4.08 eV)
and Pd (wM = 5.12 eV - 5.6 eV)[128] gates, respectively, fabricated side-by-side on the same
bilayer MoS 2 thin film. The difference in the work functions of these two metals effectively shifts
the threshold voltages of the MoS 2 FET characteristics by about 0.76 V to form a D/E-FET pair
(Figure 30). The discrepancy between the work function difference in vacuum and in HfO2 can be
attributed to the dipoles at the metal/HfO2 interface, resulting from charge transfer across this
boundary[130] as discussed above.
B
A
E-mode
Metal Layer 3 (M3,AI)
D-mode
Metal Layer 2 (M2,Pd)
Via
Vout
MoS
Metal Layer I (MI,TI/Au)
C
3
25
E
=L
20
D E
* 0 Vds=2.0 V
V
V=1.5
=
Vds=l.O V
*0
o Vds=0.5 V
Vds=O.I V
*0
D
102
10
E
S10~
10
2
15
W
10Cr
1M
105
10
10
2
Top-gate VoltageVg [V]
Figure 30 (A) Schematic representation of an E-mode and a D-mode device. (B) Schematic
illustration of an integrated 5-stage ring oscillator circuit on MoS2 thin films, which is constructed
53
by integrating 12 MoS2 FETs. Three distinct metal layers of the MoS2 IC are represented by M 1,
M2, and M3. Ml is directly in contact with the bilayer MoS2 thin film while M2 and M3 are the Pd
and Al gate layers, respectively. Via holes are etched through the HfO2 dielectric layer to allow
connections from M2 and M3 to M1. The general aspects of the fabrication process apply to all the
devices and logic circuits presented in this letter. (C) The transfer characteristics of depletion (D)
mode and enhancement (E) mode bilayer MoS2 FETs. (D) The transfer characteristics in
logarithmic scale of depletion (D) mode and enhancement (E) mode bilayer MoS2 FETs. Device
dimension: Lg=l pm and Lds=1 pm. The substrate is grounded.
Both the D-mode and E-mode FETs have a high on/off current ratio in excess of 107, which is
very close to that in the single-layer MoS 2 FETs[106]. On the other hand, in the on-state, these
devices based on bilayer MoS
2
have much higher on-state current density (exceeding 23 pA/prm at
Vds=1 .0 V and Vtg= 2.0 V for the depletion mode FET, Figure 30(c) than that reported for single-
layer MoS 2 FETs[106]'[127]. The corresponding maximum transconductance of the bilayer FETs
exceeds 12 pS/pm at Vds= 1.0 V. The on-state current and transconductance of a device are key dc
performance metrics, critical for circuit application. The high-field transport of both FETs shows
saturation behavior (Figure 31), a critical feature for both logic and analogue circuits, for the first
time in top-gate MoS
overdrive (i.e.
2
FETs. The good match between the on-set of saturation and the gate
Vsat=Vtg-Vt,
where
Vsat
is the saturation voltage and Vt is the threshold voltage of the
FETs) indicates that the current saturation is due to the classic channel pinch-off mechanism, as is
typical for long channel MOSFETs[13 1], as shown in Figure 31
54
A
20-
o E-mode FET
* D-mode Load Resistor
Vtg =2.0 V
.
E 15,
Vt =1.5 V
<
t:
00.5
=-1.0 V
.. 'V
11.5
2
Drain Voltage Vds[V]
Figure 3 1. The output performance for the E-mode FET.
3.3 FET on Single Layer MoS 2 by CVD Grown.
The devices based on exfoliated flakes have shown high on/off ratio, large on current. However,
research on flakes focuses on few layers MoS 2 because of the low yield of single layer MoS 2 and
the exfoliation technology is not scalable and can not be used in real application. On other hand, the
CVD grown single layer MoS 2 provide large area material and technology allow scalability. The
single layer MoS 2 has larger band gap, lower doping and defect density than few layer MoS2. It is
therefore important to develop device technology for CVD single layer MoS2.
3.3.1 Impact of the Ohmic Metal on the FET Performance.
Because of the large band gap (2.6eV) of single layer MoS2 and lack of doping, it is hard to
form Ohmic contact between metal and MoS 2. The contact resistances between Ti and MoS 2 thick
flake from fitting the data using long channel drift diffusion model is around 500 Q*mm[132], [133]
The transmission line method (TLM) had been applied on Ti and MoS2 contact. In TLM method,
55
the total resistance (Rit,) of a transistor is the sum of the contact resistance (Rc) and channel
resistance (Rch) , represented as:
Reot = Re + Rch = Re + Rsh
L
*
-
W
Where Rsh is the sheet resistance of material, L is the channel length and W is the channel width.
In this device W=1 Oum. TLM structure of MoS2 with different L values is fabricated for Ti contact.
The total resistance with different L values and different back gate voltage is plotted in Figure 32(a).
The intercept of the plot in Figure 32(a) is the contact resistance. Previous study about metal
contacts on graphene has revealed that the contact resistivity (pc) is determined by contact width
instead of the contact area, i.e. pc = Rc*W[134]. This means that in the case of graphene, the current
flows mainly along the edge of the graphene/metal contact. In other words, the current crowding
takes place at the edge of the contact metal. We believe this also applies to monolayer MoS2 since
it's more resistive with lower mobility than graphene. Rc*W with different back gate voltage is
plotted in Figure 32(b). The contact resistance is almost two to three orders larger than the desired
value in conventional semiconductor devices. The high contact resistance, in combination with
intrinsic and parasitic device capacitances, slows down the device'and cause serious heating at the
junction. Though Ti has been widely used for ohmic contact for MoS 2 devices and in many cases
the linear relationship of current and voltage can be achieved, however, the contact resistance
between MoS 2 and channel is still very high. Thus metals which provides smaller contact resistance
with MoS 2 is highly desirable. However, TLM measurement for CVD grown MoS2 devices is
challenging because of the large contact resistance value which might take large part of the Riot and
make the linear fitting with channel length hard, which can also be observed from the large error
bar in Figure 32(b). On the other hand, the substrate of SiO 2 is easy to be damaged during the CVD
growth process and it is hard to collect whole set of data for analysis. To get more detailed study,
optimization of the growth process is highly desired from material scientists.
In this section, mobility of MoS2 calculated from p = [dId/dVsub]x[L/(WCg Vs)] is used to
compare the different metal contacts. The inaccuracy of this calculation in devices with large
contact resistance come from the over estimation of Vds, since parts of it will drop across the contact
part. Thus the larger the mobility is calculated using the above formula, the smaller the contact
resistance in the devices is.
56
(a)
(b) 7xW
.
A
vsub =v
vsub = 10V
.-
Wx10
Ivsub = 20v\*
4x15x1
3xl4x10
1x1r.
0
212x10l
20
Lch (um)
Vsub (V)
Figure 32. Transmission line method measurement of contact resistance between MoS 2 and Ti
To investigate the metal contact, we have chosen different metals as the contact electrodes,
including Mo, In, Ag, Ti, Au, Pt, Pd, Ni. They provide a wide range of work functions, as shown in
Table 2. On the other hand, In, Mo and Ag are also transition metal and the electron in d orbitals
which helps them interact with those from Mo layer of MoS 2 , resulating better electron
injection[135]. However, it should be noted that the work function of metals can be influenced by
the substrate, thus accurate measurement of the work function using Kelvin Force Microscopy
should be included for analysis.
Metal
Y
Sc
In
Ti
Ag
Mo
Ni
Au
Pd
Pt
(Dm (eV)
3.1
3.5
4.1
4.3
4.3
4.6
4.7
5.2
5.4
5.6
samples
#1
#2
#3
#3
#3
#3
#4
#4
#4
#4
Table 2. Work function of different metals[128], [129].
The devices used in this study where fabricated on CVD large-area single layer MoS 2 directly
grown on SiO 2/Si substrate using the chemical vapor deposition method described above. Different
metals were deposited on the same CVD synthesized MoS 2 to avoid the variation from growth
condition. Then oxygen plasma RIE etch is performed to isolate different devices. The metals we
use here are 20nm In/40nm Au, 20nm Ti/40 nm Au, 20 nm Ag/40 nm Au and 15 nm Mo/45 nm Au.
For each metal, transistors with channel length of 2 pm, 1 pm, 700 nm, 500 nm, 400 nm, 300 nm,
200 nm and 100 nm are made and characterized. The summarized performances are shown in
Figure 33. It should be noted that although yttrium and scandium contacts were the first metals tried
57
in this project, they are very reactive materials. A change in the color of the contact can be detected
during the measurement. Thus they are not good for the long term reliability of the transistors and
their device performance will not be discussed here.
(a)
(b)
Ag
---
InIn
E
Mo
Ti
2---
1
-60
-40
T
0.01
1~~1E-4
a
-20 o
20
*
*lI
1E-6
01
iO
40O6 6o20
Vsub (V)
40
60
Vsub (V)
Figure 33 Basic 1-V curves of CVD single layer MoS2 with different metal contacts. The device
length is: Ag:500 nm, In:400 nm, Mo: I pm, Ti: 100 nm. The current scales with the channel length
and the Source drain voltages of devices with different metals scale with the channel length.
As shown in Figure 33, all the devices display n-type behavior with large on/off ratios exceeding
106. The threshold voltage for different metals are all around 3V, which is different from the
literature report about Sc, Ti, Au, Pd contact on exfoliated MoS 2 , where the threshold voltage can
be greatly changed by varying the metal contact [136]. The consistent and small value of threshold
voltage indicates the cleanness of the system and the low doping value of the CVD grown sample.
The Ag-MoS 2 FET contact here shows a current density of 2.4 pA/pm and no saturation here,
which means higher current density could be achieved. In-based MoS 2 FET shows a lower current
density of 1.6 pA/pm. However, Mo and Ti formed MoS 2 transistors with current density below
0.5 pA/pm. Thus, Ag and In can form better contact with MoS 2 than Ti and Mo. Figure 33 (b)
shows the semilog scale transfer characteristics. The Ti-MoS 2 and Mo-MoS 2 FETs have the largest
subthreshold swing. The large subthreshold swing indicate the interfaces of the device with Mo or
Ti as contact metal are not as good as those with Ag or In as metal contacts. The smaller value of
58
subthreshold swing and the resulting higher on/off ratio in Ag-MoS 2 and In-MoS 2 FETs indicate the
smaller interface charge between MoS 2 and SiO 2 . The output performances for these devices are
plotted in Figure 34.
(b)
(a)
E
Vds (V)
Vds (V)
, I
(C) 0.7.
0.6.
0.5.
E
:
0.4,
0.3.
0.2.
0.1.
1.0
1.5
2.0
0.00
Vds(V)
0.05
0.10
Vds(V)
Figure 34. Output performance for MoS 2 FET with different metals. (a) Ag, (b)ln, (c)Mo, (d)Ti.
The device length is (a) 500 nm, (b)400 nm, (c)l ptm, (d)100 nm.
All of the metal combinations show linear characteristics. There is no current saturation shown
here because the channel length of the device is in sub micro scale and the operation drain voltage
is always within the linear region. Current saturation can occur because of two different phenomena
59
in semiconductor devices: velocity saturation and pinch-off (typically, in current device technology,
velocity saturation always occurs in the pinch off regime). Charge carriers normally move at an
average drift velocity proportional to the electric field, with the proportionality constant being the
mobility. At high enough electric field, the charged carrier cannot move any faster due to optical
phonon scattering and they reach saturation velocity. Thus, even we keep increasing the voltage we
apply across the devices, we can not get more current, which is called velocity saturation. In Figure
34there is no velocity saturation detected at this field in MoS 2 device yet. The pinch-off saturation,
usually together with velocity saturation, happens when the drain voltage is large enough that there
is no inversion (or accumulation) channel region near the drain. In that case, the drain current is
weekly dependent upon drain voltage and controlled primarily by the gate-source. Current
saturation is very important for logic application. We can build top gate device to achieve current
saturation in MoS 2 FET as shown in section 3.2.1.
8
6
E 4
0
2
0
E
0
0
20
Vsub (V)
Figure 35. Field Effect Mobility for CVD single layer MoS 2 with different metal contacts.
The field-effect electron mobility extracted without contact corrections for CVD single layer
MoS 2 FET with different metal contacts is plotted in Figure 35. We extract the field-effect electron
mobility from the linear regime of transfer properties using the equation p =
60
[dld/d Vsub] x [L/(WCg Vds)], where L, W and Cox are the channel length, width and the gate
capacitance per unit area, respectively. The mobility under a back gate voltage of 60V for Ag-MoS 2,
In-MoS 2 , Mo-MoS 2 and Ti-MoS 2 FETs is 6.5, 4.2, 1.0 and 0.6 cm 2 /V.s, respectively. These values
vary by more than lOx between each other, indicating good contacts are essential to get higher
mobility in the device.
The Ag-MoS 2 and In-MoS 2 FETs have quite similar performance. However, In has a poor
adhesion with the substrate as well as low melting point (156'C), which may limit its usage as a
contact metal. Thus, it is desirable to explore other d-orbital contact metals for good interaction
with MoS 2 [135], which possess additional process robustness. Ti is a very commonly used metal to
form ohmic contact to MoS 2, however, it is shown that Ti-MoS 2 FET has ten times lower current
density and mobility than Ag-MoS 2 FET, indicating that large part of the source drain voltage is
dropped at the contact resistance.
3.3.2 The Schottky Barrier Between MoS 2 and Different Metal Contact.
The high work function metals shown in table 2 tend to form large Schottky barriers with MoS 2.
To extract the value of the Schottky barrier height is important for optimizing the contact.
Interestingly, all the metal contacts exhibit n-type FET characteristics, which indicate that the Fermi
levels for all of these metals line-up close to the conduction band edge of MoS 2 .
The current for through a Schottky barrier can be described using the thermal emission model:
Id = AT 2 exp((q(PB)/(KBT))[1
-
exp(-qVDS)/(KBT)]
which is equivalent to,
In
(
- =(qpB) + ln(A) + ln[1 - exp
(T2
BT
]
KBT
In this equation Id is the current, A is Richardson's constant, KB is the Boltzmann constant, q is
the electronic charge, T is the temperature, and VDS is the source to drain bias. When VDs is large
enough, the term of ln[1
-
exp
(qv
4
s) is negligible. Thus the effective Schottky barrier height
(SHB) can be extracted from the slope of ln (Id)2
kT
61
1
T
The transfer characteristics of Ni-MoS 2 junction is shown in Figure 36(a). The measured
temperatures range from 210K to 360K. In general, the current increases with temperature.
(a)
(b)
-26-
6.ox10
330K
4.OxC
7
vtg= 3V
-
vtg=25V
-28 .
A31100k
IV270K
vtg= 2V
-- 240K
vtg=1.5V
vtg= 1V
4 210K
2ox10 7
vtg=0.5V
4
-320.0.
0.O
_
0.5
1.0
1.5
2.0
2.5
_
_
_
___-_
_
__
_
_
_
_
3.0
7
\Ag~V
1000rT
Figure 36. Temperature dependent measurement of current for Ni/MoS 2 contact.
From Figure 36 (b), two different barriers can be found. For temperatures between 360K and
270K, the thermal emission current dominates and In (
)
_
follows a linear relationship.
However, at temperatures below 270K, the tunneling current dominates and the temperature
dependence is very weak. These two-energy barrier effect is also found in the graphene-silicon
junction[ 137]. This relationship can be found for different gate voltages. The slope decrease with
the increase of gate voltage, indicating the barrier is smaller at higher gate voltage. The fitted data
are used to extract the SHB of Ni-MoS 2 at different gate voltages, which is shown in Figure 37.
62
150-
150
--
n-
Schokkty Barrier Heicit
100-
50
00.0
0.5
1.0
2.5
2.0
1.5
\A9 (v
Figure 37. Schottky barrier heigh between Ni and MoS 2 at different gate voltage.
The SHB is the energy barrier of the metal-semiconductor junction. When gate voltage is applied
across the channel, the Fermi level of MoS 2 changes and the Schottky barrier between metal and
MoS 2 will be changed.
B -
Y(VGS
PBO
B
B
-,d
-
VFB)
for
for
VGS <
VFB
VGS> VFB
CIT + CCH
Cox
where
B
is the effective SHB and
4
B0
is the true Schottky barrier height. The factor y denotes
the band movement in the semiconducting channel of the transistor in response to the applied gate
bias VGS in the device off-state, Cox is the oxide capacitance and Ca is the interface trap capacitance
and VFB is the flat band voltage. (In the off-state of the device, it is justified to assume that the MoS 2
channel is fully depleted owing to its ultra-thin body nature and hence the channel capacitance CcH
= 0. A is a positive (not constant) quantity which accounts for the fact that for
VGS > VFB,
the
extracted barrier height is smaller than the true value since a significant part of the current through
63
the device is injected through thermally assisted tunneling and hence reduces the extracted barrier
height.
A similar analysis was also done for Au/MoS 2 contact. The temperature dependent measurement
is shown in Figure 38 and the SHB values are shown in Figure 39. The Schottky barrier between
Au/MoS 2 and Ni/MoS 2 are very similar.
(a)
(b)
U
6.ox10
-24-
U
a
0
AA
4.Ox104.
A
SV
vtg=3V
9 vtg=2.5V
.
A
-o
2.Ox10
4
4
vtg= 2V
V
vtg=1.5V
vtg= 1V
4
vtg= 0.5V
vtg=OV
-28-
6007
vtg (V)
1000/T
Figure 38. Temperature dependent measurement of current for Au/MoS 2 contact.
150-
-i--
Schokkty Barier Heict
100-
50-
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Vtg
Figure 39. The Schottky barrier height for Au-MoS 2 contact.
64
However, the method used in the previous paragraphs to extract the Schottky barrier height has
some limitation. First, the extracted SBH is only accurate when the thermal emission current
dominates the junction, which means the barrier should be higher than
3
k T, thus, it is hard to get
consistent and clear values for low work function metals. Secondly, the hysteresis in MoS
2
FET
also causes problem during the measurement. It is important to do double sweep and reset the
device after every measurement. The third inaccuracy may come from the MoS 2 channel in series
with the Schottky contact junction since the mobility of MoS 2 or the resistance of MoS 2 channel
change with different temperature. At high temperature, the mobility of MoS
2
will decrease because
of the increasing phonon scattering rate [138], [139].
3.3.3 Mobility of CVD MoS 2 .
As discussed above, MoS 2 transistors have a large contact resistance, which makes it hard to
extract the intrinsic mobility of MoS 2. In addition, because of the low carrier density and low
mobility in MoS 2 , it is challenging to do Hall effect measurements on MoS 2 . Hence, removing the
impact of the contact resistance from the field effect mobility will be a better way to characterize
the mobility of CVD MoS 2 .
The 4 probe measurement is conducted on 6 probe hall bar device structure is shown in Figure
40. In this figure, the purple part is single layer MoS 2 etched into desire shape. The grey area is
SiO 2 and the yellow part is the 1Onm Ti/5Onm Au metal stack as the contact electrodes. During the
measurement, certain voltage drop Vforce will be applied on electrode 1 and 2 and the current Id
through the MoS 2 will be read at the same time. The voltage difference between electrodes 3 and 4
or 5 and 6 will be measured as
Vdrop
with zero current passing through these electrodes. The voltage
drop measured using 3 and 4 or 5 and 6 should be very close, otherwise it indicates that the material
is inhomogenous. Thus the Id and Vdrop will be the true current pass through and voltage accross
the MoS 2 in the dashed rectangle shown in Figure 40.
65
T 3
L2
Li
\4
Figure 40 Optical micrograph of a Hall bar structure on MoS 2 . The voltage and current of MoS2
in white dashed rectangle is used to extract mobility.
The conductivity and sheet resistance in the white dashed rectangle can be easily calculated.
Li
W
Id
Vdrop
W
Vdrop
IId
_
Rsh-
L1
We can change the conductance of MoS 2 by applying a back gate voltage to the Si substrate.
a = uen = u
*
Cox(Vg - Vt)
80-
1
aVg
Cox
u= ---
From this structure the carrier density can also be calculated.
66
n=-
ol-
ue
The contact resistance can be calculated using:
L2
R 12 = 2Rc + Rch= 2Rc +-*
Rc=
1
(R12
2
L2
1 Vforce
Rsh)=-(
2
W
Id
-
Rsh
L2
Vdrop
L1
I
Using this 4 probe measurement, the mobility of MoS 2 on a SiO 2 surface at room is measured as
1.5 cm 2/V.s. The mobility at different temperatures is also measured using this method on the same
sample, as shown in Figure 41. When the temperature decreases, the mobility increases at first
because of the suppression of the phonon scattering at low temperature[ 138], [139]. Then the
mobility decreases from 1.8cm 2/V.s to 0.06cm 2/V.s when the temperature further decreases from
250k to 77K. This is because of the increased scattering from the charged impurity scattering. At
lower temperature, the electron travels with smaller velocity and faces more Coulomb
scattering[ 140]. This indicates the charged impurity scattering dominates the device at lower
temperature. The charged impurity may come from the SiO 2 substrate and a similar effect can be
seen in graphene on SiO 2 .
67
2.0
1.5-
cvd15-21-6hall
1.0-
0.5-
0.0
100
20
30
T(K)
Figure 41. Mobility of MoS2 on SiO2 measured using 4-probe method.
3.3.4 The High-K Dielectric for high mobility MoS*
In 2D TMDC layers, transport and scattering of the carriers are confined to the plane of the
material. The mobility of carriers is affected by the following main scattering mechanisms[141]: (i)
acoustic and optical phonon scattering; (ii) Coulomb scattering at charged impurities; (iii) surface
interface phonon scattering; and (iv) roughness scattering. The degree to which these scattering
mechanisms affect the carrier mobility is also influenced by layer thickness, carrier density,
temperature, effective carrier mass, electronic band structure and phonon band structure. Many of
these scattering mechanisms are also seen in other semiconductors and in graphene[ 142]. The
acoustic and optical phonon scattering and Coulomb scattering at charged impurities are calculated
from the theoretical transport model, as shown in Figure 42.
68
phonon
Charged im u ity
3
E= 103.
Acoustic (LA
phono
Polar
-o~'o5 r
0
optical phonon
Calculated total
100-
100
150
200
250''300
Temperature (K)
Figure 42. The Charge transport properties of the multilayer MoS2 channel. The open circles are
data measured in ref 11381, and the filled circles are data from ref. 11431. From the theoretical
transport model,the electron mobility (dashed line) is limited by impurity scattering (red line) at low
temperatures. At room temperature, the mobility is limited by the combined effect of the homopolar
(out-of-plane) phonon (green line) and the polar-optical phonon (blue) scattering1138].
Carrier mobility is increasingly affected by phonon scattering with increasing temperature.
The mobility due to acoustic phonon scattering alone is shown along with the total effect of
acoustic and optical phonon scattering. At low temperatures (T < 200 K), the acoustic component
dominates, but at higher temperatures the optical component dominates. The effect of quenching the
out-of-plane homopolar mode, as would occur for top-gated devices, contributes only slightly to
increasing the mobility. Coulomb scattering in 2D TMDCs is caused by random charged impurities
located within the 2D TMDC layer or on its surfaces, and is the dominant scattering effect at low
69
temperatures, as it is for graphene[144]. Engineering the dielectric environment can enhance
mobilities[145], as has been demonstrated for graphene[146] and for MoS 2 [106].
Other important scattering which is not shown in Figure 42 is the surface phonon scattering and
roughness scattering. They can be very important in extremely thin 2D materials which has been
shown in GaAs-based quantum wells as well as graphene devices. Suspended graphene without
surface phonon scattering and roughness scattering[67], [147]. There is no research address this
scattering mechanism in MoS 2 yet, however, freestanding MoS 2 has been shown to have similar
ripples[148] to those in graphene, which may also contribute to scattering and mobility reduction.
The phonon-limited room-temperature mobility calculated by Kaasbjerg et al[139] for MoS 2 is
-410 cm2 /V.s, and similar values are expected for other single-layer TMDs.
In this session, we deposit the high-k dielectric of A12 0 3 or HfO2 on top of the MoS 2 and extract
their mobilities at different tempratures. These mobilities are compared with the mobility without
high-k environment to investigate the scattering mechanism in CVD grown MoS 2 devices.
The sample which has been measured the mobility is cut into several pieces and they will be
covered by A12 0 3 or HfO2 deposited by ALD method. The A12 0 3 is deposited at 150 *Cwith the
thickness of 20nm and the HfO2 is deposited at 250 *Cwith thickness of 25nm. The temperature is
optimized to get both wetting of dielectric on MoS 2 as well as high quality of the dielectric layer.
After deposition, the devices are measured using the same four probe measurement method in
session 3.3.3. The temperature dependent mobility of MoS 2 covered with A12 0 3 and HfO2 are
shown in Figure 43 and Figure 44, respectively. The mobility of two different MoS 2 devices
covered with A12 0 3 (Figure 42) is about 8 cm2/V.s at room temperature. At high temperatures, the
mobility decreases because of the stronger phonon scattering. The mobility is about 3cm2 /V.s at
360K. When the temperature decreases from 250K to 77K, the mobility decreases from 8cm 2/V.s to
3cm 2/V.s.
70
1
(087
-
Q65
3
50
100
150
200
250
300
350
400
T (K)
Figure 43. Mobility of two MoS 2 devices on SiO 2 covered with A12 0
3
measured using 4 probe
methode.
Five devices covered with HfO2 are measured at different temperatures and plotted using lines
with different color in Figure 44. The mobilities are averaged between these devices. The mobility
of MoS 2 covered with HfO2 is about 18 cm 2 /N.sat room temperature. It has similar trend with MoS 2
covered with A12 0 3 as a function of temperature. At higher temperature, the mobility decreases
because of the stronger phonon scattering. The mobility is about 8cm 2 /N.s at 360K. When the
temperature decreases from 250K to 77K, the mobility decreases from 20cm 2 /N.s to 10cm 2 /N.s.
71
19-1-2-6hail21
19-1-2-6haI11
19-1-3-3hall21V19-1-3-6hail 11
+- 19-1-3-6hall12
-U-
40-
-,A
'30
10--
0
50
100
150
200
250
300 30
400
T (K)
Figure 44. Mobility of five different MoS 2 devices on SiO 2 covered with HfO2 measured using 4
probe method.
The peak mobility in different environments has been plotted in Figure 45. The dielectric
constant here is the average constant of the top and bottom dielectric. The dielectric constant for air,
SiO 2 , A12 0 3 and HfO2 are 1, 4, 8 and 22, respectively. We can see that the higher the dielectric
constant the higher the mobility. The ratio of the mobility at 77 K and 250 K is also shown in
Figure 45 (blue line). The improvements of mobility before and after dielectric of HfO2 are
170times at 77K, 10 times at 250k, demonstrating the high-k dielectric suppress the scattering that
dominates at low temperature. This may be charged impurity scattering or electron-electron
interaction and more comprehensive study is needed to elucidate this issue.
72
20- ---
peak mobility
rmbility ratio
0
15
0.4
a
10-
I
1=
0.2
5-
0I~1
0
I
5
.
k
,
10
L.0.0
,
15
average k
Figure 45. Mobility change in MoS
2
devices as a function of
the average dielectric constant of
the environment.
The high charged impurities density in MoS 2 FETs can also be detected in the relationship of
mobility with the carrier density. The mobility with carrier density is plotted in Figure 46 both for
sample on SiO 2 without (Figure 46 (a)) and with (Figure 46 (b)) HfO2 dielectric. It is easy to note
that in both structures the mobility increases with the carrier density. For conventional
semiconductors, the mobility will decrease when the carrier concentration or the doping level
increases because the dopant will be the scattering center. However, for MoS 2 system, the carriers
are induced by electrostatic doping, which does not generate ionized impurity scattering. In addition,
the increased carrier concentration helps to screen the charged impurities and defects present in the
channel material and/or dielectric layers, which increases the mobility.
73
1.6AI
(a)
(b)
.au.
25
U
1.2-
.-. n . a
IO
U
"
U
0.8-
20-
".
15-
U
.
U
".
10.
.
au .
IN
m
.
0.450.0
"00
0.00E+000
1.00E+012
2.00E+012
OEO
01
0.0
3.00E4012
5.0x10" 1.0x10 12 1.5x1012 20x10 12 2.5x1012
U.U-2
Camer DBnit
(ai2)
Figure 46. The relationship of mobility on carrier density. (a)six-Hall bar structure for MoS 2 on a
SiO 2 substrate, and (b) on SiO 2 and covered with HfO2.
However, for a given carrier density level, the mobility with and without HfO2 can be 20 times
different, which further confirms the suppression of Coulomb scattering at the high-k dielectric
environment. The carrier concentrations for different devices in Figure 41, Figure 43 and Figure 44
are also plotted below in Figure 47 and Figure 48. In all these devices, the carrier concentration
change linearly with the back gate bias, characteristic of an accumulation layer. Figure 48 shows
that even if all the devices covered with HfO 2 have similar carrier density distribution, they can
have different mobility, which should be caused by material inhomogeneity.
(a)
4x10
(b)
12
4x10
2
*
*
cW,15-21-8-LALL
3x10 12
19-1-1-21
19-1-1-12
.
..
*
..
U
2x10
12
a.03l
NEWU
*
ga.
1X1012
1x10
SEEE
nxO'
0
20
40
60
80
0
10
20
Vsub (V)
Vsub (V)
74
30
Figure 47. The carrier density of MoS 2 (a) on SiO 2 substrate (b) on SiO2 substrate covered with
A12 0 3.
4x10'2
.
U
S
3x10
I
I
2
.
A
V
2x10'2
1
19-1-2-11
19-1-2-21
19-1-3-11
19-1-3-12
19-1-3-21
,
ia
-
.
,
A
A
.U
"
*A
Sam
.'-IE
U
1x1012
() I
20 b
V10
40
vsub v)
Figure 48. . The carrier density of MoS 2 on SiO 2 substrate covered with HfO 2.
It is to be noted that the calculation of the carrier concentration is not independent with mobility,
since we use n
=
ue
, thus there may be some error here. Comprehensive study with independent
measurement of mobility and carrier concentration in Hall effect measurement is highly desirable
for MoS 2 to elucidate these issues. However, the carrier density here is able to demonstrate the
mobility increase dose not come from the extra charge introduced by the deposition of dielectric.
3.3.5 Top-gated DC and RF Devices.
Dual gate DC and RF devices arrays were also fabricated on CVD grown large area single layer
MoS 2 , as shown in Figure 49. The fabrication process for large scale single layer MoS 2 grown by
CVD method is similar to the fabrication process for flakes with an extra step of mesa isolation.
After depositing the metal contact, device isolation is achieved by 02 plasma etching at pressure of
75
1.4 x 10-4 mTorr. The top gate dielectric consisting of 30 nm HfO 2 was then deposited by ALD at
170 *C. To fabricate discrete transistors, the top gate was then formed by depositing 50 nm Pd.
Figure 49. Optical micrograph of the fabricated chip showing arrays of RF transistors, currents
sources, and 1-bit and 2-bit analog-to-digital converters (ADC).
Figure 50 shows the output characteristics of the fabricated single-layer MoS 2 FET with LG=1
pm. At the low Vds region, the current is not perfectly linear with the voltage, due to a small
Schottky barrier between MoS 2 and the metal contacts. The device shows current saturation, which
is due to the pinch-off at the drain side at high VDS. The starting voltage is indicated by the dashed
line in Figure 50. The threshold in this device is -2 V. Thus, the saturation voltage Vsat closely
matches the gate overdrive VGs-Vt. This important device characteristic has been missing in
previous reports of MoS 2 FETs[106], [127].
76
a
18
16
16
VTG=
,
14. -
V
TG=
VTrG
$O12
*
VTG
10
*
VTG
V
8.
6
4
2
0
0
1
2
3
4
5
VDS (V)
Figure 50. Output characteristics of an FET fabricated on CVD single-layer MoS 2 . The device
shows excellent current saturation. LG I [Im
The maximum on-state current reaches 16 pA/pm at VDs=5 V and VTG= 2 V, while the threshold
voltage is -2 V as shown in Figure 51, indicating that the material is unintentionally n-type doped
during the growth and fabrication process. The peak transconductance is around 3 pS/pm. Due to a
larger bandgap than Si and excellent electrostatic control of 2D electronics, the device exhibits a
remarkable on/off current ratio exceeding 108, giving the material great potential for ultra-low
power applications such as driving circuits for flat panel display, where the incumbent materials organics and amorphous Si- have mobilities below 1 cm 2/V.s due to intrinsic disorder and hoppingbased transport mechanism. In contrast, mobility of single-layer CVD MoS 2 is extracted to be
above 50 cm 2 /V.s (shown in next chapter). Such mobility enables MoS 2 to operate even at GHz
frequency.
77
0' -5
-4
-
- -
-3
-2
VTG
-1
0
-7
1
-6
-5
-4
M~~
Figure 51 Transfer characteristics of the MoS 2 FET with
-3
-2 -1
VTG(V)
LG=1
0
1
2
pm. (a) linear scale (b) log scale.
The on/off current ratio of the device exceeds 108, making these devices ideal for ultra-low power
applications. The subthreshold swing is 110 mV/dec.
Figure 52 shows the first characterization of the RF performance of MoS 2 FETs. This device
with LG=300 nm shows anfT of 900 MHz andfmax of 1 GHz, giving MoS
2
the potential to enable
high performance RF circuits on bendable and foldable substrates, such as flexible RFID tags. This
performance shows great improvement for large area semiconductor RF devices. The frequency in
organic semiconductor and amorphous silicon devices are usually several tens of mega Hertz.
30
o a
o h2 112
o MSG/MAG
o Unilateral Gain
20
10
0.01
0.1
Frequency (GHz)
1.0
Figure 52 First RF characterization of MoS 2 FETs. In this device the LG is 300 nm.f/=900 MHz
andfmax=1 GHz. This measurement is done in vacuum (~10-5 Torr) to reduce hysteresis.
78
Chapter 4. Digital and Mixed-signal Circuits on MoS2
The high on/off ratio and small subthreshold swing demonstrates that MoS2 is very good
material for low power electronics. In this chapter, fully integrated digital and analog circuits based
on MoS2 are constructed both on exfoliated flakes and CVD grown samples to demonstrate its
capability for both complex digital logic and mixed-signal applications
4.1 Logic Circuits Using DFTL Technology on MoS2 Flakes.
Using the DFTL technology described in chapter 3.1, we have built four different integrated
logic circuits entirely assembled on exfoliated bilayer MoS 2 : a logic inverter, a NAND gate, a static
random access memory (SRAM) cell, and a 5-stage ring oscillator, all constructed in DCFL
architecture. For each of the four logic circuits, all active and passive elements are integrated on the
same piece of bilayer MoS 2 . It is found that a supply voltage of Vdd=2 V is suitable for operating
the fabricated circuits. Hence, in this letter, a voltage level close to 2 V represents the logic state 1
while a voltage level close to 0 V represents the logic state 0[59]. These circuits are the first
integrated circuits on TMDs and demonstrating their capabilities of logic applications.
4.1.1 Basic Logic Unit: Inverter and NAND Gatc.
An inverter circuit is a basic logic element that outputs a voltage representing the opposite logiclevel to its input. Our inverter was constructed from an enhancement-mode MoS 2 transistor, and a
depletion-mode resistor that was formed by connecting the gate of a depletion-mode transistor
directly to its source electrode (Figure 53B inset and Figure 53A). Output characteristics (Ids-Vds) of
the E-mode FET and D-mode load for the inverter are shown in Figure 53A. For the E-mode FET,
in the linear regime at small source-drain voltages, the current is proportional to Vds, indicating that
the source and drain electrodes made of Ti/Au metal stack form ohmic contact with MoS 2. The
current saturates at higher drain bias than expected (Vds>Vg-Vt) due to the formation of a depletion
region on the drain side of the gate, as is typical of long channel MOSFETs[149].
The quality of a logic inverter is often evaluated using its voltage transfer curve (Figure 53B),
which is a plot of input vs. output voltage. When the input voltage is Vin=2 V (logic state 1), the Emode MoS 2 FET is much more conductive than the depletion-mode FET, setting the output voltage
below 0.2 V (logic state 0). When Vin is 0 V (logic state 0), the MoS 2 FET is non-conducting and
the output is close to 2 V (logic state 1). The slope of the transition region in the middle provides a
measure of the gain - or the quality of switching. In the circuit of Figure 53(B), a voltage gain close
79
to 5 is achieved. Figure 53(B) also shows the mirror reflection of the Vi,-Vout characteristics, which
highlights the robustness of the inverter towards noise for multi-stage circuits. When multiple
inverter stages are cascaded together, the output signal from the previous stage becomes the input
signal to the next stage. Hence, the shaded area (NML and NMH) represents the noise margin that
can be tolerated by the inverter for multi-stage operations, which is particularly important for the
demonstration of more complex circuits, such as a ring oscillator.
A
20
* E-mode FET
* D-mode Load Resistor
..
Vtg =2.0
B
......
16Inverter
1.
**
E 15
VDD=2-0V
V+
VOH
1.8
.4
Vtg =1-5V
..
NNML
1.2-
*
yin0-
,0
:15
~1
Vtgl.0 V
0.20
Vo
.Vtg =0.5 V
o0
1
1.5
0.5
Drain Voltage Vds[V]
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Vi [V]
Figure 53. Demonstration of an integrated logic inverter on bilayer MoS2. (A) Output
characteristics (Ids-Vds) of the E-mode FET and D-mode load for the inverter. (B) Output voltage
as a function of the input voltage, and its mirror reflection, for a bilayer MoS2 logic inverter. The
shaded area indicates its noise margins (NML and NMH) for logic operation. The gain of the
inverter is close to 5. (Inset) Schematic of the electronic circuit diagram of a logic inverter.
The schematic design and the optical micrograph of a NAND gate circuit fabricated on a sheet of
bilayer MoS 2 are shown in Figure 54 (A,C). The output of the circuit is close to 2 V (logic state 1)
when either or both of the inputs are at logic state 0 (Vin <0.5 V). Under this state, at least one of the
MoS 2 FETs is non-conducting and the output voltage is clamped to the supply voltage Vdd. The
output is at logic state 0 only when both inputs are at logic state 1, so that both MoS 2 FETs are
conducting. In Figure 54C, the output voltage is measured as a function of time while the two input
voltage states vary across all four possible logic combinations (0,0), (0,1), (1,0), and (1,1). This data
80
demonstrates the stable NAND gate functionality of this two-transistor bilayer MoS 2 circuit. A
NAND gate is one of the two basic logic gates (the other being the NOR gate) with universal
functionality. Any other type of logic gates (AND, OR, NOR, XOR, etc.) can then be constructed
through a combination of NAND gates. Hence, this first demonstration of a NAND gate shows that
it is possible to fabricate any kind of digital integrated circuit with MoS 2 thin film layers.
A
,
vd A
Vi
vd d
vn
Vi
10W
Vdd
GND
GN D
Vout
vin e
Vin,BA
Vout
SRAM
SR AM
10 p!m
B
GND
vouLAt
C 1.82-
2
1.8
1.6
1.4
1.6
1.4
>1.2 In: 1
1 Out:0
In: Open
Out: 0
In: 0
Out:1
1.2 In: 0,0:
In: Open
Out: 1
1
0
0.8
0.8
0.6'
0.6
0.4
In: 0,1
Out: 1
Out: 1
in: 1,0
Out: 1
In: 1,1
Out: 0
0.4-
SRAM
0.2
O
NAND Gate
NAND Gate
20
40
60
80
100
0.2120
C.
NAND Gate
20
40
60
80
Time [s]
Time [s]
Figure 54. Demonstration of an integrated NAND logic gate and a static random-access memory
(SRAM) cell on bilayer MoS 2 . (A) Optical micrograph of the NAND gate and the SRAM fabricated
on the same bilayer MoS 2 thin film. . (B) Output voltage of the flip-flop memory cell (SRAM). (C)
Output voltage of the NAND gate.
4.1.2 SRAM.
A flip-flop memory element (SRAM) has also been constructed from a pair of cross-coupled
inverters (Figure 54(A)). This storage cell has two stable states at the output, which are denoted as 0
and 1. The flip-flop cell can be set to logic state 1 by applying a low voltage, i.e. Vjn=0 V (logic
state 0), to the input, while it can be set to logic state 0 by applying a high voltage, i.e. Vm=2 V
81
(logic state 1), to the input. To verify the functionality of this flip-flop cell, a voltage source is
applied to the input to set Vin to 2 V at time T=O s. This drives Vout into logic state 0 (Figure 54(B)).
Then at T=20 s, the switch at Vin is opened and the output of the SRAM cell Vout remains at logic
state 1. At time T=60 s, we apply Vin=0 V at the input to write a logic state 1 into Vout. As the
switch is opened again at T=80 s, the output of the SRAM cell remains in the logic state 1. This
data demonstrates that the flip-flop SRAM circuit fabricated on the bilayer MoS 2 thin film indeed
functions as a stable memory cell.
4.1.3 Ring Oscillator.
Finally, a 5-stage ring oscillator was constructed to assess the high frequency switching
capability of MoS 2 and for evaluating the material's ultimate compatibility with conventional
circuit architecture[64]'[150]'[15 1]. The ring oscillator, which integrates 12 bilayer MoS
2
FETs
together, was realized by cascading five inverter stages in a close loop chain. An extra inverter
stage was used to synthesize the output signal by isolating the oscillator operation from the
measurement setup to prevent the interference between them. The output of the circuit was
connected to either an oscilloscope or a spectrum analyzer for evaluation. The voltage transfer
curve of the test inverter circuit fabricated side-by-side on the same piece of bilayer MoS
2
thin film
(Figure 55(B) and Figure 55(A)) as the ring oscillator, shows that the gain in each inverter stage is
close to 5. For robust ring oscillator performance, it is imperative to have stable operations in all
five inverter stages throughout the oscillation cycles, and its tolerance towards noise can be
determined from the noise margins for both low and high logic levels, i.e. the shaded regions in
Figure 55(B). The positive feedback loop in the ring oscillator results in a statically unstable system,
and the voltage at the output of each inverter stage oscillates as a function of time (Figure 55(C)).
At Vdd= 2 V, the fundamental oscillation frequency is at 1.6 MHz, corresponding to a propagation
delay of rpd =
2nf
= 62.5 ns per stage, where n is the number of stages andf is the fundamental
oscillation frequency. The frequency performance of this ring oscillator, while operating at a much
lower Vdd, is at least an order of magnitude better than the fastest integrated organic semiconductor
ring oscillators[ 152]. It also rivals the speed of ring oscillators constructed from the printed ribbons
of single-crystalline silicon reported in the literature[ 153]. The output voltage swing is measured by
the oscilloscope.
82
The output signal of the ring oscillator can also be measured in terms of its frequency power
spectrum. Figure 55(D) shows the spectrum of the output signal from the ring oscillator as a
function of the drain bias voltage Vdd (Figure 55(D)). The resonance frequency is at 0.52 MHz for
Vdd= 1.15 V. The corresponding fundamental resonance frequency reaches 1.6 MHz as Vdd increases
to 2 V. The improvement in frequency performance with increasing Vdd can be attributed to the
enhancement in the current driving capability of the ring oscillator due to the rise in the drain
current Ids in each individual MoS 2 FET with increasing drain and gate voltages. From left to right,
Vdd= 1.15 V, and 1.2 to 2.0 V in step of 0.1 V. The corresponding fundamental oscillation
frequency increases from 0.52 MHz to 1.6 MHz. The signal peaks measured by the spectrum
analyzer increases from -65 dBm to -46 dBm as Vdd raises from 1.15 V to 2V. This is again a result
of the Ids dependence on Vdd.
GND
5-stage
Ring Oscillator
AA
Vout
Vio
5-stage Ring Oscillator
vout
1
Vu
GND
Inverter
D 0-40
C
1.8
1.6
1.4
>1.21
1.0
.
-
1.6 MHz
-50-
60 0.52 MHz
-70
0-80
0.6
0.4
0.2
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5
1.0
1.5
2.0
2.5
194
06
-.
.
.
.
.
Frequency [MHz]
Time [ps]
Figure 55. A 5-stage ring oscillator based on bilayer MoS 2 . (A) Optical micrograph of the ring
oscillator constructed on a bilayer MoS 2 thin film. (B) Schematic of the electronic circuit of the 5-
83
stage ring oscillator. (C) Output voltage as a function of time for the ring oscillator at
The power spectrum of the output signal as a function of
Vdd=2
V. (D)
Vdd.
4.2 Circuits Based on Large Scale CVD Samples.
After achieving high performance integrated logic circuits on exfoliated flakes, we are able to
demonstrate chip-scale fabrication on single layer CVD grown MoS 2 , as shown in Figure 49. Fully
integrated multi-stage digital and analog circuits based on the single layer CVD grown MoS 2 are
constructed to demonstrate its capability for both complex digital logic and mixed-signal operations.
4.2.1 Integrated Logic Circuits Based on Single-Layer MoS 2
A fully integrated inverter in depletion mode resistor configuration is shown in Figure 56. The
inverter can operate under a wide range of
Vdd
from 0.5 V to 5V, shown in Figure 57(a). The very
low Vdd voltage required for inverter operation indicates that MoS 2 based inverter can be used in
low-power electronics. A high voltage gain, close to 20, can be achieved in these circuits at Vdd=5
V. The input voltage ranges from -5V to OV, because of the negative threshold voltage. This is
mainly come from the fixed charge in the dielectric layer. Further optimization of dielectric layer
or even tune the threshold voltage of MoS 2 by doping is needed to get positive input voltage range.
Figure 56. Optical micrograph of a fully integrated inverter constructed on single-layer MoS2
84
20
(a)
-O-Vde 5 V
-e-V 3 V
5
4-a-
18
16
14
Vdd= 1 V
Va 0.5 V
-i
3V+
>
12
3 10
~
0V0ut
>2
1
00
-5
(b)
6
2
-4
-3
-2
0
-1
-5
-4
-3
-2
-1
Figure 57. (a) Input-output characteristics of the inverter as a function of supply voltage Vdd.
The inverter operates on a wide range of Vdd from 0.5 V to 5V. (b) Voltage gain of the inverter. At
Vdd=5 V, the peak voltage gain of the inverter is close to 20.
A fully integrated NAND gate in depletion mode resistor configuration is shown in Figure 58.
The schematic circuit and the output voltage for this NAND gate are shown in Figure 59 (a) and
(b), respectively. A low voltage of -5 V represents a logic state 0 and a voltage close to 0 V
represents logic state 1. The NAND get function correctly for four different input states: (1,0),
(0,0), (0,1), and (1,1).
85
0
NAND Gate
GND
V1in.
B
10 pim
Figure 58. Optical micrograph of a fully integrated NAND gate constructed on single-layer
MoS2.
(a)
(b) o
Vdd
-1
Vout
VIn,A
-2
j
,
Vin,Bo--
In: 1,0
In: 0,0
In: 0,1
In: 1,1
Out: I
Out: I
Out: I
Out: 0
NAND Gate
~
0
20
40
60
Time (s)
--
Figure 59. (a) Schematic circuit for the NAND gate. (c) Output voltage of the NAND gate
86
80
80
(b) Schematic circuit for the NAND gate. (b) Output voltage of the NAND gate for four different
input states: (1,0), (0,0), (0,1), and (1,1). A low voltage of -5 V represents a logic state 0 and a
voltage close to 0 V represents logic state 1.
4.2.2 Integrated Mix-Signal Circuits Based on Single-Layer MoS 2
Finally, to demonstrate the mixed-signal capability of MoS 2 based circuits, an 1-bit analog-todigital converter (ADC) is constructed, as shown in Figure 60. The ADC is essentially a voltage
comparator based on a differential amplifier with matched long-tail pair configuration, which
requires well-matched characteristics in the transistors involved. The schematic diagram of the
ADC is shown in Figure 61(a). The resistor value in Figure 61(a) can be controlled by the gate.
Using the differential gain of the long-tail pair, the ADC converts a 1 kHz sinusoidal signal to a
square wave, which is essentially a digital output with two logic levels. Any part of the input signal
above (or below) the reference voltage Vref is represented by logic level 0 (or 1) is the output signal
V 1-V2 (Figure 11(c)). The successful operation of the ADC also demonstrates the excellent
matching characteristics of the fabricated MoS 2 transistors, which is for realizing the differential
amplifier.
Vd d
V1
V2
Vref
Vi
GN D
Figure 60. Optical micrograph of a fully integrated 1-bit ADC constructed on single-layer MoS 2
87
Vdd
(b)(n
OV1 V202
0
Time (mS)
Figure 61. (a) Schematic circuit for the ADC. (b) AC coupled oscilloscope reading of the input
and output signals (1kHz) of the ADC
88
Chapter 5. Graphene as Electrodes for Flexible Electronics.
For the ultimate transparent flexible electronics, all parts of the device should come from 2D
materials. One potential structure for such a flexible electronic system would be made by MoS 2 as
the active channel, BN as the gate dielectric and graphene as the transparent electrode, all of which
will be integrated on a flexible substrate such as Polyethylene naphthalate (PEN). In this chapter,
CVD grown large area single layer graphene is integrated in MoS 2 devices and circuits as metal
electrodes and interconnect.
5.1 Fabrication of Devices and Circuits
The fabrication of MoS 2 starts by patterning a single layer of CVD-grown MoS 2 into isolated
channels using PMMA as the etch mask. After that, the sample is coated with MMA(6%
concentration in ethyl lactate), baked at180 'C for 7 min, then coated with PMMA (2%
concentration in anisole), baked at 180 'C for 7 min, and exposed using an electron-beam
lithography system. A low temperature ALD step plus liftoff form the dielectric layer as well as
etch stop layer. The temperature is controlled to be below the glass transition temperature of
PMMA/MMA stack. Then graphene is transferred on to the wafer. Then EBL and RIE etch are used
to define the source, drain and gate, respectively. Finally, the PMMA is cleaned by acetone. The
process flow is shown in Figure 62 and the corresponding image of a Hall bar structure at step 2,3,4
is shown in Figure 63.
89
Top
view
MMA/PMMA stack, EBL
Side
View
Low-T ALD, lift off
Pattern the CVD MoS2
EBL, 02 RIE etch
Pattern Graphen
Figure 62. Fabrication process of devices or circuits using graphene as ohmic contacts.
90
..........
Figure 63. Optical Microscope image of different steps along fabrication process, using Hall bar
structure as illustration. (a) The Optical Microscope image after ALD lift off, (b) The Optical
Microscope image after transfer of graphene. (c) The Optical Microscope image of the completed
device.
In Figure 63(a), the blue part is the A12O3 by ALD, the purple part is the CVD grown single layer
MoS 2 , the red part is the SiO 2 substrate. The ALD dielectric after lift-off has a well defined shape.
Figure 63(b) shows the optical image right after the transfer of graphene. Figure 63(c) shows a
finished dual gated six Hall bar structure. The corresponding schematic diagram is shown in Figure
64.
91
MoS 2
ALD A1203
Graphene
Al20 3/Grphene
Figure 64. The schematic for the Hall bar structure micrographed in Figure 63 (c).
The ALD A12 0 3 layer act as both an etch stop layer, and as the top gate dielectric layer. The
graphene is used as source, drain and gate electrode. As the transistor is not self-aligned, there is
some space between the source and drain graphene and gate graphene, resulting in ungated access
regions that will increase the total resistance. The graphene electrodes are connected to large metal
pads for measurement convenience, however these are not necessary in the final system.
5.2 Device
The fabricated graphene-MoS 2 transistor is shown in the optical micrograph of Figure 65(a). The
single layer graphene and single layer MoS 2 can be clearly shown through the optical contrast
because of the interference effect between the MoS 2 and the SiO 2/Si substrate underneath. The
corresponding AFM image is shown in Figure 65(b), where small graphene winkles can be
perceived. The height of the ALD layer can be measured at the edge of the A12 0 3 layer. Further
process optimization is needed to ensure a clean surface.
92
(c)
MoS 2
ALD A12 0 3
Graphene
A120 3/Grphene
Figure 65.The top gated MoS 2 -graphene transistor.
The graphene-MoS2 FETs are usually several micrometers in size ranging from 1 pm to 30 pm.
5.2.1 Back Gate Performance
The back-gated output performance of the graphene-MoS 2 transistor is shown in Figure 66. This
device has a channel length of 15 pm. Figure 66(a) shows that the current is linear with source drain
voltage, indicating the good contact between graphene and MoS 2 . A detailed low-field
93
measurement is shown in Figure 66(b). We can see that the graphene-MoS 2 devices are ohmic for
different gate voltages. The current at higher Vda values in Figure 66(a) shows clear saturation.
(a) 3 5. -
(b)
-'*'-
3.0
I
2.0
=
1.5
0002
-,0
2.5-
E
vsub from -1OV to SOV
with step of 1OV
0.003
E
Vsub from -1OVto6OV
with step of 10V
0001
0000
-0.001
1.0-
-0002-
0.5-
-0003,
0.0
-0004
-"-"
25
1
0
,
-0.010
.
.
0.000
-0.005
Vds (V)
0.005
0 010
V
Figure 66. The output i-v properties of graphene -MoS2 transistor.
The transfer characteristics of the graphene-MoS 2 transistor in Figure 66 are shown in Figure 67.
From (a), the threshold voltage is around OV, which is consistent with other gate metals such as In,
Ag, Ti, Mo. The current shows no saturation with the source drain voltage up to a bias of 7V. The
high current level of this device is because the low contact resistance between graphene and MoS
2
and the ALD high-k dielectric layer on top of MoS 2. Figure 67(b) shows the transfer characteristics
in log scale, the on/off ratio of this device is larger than 106.
--6
--
E
Vd = 7V
Vd=1V
Vd=0.5 V
10
.
.1
E
4
1E-3
-
32 2
Vd=7V
--
1E-5
Vd=1V
c
Vd=0.5 V
0
40
-60
-40
-20
0
20
40
60
1E-7
-100
80
Vsub (V)
,
,
-50
,
0
,
Vsub (V)
94
50
100
Figure 67. The transfer characteristics of a typical graphene-MoS 2 FET in (a) linear, and (b)
semilog scales.
The mobility calculated from Figure 67(a) shown in Figure 68. The mobility of MoS 2 can be up
to 23 cm 2/V.s. It should be noted that all the top gates are grounded during the measurement to
avoid the coupling between the top gate and back gate.
25
20
Cn
15
E
10
0
5
E
0
-80
-40
40
0
80
Vsub (V)
Figure 68. Field effect mobility calculated from Figure 67 (a).
5.2.2 Top Gate Performance.
The top gated performance of the graphene-MoS 2 transistors is plotted in Figure 69. The output
performance shows a linear current behavior at low drain bias voltages, and current saturation at
higher biases. The onset of source drain voltage of the current saturation follows the relationship of
pinch off saturation Vd= Vtg- Vt. The output performance is shown in Figure 69 (b). The current
seems to saturate at the high gate voltage region. This is because the device is non-self aligned and
the access resistance limits the maximum current level.
95
(a)
(b)
0.6.
0.
0.
0.0
0.5
1.5
1.0
Vds
2.0
-5
-4
-3
-2
-1
Vtg (V)
(V)
Figure 69. (a) The output and (b) transfer characteristics of graphene-MoS
2
FETs.
5.2.3 Temperature Dependent Measurements of Graphene/MoS2 Junctions.
To investigate the contact of graphene and MoS 2 , temperature-dependent measurements similar
to the ones described in chapter 3.2.2 are conducted on the graphene-MoS 2 FET. The source drain
current as a function of temperature are shown in Figure 70. From (a), the hysteresis effect is
greatly suppressed at lower temperature. The difference of threshold voltage between different
sweeping direction at 300K is about 30 V. However, at lower temperature, the effects is
unnoticeable as shown in Figure 70.
10
1
0.1
0.01
I E-3
V
V
1E-4
1E-5
I E-6
1E-7
40
Vsub (V)
60
Vsub (V)
Figure 70. Temperature dependent measurement of graphene-MoS
96
2
FET.
100
The temperature from Figure 70 is calculated and plotted into In
- -
T
as shown in Figure
71(a). Similar to other metals described in session 3.2.2, the plot shows two regions with different
energy barrier, the high temperature is related to the Schottky barrier of thermal emission, which is
used to extract the Schottky barrier. However, the mechanism of low temperature from 80K to
)-
250K is unclear and need further research. The In
plot follows the linear relationship for
different back gate voltages. The Schottky barrier heights (SHE) calculated from the slope are
plotted in Figure 71(b). The barrier at the threshold voltage is about 30 meV. The SHE can be tuned
from 0 V up to 270 meV. This is because both the Fermi level energy of graphene and MoS 2 can be
tuned by the gate voltage at the same time.
-22-
300
Vbg=OV
-24 -
-26 -28 -30-
''
C
-32 -34 -
250
---Vbg= 10V_
--15
Vbg=20V
-- 25
Vbg=30V ~
-.- 35
~
- Vbg=40V - _45
-Vbg=50V---- 55
-0
-+-Vbg=60V-
200
E 150
I
S100
50
-360
4
6
8
10
12
14
16
18
Vbg (V)
1000K/T
Figure 71. SHB of the MoS 2-graphene contact.
5.3 Integrated Circuits.
An integrated inverter and NAND gate were also demonstrated for this graphene-MoS 2
technology. An optical micrograph of the NAND gate is shown in Figure 72.
97
MoS2
ALD A12 0 3
Graphene
Vdd
"in.A
9"
8
A1 20 3 /Grphene
10
NAND Gate
Figure 72. The optical image and the schematic diagram of a NAND gate of MoS2 circuits with
Graphene as the metal contacts.
The output characteristics of a fully integrated inverter in depletion mode resistor configuration
are shown in Figure 73. A low voltage of -4 V represents a logic state 0 and a voltage close to 0 V
represents logic state 1. Similar with the inverters for Ti/Au contacts, optimization of dielectric and
the doping control are desirable to get positive threshold voltage and get positive input voltage. The
inverter is able to operate under
Vdd
of 3V, as shown in Figure 73(a). The high voltage gain is close
to 12 (Figure 73(b)).).
(a)
'.0-
(b)12
2.5102.0
inverter
8-
V+
out
> 1.0-
4
0.5-
20
0.0
0
-4
-3
-2
-1
0
-4
-3
-2
-1
0
Mn (V)
Mn (V)
Figure 73. (a) Input-output characteristics of the inverter at supply voltage Vdd=3V. (b) Voltage
gain of the inverter.
98
Chapter 6 Conclusions and Future Plans
6.1 Conclusion.
This thesis focuses on the development of the device technology for MoS 2 devices. Both
depletion mode and enhancement mode transistors are fabricated. Their threshold voltage is
controlled by engineering the respective gate metal work function. An MoS
2
transistor with low
work function Al gate leads to a depletion mode FET while an MoS 2 transistor with high work
function Pd gate gives an enhancement mode FET. Both types of transistors exhibit excellent
current saturation behavior, a device feature critical for constructing both digital and analog circuits.
These MoS 2 FETs demonstrates high on/off current ratio exceeding 107. Their on-state current
density and transconductance are an order of magnitude higher than the best single-layer MoS 2 FET
reported in the literature until now. The field effect mobility in these devices is above 50 cm 2/V.s,
which is enhanced by the screening of Coulomb scattering due to the high-k dielectric environment.
We have also systematically studied the device technology for CVD large area single layer MoS 2
samples: contact metal, mobility measurement and dielectric integration. The transport properties
with different low work function metals have been compared carefully. Ag and In metals show low
contact resistance with MoS 2, better than the commonly used Ti metal. For high work function
metals, temperature dependent measurement was performed to extract the Schottky barrier height
between the metal and MoS 2 . Then, four probe measurements were conducted to extract the
accurate field effect mobility of MoS 2 on SiO 2 without dielectric layer, or on SiO 2 covered by A120 3
and on SiO 2 covered by HfO2. Mobility enhancement can be observed for both A12 0 3 and HfO 2 ,
because of the screening of Coulomb scattering in the high-k dielectric environment. Then top gated
DC and RF devices are fabricated on CVD grown single layer MoS 2 , and they demonstrate
excellent characteristics such as record mobility for CVD MoS 2 , ultra-high on/off current ratio,
record current density and GHz RF performance.
Based on the demonstrated device technology, we fabricated 4 different logical circuits on
exfoliated MoS
2
flakes: an inverter, an NAND gate, a static random-access memory, and a 5-stage
ring oscillator circuit. The ring oscillator can operate at frequency of 1.6 MHz. Then wafer scale
fully integrated both digital and analogue circuits were demonstrated on CVD grown large scale
single layer MoS 2 , showing the remarkable ability of this single-molecular-layer thick material for
99
mixed-signal applications, offering scalable new materials that can combine silicon-like performance
with the mechanical flexibility and integration versatility of organic semiconductors.
Finally, the integration of CVD single layer graphene on CVD single layer MoS2 as metal
contacts has been demonstrated for the first time. The fabricated graphene-MoS 2 FETs demonstrates
high on/off current ratio exceeding 107, high on-state current density. The intrinsic Schottky barrier
height between graphene and MoS 2 is 30meV. The field effect mobility in these devices is above 23
cm 2/V.s. Then logic circuits are demonstrated, showing the scalability of this technology.
To summary, this MSc thesis has shown the remarkable capability of MoS 2 for digital, analogue
and mixed signal applications, offering excellent new options for flexible electronics
6.2 Future Work.
In this section, we describe some future research efforts that are needed in order to further
advance our device and circuits technology based on MoS 2 and other TMDs such as MoSe 2, WS 2
and WSe 2.
6.2.1 Further Optimization of the Device Technology.
Though In and Ag form better ohmic contacts to MoS 2 than Ti, the contact resistance is still
higher than that of graphene-metal contact. Annealing or new contact structures are necessary to
reduce the contact resistance.
6.2.2 Doping of TMDs.
One of the important characteristics of semiconductor is that the conductive properties of a
semiconductor can be modified by controlled addition of impurities. By controlling the doping level,
we can reduce the contact resistances, achieve p-n junction and even complementary metal-oxidesemiconductor field effect transistor, however it is still not clear what the best doping approach for
TMDs is.
6.2.3 Compact Modeling of TMD FET.
To boost the development of electronic circuits based on 2D-materials, modeling of the electrical
characteristics is essential to optimize the device design, project the performance and design
complex circuits. Some models have been developed to explore the performance limits of
monolayer TMD transistors assuming ballistic transport. However, the behavior of state-of-the art
devices is far from ballistic and flexible electronics is based on mainly long channel devices with
100
lengths well above the carrier mean free path. Thus, a compact model is needed for device and
circuit design with a technology node in the micrometer level scale. This should be implemented in
Verilog-A for use in complex circuit simulations
6.2.4 Integration of 2D Circuits on Flexible Substrates.
The 2D material systems and devices described in this thesis are excellent candidates for flexible
electronics. An all-2D system with graphene as electrode and interconnect, and TMD's as the
semiconductor channel will be the ultimate structure for flexible electronics. It is expected that the
full integration on flexible substrate will be demonstrated in the near future.
101
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