18-447
Computer Architecture
Lecture 7: Microprogrammed Microarchitectures
Prof. Onur Mutlu
Carnegie Mellon University
Spring 2013, 1/30/2013
Homework 2
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Homework 2 out
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Due February 11
LC-3b microcode
ISA concepts, ISA vs. microarchitecture, microcoded machines
2
Reminder: Lab Assignment 1
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Due this Friday (Feb 1), at the end of Friday lab
A functional C-level simulator for a subset of the MIPS ISA
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Study the MIPS ISA Tutorial
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Go to the Lab Sessions, especially if you need help
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3
Lookahead: Lab Assignment 2
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Lab Assignment 1.5
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q
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Verilog practice
Not to be turned in
Lab Assignment 2
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Due Feb 15
Single-cycle MIPS implementation in Verilog
All labs are individual assignments
No collaboration; please respect the honor code
4
Lookahead: Extra Credit for Lab Assignment 2
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Complete your normal (single-cycle) implementation first, and
get it checked off in lab.
Then, implement the MIPS core using a microcoded approach
similar to what we will discuss in class.
We are not specifying any particular details of the microcode
format or the microarchitecture; you can be creative.
For the extra credit, the microcoded implementation should
execute the same programs that your ordinary
implementation does, and you should demo it by the normal
lab deadline.
You will get partial credit for the extra credit
Document what you have done and demonstrate well
5
Readings for Next Lecture
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Pipelining
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P&H Chapter 4.5-4.8
Pipelined LC-3b Microarchitecture
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http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?
media=18447-lc3b-pipelining.pdf
6
Today’s Agenda
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Finish the Microprogrammed LC-3b Design
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Do some microprogramming
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Start pipelining
7
Review: Last Lecture
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Finished single-cycle microarchitectures
Microarchitecture design principles
Basic performance evaluation (execution time equation)
What does it mean to design for the common case (or
bread and butter design)?
q
n
n
If memory takes 90% of execution time …
How does the single cycle microarchitecture make “critical
path design” difficult?
Remember the performance equation that consists of three
components… How can you improve each component in a
multi-cycle microarchitecture?
8
Review: Microarchitecture Design Principles
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Critical path design
q
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Find the maximum combinational logic delay and decrease it
Bread and butter (common case) design
q
Spend time and resources on where it matters
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q
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i.e., improve what the machine is really designed to do
Common case vs. uncommon case
Balanced design
q
q
Balance instruction/data flow through hardware components
Balance the hardware needed to accomplish the work
9
Review: Multi-Cycle Microarchitectures
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Goal: Let each instruction take (close to) only as much time
it really needs
Idea
q
q
Determine clock cycle time independently of instruction
processing time
Each instruction takes as many clock cycles as it needs to take
n
n
Multiple state transitions per instruction
The states followed by each instruction is different
10
Quick Review: A Microprogrammed
Multi-Cycle Microarchitecture
11
Review: The Instruction Processing Cycle
q
q
q
q
q
q
Fetch
Decode
Evaluate Address
Fetch Operands
Execute
Store Result
12
Review: A Basic Multi-Cycle Microarchitecture
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Instruction processing cycle divided into “states”
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A multi-cycle microarchitecture sequences from state to
state to process an instruction
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A stage in the instruction processing cycle can take multiple states
The behavior of the machine in a state is completely determined by
control signals in that state
The behavior of the entire processor is specified fully by a
finite state machine
In a state (clock cycle), control signals control
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How the datapath should process the data
How to generate the control signals for the next clock cycle
13
Review: Microprogrammed Control Terminology
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Control signals associated with the current state
q
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Act of transitioning from one state to another
q
q
n
Determining the next state and the microinstruction for the
next state
Microsequencing
Control store stores control signals for every possible state
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Microinstruction
Store for microinstructions for the entire FSM
Microsequencer determines which set of control signals will
be used in the next clock cycle (i.e. next state)
14
Review: A Simple LC-3b Control and Datapath
15
Review: An LC-3b State Machine
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Patt and Patel, App C, Figure C.2
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Each state must be uniquely specified
q
n
31 distinct states in this LC-3b state machine
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Done by means of state variables
Encoded with 6 state variables
Examples
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q
State 18,19 correspond to the beginning of the instruction
processing cycle
Fetch phase: state 18, 19 à state 33 à state 35
Decode phase: state 32
16
Review: LC-3b State Machine: Some Questions
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How many cycles does the fastest instruction take?
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How many cycles does the slowest instruction take?
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Why does the BR take as long as it takes in the FSM?
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What determines the clock cycle?
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Is this a Mealy machine or a Moore machine?
17
LC-3b Datapath
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Patt and Patel, App C, Figure C.3
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Single-bus datapath design
q
q
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At any point only one value can be “gated” on the bus (i.e.,
can be driving the bus)
Advantage: Low hardware cost: one bus
Disadvantage: Reduced concurrency – if instruction needs the
bus twice for two different things, these need to happen in
different states
Control signals (26 of them) determine what happens in the
datapath in one clock cycle
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Patt and Patel, App C, Table C.1
18
GateMARMUX
GatePC
16
16
16
LD.PC
MARMUX
16
2
16
PC
+2
PCMUX
REG
FILE
16
+
SR2
ZEXT &
LSHF1
[7:0]
LSHF1
ADDR1MUX
16
16
[10:0]
SR1
OUT
16
16
3
DR
SR1
16
16
16
0
SEXT
[4:0]
SR2
OUT
16
16
[5:0]
3
2
ADDR2MUX
[8:0]
3
LD.REG
16
SR2MUX
SEXT
SEXT
CONTROL
SEXT
R
LD.IR
IR
2
N Z P
LD.CC
16
B
ALUK
LOGIC
6
A
ALU
SHF
16
16
GateALU
IR[5:0]
GateSHF
16
GateMDR
MAR
L D .M AR
DATA.SIZE
[0]
LOGIC
R.W
WE
LOGIC
MAR[0]
MIO.EN
DATA.
SIZE
16
MEMORY
L D .MDR
MDR
MIO.EN
16
LOGIC
ADDR. CTL.
LOGIC
2
MEM.EN
R
16
DATA.SIZE
MAR[0]
INMUX
INPUT
OUTPUT
KBDR
WE1 WE0
DDR
KBSR
DSR
C.4. THE CONTROL STRUCTURE
11
IR[11:9]
IR[11:9]
DR
SR1
111
IR[8:6]
DRMUX
SR1MUX
(b)
(a)
IR[11:9]
N
Z
P
Logic
BEN
(c)
Figure C.6: Additional logic required to provide control signals
LC-3b Datapath: Some Questions
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How does instruction fetch happen in this datapath
according to the state machine?
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What is the difference between gating and loading?
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Is this the smallest hardware you can design?
22
LC-3b Microprogrammed Control Structure
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Patt and Patel, App C, Figure C.4
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Three components:
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Microinstruction: control signals that control the datapath
(26 of them) and determine the next state (9 of them)
Each microinstruction is stored in a unique location in the
control store (a special memory structure)
Unique location: address of the state corresponding to the
microinstruction
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Microinstruction, control store, microsequencer
Remember each state corresponds to one microinstruction
Microsequencer determines the address of the next
microinstruction (i.e., next state)
23
R
IR[15:11]
BEN
Microsequencer
6
Control Store
2 6 x 35
35
Microinstruction
9
(J, COND, IRD)
26
10APPENDIX C. THE MICROARCHITECTURE OF THE LC-3B, BASIC MACHINE
COND1
BEN
R
J[4]
J[3]
J[2]
IR[11]
Ready
Branch
J[5]
COND0
J[1]
0,0,IR[15:12]
6
IRD
6
Address of Next State
Figure C.5: The microsequencer of the LC-3b base machine
Addr.
Mode
J[0]
J
d
Co
n
IR
D
LD
.M
LD AR
.M
LD DR
.IR
LD
.BE
LD N
.RE
LD G
.CC
LD
.PC
Ga
teP
Ga C
teM
Ga DR
teA
Ga LU
teM
Ga ARM
teS
HF UX
PC
MU
X
DR
MU
SR X
1M
AD UX
DR
1M
UX
AD
DR
2M
UX
MA
RM
UX
AL
UK
MI
O.
E
R.W N
DA
TA
LS .SIZ
HF E
1
000000 (State 0)
000001 (State 1)
000010 (State 2)
000011 (State 3)
000100 (State 4)
000101 (State 5)
000110 (State 6)
000111 (State 7)
001000 (State 8)
001001 (State 9)
001010 (State 10)
001011 (State 11)
001100 (State 12)
001101 (State 13)
001110 (State 14)
001111 (State 15)
010000 (State 16)
010001 (State 17)
010010 (State 18)
010011 (State 19)
010100 (State 20)
010101 (State 21)
010110 (State 22)
010111 (State 23)
011000 (State 24)
011001 (State 25)
011010 (State 26)
011011 (State 27)
011100 (State 28)
011101 (State 29)
011110 (State 30)
011111 (State 31)
100000 (State 32)
100001 (State 33)
100010 (State 34)
100011 (State 35)
100100 (State 36)
100101 (State 37)
100110 (State 38)
100111 (State 39)
101000 (State 40)
101001 (State 41)
101010 (State 42)
101011 (State 43)
101100 (State 44)
101101 (State 45)
101110 (State 46)
101111 (State 47)
110000 (State 48)
110001 (State 49)
110010 (State 50)
110011 (State 51)
110100 (State 52)
110101 (State 53)
110110 (State 54)
110111 (State 55)
111000 (State 56)
111001 (State 57)
111010 (State 58)
111011 (State 59)
111100 (State 60)
111101 (State 61)
111110 (State 62)
111111 (State 63)
LC-3b Microsequencer
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Patt and Patel, App C, Figure C.5
The purpose of the microsequencer is to determine the
address of the next microinstruction (i.e., next state)
Next address depends on 9 control signals
27
10APPENDIX C. THE MICROARCHITECTURE OF THE LC-3B, BASIC MACHINE
COND1
BEN
R
J[4]
J[3]
J[2]
IR[11]
Ready
Branch
J[5]
COND0
J[1]
0,0,IR[15:12]
6
IRD
6
Address of Next State
Figure C.5: The microsequencer of the LC-3b base machine
Addr.
Mode
J[0]
The Microsequencer: Some Questions
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When is the IRD signal asserted?
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What happens if an illegal instruction is decoded?
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What are condition (COND) bits for?
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How is variable latency memory handled?
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How do you do the state encoding?
q
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Minimize number of state variables
Start with the 16-way branch
Then determine constraint tables and states dependent on COND
29
An Exercise in
Microprogramming
30
Handouts
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7 pages of Microprogrammed LC-3b design
http://www.ece.cmu.edu/~ece447/s13/doku.php?
id=manuals
http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?
media=lc3b-figures.pdf
31
A Simple LC-3b Control and Datapath
32
18, 19
MAR <! PC
PC <! PC + 2
33
MDR <! M
R
R
35
IR <! MDR
32
RTI
To 8
1011
BEN<!IR[11] & N + IR[10] & Z + IR[9] & P
To 11
1010
[IR[15:12]]
ADD
To 10
BR
AND
DR<!SR1+OP2*
set CC
1
0
XOR
JMP
TRAP
To 18
DR<!SR1&OP2*
set CC
[BEN]
JSR
SHF
LEA
LDB
STW
LDW
STB
1
PC<!PC+LSHF(off9,1)
12
DR<!SR1 XOR OP2*
set CC
15
4
MAR<!LSHF(ZEXT[IR[7:0]],1)
To 18
[IR[11]]
0
R
To 18
PC<!BaseR
To 18
MDR<!M[MAR]
R7<!PC
22
5
9
To 18
0
1
20
28
R7<!PC
PC<!BaseR
R
21
30
PC<!MDR
To 18
To 18
R7<!PC
PC<!PC+LSHF(off11,1)
13
DR<!SHF(SR,A,D,amt4)
set CC
To 18
14
2
DR<!PC+LSHF(off9, 1)
set CC
To 18
MAR<!B+off6
6
7
MAR<!B+LSHF(off6,1)
3
MAR<!B+LSHF(off6,1)
MAR<!B+off6
To 18
29
NOTES
B+off6 : Base + SEXT[offset6]
PC+off9 : PC + SEXT[offset9]
*OP2 may be SR2 or SEXT[imm5]
** [15:8] or [7:0] depending on
MAR[0]
MDR<!M[MAR[15:1]’0]
R
31
R
DR<!SEXT[BYTE.DATA]
set CC
MDR<!SR
MDR<!M[MAR]
27
R
DR<!MDR
set CC
R
To 18
MDR<!SR[7:0]
16
17
M[MAR]<!MDR
R
To 18
24
23
25
To 18
M[MAR]<!MDR**
R
R
To 19
R
GateMARMUX
GatePC
16
16
16
LD.PC
MARMUX
16
2
16
PC
+2
PCMUX
REG
FILE
16
+
SR2
ZEXT &
LSHF1
[7:0]
LSHF1
ADDR1MUX
16
16
[10:0]
SR1
OUT
16
16
3
DR
SR1
16
16
16
0
SEXT
[4:0]
SR2
OUT
16
16
[5:0]
3
2
ADDR2MUX
[8:0]
3
LD.REG
16
SR2MUX
SEXT
SEXT
CONTROL
SEXT
R
LD.IR
IR
2
N Z P
LD.CC
16
B
ALUK
LOGIC
6
A
ALU
SHF
16
16
GateALU
IR[5:0]
GateSHF
16
GateMDR
MAR
L D .M AR
DATA.SIZE
[0]
LOGIC
R.W
WE
LOGIC
MAR[0]
MIO.EN
DATA.
SIZE
16
MEMORY
L D .MDR
MDR
MIO.EN
16
LOGIC
ADDR. CTL.
LOGIC
2
MEM.EN
R
16
DATA.SIZE
MAR[0]
INMUX
INPUT
OUTPUT
KBDR
WE1 WE0
DDR
KBSR
DSR
State Machine for LDW 10APPENDIX C. THE MICROARCHITECTURE OF THE LC-3B, BASIC MACHINE
Microsequencer COND1
BEN
R
J[4]
J[3]
J[2]
IR[11]
Ready
Branch
J[5]
COND0
J[1]
Addr.
Mode
J[0]
0,0,IR[15:12]
6
IRD
6
Address of Next State
Figure C.5: The microsequencer of the LC-3b base machine
State 18 (010010) State 33 (100001) State 35 (100011) State 32 (100000) State 6 (000110) State 25 (011001) State 27 (011011) unused opcodes, the microarchitecture would execute a sequence of microinstructions,
starting at state 10 or state 11, depending on which illegal opcode was being decoded.
In both cases, the sequence of microinstructions would respond to the fact that an
instruction with an illegal opcode had been fetched.
Several signals necessary to control the data path and the microsequencer are not
among those listed in Tables C.1 and C.2. They are DR, SR1, BEN, and R. Figure C.6
shows the additional logic needed to generate DR, SR1, and BEN.
The remaining signal, R, is a signal generated by the memory in order to allow the
C.4. THE CONTROL STRUCTURE
11
IR[11:9]
IR[11:9]
DR
SR1
111
IR[8:6]
DRMUX
SR1MUX
(b)
(a)
IR[11:9]
N
Z
P
Logic
BEN
(c)
Figure C.6: Additional logic required to provide control signals
R
IR[15:11]
BEN
Microsequencer
6
Control Store
2 6 x 35
35
Microinstruction
9
(J, COND, IRD)
26
10APPENDIX C. THE MICROARCHITECTURE OF THE LC-3B, BASIC MACHINE
COND1
BEN
R
J[4]
J[3]
J[2]
IR[11]
Ready
Branch
J[5]
COND0
J[1]
0,0,IR[15:12]
6
IRD
6
Address of Next State
Figure C.5: The microsequencer of the LC-3b base machine
Addr.
Mode
J[0]
J
d
Co
n
IR
D
LD
.M
LD AR
.M
LD DR
.IR
LD
.BE
LD N
.RE
LD G
.CC
LD
.PC
Ga
teP
Ga C
teM
Ga DR
teA
Ga LU
teM
Ga ARM
teS
HF UX
PC
MU
X
DR
MU
SR X
1M
AD UX
DR
1M
UX
AD
DR
2M
UX
MA
RM
UX
AL
UK
MI
O.
E
R.W N
DA
TA
LS .SIZ
HF E
1
000000 (State 0)
000001 (State 1)
000010 (State 2)
000011 (State 3)
000100 (State 4)
000101 (State 5)
000110 (State 6)
000111 (State 7)
001000 (State 8)
001001 (State 9)
001010 (State 10)
001011 (State 11)
001100 (State 12)
001101 (State 13)
001110 (State 14)
001111 (State 15)
010000 (State 16)
010001 (State 17)
010010 (State 18)
010011 (State 19)
010100 (State 20)
010101 (State 21)
010110 (State 22)
010111 (State 23)
011000 (State 24)
011001 (State 25)
011010 (State 26)
011011 (State 27)
011100 (State 28)
011101 (State 29)
011110 (State 30)
011111 (State 31)
100000 (State 32)
100001 (State 33)
100010 (State 34)
100011 (State 35)
100100 (State 36)
100101 (State 37)
100110 (State 38)
100111 (State 39)
101000 (State 40)
101001 (State 41)
101010 (State 42)
101011 (State 43)
101100 (State 44)
101101 (State 45)
101110 (State 46)
101111 (State 47)
110000 (State 48)
110001 (State 49)
110010 (State 50)
110011 (State 51)
110100 (State 52)
110101 (State 53)
110110 (State 54)
110111 (State 55)
111000 (State 56)
111001 (State 57)
111010 (State 58)
111011 (State 59)
111100 (State 60)
111101 (State 61)
111110 (State 62)
111111 (State 63)
10APPENDIX C. THE MICROARCHITECTURE OF THE LC-3B, BASIC MACHINE
COND1
BEN
R
J[4]
J[3]
J[2]
IR[11]
Ready
Branch
J[5]
COND0
J[1]
0,0,IR[15:12]
6
IRD
6
Address of Next State
Figure C.5: The microsequencer of the LC-3b base machine
Addr.
Mode
J[0]
End of the Exercise in
Microprogramming
42
Homework 2
n
You will write the microcode for the entire LC-3b as
specified in Appendix C
43