18-447
Computer Architecture
Lecture 5: ISA Wrap-Up and
Single-Cycle Microarchitectures
Prof. Onur Mutlu
Carnegie Mellon University
Spring 2012, 1/25/2012
Homework 0

Was due Wednesday!

34 received
2
Reminder: Homeworks for Next Two Weeks

Homework 1




Due Monday Jan 28, right before lecture
Turn in via AFS (hand-in directories)
MIPS warmup, ISA concepts, basic performance evaluation
Homework 2

Will be assigned next week. Stay tuned…
3
Reminder: Lab Assignment 1

Due next Friday (Feb 1), at the end of Friday lab
A functional C-level simulator for a subset of the MIPS ISA

Study the MIPS ISA Tutorial

TAs will cover this in Lab Sessions this week

4
A Note on Lab and Homework Dates

Intended dates are on your syllabus



http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?medi
a=syllabus-18-447-mutlu-s13.pdf
We will try to stick to them.
Last year’s website can provide you a good lookahead into
what is coming…


http://www.ece.cmu.edu/~ece447/s12/doku.php
http://www.ece.cmu.edu/~ece447/s12/doku.php?id=wiki:lect
ures
5
Readings for Next Lecture

P&P, Revised Appendix C



P&H, Appendix D


Microarchitecture of the LC-3b
Appendix A (LC-3b ISA) will be useful in following this
Mapping Control to Hardware
Optional

Maurice Wilkes, “The Best Way to Design an Automatic
Calculating Machine,” Manchester Univ. Computer Inaugural
Conf., 1951.
6
Review of Last Lecture: ISA Tradeoffs





Complex vs. simple instructions: concept of semantic gap
Use of translation to change the tradeoffs
Fixed vs. variable length, uniform vs. non-uniform decode
Number of registers
What is the benefit of translating complex instructions to
“simple instructions” before executing them?




In hardware (a la Intel, AMD)?
In software (a la Transmeta)?
Which ISA is easier to extend: fixed length or variable length?
How can you have a variable length, uniform decode ISA?
7
Review: x86 vs. Alpha Instruction Formats

x86:

Alpha:
8
Review: ISA-level Tradeoffs: Number of Registers

Affects:




Number of bits used for encoding register address
Number of values kept in fast storage (register file)
(uarch) Size, access time, power consumption of register file
Large number of registers:
+ Enables better register allocation (and optimizations) by
compiler  fewer saves/restores
-- Larger instruction size
-- Larger register file size
9
ISA-level Tradeoffs: Addressing Modes

Addressing mode specifies how to obtain an operand of an
instruction




Register
Immediate
Memory (displacement, register indirect, indexed, absolute,
memory indirect, autoincrement, autodecrement, …)
More modes:
+ help better support programming constructs (arrays, pointerbased accesses)
-- make it harder for the architect to design
-- too many choices for the compiler?

Many ways to do the same thing complicates compiler design

Wulf, “Compilers and Computer Architecture,” IEEE Computer 1981
10
x86 vs. Alpha Instruction Formats

x86:

Alpha:
11
x86
register
indirect
absolute
register +
displacement
register
12
x86
indexed
(base +
index)
scaled
(base +
index*4)
13
X86 SIB-D Addressing Mode
x86 Manual Vol. 1, page 3-22 -- see course resources on website
Also, see Section 3.7.3 and 3.7.5
14
X86 Manual: Suggested Uses of Addressing Modes
x86 Manual Vol. 1, page 3-22 -- see course resources on website
Also, see Section 3.7.3 and 3.7.5
15
X86 Manual: Suggested Uses of Addressing Modes
x86 Manual Vol. 1, page 3-22 -- see course resources on website
Also, see Section 3.7.3 and 3.7.5
16
Other Example ISA-level Tradeoffs









Condition codes vs. not
VLIW vs. single instruction
Precise vs. imprecise exceptions
Virtual memory vs. not
Unaligned access vs. not
Hardware interlocks vs. software-guaranteed interlocking
Software vs. hardware managed page fault handling
Cache coherence (hardware vs. software)
…
17
Back to Programmer vs. (Micro)architect

Many ISA features designed to aid programmers
But, complicate the hardware designer’s job

Virtual memory





vs. overlay programming
Should the programmer be concerned about the size of code
blocks fitting physical memory?
Addressing modes
Unaligned memory access

Compile/programmer needs to align data
18
MIPS: Aligned Access
MSB

byte-2
byte-1
byte-0
byte-7
byte-6
byte-5
byte-4
LSB
LW/SW alignment restriction: 4-byte word-alignment



byte-3
not designed to fetch memory bytes not within a word boundary
not designed to rotate unaligned bytes into registers
Provide separate opcodes for the “infrequent” case


A
B
C
D
LWL rd 6(r0) 
byte-6
byte-5
byte-4
D
LWR rd 3(r0) 
byte-6
byte-5
byte-4
byte-3
LWL/LWR is slower
Note LWL and LWR still fetch within word boundary
19
X86: Unaligned Access


LD/ST instructions automatically align data that spans a
“word” boundary
Programmer/compiler does not need to worry about where
data is stored (whether or not in a word-aligned location)
20
X86: Unaligned Access
21
Aligned vs. Unaligned Access

Pros of having no restrictions on alignment

Cons of having no restrictions on alignment

Filling in the above: an exercise for you…
22
Implementing the ISA:
Microarchitecture Basics
23
How Does a Machine Process Instructions?


What does processing an instruction mean?
Remember the von Neumann model
A = Architectural (programmer visible) state before an
instruction is processed
Process instruction
A’ = Architectural (programmer visible) state after an
instruction is processed

Processing an instruction: Transforming A to A’ according to
the ISA specification of the instruction
24
The “Process instruction” Step

ISA specifies abstractly what A’ should be, given an
instruction and A

It defines an abstract finite state machine where



From ISA point of view, there are no “intermediate states”
between A and A’ during instruction execution


State = programmer-visible state
Next-state logic = instruction execution specification
One state transition per instruction
Microarchitecture implements how A is transformed to A’


There are many choices in implementation
We can have programmer-invisible state to optimize the speed of
instruction execution: multiple state transitions per instruction


Choice 1: A  A’ (transform A to A’ in a single clock cycle)
Choice 2: A  A+MS1  A+MS2  A+MS3  A’ (take multiple clock
cycles to transform A to A’)
25
A Very Basic Instruction Processing Engine


Each instruction takes a single clock cycle to execute
Only combinational logic is used to implement instruction
execution
 No intermediate, programmer-invisible state updates
A = Architectural (programmer visible) state
at the beginning of a clock cycle
Process instruction in one clock cycle
A’ = Architectural (programmer visible) state
at the end of a clock cycle
26
A Very Basic Instruction Processing Engine

Single-cycle machine
ANext
Combinational
Logic


Sequential
Logic
(State)
A
What is the clock cycle time determined by?
What is the critical path of the combinational logic
determined by?
27
Remember: Programmer Visible (Architectural) State
M[0]
M[1]
M[2]
M[3]
M[4]
Registers
- given special names in the ISA
(as opposed to addresses)
- general vs. special purpose
M[N-1]
Memory
Program Counter
array of storage locations
indexed by an address
memory address
of the current instruction
Instructions (and programs) specify how to transform
the values of programmer visible state
28
Single-cycle vs. Multi-cycle Machines

Single-cycle machines




Each instruction takes a single clock cycle
All state updates made at the end of an instruction’s execution
Big disadvantage: The slowest instruction determines cycle time 
long clock cycle time
Multi-cycle machines





Instruction processing broken into multiple cycles/stages
State updates can be made during an instruction’s execution
Architectural state updates made only at the end of an instruction’s
execution
Advantage over single-cycle: The slowest “stage” determines cycle time
Both single-cycle and multi-cycle machines literally follow the
von Neumann model at the microarchitecture level
29
Instruction Processing “Cycle”



Instructions are processed under the direction of a “control
unit” step by step.
Instruction cycle: Sequence of steps to process an instruction
Fundamentally, there are six phases:

Fetch
Decode
Evaluate Address
Fetch Operands
Execute
Store Result

Not all instructions require all six stages (see P&P Ch. 4)





30
Instruction Processing “Cycle” vs. Machine Clock Cycle

Single-cycle machine:


All six phases of the instruction processing cycle take a single
machine clock cycle to complete
Multi-cycle machine:


All six phases of the instruction processing cycle can take
multiple machine clock cycles to complete
In fact, each phase can take multiple clock cycles to complete
31
Instruction Processing Viewed Another Way


Instructions transform Data (AS) to Data’ (AS’)
This transformation is done by functional units

Units that “operate” on data

These units need to be told what to do to the data

An instruction processing engine consists of two components

Datapath: Consists of hardware elements that deal with and
transform data signals




functional units that operate on data
hardware structures (e.g. wires and muxes) that enable the flow of
data into the functional units and registers
storage units that store data (e.g., registers)
Control logic: Consists of hardware elements that determine
control signals, i.e., signals that specify what the datapath
elements should do to the data
32
Single-cycle vs. Multi-cycle: Control & Data

Single-cycle machine:



Multi-cycle machine:



Control signals are generated in the same clock cycle as data
signals are operated on
Everything related to an instruction happens in one clock cycle
Control signals needed in the next cycle can be generated in
the previous cycle
Latency of control processing can be overlapped with latency
of datapath operation
We will see the difference clearly in microprogrammed
multi-cycle microarchitecture
33
Many Ways of Datapath and Control Design



There are many ways of designing the data path and
control logic
Single-cycle, multi-cycle, pipelined datapath and control
Single-bus vs. multi-bus datapaths


Hardwired/combinational vs. microcoded/microprogrammed
control



See your homework 2 question
Control signals generated by combinational logic versus
Control signals stored in a memory structure
Control signals and structure depend on the datapath
design
34
Flash-Forward: Performance Analysis

Execution time of an instruction


Execution time of a program



Sum over all instructions [{CPI} x {clock cycle time}]
{# of instructions} x {Average CPI} x {clock cycle time}
Single cycle microarchitecture performance



{CPI} x {clock cycle time}
CPI = 1
Clock cycle time = long
Multi-cycle microarchitecture performance

CPI = different for each instruction


Average CPI  hopefully small
Clock cycle time = short
Now, we have
two degrees of freedom
to optimize independently
35
A Single-Cycle Microarchitecture
A Closer Look
36
Remember…

Single-cycle machine
ASNext
Combinational
Logic
Sequential
Logic
(State)
AS
37
Let’s Start with the State Elements

Data and control inputs
on
5
R e g is te r
5
n u m b e rs
PC
In s tru c tio n
A dd
5
S um
io n
D a ta
ry
3
R ead
re g is t e r 1
R ead
re g is t e r 2
R e g is te rs
W rite
re g is t e r
W rite
d a ta
R e ad
d a ta 1
D ata
AL
R e ad
d a ta 2
R e g W rite
u c tio n m e m o r y
b . P ro g ra m c o u n te r
c. A dder
a . R e g is t e rs
b
M e m W rit e
In s tr u c tio n
ad dress
R ead
d a ta
A d d re s s
PC
In s tru c tio n
In s t ru c tio n
m em ory
a . In s t ru c tio n m e m o r y
W rite
d a ta
b . P ro g ra m c o u n te r
S um
D a ta
S ig n
e x te n d
m e m o ry
M em R ead
a . D a ta m e m o ry u n it
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
16
A dd
c. A d de r
38
b . S ig n -e x te n
For Now, We Will Assume

“Magic” memory and register file

Combinational read


output of the read data port is a combinational function of the
register file contents and the corresponding read select port
Synchronous write

the selected register is updated on the positive edge clock
transition when write enable is asserted



Cannot affect read output in between clock edges
Can affect read output at clock edges (but who cares?)
Single-cycle, synchronous memory


Contrast this with memory that tells when the data is ready
i.e., Ready bit: indicating the read or write is done
39
Instruction Processing

5 generic steps (P&H)





Instruction fetch (IF)
Instruction decode and register operand fetch (ID/RF)
Execute/Evaluate memory address (EX/AG)
Memory operand fetch (MEM)
Store/writeback result (WB)
WB
IF
D a ta
R e g is t e r #
PC
A d d re s s
In s tru c tio n
m e m o ry
In s tru c tio n
R e g is te rs
ALU
A d d re s s
R e g is t e r #
ID/RF
R e g is t e r #
D a ta
EX/AG
m e m o ry
D a ta
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
MEM
40
What Is To Come: The Full Datapath
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
Z e ro
bcond
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier.
ALL RIGHTS RESERVED.]
41
JAL, JR, JALR omitted
Single-Cycle Datapath for
Arithmetic and Logical Instructions
42
R-Type ALU Instructions



Assembly (e.g., register-register signed addition)
ADD rdreg rsreg rtreg
Machine encoding
0
rs
rt
rd
0
ADD
6-bit
5-bit
5-bit
5-bit
5-bit
6-bit
R-type
Semantics
if MEM[PC] == ADD rd rs rt
GPR[rd]  GPR[rs] + GPR[rt]
PC  PC + 4
43
ALU Datapath
A dd
4
PC
25:21 R e a d
re g is te r 1
R ead
a d d re s s
In s tr u c tio n
I n s tru c t io n
In s tru c tio n
20:16 R e a d
re g is te r 2
R e g is te rs
15:11 W rite
re g is te r
m e m o ry
W rite
d ata
A L U o p e ra tio n
3
R ead
d a ta 1
Z e ro
ALU
ALU
re s u lt
R ead
d a ta 2
R e g W rite
1
IF
if MEM[PC] == ADD rd rs rt
GPR[rd]  GPR[rs] + GPR[rt]
PCfrom
+ 4 2004 Elsevier. ALL RIGHTS RESERVED.]
**Based on original figure
[P&HPC
CO&D, COPYRIGHT
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
ID
EX
MEM WB
Combinational
state update logic
44
I-Type ALU Instructions



Assembly (e.g., register-immediate signed additions)
ADDI rtreg rsreg immediate16
Machine encoding
ADDI
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
I-type
Semantics
if MEM[PC] == ADDI rt rs immediate
GPR[rt]  GPR[rs] + sign-extend (immediate)
PC  PC + 4
45
Datapath for R and I-Type ALU Insts.
A dd
4
PC
25:21
R ead
a d d re s s
20:16
In s tru c tio n
I n s tru c t io n
In s tru c tio n
15:11
3
R ead
re g is te r 1
isItype
M em
R ead
d a ta 1
R ead
re g is te r 2
Zero
R e g is te r s
W rite
re g is te r
m e m o ry
RegDest
A L U o p e r a tio n
W rite
d a ta
ALU
A LU
re s u lt
A d d re s s
R ead
d a ta 2
D a ta
m em o
R e g W rit e
W rite
d a ta
ALUSrc
11 6
32
S ig n
isItype
M em
e x te n d
IF
if MEM[PC] == ADDI rt rs immediate
GPR[rt]  GPR[rs] + sign-extend (immediate)
PC  PC + 4
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
ID
EX
MEM WB
Combinational
state update logic 46
Single-Cycle Datapath for
Data Movement Instructions
47
Load Instructions



Assembly (e.g., load 4-byte word)
LW rtreg offset16 (basereg)
Machine encoding
LW
base
rt
offset
6-bit
5-bit
5-bit
16-bit
I-type
Semantics
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
GPR[rt]  MEM[ translate(EA) ]
PC  PC + 4
48
LW Datapath
A dd
add
4
PC
3
R ead
re g is te r 1
R ead
a d d re s s
In s tru c tio n
M e m W rite
R ead
d a ta 1
R ead
re g is te r 2
I n s tru c t io n
Zero
ALU
R e g is te r s
W rite
re g is te r
In s tru c tio n
W rite
d a ta
isItype
A d d re s s
W rite
d a ta
ALUSrc
16
32
S ig n
M em R ead
isItype
M em R ead
e x te n d
if MEM[PC]==LW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
GPR[rt]  MEM[ translate(EA) ]
PC  PC + 4
16
R ea d
d a ta
D a ta
W rite
d a ta D a ta m e m o ry
m e m o ry
R e g W rit e
1
R ead
d a ta
A d d re s s
A LU
re s u lt
R ead
d a ta 2
m e m o ry
RegDest
M e m W rit e
A L U o p e r a tio n
a . D a ta m e m o ry u n it
IF
ID
EX
MEM WB
Combinational
state update logic 49
b. Si
Store Instructions



Assembly (e.g., store 4-byte word)
SW rtreg offset16 (basereg)
Machine encoding
SW
base
rt
offset
6-bit
5-bit
5-bit
16-bit
I-type
Semantics
if MEM[PC]==SW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
MEM[ translate(EA) ]  GPR[rt]
PC  PC + 4
50
SW Datapath
A dd
add
4
PC
3
R ead
re g is te r 1
R ead
a d d re s s
In s tru c tio n
M e m W rite
R ead
d a ta 1
R ead
re g is te r 2
I n s tru c t io n
Zero
ALU
R e g is te r s
W rite
re g is te r
In s tru c tio n
W rite
d a ta
isItype
A d d re s s
W rite
d a ta
ALUSrc
16
32
S ig n
M em R ead
isItype
M em R ead
e x te n d
if MEM[PC]==SW rt offset16 (base)
EA = sign-extend(offset) + GPR[base]
MEM[ translate(EA) ]  GPR[rt]
PC  PC + 4
16
R ea d
d a ta
D a ta
W rite
d a ta D a ta m e m o ry
m e m o ry
R e g W rit e
0
R ead
d a ta
A d d re s s
A LU
re s u lt
R ead
d a ta 2
m e m o ry
RegDest
M e m W rit e
A L U o p e r a tio n
a . D a ta m e m o ry u n it
IF
ID
EX
MEM WB
Combinational
state update logic 51
b. Si
Load-Store Datapath
A dd
add
4
PC
R ead
re g is te r 1
R ead
a d d re s s
In s tru c tio n
I n s tru c t io n
R ead
re g is te r 2
R e g is te r s
W rite
re g is te r
In s tru c tio n
m e m o ry
W rite
d a ta
RegDest
isItype
3
isStore
A L U o p e r a tio n
M e m W rite
R ead
d a ta 1
Zero
ALU
A LU
re s u lt
R ea d
d a ta
A d d re s s
R ead
d a ta 2
D a ta
m e m o ry
R e g W rit e
ALUSrc
!isStore
16
32
S ig n
isItype
W rite
d a ta
M em R ead
e x te n d
isLoad
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
52
Datapath for Non-Control-Flow Insts.
A dd
4
PC
R ead
re g is te r 1
R ead
a d d re s s
In s tru c tio n
I n s tru c t io n
R ead
re g is te r 2
R e g is te r s
W rite
re g is te r
In s tru c tio n
m e m o ry
W rite
d a ta
RegDest
isItype
3
isStore
A L U o p e r a tio n
M e m W rite
R ead
d a ta 1
Zero
ALU
A LU
re s u lt
R ea d
d a ta
A d d re s s
R ead
d a ta 2
D a ta
m e m o ry
R e g W rit e
ALUSrc
!isStore
16
32
S ig n
isItype
W rite
d a ta
M em R ead
e x te n d
isLoad
MemtoReg
isLoad
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
53
Single-Cycle Datapath for
Control Flow Instructions
54
Unconditional Jump Instructions



Assembly
J immediate26
Machine encoding
J
immediate
6-bit
26-bit
J-type
Semantics
if MEM[PC]==J immediate26
target = { PC[31:28], immediate26, 2’b00 }
PC  target
55
Unconditional Jump Datapath
isJ
A dd
PCSrc
4
PC
R ead
re g is te r 1
R ead
a d d re s s
R ead
re g is te r 2
In s tru c tio n
I n s tru c t io n
R e g is te r s
W rite
re g is te r
In s tru c tio n
concat
m e m o ry
?
W rite
d a ta
3
XA L U o p e r a tio n
0
M e m W rite
R ead
d a ta 1
Zero
ALU
A LU
re s u lt
R ea d
d a ta
A d d re s s
R ead
d a ta 2
D a ta
m e m o ry
R e g W rit e
0 16
32
S ig n
ALUSrc
X
W rite
d a ta
M em R ead
e x te n d
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
if MEM[PC]==J immediate26
PC = { PC[31:28], immediate26, 2’b00 }
0
56
What about JR, JAL, JALR?
Conditional Branch Instructions



Assembly (e.g., branch if equal)
BEQ rsreg rtreg immediate16
Machine encoding
BEQ
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
I-type
Semantics (assuming no branch delay slot)
if MEM[PC]==BEQ rs rt immediate16
target = PC + 4 + sign-extend(immediate) x 4
if GPR[rs]==GPR[rt] then PC  target
else
PC  PC + 4
57
Conditional Branch Datapath (For You to Fix)
watch out
P C + 4 fro m in s t ru c tio n d a ta p a th
A dd
PCSrc
Add
Sum
B ra n c h ta rg e t
4
S h if t
PC
le ft 2
R ead
a d d re s s
In s tru c tio n
3
R ead
re g is te r 1
I n s tru c t io n
In s tru c tio n
concat
m e m o ry
sub
A L U o p e r a tio n
R ead
re g is te r 2
R e g is te rs
W rite
re g is te r
W rite
d ata
R ead
d a ta 1
ALU
Z e ro
bcond
T o b ra n c h
c o n tro l lo g ic
R ead
d a ta 2
R e g W rit e
0
16
32
S ig n
e x te n d
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
58
How to uphold the delayed branch semantics?
Putting It All Together
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
Z e ro
bcond
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
Read
d a ta
1
M
u
x
0
32
S ig n
e x te n d
ALU
c o n tro l
ALU operation
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier.
ALL RIGHTS RESERVED.]
59
JAL, JR, JALR omitted
We did not cover the following slides in lecture.
These are for your preparation for the next lecture.
Single-Cycle Control Logic
61
Single-Cycle Hardwired Control

As combinational function of Inst=MEM[PC]
31
21
16
11
6
0
0
rs
rt
rd
shamt
funct
6-bit
5-bit
5-bit
5-bit
5-bit
6-bit
31
26
21
16
0
opcode
rs
rt
immediate
6-bit
5-bit
5-bit
16-bit
31

26
26
0
opcode
immediate
6-bit
26-bit
R-type
I-type
J-type
Consider
 All R-type and I-type ALU instructions
 LW and SW
 BEQ, BNE, BLEZ, BGTZ
 J, JR, JAL, JALR
62
Single-Bit Control Signals
When De-asserted
RegDest
ALUSrc
MemtoReg
RegWrite
When asserted
Equation
GPR write select
according to rt, i.e.,
inst[20:16]
GPR write select
according to rd, i.e.,
inst[15:11]
opcode==0
2nd ALU input from 2nd
GPR read port
2nd ALU input from sign- (opcode!=0) &&
extended 16-bit
(opcode!=BEQ) &&
immediate
(opcode!=BNE)
Steer ALU result to GPR
write port
steer memory load to
GPR wr. port
opcode==LW
GPR write disabled
GPR write enabled
(opcode!=SW) &&
(opcode!=Bxx) &&
(opcode!=J) &&
(opcode!=JR))
63
JAL and JALR require additional RegDest and MemtoReg options
Single-Bit Control Signals
When De-asserted
MemRead
MemWrite
Equation
Memory read disabled
Memory read port
return load value
opcode==LW
Memory write disabled
Memory write enabled
opcode==SW
According to PCSrc2
next PC is based on 26bit immediate jump
target
(opcode==J) ||
next PC is based on 16bit immediate branch
target
(opcode==Bxx) &&
PCSrc1
next PC = PC + 4
PCSrc2
When asserted
(opcode==JAL)
“bcond is satisfied”
64
JR and JALR require additional PCSrc options
ALU Control

case opcode
‘0’  select operation according to funct
‘ALUi’  selection operation according to opcode
‘LW’  select addition
‘SW’  select addition
‘Bxx’  select bcond generation function
__  don’t care

Example ALU operations


ADD, SUB, AND, OR, XOR, NOR, etc.
bcond on equal, not equal, LE zero, GT zero, etc.
65
R-Type ALU
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
1
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
0
32
S ig n
e x te n d
funct ALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
66
I-Type ALU
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
1
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
0
32
S ig n
e x te n d
opcodeALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
67
LW
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
1
1
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
0
32
S ig n
e x te n d
Add
ALU
c o n tro l
ALU operation
1
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
68
SW
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
*
M
u
x
1
0
1
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
In s tr u c tio n [1 5 – 0 ]
16
1
M
u
x
*
0
32
S ig n
e x te n d
Add
ALU
c o n tro l
ALU operation
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
69
Branch Not Taken
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
*
1
In s tr u c tio n [1 5 – 0 ]
0
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
16
1
M
u
x
*
0
32
S ig n
e x te n d
bcondALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT 2004
Elsevier. ALL RIGHTS RESERVED.]
70
Branch Taken
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
A LU
re s u lt
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
*
1
In s tr u c tio n [1 5 – 0 ]
0
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
bcond
Z e ro
ALU
0
M
u
x
W rite
d a ta
ALU
re s u lt
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
16
1
M
u
x
*
0
32
S ig n
e x te n d
bcondALU operation
ALU
c o n tro l
0
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
71
Jump
In s tru c tio n [2 5 – 0 ]
26
S h ift
le ft 2
PCSrc1=Jump
J u m p a d d r e s s [3 1 – 0 ]
28
P C + 4 [3 1 – 2 8 ]
Add
Add
1
M
u
x
M
u
x
1
0
*
A LU
re s u lt
PCSrc2=Br Taken
S h ift
le ft 2
Re g D st
Ju m p
4
0
B ra n c h
MemRead
In s tr u c tio n [3 1 – 2 6 ]
C o n tro l
M e m to R e g
ALUOp
M e m W rite
A L U S rc
R e g W rite
In s tr u c tio n [2 5 – 2 1 ]
PC
R ea d
re g is te r 1
Read
a d d re s s
In s tr u c tio n [2 0 – 1 6 ]
In s tr u c tio n
[3 1 – 0 ]
In s tr u c tio n
m e m ory
0
In s tr u c tio n [1 5 – 1 1 ]
M
u
x
*
1
In s tr u c tio n [1 5 – 0 ]
0
bcond
Z e ro
ALU
0
M
u
x
*
W rite
d a ta
ALU
re s u lt
16
Read
d a ta
A d d re s s
D a ta
m e m o ry
1
W rite
d a ta
1
M
u
x
*
0
32
S ig n
e x te n d
In s tru c tio n [5 – 0 ]
**Based on original figure from [P&H CO&D, COPYRIGHT
2004 Elsevier. ALL RIGHTS RESERVED.]
0
Read
d a ta 1
R ea d
re g is te r 2
R e g is te rs R e a d
W rite
d a ta 2
re g is te r
*
ALU
c o n tro l
ALU operation
0
72
What is in That Control Box?

Combinational Logic  Hardwired Control


Idea: Control signals generated combinationally based on
instruction
Sequential Logic  Sequential/Microprogrammed Control


Control Store
Idea: A memory structure contains the control signals
associated with an instruction
73