Design of a Silicon Carbide Micro-Hotplate Geometry
for High Temperature Chemical Sensing
Gregory Benn
B.S. Aerospace Engineering
University of Colorado, Boulder, 1999
Submitted to the Department of Aeronautics and Astronautics in
partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE IN AERONAUTICS AND
ASTRONAUTICS
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
May 2001
AUG 1 9 2002'TE
© 2001 Gregory Benn. All Rights Reserved.
LIBRARIES
The author hereby grants to MIT permission to reproduce and to
distribute publicly paper and electronic copies of this thesis document in whole or in part.
09
Author
n
AERO
1
....................................
- .
.
............
...............
. .. . .. . . .. . .. .
ment of Aeronautics and Astronautics
August 15, 2000
Certified by ................
.. ,r ......... \ / ........................................................................
John Brisson
ssociate Professor, Department of Mechanical Engineering
Thesis Supervisor
Certified by
I
Accepted by
VOf
VMark
Spearing
Esher and Harold E. Edgerton Asssociate Professor,
Department of Aeronautics and Astronautics
Thesis Reader
..........................
Wallace E. Vander Velde
Professor Emeritus, Department of Aeronautics and Astronautics
Chairman, Committee of Graduate Studies
MASSACHUSETTS INSTITUTE
OF TECHNOLOGY
LIBRARIES
2
Design of a Silicon Carbide Micro-Hotplate Geometry for High
Temperature Chemical Sensing
by
Gregory Benn
Submitted to the Department of Aeronautics and Astronautics on
May 25, 2001, in partial fulfillment of the requirements for the
degree of Master of Engineering in Aeronautics and Astronautics
Abstract
Silicon carbide, high temperature, chemical sensors are the next step in chemical detection
technology; allowing for the development of low cost, robust, lower power, and widely
applicable chemical sensors. SiC offers the thermal conductivity, electrical properties, and
operating temperatures not currently available in silicon sensors. Boston Micro Systems, a
Wobum, Massachusetts based company, has developed technologies for bulk manufacturing of single crystal SiC material. Using this technology, geometries optimizing thermal
and electrical performance have been developed to create a SiC micro-hotplate for chemical sensors.
Under etching allows for the manufacturing of micro-hotplates. Micro hotplates allow
sensors to discriminate between chemical species by controlling absorption and desorption of chemicals. Optimization of the performance of such a device is achieved by developing hotplates that are suspended by necked tethers. Tether designs minimize heat lose
from the hotplate and necking creates heat generation regions. The excellent thermal properties of SiC allow heat to be transferred from the necked tethers to the hotplate; producing a hotplate with a uniform temperature distribution, important to the sensitivity and
accuracy of the sensing film.
Testing of tethered and necked hotplates identified several areas of improvement in hotplate design. These include under etching, improvement in the plates response to thermal
stresses, and p-n junction performance improvements.
Using such design improvements as tethers and necking the thermal performance of SiC
micro-hotplates has improved by two orders of magnitude. This thesis discusses the
design, modeling, and testing of single crystal SiC micro-hotplates.
Advisor: John Brisson
Title: Associate Professor of Mechanical Engineering
4
Table of Contents
Table of Contents ..............................................................................................................................
5
List o f F ig u re s ...................................................................................................................................
List o f T ab le s .....................................................................................................................................
Acknow ledgm ents...........................................................................................................................11
List of A cronym s.............................................................................................................................13
7
9
S ymb o ls ...........................................................................................................................................
15
1 . In tro d u ctio n ................................................................................................................................
1. 1 Project Overview ............................................................................................................
1.2 Basic D evice Overview ...............................................................................................
1.3 Project Objectives ..........................................................................................................
1.4 Thesis O verview .............................................................................................................
17
17
18
19
21
2. Background ................................................................................................................................
23
2.1 Chapter Overview ..........................................................................................................
23
2 .2 M a teria l ..........................................................................................................................
23
2.3 P-n Junctions ..................................................................................................................
24
2.4 Chem ical Sensing ...........................................................................................................
25
2.5
3. Initial
3.1
3.2
Conclusions ....................................................................................................................
D esign Analysis...............................................................................................................29
Chapter Overview ..........................................................................................................
G eom etry ........................................................................................................................
3.3 M odeling A ssum ptions ..............................................................................................
3.4 Perform ance Analysis of Original Design .................................................................
3.5 Conclusions ....................................................................................................................
4. First D esign Iteration..................................................................................................................37
4.1 Chapter Overview ..........................................................................................................
4.2 G eom etry ........................................................................................................................
4.3 M odeling Assum ptions ..............................................................................................
4.4 Perform ance A nalysis of First Iteration Design.........................................................
4.5 Conclusions ....................................................................................................................
5. Second D esign Iteration .............................................................................................................
5.1 Chapter Overview ..........................................................................................................
5.2 Geom etry of Long Tethered Plate ...............................................................................
5.3 Modeling Assumptions and Calculations for Long Tethered Plate ...........................
5.4 Finite D ifference Results for Long Tethered D esign................................................
5.5 Finite Elem ent Results for Long Tethered Design.....................................................
5.6 Conclusions ....................................................................................................................
6. Tether D esign and the Final Design........................................................................................
6.1 Chapter Overview ..........................................................................................................
6.2 Length Considerations.................................................................................................
6.3 Tether N ecking ...............................................................................................................
6.4 Analysis of N ecked Tether Design.............................................................................
6.5 Design Com parisons ...................................................................................................
6.6 Conclusions ....................................................................................................................
7. Tem perature D ependent Properties........................................................................................
7.1 Chapter Overview ..........................................................................................................
7.2 M easuring Electrical Properties Dependent on Tem perature ....................................
28
29
29
30
32
35
37
37
38
39
42
45
45
45
47
53
55
55
57
57
57
60
67
70
72
75
75
76
5
7.3 M odeling the Electrical Properties ............................................................................
7.4 Tem perature Dependence of Therm al Properties......................................................
7.5 Conclusions ..................................................................................................................
8. Device Testing .........................................................................................................................
8.1 Chapter Overview ........................................................................................................
8.2 Experim ental Set-Up ..................................................................................................
8.3 Experim ent Results ....................................................................................................
8.4 Analysis of Experim ent ..............................................................................................
8.5 Conclusions ..................................................................................................................
9 . Co n c lu sio ns ..............................................................................................................................
9.1 Design Overview ..........................................................................................................
9 .2 L e sso n s .........................................................................................................................
9.3 Future W ork .................................................................................................................
Appendix A Finite Differencing of the Hotplate. ........................................................................
A .1 Overview .....................................................................................................................
A .2 Finite Differencing Technique ....................................................................................
Appendix B Finite Elem ent Analysis and ADINA ......................................................................
B . O verv iew .....................................................................................................................
B.2 M athem atical M odel using FEM .................................................................................
B.3 Transient Response M odeling .....................................................................................
B.4 ADINA m odeling ........................................................................................................
Appendix A Test Device M ask Sets ............................................................................................
A . O ve rv iew .....................................................................................................................
A .2 Tested designs .............................................................................................................
A .3 Non-Tested Designs ....................................................................................................
6
80
85
90
91
91
91
96
98
103
10 5
105
10 6
107
109
109
109
115
115
115
120
121
123
12 3
123
125
List of Figures
F ig u re 1.1: B asic de sig n ..................................................................................................................
18
22
Figure 1.2: B asic design layouts ................................................................................................
25
Figure 2.1: Structure of unetched w afer......................................................................................
Figure 2.2: Programmed temperature response of a tin oxide micro-hotplate to a series of organic
v ap o rs (fro m N IS T) [1] ...................................................................................................................
Figure 3.1: Initial plate design .....................................................................................................
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
27
30
34
3.2: Analytical temperature distribution over the initial plate design .............................
35
method
...........................................
3.3: Interior grid designations for finite difference
36
3.4: Tem perature distribution over plate ..........................................................................
4. 1: First design iteration (plate section only).................................................................38
40
4.2: Temperature distribution over plate of first design iteration...................................
4.3: Temperature distribution over the plate center and plate edges respectively...........40
41
4.4: Temperature distribution over 40 mm tether design ....................................................
4.5: Center and end temperature distribtuion for 40 mm tethers.....................................42
46
5.1: Long tether design layout ..........................................................................................
49
5.2: Fintie elem ent breakdow n .......................................................................................
54
5.3: Finite difference results for long tether design........................................................
54
5.4: Temperature distribution over the center (AA') and edge (BB') of the plate .......
56
5.5: Finite element results for 240 mm tether design ......................................................
59
6.1: Temperature distribution over 240 mm tethers ............................................................
60
6.2: N ecked tether design ................................................................................................
61
6.3: N ecked tether layout.................................................................................................
current
a
constant
at
neck
lengths
for
different
6.4: Comparison of temperature distribution
o f 0 .4 88 mA ....................................................................................................................................
63
64
Figure 6.5: Necking length vs current required at a constant plate temperature of 1000K ......
Figure 6.6: Necked length vs voltage at a constant plate temperature of 1000 K.......................65
65
Figure 6.7: Necked length vs power at a constant plate temperature of 1000 K .......................
Figure 6.8: Comparison of temperature distributions of different necking lengths for a constant plate
66
tem p eratu re o f 10 0 0 K ....................................................................................................................
Figure 6.9: Comparison of heat transfer rate of different necking lengths at a constant plate temper67
atu re o f 10 0 0 K ................................................................................................................................
68
Figure 6.10: Temperature distribution of necked tether design ..................................................
71
Figure 6.11: Drive voltage of four main designs at 1000 K.......................................................
Figure 6.12: Power comparison of four main designs at 1000 K................................................72
77
Figure 7.1: Four point probe test structure.................................................................................
79
Chip
#1.............................................
Temperature
Tests,
of
Resistance
vs
Figure 7.2: Results
79
#2.............................................
Figure 7.3: Results of Resistance vs Temperature Tests, Chip
#1
...
chip
for
Figure 7.4: Plot of log(R/T3/2) vs 1/T and a linear curve fit to the non degraded data
83
Figure
Figure
Figure
Figure
7.5:
7.6:
7.7:
7.8:
83
Chip #1, comparison of experimental results to modeling fit ..................................
84
Chip #2, Comparison of Experimental Results to Modeling Fit ..............................
Temperature dependence of resistivity based on model results for chip #1.............84
Research Results for Temperature Dependence of SiC for a 1018 cm-3 Doping Density
86
Figure 7.9: Test Structure to Measure Thermal Conductivity ....................................................
Figure 7.10: Temperature Over the Bridge Structure .................................................................
87
88
7
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
8
8. 1: Test plate layout............................................................................................................92
8.2: Circular TLM pattern....................................................................................................93
8.3: M anufactured hotplate ..............................................................................................
94
8.4: M icro-machined tethers............................................................................................
94
8.5: Tether-hotplate junction ...........................................................................................
95
8.6: Tether hotplate junction and contact pad.................................................................
95
8.7: Basic modeling of experimental results...................................................................
99
8.8: M odel of final device results ......................................................................................
100
8.9: Buckling model of tethers...........................................................................................101
8.10: Deflection modeling of tethers .................................................................................
102
8.11: Modeling tether bending to determine the vertical deflection of the tether ............. 102
A. 1: Nodal layout for finite difference method .................................................................
110
A.2: Edge element for finite difference method ................................................................
112
A.3: Inside corner element for finite difference method ...................................................
112
A.4: .......................................................................
Outside corner for finite differencingl 13
B.1: General finite element body.......................................................................................116
B.2: Example finite element ..............................................................................................
119
C.1: Test Device 1, Large Perforations .............................................................................
123
C.2: Test Device 2, Small Perforations .............................................................................
124
C.3: Test Device 3, Necking and Large Perforations ........................................................
124
C.4: Test Device 4, 64 mm Tethers, Large Perforations ...................................................
125
C.5: Test Device 5, 440 mm Tethers, 200 x 200 mm Plate ...............................................
125
List of Tables
Table 2.1: SiC room tem perature properties [6,7,8]. .................................................................
Table 8. 1: Comparison of expected verses measured resistances............................................
Table 8.2: A djusted resistance com parison................................................................................
23
96
97
9
10
Acknowledgments
As with most graduate students, this work reflects the efforts of many people, not just
the person with their name on the cover. It is the culmination of work between professor
and student, lab and company, husband and wife (to be), friends, and family. As such,
there are several people who contributed to this work who I would like to thank with all
my heart for there effort, support, and guidance.
First, to Professor John Brisson. Without his advice and guidance this project would
have never even begun, and never finished.
Professor Mark Spearing who helped get me this project and provided insight into the
mechanics of micro devices. An invaluable wealth of information related to micro structures.
A special thanks to Rick Mlcak and Boston Micro Systems. First, for their funding of
the project, but more importantly for their advice, their time and patience, and the use of
their facilities. And a special thanks to Rick for all of his help and wisdom. I learned so
much from him about semiconductors and micro machining I am forever indebted. I can
only hope that this work helps to make a profitable and successful product for BMS.
To the love of my life and best friend, Cari. For her countless hours of editing and faxing of thesis drafts. For her tireless support, attentive ear, and comforting voice. For allowing me to go 2000 miles away from her for two years to get this degree. I love you with all
my heart.
To my parents and family, Mom and Dad, Sally, Brian, and Jeff. For always supporting
me and believing in me, not just for this work, but everything in my life. This work is the
culmination of 24 years of life, of growing and learning.
11
12
List of Acronyms
BMS
MEMS
Boston Microsystems
Micro Electrical Mechanical System
SiC
Silicon Carbide
FEM
TLM
ADINA
NIST
Finite Element Modeling
Transmission Line Method
Automatic Dynamic Incremental Nonlinear Analysis
National Institute for Standards and Tests
13
14
Symbols
B
Temperature gradient interpolation gradient
c
Specific heat, J/kg-K
e
Ed
H
h
k
k
K
Kc
L
P
m*
ND
n
qdot
Elementary charge, C
Donor energy, J
Element temperature interpolation matrix
Convective heat transfer coefficient, W/m 2 -K
Thermal conductivity, W/m-K
Boltzmann constant, J/K
Conductivity matrix
Convection matrix
Length, m
Power, W
Effective mass, kg
Doping density, cm-3
Density of free electrons, cm-3
Heat generation per unit volume
Heat flow input, W
Heat transfer rate, W
Heat flux, W/m 2
Internal heat generation,2 W/m-K
Surface heat flow, W/m
Q
q
q"
qB
qS
R
T
TS
Tinf
t
V
Resistance, Ohm
Temperature, K
Surface temperature, K
Temperature of and infinite mass of surrounding air
Thickness
Volume, m
w
Width, m
x
0
O
0'
Position, m
Virtual temperature distribution
Temperature distribution
Heat change with position, heat flow, W/m
Mobility, cm 2 /V-s
3
Resistivity, Ohm-cm, density, kg/m
Electrical conductivity, 1/Ohm-cm
Thermal expansion coefficient, K~1
p
G
a
15
16
Chapter
1
Introduction
1.1 Project Overview
Micro-machined chemical sensing devices improve the functionality of chemical sensors
while reducing size, lowering power requirements, lowering cost, and improving manufacturability compared to previous designs [1]; previous designs of such systems revolve
around large, costly, and cumbersome devices that have slow response times, poor selectivity, long-term drift, and high power input [2]. Micro-sensors are power efficient, easy to
use, and allow for long term and permanent chemical sensing use. Silicon micro-sensors
have been successfully used in chemical sensing applications [1], but silicon lacks the
robustness to operate at high temperatures of 5000 C or more. Silicon carbide (SiC) is
emerging as the new material of choice for sensing applications; SiC not only allows
higher temperature use, but also has a larger band gap and higher thermal conductivity
than silicon. SiC is chemically inert, making it ideal for operation in an adverse environment [3,4].
Development of the necessary processing and manufacturing techniques to make SiC
chemical sensors possible has been worked on by Boston Microsystems (BMS), a small
micro-fabrication company based out of Woburn, MA. BMS is sponsoring this research to
17
1: Introduction
Chap~ter
te1:Itouto
18
18Ch
-SiC etch
stop
N-SiC
Substrate
P-n junction
Figure 1.1: Basic design
develop SiC chemical sensors for common, commercial use. To make this device practical, the development of an efficient thermal design is needed to reduce the power requirements for a SiC chemical sensing device. This development work requires the exploration
of different geometric configurations and the use of heat transfer analysis, both analytical
and numerical, to optimize the performance of the SiC micro-sensor.
1.2 Basic Device Overview
SiC is a semiconductor material and can be doped with nitrogen (n-type) and with aluminum (p-type). The n-type can be preferentially etched using a photochemical etch stop
process developed by BMS to create a plate, or "bridge," as is shown in Fig. 1.1. When
current is made to flow in the under etched plate, or bridge, resistive heating occurs,
increasing the plate's temperature. Sensing film, such as a conductometric semiconducting
oxide (eg. tin oxide), can be deposited on the top of the plate. This sensing film will react
differently to different chemicals at different temperatures; this reaction is measured by
changes in the electrical properties of the sensing film. For example, a tin oxide film is
sensitive to reducing gases such as CO, H 2 , or acetone. At high temperatures the tin
Section 1.3: Project Objectives
Section 1.3: Project Objectives
19
19
oxide's conductance can be increased by as much as 25% by the presence and concentration of CO, H 2 , or acetone. This conductance change occurs because of the absorption and
desorption of the chemical being sensed onto the tin oxide film [2], which effects the oxygen vacancy concentration in the film and hence its hole concentration. The correlation
between electrical behavior and temperature with different films has been documented in
work done by Semancik and Cavicchi [1] and will be discussed in greater detail later.
Improvements are made in the performance of the SiC micro-sensor by changing the
design of the plate section. Heat transfer modeling is used to maximize the heating that
will occur in the plate, minimizing power usage and heat losses. This work focuses on the
plate section design and the thermal modeling of the micro-sensor.
1.3 Project Objectives
Design drawbacks existing in current chemical sensing technology determined several
objectives for the plate design. These include manufacturability, electronics compatibly,
temperature uniformity, fast time response, low power draw, and high operating temperature. These requirements are the guidelines used for the designs described in this thesis.
Manufacturability of the sensor is the first design driver; the sensor must be designed
within the constraints of current manufacturing capability. The sensor also must be
designed to survive processing; steps in the processing, such as lithography, expose the
chip to both high frequency and static loads. Reducing cost is an additional manufacturing
concern. Fortunately, because of the high yield from each SiC wafer used to manufacture
the hotplates, such micro electrical mechanical devices (MEMS) are relatively inexpen-
sive [5].
In addition to manufacturability, the SiC micro-sensor must be compatible with low
cost electronics. Electronics are used to control the hotplate's temperature and heating
20
Cha ter 1:YIntrodu -irn
pr
characteristics, as well as sense the changes in conductivity of the sensing film. Expensive
electronics would prohibit the use of micro-sensors as a replacement for the more costly
sensors used today. Necessary to keeping the cost of electronics down is lower power, low
voltage hotplates that are simple to operate.
Temperature uniformity over the hotplate is also crucial; assuring the chemical selectivity of the sensing film remains high. Since these measurements are dependent on equilibrium of oxygen vacancies in the film, it is critical that the temperature remain uniform
over the sensing film [2]. To minimize this error an objective of less than 1% relative temperature variation over the plate is desired.
Time response is also important. Fast time response is important to quick sensor
cycling, minimizing power requirements, and real time sensing capabilities. Response
time is an important area for chemical sensor development in general, allowing for virtual
real time information processing [5]. Applications such as combustion control require millisecond sensor response times to allow active feedback based upon the sensing results.
Low power has a direct relation to low cost electronics; it allows for simple electronics
and the use of common batteries. Many of the applications for this micro-sensor are
remote sensing related, where the sensor operates off a battery and transmits sensor data.
With such applications sensor life is important. A power efficient sensor can be operated
with infrequent battery replacement. The objective of this project is to develop a sensor
that operates on 50 mW or less, allowing it to operate off common, readily available, batteries.
The final requirement for such a sensor is high temperature capability. The plate
should be designed to achieve temperatures of above 1300 K while minimizing the power
required to achieve such high temperatures. The high temperature capability assures the
sensor can detect most chemicals using the appropriate sensing films.
21
Section 1.4: Thesis Overview
These factors served as the design focal points throughout this work and will be used
for comparison of the different designs.
1.4 Thesis Overview
This thesis is organized in a manner that follows the analysis steps taken during the design
of this SiC micro-sensor. The following chapter provides the basic background of microsensor operations. It then moves on to an analysis of the initial design, which is a simple
plate, similar to the one shown in Fig. 1.1. The redesign will be focused on in Chapter 4,
including a discussion of the analysis techniques used to model the designs. Chapter 5 will
cover the design of tethers. Tethers are bridges used to hold the hotplate, reduce conductive heat loss, and provide localized heating. Chapter 6 covers the final design of the sensor. An analysis, including experimental results,
is then discussed evaluating the
temperature dependent properties of SiC in Chapter 7, focusing on resistivity and thermal
conductivity. Finally, the experimental tests of the sensor are analyzed and compared to
the model results in Chapter 8, followed by conclusions and suggestions for design and
modeling improvements.
The design and analysis of the hotplate will follow four major design changes and use
both analytical and numerical solution techniques. Figure 1.2 shows the basic layout of
these four designs and the progression of the designs from design 1 to design 4. Design
improvements are achieved by the increasing heating in the tethers, reducing heat loss out
of the plate, and using geometry to position heat generation in the most efficient areas.
Chapter
Introduction
1: Introduction
Chan~ter 1:
22
22
Design 1: Bridge
(Origial Design)
Design 2: Mini tethers
kz
Design 4: Necking
Design 3: Tethers
Figure 1.2: Basic design layouts
Chapter
2
Background
2.1 Chapter Overview
This chapter covers the operation of the SiC micro-hotplate designed for this project. It
includes a description of the p-n junction used in this design, material properties, and the
electrical contacts used in the device.
2.2 Material
The material chosen for the micro-sensor is silicon carbide (SiC). This material was chosen for many reasons, including its high operating temperatures and excellent thermal conductivity, as well as being a good semiconductor. The Cree company's single crystal 6H
SiC [6] is used for this device. Some of the physical properties of this material are listed in
Table 2.1.
Density
Specific Heat
Themial Conducity
3.211g/cm321
580 J/kg
3.0-3.8 W/cm*
3.03 e
Bandgap
Resistivity Range (specific vakie dependent on doping):
.04-.09 OHM-,
N-type
1.0-5.0 OHM-cmn
P-type
Table 2.1: SiC room temperature properties [6,7,8].
23
24
Chaoter 2: Backgiround
Many of the properties in Table 2.1 are temperature dependent and require some additional analysis and experimentation to determine their properties as the hotplate heats to
high temperature. The temperature dependent thermal conductivity and resistivity are
important to the modeling of the designs discussed in this work. To account for this effect
the temperature dependent properties are measured and discussed in the final chapters of
this work. There the design of experimental structures to measure electrical resistivity and
thermal conductivity as a function of temperature are discussed. These chapters also
include experimental results obtained from these devices.
SiC is an excellent semiconductor for high temperature chemical sensing because of
its large band gap, good electrical conductivity, and high operating temperature. SiC is a
wide energy band gap material, with a band gap of 3.03 eV [6]. This wide band gap allows
SiC to operate at high temperatures without suffering from intrinsic conduction effects,
which cause a significant decrease in electrical resistivity. It is approximated that at temperatures above 1800 K [10] SiC begins to behave intrinsically, exciting valence band
electrons into the conduction band and causing the decrease in resistivity. The wide band
gap also allows the electrical properties of the SiC to be controlled by doping. This allows
currents and voltages to be optimized for the electronics being used to control the microhotplate. It is these properties that make SiC an excellent choice for these micro-sensors.
2.3 P-n Junctions
The SiC sensors discussed here are fabricated from a three-layered SiC wafer. The wafer
consists of a p-layer and a n-layer on a n-substrate (see Fig. 2.1). The substrate has a thick-
25
25
Section 2.4: Chemical Sensing
Section 2.4: Chemical Sensing
n-type
1gm
350 gm
n- substrate
p-type
Figure 2.1: Structure of unetched wafer
ness of 350 gm, the p-type layer is 2 gm thick, and the top n-layer is 1 gm thick. The top p
and n-layer SiC serve as part of a proprietary sensor transduction mechanism developed
by BMS with the top n-layer used as a heater. The p-n junction between the top n and p
layers electronically isolates the top n-layer, allowing electricity to conduct through the nlayer without current leakage to the underlying layers. The n-substrate provides support
for the micro-hotplate.
2.4 Chemical Sensing
A critical aspect of a SiC chemical sensor is the films used for sensing. Typical micro electrical mechanical system (MEMS) sensors use oxides to detect physical, chemical, and
biological characteristics of different chemicals. Oxides exhibit a wide range of properties
which make them useful for measuring the mechanical and biological properties of different substances [5]. Chemicals can be detected by a variety of methods, including electrical
resistivity, mechanical deflection, resonance principles, capacitance changes, or calorimetric effects [1]. The electrical resistivity method will be the method used for the sensor
developed in this work. The method entails measuring the changes in the electrical resis-
26
Chapter 2: Backgr
d
tivity of the sensing film with changes in temperature, and correlating the changes to the
presence of specific chemicals. This method has also been called conductometric sensing
[1]. The micro-hotplate designed in this work serves as a platform for heating the sensing
films to their operating temperatures.
Absorption of molecules onto the surface of the sensing film and diffusion of oxygen
into and out of the film's interior are the main mechanisms for conductometric sensing;
this absorption and diffusion cause changes in the electrical conductivity of the film.
Increasing temperature causes change in the partial pressure of oxygen, increasing oxygen
vacancies or interstitials sites [5]. This allows the absorption of chemicals, creating donors
and acceptors. The addition of donors or acceptors changes the electrical conductivity of
the sensing film, which can be measured and correlated to the chemicals present in the
measured gas. Materials that are dependent on changes in their bulk resistances must
either be highly porous or heated to high temperature in order to assure adequate diffusion
[9].
A high level of selectivity is required in sensing films in order to be able to distinguish
between several different chemicals and to determine amounts present. Two methods are
used to achieve this selectivity, "materials selectivity" and "kinetic selectivity." Materials
selectivity is using compositionally different films to detect different chemicals and properties [1]. Developing a picture of the chemical make-up of a gas is completed by comparing the reactions between different films. Kinetic selectivity uses rapid heating of the films
and measures resistive changes in relation to rapid changes in the temperature. This
response can then be correlated to the type and the amounts of the chemicals present [1].
Use of arrays of different types of sensors can be used in either case to allow greater selectivity.
Section 2.4: Chemical Sensing
Section 2.4: Chemical Sensing
27
27
Figure 2.2: Programmed temperature response of a tin oxide micro-hotplate to a series of
organic vapors (from NIST) [1]
Figure 2.2 shows the measurement capabilities using kinetic selectivity. The device
used to obtain these results is a silicon based device with a SiO 2 substrate and a coil heater
developed by NIST [1]. On top of this device is deposited a tin oxide sensing film [1].
Contacts are attached to the sensing film to measure the change in electrical properties.
Figure 2.2 represents an example of measurements made during a testing of the tin oxide
sensing film. The test involves introducing the sensor to several different chemicals and
measuring conductance of the tin oxide over several, ramped temperature sweeps. The
temperature is ramped up over time to a peak, then the device is cooled, and the temperature is ramped again. This cycle is repeated, producing the heating pattern shown in the
Fig.2.2 by the temperature bars across the horizontal axis. The results show the correlation
between temperature and conductance in relation to several different chemicals, as well as
the repeatability of the results. Each different chemical has a clear and distinct effect on
the tin oxide's conductance as the tin oxide is heated over time. This change in conduc-
28
Chapter 2: Backgr
d
tance can be correlated to type and amount of chemicals present. This measurement technique has been developed and tested by the National Institute for Standards and Tests
(NIST).
2.5 Conclusions
The measurement techniques developed by the NIST using Silicon Oxide heaters and different sensing films can be applied to SiC based micro-hotplates to make micro-sensors.
These SiC based micro-hotplates are expected to out perform the Si0
2
used by NIST
because of the superior high temperature properties of SiC. Further performance improvements can be gained by thermally modeling the SiC micro-hotplates and using the hotplate's geometry to optimize the performance of the plate, and is the focus of this thesis.
Chapter
3
Initial Design Analysis
3.1 Chapter Overview
Prior to this research, Boston Micro Systems fabricated and tested a very basic initial hotplate design for chemical sensing applications to verify the manufacturing techniques and
processes necessary for SiC micro-sensor development. The device performed poorly,
however, due to contact overheating. In this chapter, an analysis of this initial design is
discussed that will serve as a baseline for follow-on designs and improvements. In addition, this chapter will cover the layout and the geometry of the device. A discussion of the
device's advantages and its drawbacks is included; design improvements are identified for
further analysis in later chapters.
3.2 Geometry
The geometry of BMS's original device is a simple plate that consists of a 200 x 200 jim
bridge-like structure as shown in Fig. 3.1. The design uses a p-n junction material with a
n-type substrate, a p-type middle layer, and a n-type top layer. The n-substrate is removed
from below a 200 x 200 jim region of the top p and n-layers leaving a suspended bridge.
The bridge section is referred to as the plate and the whole device is called the chip.
29
30
Chapter 3: Initial Design Analysis
Plate
Chip
N-Layer
P-Layer
N substrate
Figure 3.1: Initial plate design
3.3 Modeling Assumptions
A simple analysis of the initial plate design can be performed analytically. Several key
assumptions are made to develop this simple model. The first is that convective heat transfer to the air surrounding from the plate is negligible. This can be shown using Newton's
law of cooling [11],
q" = h(Ts
-
Tinf)
(3.1)
where h is the convective heat transfer coefficient, TS is forced convection, and Tinf at is
the temperature of the surrounding air. Typical heat transfer coefficients to the air range
from 10 W/m 2-K for natural convection to 1000 W/m 2-K for forced convection. For
forced convection, assuming the surrounding air is at room temperature (with h=1000 W/
m-K) and the surface temperature of the plate is 1000 K, q" is 701,000 W/m 2 . When considered with the size of the plate the heat transfer loss is only 0.028 W. In the more reason-
31
Section 3.3: Modeling Assumptions
able natural convection case the heat transfer loss is 0.00028 W. For comparison to
conduction, assume that the center of the plate is operating at 1000 K and the ends are at
room temperature. Assuming one-dimensional heat conduction the conductive heat transfer can be calculated using
q = kA
dx
(3.2)
where, k is the thermal conductivity and A is the cross-sectional area. The heat transfer
due to conduction, using the cross sectional area of the plate, is 1 W. That is two orders of
magnitude greater then the high speed flow case, and four orders of magnitude greater
then the low speed flow case. Based on these results convective effects can be neglected in
the modeling. This assumption is carried through the analysis of all of the designs. The
small size of the plate causes conduction to be the dominant effect since the surface of the
plate is too small for convection to become a significant factor.
The ends of the plate are assumed to be at room temperature for this analysis. This
assumption is reasonable because the chip is significantly larger, 100,000 times larger,
than the plate and is thus able to absorb the heat lost from conduction out of the plate. In a
more sophisticated finite element model discussed later the validity of this assumption
will be shown (see Chapter 5).
The thermal and electrical properties are also assumed to be temperature independent.
This assumption, while reasonable for basic analysis, cannot be maintained in more accurate models since both electrical and thermal properties are highly dependent on temperature. As such, an entire experiment has been developed to determine the thermal and
electrical conductivities for doped SiC in relation to temperature (see Chapter 7). Since the
thermal conductivity of SiC decreases with increasing temperature the power required to
heat the hotplate will improve as temperature increases [10]. It can therefore be assumed
32
Chapter 3: Initial Design Analysis
that this assumption will represent a worst case scenario for the plate performance. In later
iterations, this assumption will be replaced with reasonable temperature dependent properties found from the experimental results.
One final significant assumption is that the electrical current flow through the plate is
uniform. No local heating effects in the plate due to non-uniformities will be considered in
the modeling of the hotplate. This is a reasonable assumption considering the size of the
plate as well as the excellent thermal conductivity of the SiC. The high thermal conductivity in SiC, especially at high temperatures, tends to smooth the temperature distribution. In
Chapter 6, where the final necked design shown in Fig. 1.2 is analyzed, this assumption
will be discussed further.
Internal resistive heating is the mechanism used to obtain high temperatures. For this
analysis resistance becomes a critical factor for producing the heat in the plate; the plate
section has a resistance of 890 Ohms. Using these assumptions the model of the plate can
now be discussed.
3.4 Performance Analysis of Original Design
With these assumptions the initial plate design is analyzed using both analytical methods
and finite difference methods. The hotplate is first analyzed analytically using Poisson's
equation for heat diffusion with a source term and a constant thermal conductivity [11],
-4 = kV 2T
(3.3)
where q is the internal heat generation per unit volume and k is the thermal conductivity. A
one-dimensional solution of this equation is of the form
T =
-_j - x2 + A - x + B
2k
(3.4)
where A and B are constants of integration that will be determnined by the boundary condi-
Section 3.4: Performance Analysis of Original Desig
33
tions of the plate.
The boundary conditions used to find A and B are calculated from the assumption that
the chip is at room temperature. At both ends of the plate, where x is zero and x is L, the
length of the plate, the temperature will be Trt = 298.15 K. Using these boundary conditions A and B are calculated to be
A =4
2k
B =
(3.5)
rt
The solution is now written as
T = -- 1-x2+SI - x+T
t
2)
2k
-
(3.6)
The value q is an important aspect of this equation since it determines the effect of the
internal heating on the temperature distribution. It is calculated from the following:
.
q
2
2 2 -
t w
(3.7)
Equation 3.7 is based on the power produced by resistive heating per unit volume. In Eq.
3.7, p is the resistivity of SiC, I is the current in the plate, and t and w are the plate's thickness and width, respectively. The temperature distribution as a function of position given
in Eq. 3.6 is plotted in Fig. 3.2 for values of k = 230 W/m-K, q = 3.12 x 1013 W/m 3 , L 200 pm, and w = 200 gim. Under these conditions, the total power dissipated in the plate is
1.3 W. The plot in Fig. 3.2 is an inverse parabola and show the large temperature distribution over the plate.
Following this work, a more sophisticated two-dimensional model was developed
using a finite difference method. This method involves dividing the plate up into several
2-d squares and using boundary conditions to average each point in the grid with it sur-
34
Chapter 3: Initial Design Analysis
1200
1000
800
-
600
E
400
0
200
0
0
0.0001
0.00005
0.00015
0.0002
x-position (m)
Figure 3.2: Analytical temperature distribution over the initial plate design
rounding points. By iterating the solution between each successive step the error decreases
to a set size. The plate was broken up into a grid of 10,000 2 x 2 jim squares. Using such a
grid a model can be developed using Eq. 3.8 and Fig. 3.3 [11],
T
m, n
= Tm,n+1+Tm,n-1 +m+1,n
4-
m-1,n
(3.8)
Due to the electrical current flow through it, the plate is internally heated, so an additional
term must be added to account for this heat generation,
P
AT ml,nn
(3.9)
-
t -k
where P represents the power introduced by each individual 2x2 jim element in the grid
due to resistive heating and t is the plate thickness, which is 3 jim for this case. This gives
the following for the finite difference model:
T
mn,n
- Tm, n + 1+ Tm, n- 1 + Tm+ 1, n + T
4
im1, n + P
(3.10)
t -k.
The power is determined by calculating a power density for the device by taking the entire
plate resistance times the square of the current and dividing by the plate's volume. If, as it
35
Section 3.5: Conclusions
m, n+1
Ay
m, n
m+1, n
m-1, n 4±
Ax
m, n-1
Figure 3.3: Interior grid designations for finite difference method
is assumed, current density is uniform, the power is the power density times the volume of
each, individual, element. For the plate being modeled there is a power density of 3.23 x
1013 W/m 3 , producing an elemental power generation of 0.000129 W. A further discussion of this modeling technique can be found in Appendix A. It includes a discussion of
equations and methods used to calculate edge effects and including boundary conditions in
the analysis.
The data was entered into an ExcelTM spreadsheet and iterated using the ExcelTM calculation feature until the error was less then one thousandth of a degree. The error is calculated by ExcelTM by taking each node's temperature for the prior iteration and comparing
it to the current iteration. Once the difference between the two iterations is less then the set
error value of one thousandth of a degree the calculation is stopped, displaying the results.
The results of this calculation are in Fig. 3.4. These results match the results from the analytical analysis, with a power requirement of 1.3 W.
3.5 Conclusions
Several observations can be made about this design. First, this design requires a very high
power to operate at 1000 K. At such a high power consumption, the chip is not practical
36
Chapter 3: Initial Design Analysis
Temp (K)
* 900-1000
0800-900
0 700-800
0600-700
0500-600
0 400-500
IM300-400
Figure 3.4: Temperature distribution over plate
for use in the applications discussed earlier and would have little advantage over existing
systems. The high power consumption comes from significant thermal contact between
the plate and chip, which allows significant conductive heat loss into the large surrounding
chip.
A second concern of such a design is a lack of temperature uniformity. The temperature variations over the plate covers temperatures from 298 K to 1000 K. Such a variation
of temperature prevents the measurement of the sensing films conductivity from being
accurate. With this temperature distribution the design does not meet the temperature uniformity requirements set forth earlier in the work.
The failure of the design in testing can be attributed to the small contact pads used to
make electrical connections between the device and the controlling electronics. These
contact pads, due to their smaller size and geometry, have a electrical contact resistance
comparable to the plate. Because of the high power needed to heat the plate the contacts
will also heat, and their large resistances will cause them to heat to high temperature,
degrading the electrical contacts and ultimately destroying the device.
Chapter
4
First Design Iteration
4.1 Chapter Overview
This chapter will look at some design modifications made to improve the performance of
the initial plate design. The most important and significant change made minimizes the
conductive heat loss from the plate to the chip. A detailed description of the change will be
discussed as well as a detailed analysis of the performance of the new design. Advantages
and disadvantages will be delineated for further design improvement.
4.2 Geometry
The next design is shown in Fig. 4.1. The center plate is 200 x 200 tm and is attached to
the rest of the chip by four 20 im long, 10 gm wide, tethers, one in each corner. Since this
new geometry reduces the contact area between the plate and the chip by a factor of 10,
the conductive heat transfer out of the chip is expected to be significantly less then in the
previous design.
37
Chapter 4: First Design Iteration
38
11R
Tethers connected to chip
200 Rm
10 RM
3
200 Rm
20 Rm
Tethers connected to chip
Figure 4.1: First design iteration (plate section only)
4.3 Modeling Assumptions
A finite difference model was used to analyze this design. The assumptions used in this
model mirror those applied to the model discussed in Chapter 3. The convective heat
losses are assumed negligible, the current density, and hence heating, is assumed uniform,
and the surrounding chip is assumed to remain at room temperature. The surrounding
boundary condition is applied to the chip end of the tethers that connect the plate to the
chip.
Internal heat generation is calculated separately for the tether sections and the plate
section. Each of these sections will have a different resistance determined by their geometry. The resistivity of n-type Si-C doped at 10-19 cm-3 , as is used for this modeling, is
0.00089 Ohm-in [6], thus producing a resistivity for the tethers of 1780 Ohms each and a
resistivity for the plate of 890 Ohms. This significant difference in resistivity is a critical
factor in this and later designs. It causes most heating to occur in the tethers as current is
passed through them, into the plate, and out the opposing tether. The final important
Section 4.4: Performance Analysis of First Iteration Design
39
assumption, as was made in Chapter 3 for the plate design, is that the material properties
of the SiC do not change with temperature.
4.4 Performance Analysis of First Iteration Design
For the finite differencing model of this new hotplate design 2x2 gm elements were used
to develop the finite differencing grid. The internal heat generation used in Eq. 3.9 will be
different between elements used in the tethers and elements used in the plate. The power
generation will be based on resistances calculated from the tether and plate geometries.
Grid elements modeling the tethers will have the power produced from the tethers resistance, and grid elements modeling the plate will have power produced from the plate resitance. Equation 3.10 was used to calculate the results and the edge effect equations
discussed in Appendix A.
The results are obtained from ExcelTM after running the iterative calculation option
until the error between each successive step is less then one thousandth of a degree (see
Fig. 4.2). The current required for the plate was found to be 0.011 A, in order to achieve a
peak temperature of 1000 K. Thus, the operating power of the design is 0.309 W, an order
of magnitude improvement over the design discussed in Chapter 3. The power dissipated
in each of the tethers is 0.051 W, and 0.103 W for the plate; power for all four tethers is
0.206 W, or twice as much as the plate. The temperature distribution of this design can be
seen in Fig. 4.2. In this picture only temperatures from 950 K to 1010 K are shown, the
peak temperature is shown in the diamond shape center region and is approximately 1000
K. Temperature distribution is improved over the previous design, as well the required
operating power to achieve temperatures of 1000 K. Figure 4.3 shows the temperature distribution of the plate along a line AA' in Fig. 4.2, and along a line BB'.
Chapter 4: First Design Iteration
40
Temp (K)
3 1000-1010
A 0990-1000
m 980-990
E 970-980
0 960-970
m 950-960
B
B'
Figure 4.2: Temperature distribution over plate of first design iteration
1010
990
970
CL
AA'
950
--
BB'
E
CD 930
910
890
20
40
60
80
100 120
140 160
180 200 220
X-position (micro-m)
Figure 4.3: Temperature distribution over the plate center and plate edges respectively
Figure 4.3 shows that the temperature distribution is much improved over the previous
design. In the previous design the distribution was an inverted parabola and the temperature ranged from 298.15 K to 1000K. The distribution over the center of the plate for this
tether design is less then +/- 20 degrees, but is still over 100 degrees for the edges. This is
Section 4.4: Performance Analysis of First Iteration Design
41
Temp (K)
l 1000-1010
A'A
M990-1000
o9980-990
o 970-980
* 960-970
o 950-960
B'B
Figure 4.4: Temperature distribution over 40 gm tether design
an improvement, but still does not meet the goals outlined in Chapter 1, requiring a 1%
relative temperature variation over the plate, or +/-10 degrees for a plate at 1000 K. The
improved distribution can be attributed to SiC's excellent thermal conductivity coupled
with the heat generation in the tethers. This allows the heat generated from the much
higher power dissipating tethers to distribute to the rest of the plate.
From these results it can be concluded that lengthening the tethers, thus increasing the
resistivity of the tethers, improves the heating of the micro-hotplate. An analysis of a
model using 40 prm tethers instead of 20 pm tethers gives the following changes and
improvements. This increases the resistance of each tether to 3560 Ohms each, producing
an overall resistance of 4450 Ohms for the entire plate and tether combination. A current
of 0.007 A will heat the center of the plate to 1000 K. At this current the total power draw
of the device is 0.218 W, a ten fold improvement over the shorter tethers. Each tether dissipates 0.0436 W, and the plate draws the same 0.0436 W as in the shorter tether design.
Thus, the tethers as a whole dissipate four times the power as that in the plate, or 0.1744
W. That is a doubling of the ratio of heating power between tethers and plate from the
shorter tether design. Figure 4.4 shows the temperature distribution over this design. The
First Design Iteration
Chaoter 4:
Chapter 4: First Design Iteration
42
42
1010
990
970
-BB'
950-
-AA'
1~
C)
0.
930910 -890
40
60
80
100 120 140
160 180 200 220 240
X-position (micro-m)
Figure 4.5: Center and end temperature distribtuion for 40 grm tethers
high temperature zone, those areas close to 1000 K, is much larger then in the previous
short tether design. The center, along line AA' in Fig. 4.4, and edge, along line BB', crosssection temperatures can be found in the Fig. 4.5. The temperature distribution over the
plate for this design is closer to +/- 50 degrees, a two fold improvement over the shorter
tether design.
4.5 Conclusions
The performance improvements of the tether design over the initial design are significant
for several reasons: power improvements, temperature uniformity, and heating efficiency.
First, there is an order of magnitude reduction in the power required to achieve 1000 K
between the tether designs and the design discussed in Chapter 3. This improvement is
made by decreasing heat loss from the plate and providing heating from the more power
efficient tethers. Temperature uniformity is also greatly improved, improving sensor reli-
ability.
Section 4.5: Conclusions
43
This work suggests that lengthening the tethers will result in improved thermal performance: however other concerns must be considered, such as packaging, structural stability, and electrical performance. These factors will be considered in the designs discussed
in the following chapters.
44
Chapter 4: First Design Iteration
Chapter
5
Second Design Iteration
5.1 Chapter Overview
Now that tethers have been identified as a important design feature, this chapter will analyze different tether designs, optimizing the sensors performance with respect to design
variable such as length, width, and geometry. First, an analysis of tether length is presented, and secondly consideration of the geometry of the tethers is discussed. New analysis techniques are utilized including the use of finite element modeling (FEM) and the
FEM program ADINA. FEM provides a more accurate solutions to the model as well as
being more computationally efficient then finite differencing techniques. A discussion of
FEM methods will be included as it pertains to this modeling. Further discussion of this
method can be found in Appendix B.
5.2 Geometry of Long Tethered Plate
As shown in Fig. 5.1, the plate is 200 x 200 km. It is now supported by four 240 gm long,
10 gm wide, tethers sections that connect the plate to the chip. These tethers are
"wrapped" around the plate to help prevent failure when the plate is fatigued or stressed
due to thermal expansion.
45
46
Chapter 5: Second Design Iteration
Tethers
connected to
chip
10 tm
9m
/200m3
Tethers
onnected to
chip
200 gm tethers
Figure 5.1: Long tether design layout
This spider like design is advantageous because it helps to minimize stress in the tethers
and should prevent the chip from buckling or bending from thermal expansion induced
stresses. The material composition is the same as in previous design, with a n-substrate, a
p-layer, and a top n-layer. The p and n-layer remain in the hotplate section while the n-substrate is removed underneath this section.
One geometric consideration of the plate design is the stress placed on the plate during
manufacturing. This was not a concern in previous designs, but as the tethers length
increases it becomes a greater issue. During the processing there are photolithography
steps where the device is spun at approximately 3000 rpm. The sensor needs to structurally survive during this processing phase. To perform a simple structural analysis, the 240
gm tethers are treated as individual cantilevers with a force loading at their ends of
approximately one quarter of the weight of the center plate. Using a modulus of 450 GPa
for SiC [12], an end deflection of the device can be calculated and checked. The moment
Section 5.3: Modeling Assumptions and Calculations for Long Tethered Plate
47
of inertia is calculated using the equation for a rectangular cross-section [13]. A deflection
of 3.58 x 10-4 tm is calculated for a load of 9.15 x 10-1 0N, which represents the force of
the weight of the plate. This is a small deflection and leaves plenty of clearance between
the plate and surrounding chip. The natural frequency of the tethers is also calculated
using these parameters and is found to be 165.5 KHz, which is well above the 3000 rpm,
or 50 Hz, loading the photolithography processing step produces.
5.3 Modeling Assumptions and Calculations for Long Tethered Plate
Two techniques are used in this analysis for modeling the long tether hotplate design. The
first is an analysis using the same finite differencing method as used previously. The
assumptions used for the short tether hotplates still apply, including room temperature
boundary conditions at the end of the tethers, non-temperature dependent properties, and
no convective heat loss. The ends of the tethers, where they make contact with the chip,
are still assumed to be at room temperature. The power inputs for each tether are recalculated to accommodate the longer tethers. The resistance of the tethers increase to 21360
Ohms each by taking 0.00089 Ohms-in times the tether length of 240 im, and divided by
the cross-sectional area of 10
mi2 . This resistance is a 10 fold increase over the shorter
tether designs. The plate resistivity will remain at 890 Ohms since its geometry has not
changed.
The second analysis is completed using finite elements and ADINA, a FEM modeling
program [14]. A finite element model is a more accurate and efficient model then the finite
difference model. While finite differencing is an ideal system for modeling simpler structures, with its simplicity and ease of use, it becomes cumbersome with added structural
complexity, and loses accuracy. A FEM approach using a program such as ADINA is a
much more accurate and robust method compared to that of finite differencing.
trto
Design Iteration
eodDsg
Chapter
Catr5 5: Second
48
48
A FEM model is based on the "principle of virtual work". This principle states that for
the equilibrium of a body it is required that for any small virtual displacements, in this
case changes in temperature, the total internal virtual work must equal the external virtual
work. This statement can be shown in the following equation:
5qBdV+
,Tko'dV =
V
V
0s sdS+
Q
(5.1)
S
Eq. 5.1[15] is the "principle of virtual temperature", since it is the heat transfer representation of the "principle of virtual work". The right hand side represents the external virtual
work, and the left hand side represents the internal virtual work. 0 represents the temperature, and the bar over 0 represents the virtual temperature distribution being considered. V
represents the integration over the volume of body being considered, such as in Figure 5.2,
and S represents the surface. The internal heat generation is represented by qBand the heat
flow into the body is qs.
Q' represents the concentrated heat flow inputs, and is actually
neglected for this analysis because the only heat flow is internally generated. 0' is the representation of the change in temperature with change in position. The thermal conductivity
matrix is represented by k.
The "principle of virtual temperature" refers to virtual temperature changes in the
body, but do not represent actual temperature changes. Virtual temperatures are a thought
experiment used to establish the equilibrium equation in Eq. 5.1 [15]. If the correct 0' is
known, then Eq. 5.1 holds true for any arbitrary virtual displacement that is continuous
and has the same prescribed boundary conditions as the body. If 5.1 is not true in such a
case, the 0' is not the exact temperature changes in the body. The concept of virtual temperatures and virtual work is a rather complex subject, and since it is not the focus of this
work will not be discussed further. For more detailed explanations and discussion of this
Secton
53: MdeliQ Asuptions and Calculations for Long Tethered Plate
Section 5.3: Modeling Assumptions and Calculations for Long Tethered Plate
49
49
Surface
4-
node
09'
Figure 5.2: Fintie element breakdown
concept readers are referred to Bathe and Bucahanan's works [15, 16], or any other FEM
text. The "principle of virtual temperature" will become important in the next section.
First, to understand the FEM analysis in this work, the important assumptions and
their effect on boundary conditions, the basic model construction must be explained. Any
body can be divided up into many different elements. Figure 5.2 shows a body and one
element in the body.
The body has boundary conditions and loadings placed on it to fit the object being
modeling; in the case of the hotplate these are in the form of temperature boundary conditions placed on the chip's edges. The body is then approximated using many of these elements put together by a process called meshing. The elements can have any shape,
although there are some efficient meshing techniques that will be discussed later. Each
element is made up of nodes and each node has a displacement, in this case a temperature
and temperature change, associated with it. For heat transfer, several other factors can also
be included, such as heat transfer through conduction, convection, and radiation. These
elements put together make up the body of the device, the hotplate for this modeling.
50
For each element m, the following set of equations [15] are true:
0(m)
eS(m)
6(m)
-
(m)g
(5.2)
_
S(m)g
(3)
(m)g .
(5.4)
The temperature vector on the right hand side of these equations represents the matrix of
all nodal point temperatures. H is the element temperature interpolation matrix, B is the
temperature gradient interpolation matrix, and HS is the surface temperature interpolation
matrix. These matrices are critical for solving for the temperature changes in the body.
Before solving for the temperature from these equations the boundary condition temperatures are applied, the edges of the chip are at room temperature. Substituting these equations into Eq. 5.1 and simplifying yields Eq. 5.5, which represents the relation between
heat input and temperature for each node. The virtual temperatures assumed for this analy-
sis are simple unit temperature changes.
itk
c
e
(5.5)
Appendix B contains a detailed explanation of the calculation performed to obtain Eq. 5.5.
Kk is the conductivity matrix and is formed from the temperature gradient interpolation
matrix and the matrix k, which is the thermal conductivity properties of the material (see
Appendix B). Matrix k is a simple matrix made with the thermal conductivity value of SiC
placed along the matrix's diagonal. K' is the convection matrix, and is neglected for this
calculation since convection is ignored because of its negligible effect, as in previous calculations.
Q is
the nodal heat flow input vector and represents internal heat generation by
the nodes, the surface heat input, and other heat inputs. For this model only internal heat
generation needs to be considered as it is the only source of heat.
Qe is the nodal point heat
51
Section 5.3: Modeling Assumptions and Calculations for Long Tethered Plate
concentration due to convective boundary conditions, and can be neglected since convection is not significant (see Chapter 3).
These assumptions leave the following equation to solve:
(5.6)
k
This equation is the governing finite element equation. Kk in this equation expressed as:
k
If (m)T-(m)
kdv (mn)d
.((.7
(5.7)
mV
Eq. 5.7 is constructed by calculating B for each model element, solving the integration for
each element using Eq. 5.7, and summing. B and H become important at this point
because they are critical to the solution. H is a function that defines the positional relation
between each node and the appropriate coordinate for each element based on the local
coordinate system. H represents each node in the element and each degree of freedom. For
the modeling of temperature there is only one degree of freedom in H, that of temperature.
H is thus a 1 row, n column matrix, where n is the number of nodes in the element. Each
position in the matrix represents the temperature of a different node (a further discussion
of the development of H for temperature is included in Appendix B). B, being the temperature-gradient interpolation matrix is dependent on the derivative of H; it is the inverse
Jacobian of H times the derivative of H with respect to each coordinate direction. The
solution gives a B that will be 3 rows, for a 3-D system, and n columns and represents the
heat gradients within the body. With these two matrices known, the operation in equation
5.7 is performed creating Kk, the conductivity matrix. All of this being completed, equation 5.6 is then used to solve for the temperature distribution.
In a steady state, linear case, with appropriate boundary conditions, equation 5.6 is
determinate and a solution is found by simultaneously solving for the unknown values
52
Chapter 5: Second Design Iteration
using the known equations from the matrices. In large systems this process is difficult to
perform by hand as there are hundreds of unknowns and hundreds of equations, so
ADINA performs the integrations of Kk and the calculations required to determine the
solution. Understanding these concepts is important in order to define boundary conditions and assumptions. Boundary conditions will be placed into 6, the term being solved
for in Eq. 5.6. The boundary conditions provide the matrices with enough known variables
to solve for the unknowns in the matrix. Without the boundary conditions the unknowns
would exceed the number of calculable equations.
For this modeling the whole device is used: including the plate, tethers and chip. The
edge of the chip at room temperature is the boundary condition used in this analysis. The
chip is large enough that this is a very reasonable assumption and allows for an analysis of
localized heat build up around the chip where the tethers make contact with chip. As in the
previous models, the convective losses are ignored.
In order to assure accuracy and computational efficiency the type of elements and
number of nodes must be decided upon. Generally the more elements used the more accurate the result, but also the more computationally intensive the process. Each additional
node adds four unknowns, one temperature and three temperature gradients, and four
additional equations to be solved. In many cases computing power is wasted for very fine
grid generation. The nature of the location on the device being modeled determines the
need for accuracy; a location with significant temperature gradients over small areas
should have smaller meshing to account for the changes in temperature. For many areas of
the device it is not necessary to have a fine grid of elements because the temperature gradients are not significant and are easily accounted for with larger meshing; for others, such
as the tethers, a fine grid was used, as this is the area of greatest temperature gradient.
Four, ten, and eleven node elements are allowed by ADINA for this type of calculation. 4
Section 5.4: Finite Difference Results for Long Tethered Design
53
node elements were used in the modeling because the added accuracy is not needed due to
the straight forward heating and the meshing quality.
Experimenting with element sizes determined the final mesh used in this analysis.
Grids with elements of 1 jim were too small and exceeded the available memory capacity
of the computer. A mesh of this refinement creates well over 50,000 elements, each with
four nodes and three degrees of freedom. Grids of larger elements were also tested. 10 jim
was the maximum size, since the tethers are only 10 pm wide. This yielded good results,
but a greater accuracy is needed in the plate section of the device, especially the tethers.
Thus, different element sizes are used for each section. The chip area has very large elements around its edge and decreasing in size towards the plate. The tethers have a very
fine grid and the plate has a coarser grid.
5.4 Finite Difference Results for Long Tethered Design
The finite differencing model was completed using Excel. This model only included the
plate and tethers. The model showed that a current of 15.5 mA was required to achieve
temperatures of approximately 1000 K in the plate center, yielding a total power requirement of 0.0534 W. The power dissipated by each tether is 0.0 128 W each and the plate dissipates 0.00214 W. The plate contribution to the heating is further reduced in this design.
This improves the temperature gradient over the plate section even further. Figure 5.3
shows the analysis results. The yellow section of the plate indicates that there is less than a
+/- 10 degree temperature difference over the plate. Figure 5.4 shows the temperature distribution over the center, along the line AA', and edge, along line BB' of the plate.
Design Iteration
Chaoter 5: Second
Chapter 5: Second Design Iteration
54
54
01000-1010
U990-1000
U 980-990
M970-980
M960-970
U 950-960
M940-950
M930-940
M920-930
B 910-920
U 900-910
A
B
B9
Figure 5.3: Finite difference results for long tether design
10 06-
10 05BB
10
C10
-BB'
10
10
01
10
0
0.00005
0.0001
0.00015
0.0002
X-position (m)
Figure 5.4: Temperature distribution over the center (AA') and edge (BB') of the plate
These results show a significant improvement over the previous designs. The edge
temperature measurement is no longer symmetric due to the spider like positioning of the
Section 5.5: Finite Element Results for Long Tethered Design
55
tethers. Figure 5.4 shows the temperature distribution is improved, giving temperature
variations of less then +/- 5 degrees over the plate. This design meets the temperature uniformity goals set out in Chapter 1. The temperature variation over the plate is less then a
one percent variation in temperature when compared to the plate's temperature of 1000 K.
5.5 Finite Element Results for Long Tethered Design
An ADINA model was built of the plate using the same assumptions as discussed in the
previous sections. The boundary conditions are changed to allow the chip to be included in
the model. The edges of the chip are assumed to be at room temperature. The required
power to achieve temperatures of 1000 K on the plate is 0.054 W, almost an exact match to
the finite difference model. Figure 5.5 shows the temperature distribution over the plate.
The image in Fig. 5.5 shows the plate and tethers, as well as the contacts, but not the entire
chip. The results show a uniform temperature distribution, with temperature varying +/- 5
degrees over the plate. The surrounding chip structure heats up a few degrees due to heating losses out of the tethers, but the effect is negligible, validating the boundary conditions
used in the previous finite differencing and analytical models. The large n-layer rectangles
located at the end of each tether in Fig. 5.5 are the top n-layer material contacts. Metals are
deposited and annealed to these pads to make low resistance electrical contacts to the hotplate. These contact pads will be briefly discussed later in Chapter 8.
5.6 Conclusions
The results of both the finite difference and the finite element analysis give the same solutions. This serves as a check of the validity of both processes. Both methods show significant improvement in plate performance for the long tether designs over the designs
discussed in Chapter 4. The power improvement over the 20 gm long tethers in Chapter 4
Design Iteration
Chanter
trto
eodDsg
Catr5 5: Second
56
56
TEMPE RATURE
TIME 1.000
950.
85D.
75D.
6:50.
550.
46D.
350.
Figure 5.5: Finite element results for 240 gm tether design
is approximately 0.25 W. Temperature distribution is improved from +/- 100 degrees for
the 20 gm long tethers to +/- 5 degrees for the 240 gm long tethers. The higher resistance
240 gm tethers heat up to greater temperatures with less current than the shorter tethers
discussed in Chapter 3. The lower current traveling through the tethers into the plate
reduces the heating and power dissipation in the plate. The plate witll keep the same resistance of 890 Ohms for all of the designs because its geometry will not change. The high
thermal conductivity of SiC tends to maintain the plate at a uniform temperature, as well
as the reduction in plate heating caused by the reduced current. The next step is to consider
what tether length is ideal for these operations and what other tether modifications can be
performed to maximize plate performance.
Chapter
6
Tether Design and the Final
Design
6.1 Chapter Overview
This chapter will consider the performance advantages of the tether design and maximize
the performance of the hotplate. The focus will be on the tethers, using appropriate
assumptions about its surroundings. Consideration will also be made about tether geometry to maximize performance. Finally, the tether improvements made will be applied to the
whole micro-hotplate and an FEM analysis will be performed using ADINA.
6.2 Length Considerations
The tethers were modeled analytically using the same technique as used to model the initial plate design in Chapter 3. Namely,
T = Lx2 +Ax+B -
2k
(6.1)
This equation assumes no convective heat loss and axial direction heat flow down the
tether. The temperature and heat flow across the width of the tether is assumed to be uniform because of the tethers small width and thickness. A and B are determined from the
boundary conditions. The first condition is that the tether end, at x=O, is at room tempera-
57
58
ture. This is again based on the assumption that the chip acts as a large heat sink. The second boundary condition assumes that at a steady state the temperature over the plate
section is uniform. This assumed uniformity will allow the change in temperature between
the plate and the end of the tether connected tot he plate to be zero. This can be shown by
comparing the heat generation for the plate in comparison to the heat generation of the
tethers. For this boundary condition to be true the following must be true:
Pplate «
tethers -
The powers can be compared using the following equation:
2
I pL
2
I pLt
tw k
tw k
t
p
&
(6.2)
where I is the current for the whole device, p is the electrical resistivity of SiC, Lp and Lt
are the lengths of the plate and tether respectively, wP and wt are the widths of the plate
and tether respectively, t is thickness, and k is thermal conductivity of SiC. Reducing Eq.
6.2 produces the following relation:
L
w-E
w
L
w-
w t'
(6.3)
Comparing the two values in Eq. 6.3, using a plate length and width of 200 jIm and tether
length of 240 jim and width of 10 jim, shows that there is 24 times more heat dissipation
in the tethers then in the plate, making the second boundary condition appropriate.
Using these boundary conditions the following are the values for A and B:
A = 4L
k
B = 298.15K
(6.4)
Section 6.2: Length Considerations
Section 6.2: Lentith Considerations
59
59
1200
1000
800 00
E
400 200
0
0
20
40
I
60
I
I
80
100
I
120 140
I
I
160
I
I
180 200 220 240
x-position (micro-m)
Figure 6.1: Temperature distribution over 240 tm tethers
Using Eq. 6.4, Eq. 6.1 becomes:
T
=
2k
x 2 +9Lx+298.15K -
k
(6.5)
Using this equation the temperature distribution of a tether is plotted in Fig. 6.1 using the
following values: q= 5.6 x 1012 W/m 3 , L =240 gim, and k = 230 W/m-K. The distribution
in Fig. 6.1 represents a 0.00155 A current flow for the entire device, with this current
flowing in two tethers and out the opposite two tethers. The same plate with tethers half as
long will heat to only 450 K when subjected to the same 0.00155 A current. Similarly, the
same plate with 360 gm long tethers yields heats to 1800 K when subjected to a 0.00155 A
current. Based on these results, it seems the longer the tether, the better the thermal performance, and the limiting issues become packaging, strength, manufacturing, and electronics. Because of packaging and manufacturing concerns, it was decided to continue using
tethers of the length of 240 gm for analysis of other possible tether geometries.
Chapter 6: Tether Design and the Final Design
60
Tethers
connected
to chipm
200 gm
necking
width
Tethers
connected
to chip
3 gm
240 jim long tethers
Figure 6.2: Necked tether design
6.3 Tether Necking
The design process to this point has highlighted some important ideas for the efficient
operation of a micro-hotplate. The tether designs show that heat does not have to be generated by the plate, but can be generated off the plate and conducted into the plate because of
SiC high thermal conductivity. This allows for the design of ideal heating devices while
reducing the plate sections heating effects that lead to non-uniform heat distribution.
The critical factor for heat generation is resistance, which is dependent on material,
but also on dimension. Adding length to the tethers increases resistance, causing greater
heat generation at lower currents, but the added length also wastes energy heating the
tether far away from the plate where it is not needed, increasing heat losses to the surrounding chip. Any heating that occurs near the connection of the tether to the chip is conducted into the chip and is not used to heat the plate section. A design to counter this
increased heat lost from the tethers to the chip is to neck down the tether near the plate, as
Section 6.3: Tether Necking
61
61
Section 6.3: Tether Necking
wi
wn
L
L
L
x
x-LI
Figure 6.3: Necked tether layout
shown in Fig. 6.2. This necking increases the heating power near the plate without wasting
heating energy to the chip.
Fig. 6.3 shows the basic design layout of the tethers. Using Eq. 6.1 to model this
necked tether design, a necking length can be found that maximizes performance of the
hotplate. The values of Ln , necked length, and w, , necked width, are investigated in this
analysis. The necked and the unnecked section are divided into two separate equations,
respectively. The solutions of the one-dimensional thermal diffusion equations for both
T's are:
T(x)
=
~q 2
-x 1 +Ax+B
2k
2n
2
0O x
L
(6.6)
where L, is the length of the unnecked region of the tether and Ln is the length of the
necked region, as shown in Fig. 6.3. The values qn and qi are the necked region's heat generation per unit volume and the non-necked region's heating per unit volume, respectively.
Four boundary conditions are used to solve for the constants A, B, C, and D. The first is
that the chip end of the tether is at room temperature, as described in the analytical modeling of the non-necked tethers in the previous section. The second is that the heat flow out
of the plate into the tethers due to plate heating is negligible, which was discussed in the
62
Chapter 6: Tether Design and the Final Design
previous section. The final two boundary conditions are determined from the relationship
between Eq. 6.6 and 6.7. First, the temperature at x = L, is the same for both equations.
The second is that the heat transfer must also be the same. Heat transfer is the product of
the derivative of T(x) times the thermal conductivity and the cross-sectional area. This
relation can be shown by
dT
kA '
-
dT
kA
n
(6.8)
x= L
x=L
where A, and An are the cross-sectional areas of the unnecked and necked tethers, respectively, T, and Tn and the equations for the unnecked and necked cases, respectively, and L
is the unnecked length. From this relation it can be shown that the derivatives of the temperature are inversely proportional to the cross-section area of the necked and unnecked
regions.
dTI dT n
_._
-n
dx dx
_
A
(6.9)
-
A
This relation represents the fourth boundary condition required to determine the constants
in Eq. 6.6 and 6.7. Applying these boundary conditions to solve for A, B, C, D yield the
following values:
A = 24nL n+2 4
1L
B
C
=
=
298.15K
(6.10)
24 L
n
2 I n n
2 9 8 .15K
D =-4 1 L1 +( 2 qnLn + 2 41 L1 )L 1 ±+
-
Using these values and Eq. 6.6 and 6.7, an analytical solution was calculated. First a comparison of necking lengths, Ln , was made. A set necking width, wn, of 5 gm was used.
Section 6.3: Tether Necking
63
63
Section 6.3: Tether Necking
1800
1600
1400
1200
1000
800
0.
E 600
400
200
0
0
20
40
60
80
100 120
140 160 180 200 220 240
x-position (gm)
1/2 Necking -
No Necking -
1/4 Necking
-
3/4 Necking -
All necking
Figure 6.4: Comparison of temperature distribution for different neck lengths at a constant current of 0.488 mA
The value of the necking width is not seen in these equations, but is represented in the
value of qn, shown in Eq. 6.11:
2
n
(1/2) p
2 2
t w
(6.11)
n
where value t represents the tether thickness. The total current, I, is divided by two since
there are two tethers with current entering and two tethers with current exiting the plate.
Five different lengths, LI, were examined and a comparison of temperature distributions can be found in the Fig. 6.4. The dimensions used for this calculations are: L = 240
pm, qn = 2.21 x 1010 W/m3 , q= 4.6 x 10' W/m 3 , wn = 5
sm, and w, = 1Ogm. The analysis
was performed with a current of 0.000488 A for each tether. The results of this analysis
show longer necking lengths will reach higher temperatures with smaller currents. Other
factors will also be affected by different necking lengths, such as power and voltage. Voltage is an important factor because of its effect on the necessary electronics to drive the
64
Chapter 6: Tether Design and the Final Design
device. Lower voltage is better because it requires less complex and costly electronics
than higher voltage devices. Fig. 6.5, Fig. 6.6, and Fig. 6.7 show the electronic performance of the device for different necking lengths (the necked width is 5 gm and nonnecked width is 10 j.m). This circuit analysis considers the whole device, including four
tethers and the plate. These results show the power and voltage minimums to occur when
the entire tether is necked. The temperature distributions for no necking, 1/4 necking, 1/2
necking, and 3/4 necking can be seen in Fig. 6.8 for a plate temperatures of 1000 K. This
highlights a key aspect to minimizing the power, which is the heat loss out of the tether to
the plate. This value is determined by the slope of temperature distribution where the
tether meets the chip.
0.0018
0.0016
0.0014
0.0012
0.001
0.0008
0.0006
0.0004
0.0002
00
20
40
60
80
100 120 140 160 180 200 220 240
Necked Length (microns)
Figure 6.5: Necking length vs current required at a constant plate temperature of 1000K
65
-Section 6.3: Tether Necking
36
35.5
35
34.5
34
33.5
o
33
32.5
32
-
31.5
31 -0
20
40
60
80
100
120
140 160 180 200 220 240
Necked Length (microns)
Figure 6.6: Necked length vs voltage at a constant plate temperature of 1000 K
0.06
0.05
0.04
0.03
0
0L
0.02
0.01
0
0
20
40
60
80
100
120
140
160
180 200 220 240
Necked Length (microns)
Figure 6.7: Necked length vs power at a constant plate temperature of 1000 K
66
Chapter 6: Tether Design and the Final Design
1200.0000
1000.0000
800.0000
600.0000
E
400.0000
200.0000
0.0000
0
20
40
60 80 100 120 140 160 180 200 220 240
x-position (microns)
-
50/50 necking -
none -
1/4 necking -
3/4 necking
Figure 6.8: Comparison of temperature distributions of different necking lengths for a
constant plate temperature of 1000 K
To determine the heat transfer rate, Fourier's law can be used [11]:
q = kA
-
(6.12)
The derivative of equations 6.6 and 6.7 are:
dT1 (x)
dx
dT (x- L1 )
dn
dx
-q 1
kx
n n +2q 1 L
0
x
(6.13)
L1
-n
k
n x - L) + 2q L
1
nn
LL <x
1
L
.
(6.14)
Using Eg. 6.14 and 6.13 in Eg. 6.12 the heat transfer rate is plotted in Fig. 6.9 for each of
the four necking cases, for a plate temperature of 1000 K.
The heat loss out of the tethers for each case is dependent on the gradient of the temperature distribution where the tethers meet the chip. Both no necking and 1/4 necking
will cause there to be a large gradient near the tether's end. The advantages gained by the
increased necking will eventually be decreased by the additional heat loss out of the tether
67
Section 6.4: Analysis of Necked Tether Design
0.0160 0.0140 S0.0120
a
0.0100
4 0.0080
0.0060
0.0040
0.0020
0.0000
0
20
40
60
80
100 120 140 160 180 200 220 240
x position (microns)
-
50/50 necking -
none
1/4 necking -
3/4 necking
Figure 6.9: Comparison of heat transfer rate of different necking lengths at a constant
plate temperature of 1000 K
by the greater temperature gradient at the end of the tether. This can be seen in the
decrease in difference between each design for heat transfer. There is an improvement
from no necking to 1/4 necking of 0.004 W, but only an improvement from 1/2 necking to
3/4 necking of 0.001 W. From this analysis, a entirely necked, or thinner tether, is best for
performance improvements, but the greatest improvement in performance are seen from
necking the first half of the tether. As such and considering manufacturing and structural
limitations a 1/2 necked tether will be considered in the following analysis.
6.4 Analysis of Necked Tether Design
Using finite elements, as discussed in the previous chapter, a model was built for the tether
design with a necking length of 120 pm and a width of 5 pm. The boundary conditions
and assumptions are the same as for the long tether case in the previous chapter and
includes uniform plate heating. There is no convection and the edges of the chip are
assumed to be room temperature. The internal heating was again determined and applied
68
Chapter 6: Tether Design and the Final Design
TEMPERATURE
TIME 1.000
960.
840.
720.
800.
480.
360.
Figure 6.10: Temperature distribution of necked tether design
by section of the hotplate, i.e. plate, necked tether regions, non-necked tether regions. The
modeling yielded the temperature distribution shown in Fig. 6.10 for a case when the plate
reaches a temperature of 1000 K. This result yields small variation in the temperature distribution in the plate section. Temperature change over the plate is only +/- 3 degrees (the
change in color from red to pink represents a temperature value of 1000 K). The power
requirement for this configuration is 0.022 W. A significant improvement over the previous designs and one that meets the design objective of 50 mW.
The resistivities of each major section of the model are as follows: 890 Ohms for the
plate, 21360 Ohms for the necked region of each tether, and 10680 Ohms for the unnecked
region. At an operating current of 0.000809 A the power production for each element is as
69
Section 6.4: Analysis of Necked Tether Design
follows: 0.000582 W for the plate, 0.0035 W for the necked region, and 0.00175 W for the
unnecked region. The necked region is producing 24 times the heating in the plate, when
all four tethers are included. This hotplate geometry leads to an excellent heat distribution
for this design.
The effects of the uniform current flow assumed in the plate will now be revisited. The
assumption made for these calculations has been that current flow in the plate will be uniform, and thus the internal heating of the plate will be uniform. This assumption is valid
based on the following analysis. It is first assumed all of the heat generated by the plate is
located across the plate's center. The change in temperature can be calculated from the
center of the plate to the edge of the plate due to the heat generation and is given by the
following circuit analogy of heat transfer, where the heat transfer rate is equivalent to current, thermal conductivity to electrical conductivity, and temperature changes to voltage
[11],
AT
q
L/(kA)
(6.15)
where AT is the change in temperature from the center to the edge of the plate, L is the
length of half the plate, k is thermal conductivity, A is the cross-sectional area. The heat
transfer rate, q, is calculated from a plate resistance of 890 Ohms and a operating current
of 0.000809 A, and is 0.000582 W while L is 100 Rm, and A is 200
2 . Using these valmin
ues and Eq. 6.13 the temperature change due to internal heating is calculated to be 0.5 K.
This result is negligible compared to the heating effects produced by the tethers and validates the assumption that the non-uniform heating in the plate can be neglected due to the
thermal conductivity of SiC.
Time response is also a factor not considered to this point in the design analysis. Thermal time response will be slower then electrical time response, and thus will be the effect
70
Chapter 6: Tether Design and the Final Design
considered to determine the time constant. First the time constant must be considered
using the lumped thermal capacitance for the plate and a thermal resistance from the tethers, shown by:
I _ L pVc
kA
(6.16)
t is the thermal time constant, L is the tether length, k the thermal conductivity, A the
tether cross-sectional area, p the density of SiC, V the volume of the plate, and c the specific heat of SiC. Using the following values, the time constant was calculated: L = 240
jim, k = 230 W/m-K, A = 30 ptm 2 , p = 3210 kg/mI3 , V = 120,000 jim 3 , and c = 675 J/kg-K.
The time constant is 9 ms, meaning to reach steady state the plate must operate three times
the time constant, or 27 ms. Performing a time dependent analysis using ADINA produces
a time to reach steady state of 25 ms, which corresponds closely to the analytical analysis.
This time response is more then adequate to provide for real time sensing.
6.5 Design Comparisons
The sequence of design improvements can now be compared against the set objectives
laid out in Chapter 1. These include manufacturability, electronics compatibly, temperature uniformity, fast time response, low power draw, and high operating temperature.
BMS checked all of these designs to assure their manufacturability. Many of the identified design improvements were limited due to manufacturability concerns including feasibility and yield. Electronics compatibility is also very important to the versatility of the
sensor. The electrical properties and behavior encompass many of the requirements, but
mainly drive low power requirements for long life and battery operations, and low voltage
requirements for low cost electronics. Low voltage is desired in order to simplify the electronics. Figure 6.11 is a comparison of the operating voltages of the four main designs.
71
Section 6.5: Design Comparisons
35
301
2 20-
10
5
0
Bridge
Mini Tethers
Tethers
Necking
1_7 4 l
Figure 6.11: Drive voltage of four main designs at 1000 K
For temperature uniformity a less than 1% variation in relative temperature is the
objective. For the plate at 1000 K that is +/-10 degrees. The longer tether and the necking
designs both met this requirement, with the necking design performing at a less than 0.3%
variation.
Another important electrical consideration is the power required for the device to
achieve operating temperatures of 1000 K. Figure 6.12 shows a comparison of the power
requirements of the designs. There is a two orders of magnitude improvement in power for
steady-state conditions from the initial to final design.
Finally, the ability to achieve high temperatures achieved by each design as long as
there is sufficient power. A better measure is the ability to achieve temperatures of over
1000 K while minimizing power. The necking design best achieved this goal out of the
four main designs, minimizing the power requirements of the micro-hotplate while
achieving operating temperatures of 1000 K.
Chapter 6: Tether Desn adteFnlDsgn
hanter 6: Tether Design and the Final Design
72
T?
1.4
................
0.8
0. 6
0
Bridge
Mini Tether
Tether
Necking
Figure 6.12: Power comparison of four main designs at 1000 K
6.6 Conclusions
This chapter combines the analytical techniques with a finite element model to produce
the best hotplate design given the design specifications discussed in Chapter 1. Using analytical techniques an examination of the necking design features was made to minimize
power and voltage of the hotplate, as well as improve temperature uniformity over the
plate. This analysis indicates greatest performance gains are achieved by necking the
entire length of the tether, essentially reducing its width. The also show that the greatest
performance gains are achieved in the necking of the first half of the tethers. Minimal
improvement is seen by continuing to neck the whole tether. Based on this fact, as well
structural and manufacturing considerations, a 1/2 necked tether design was modeled in
ADINA to examine the effect of necking features.
Section 6.6: Conclusions
73
The ADINA results show that the necking design is the best solution for a SiC microsensor of the four main designs examined. This necking design meets or exceeds all of the
design objectives set forth in Chapter 1. Further improvement can be made, though, by
continuing to reduce the tether width. A device with the tether width minimized will produce the best performance without compromising the structural stability of the device.
Considering the structural and manufacturing capabilities of a very slender tether, such
tools as necking can be used to minimize the width uses in the tethers while maximizing
the hotplate performance.
74
Chapter 6: Tether Design and the Final Design
Chapter
7
Temperature Dependent Proper-
ties
7.1 Chapter Overview
One important factor has yet to be taken into account in the modeling of the SiC microhotplate; the temperature dependent electrical and thermal properties of highly doped SiC.
That topic will be the focus of this chapter, which will cover the design, testing, and analysis of test structures used to determine these properties. Experimental results for n-type
SiC doped at 1019 cm- 3 were found in Parfenova [10], but only up to temperatures of 450
K. This extrapolation was the basis for the value of the thermal conductivity used in the
final ADINA modeling, but does not represent the true behavior of SiC above 450 K.
Other works have modeled the behavior of doped SiC, such as Ruff [18], and compared
them to the results in Parfenova[10], but with limited adaptability to the model in this thesis. Other sources [8, 18] provide results for SiC up to temperatures of 1500 K, but not for
highly doped SiC [17]. In this chapter several measurement devices are discussed and the
results used to determine the electrical resistivity and conductivity of specific wafers due
to temperature, as well as the thermal conductivity. These devices are manufactured by
BMS and tested to determine how SiC properties vary with temperature. This analysis
75
76
Chapter 7: Temperature Dependent Properties
provides a specific behavior of the wafer's properties with temperature, allowing results to
be correlated between the model and the testing.
Another important reason to determine the electrical properties in relation to temperature is to measure the plate temperature. No method is readily available to determine the
operating temperature the plate without using expensive, optically based imaging systems.
If resistivity can be correlated to temperature, then the plate resistivity can be measured to
determine temperature. This is important in order to verify the performance of the plate.
7.2 Measuring Electrical Properties Dependent on Temperature
For this experiment the main device for measuring resistivity verses temperature is the
simple four point probe. This device allows electrical resistivity and conductivity to be
measured. The four point probe method eliminates the contact resistances between the SiC
and metal contacts from the results by using two, high impedance tethers to measure the
resistance in the bridge. The device is shown in the Fig. 7.1. A current is run through the
bridge using the end contacts. The two tethers branching off the bridge are used to measure voltage and resistance across the middle section of the bridge. A Solatron 1286 potentiostat was used to measure voltage as a function of applied current.
Contacts used in this case are platinum and titanium, because of their electrical bonding with SiC when annealed and their high temperature properties. A small layer of titanium is laid down directly on the n-layer contact pads, and is then covered with a thicker
layer of platinum. Then a high temperature anneal is performed. Through experimentation
using circular and linear Transmission Line Methods (TLM) [21] and a microprobe station, it was discovered that a high temperature anneal for approximately 5 minutes at 1000
C provides a good ohmic contact with contact resistances of approximately 5 x 10-4 Ohm-
enntoTmeaue
Section 7.2: Measuring Electrical Properties De endent on Tern erature
Section 7.2: Measuring Electrical ProprisD
77
77
SiC
Current
Tambient
Voltage
Bridge
Tet ers
Figure 7.1: Four point probe test structure
cm 2 . During the anneal, the titanium reacts with the SiC and alloys with the platinum to
form a bond. These materials were chosen because of their high melting points and performance at high temperature.
Pieces of platinum foil are cut to fit the contact pads and are attached to platinum
wires. The foil is carefully placed over the contact pads, making sure they do not touch
any other part of the chip.Using sapphire as an insulator, the whole device is tightly wound
with spare platinum wire, insulated from the plate by the sapphire. The device is then
attached to a long alumina rod with a internal thermal couple and placed inside a sealed
ampoule. The electrical wires run through the rod, through a seal, and out to the Solatron.
Forming gas is run through the ampoule to prevent the oxidation of the Ti and SiC at the
contact interface. The whole device is then placed inside a high temperature furnace. The
furnace heats the device through a range of temperatures, up to 1000 C. Using a specifi-
Chapter 7: Temperature Dependent Properties
78
cally developed Lab View program to control the Solatron, I-V sweeps are performed at
several different temperatures, determining the resistance verses temperature of the highly
doped SiC.
Two devices were manufactured by BMS from two different wafers and tested using
this method. During the first test the devices began to break down at 450 C. The resistance
began irreversibly decreasing between 450 C and 800 C, indicating a shorting current path
parallel to the n-SiC layer. After examination under a microscope and stripping the chip of
metals it was discovered that the contact and platinum foil had continued to react with the
SiC during the measurement. The reaction created deep craters in the contact pads, all the
way through to the n substrate, causing the shorting path. While titanium, platinum, and
SiC are each able to handle high temperatures alone, it is clear that a eutectic alloy formed,
accelerating the metal reaction with the SiC.
The second test structure used less titanium as a result of the first experiment. The
same process and set-up was followed as outlined above for the first device. Again, at
approximately 450 C the device began to show signs of a Schottky junction. Further
examination shows that there was still shorting through the contact pads.
Despite these problems the data from the experiments are still valid up to 400 C. The
results for both experiments are shown in Fig. 7.2 and 7.3. The difference in the overall
magnitude of the resistance between the two samples is due to differences in the wafers
used in fabrication. The wafers were old, manufactured with less accuracy than current
wafer technology, and doped slightly different.
Both the devices show very similar behavior, and both appear to break down around
400-450 C. According to semiconductor theory there are three type of electrical behavior
caused by temperature changes in a semiconductor. A freeze-out range occurs at low temperatures where donor electrons are still being excited into the conduction band. For these
Section 7.2: Measuring Electrical ProprisDenntoTmeaue
Section 7.2: Measurin Electrical Pro erties Dependent on Temperature
1800
79
79
-
E
0
UO
m00200
10
1400
0
200
400
800
600
1000
1200
Temperature (C)
Figure 7.2: Results of Resistance vs Temperature Tests, Chip #1
140
120
E 100
0
0
80
60
40
20
0
0
200
400
600
800
1000
1200
Temperature (C)
Figure 7.3: Results of Resistance vs Temperature Tests, Chip #2
80
Chapter 7: Temperature Dependent Properties
devices this region occurs is from room temperature to 300 C. The next range is the saturation range. This region is the region where all of the donor electrons are excited into the
conduction band and there are no more charge carriers to be added. The dominant effect
on resistivity in this region is mobility, which increases the resistance with temperature,
although not significantly. This effect is typically exhibited by a slightly sloped linear
region of the graph, and can be seen in Fig. 7.2 and 7.3 over the 300 to 400 degree C temperature range. The final region is the intrinsic range where valence band electrons are
excited into the conduction band. The intrinsic region would show a significant drop in
resistance and a steep slope [19].
For SiC, the intrinsic region is not expected to occur until temperatures of 1800 K[10],
well above the experimental temperatures used. The results for this experiment do not
show the intrinsic region exists in the temperature region examined. These results are not
reproducible during cool down, thus proving the chip is damaged, which is verified by further examination. However, the experiment did capture the freeze-out and the saturation
ranges. From these results the behavior can be modeled very accurately throughout the
rest of the temperature region, up to 1800 K.
7.3 Modeling the Electrical Properties
The electrical properties can still be accurately modeled using the low temperature data
from the experiment. The method is described for chip #1, while results will be shown for
both chips. The governing equation for the resistivity verses temperature for semiconductors and p-n junctions is the following [19]:
1
_1
-(7.1)
p = 3Y
neji
The resistivity is the same as the inverse of the electrical conductivity. The value n is the
density of free electrons, or the number of electrons in the conduction band, e is the ele-
81
Secton
73: MdeIg the Electrical Properties
mentary charge, and g is the mobility of the charge carriers. There are two major effects
on resistivity governed by this equation. The first is n, which dominates the behavior of
the semiconductor in the freeze-out range. In this region donor charge carriers are still
being excited into the conduction band. The value n is determined from [19]
n = ND EXP(
db}.
(7.2)
This equation represents the donor electrons excited into the conduction band with temperature. ND represents the doping density, Ed is the donor energy, kb is the Boltzmann
constant, and T is temperature.
The other major effect is the mobility, which will dominate the behavior in the saturation regions. The mobility is affected by acoustic phonons and ionized impurities. The
total mobility is [19]
(
1(7.3)
The values pi and of i are the phonon and impurity effects respectively. The ionized
impurity effect is only a significant and a dominating factor below room temperature.
Above room temperature the acoustic phonon effect becomes dominate[19]. Thus, the
can be neglected and the
i
;t is the only effect to be modeled in the high temperature case.
1
The phonon mobility can be approximated by [19]
-5/2
-3/2
(74)
where m* is the conductivity effective mass.
If the results are plotted as log (R) verses 1/T, a linear graph is produced that can be
easily curve fit. First, the governing equations must be reduced to the same form for plot-
82
ting. By combining Eq. 7.2 and 7.4 with 7.1, the resistance of the SiC should be of the
form
(Ed\
EXP
R=
3/2
-T
kT
NDe(m*)
(7.5)
-5/2
in the extrinsic region. This equation can be cast into the log R verses 1/T form as
(
R
-5/2)
_
Ekd 3/2
TI -lgNe(m*)
lg
.
(7.6)
Plotting the results from the experiment as log(R/T 3/2 ) vs 1/T gives Fig. 7.4. From Fig.
7.4, the experimental results can be seen degrade at 650 K due to contact degradation. The
data between 298 K and 650 K is where the contacts were still functioning. A linear line is
fitted to the first couple of data points in this region and is indicated by the curve fit line.
The slope of the curve fit is the value of Ed/k and the intercept is a constant equal to the
log(NDe(m*)-/
2
). The curve fit provides these values. For now, the intercept value will
just be considered a constant since none of the terms included in it are temperature dependent. These values of Ed and the constant are put back into Eq. 7.5 and plotted against the
experimental solution. The results are shown in the following figures for both chips; to
eliminate geometry effects the resistivity is plotted instead of resistance, as in Fig. 7.2 and
7.3. The solution method gives accurate results for the model based on known semiconductor behavior [19], providing a model for the data up to higher temperatures. Figure 7.7
shows the model for chip #1 through a much greater temperature range.
Section 7.3: Modelinga the Electrical Pro~ete
Section 7.3: Modeling the Electrical Properties
83
83
-12
-13
-14
<0
-15
-16
-17
-18
-19
0
0.0005
0.001
0.0015 0.002
0.0025 0.003
0.0035 0.004
1/T (1/K)
-
Experimental -
Curve Fit
Figure 7.4: Plot of log(R/T 312) vs l/T and a linear curve fit to the non degraded data for
chip #1
0.02
0.018
0.016
0.014
E 0.012
0.01
0
0.008
0.006
0.004
0.002
0
0
200
400
600
1000
800
1200
1400
Temperature (K)
-
Experimental
-
Fit
Figure 7.5: Chip #1, comparison of experimental results to modeling fit
84
Chap~ter 7: Temperature Dep~endent
Proteis
Chapter 7: Temperature Dependent Properties
84
0.0014
E 0.0012
0.001
0.0008
0
0.0006
0.0004
0.0002
0
0
200
600
400
800
1000
1200
1400
1600
Temperature (K)
-
Experiment -
Fit from Chip#2
Figure 7.6: Chip #2, Comparison of Experimental Results to Modeling Fit
0.45
0.4
E
0
0.35
E 0.3
0.25
0
0.2
0.15
0.1
0.05
0
0
200
400
600
800
1000
1200
Temperature (K)
Figure 7.7: Temperature dependence of resistivity based on model results for chip #1
empratue Dpendence of Thermal Properties
Secton
.4:
85
Fig. 7.7 corresponds with expected behavior as described in Sze [19]. Note that the resistive change above 400 K is due to mobility effects, which are small. This means that there
is little change in resistivity due to temperature above 400 K. The constant inputs for electrical heating due to resistivity used in the hotplate modeling are therefore reasonably
accurate because of this small change of resistivity .
The method developed from this experiment can be used for any chip. Simply by measuring the resistivity of the material for a temperature range from 273.18-400 K, a model
can be developed for the electrical, temperature dependent properties. Of course, that is
true only if the freeze-out region is measured. This method should be used to check the
specific electrical property behavior for any wafer used in SiC micro-sensor production.
7.4 Temperature Dependence of Thermal Properties
The thermal conductivity of SiC is an important factor in modeling the sensor. Thermal
conductivity will have a significant impact on the operation of the micro-sensor at higher
temperatures. For semiconductors, thermal conductivity can be broken down into two
regions in relation to temperature, an increasing region and a decreasing region. At low
temperatures, typically much lower than room temperature the thermal conductivity will
increase with temperature. This increase in thermal conductivity occurs as thermal carriers
are freed with the temperature increase. The effect in SiC peaks below room temperature,
and then the conductivity will decrease with temperature. Thermal conductivity decreases
because there is more obstruction from excited carriers as temperature increases [19]. The
temperature range of operation of the micro-hotplate is high enough to ensure that the
thermal conductivity will be decreasing as temperature increases.
86
Chapter 7: Temperature Dependent Properties
3
2.5
2
E
S1.5
0.5
0
300
320
340
360
380
400
420
440
460
Temperature (K)
Figure 7.8: Research Results for Temperature Dependence of SiC for a 1018 cm- 3 Doping
Density
Work in this area has been investigated at low temperature for SiC by Parfenova [15].
In this reference there is actual experimental data for doped SiC up to temperatures of 450
K. A fit to the experimental data is shown in Fig. 7.8 [15]. Using this data an equation was
fitted to give the relation between temperature and thermal conductivity.
k(T) = EXP - 0.0683(nT) 3 + 1.1055(In2T)
6.6675(InT) + 20.478W/mK
(7.7)
It is necessary to fit the curve to a log-log plot of temperature and thermal conductivity to
obtain the desired accuracy.
This model is not accurate for temperatures above 450 K and is only useful for doping
of 1018 cm- 3 . As doping density is increased it can be expected that thermal conductivity
will decrease [19]. Test structures were developed to determine the thermal conductivity,
specifically for the wafers used as well as the doping used. The test structure is a long
bridge with several very slender tethers extending off it (see Fig. 7.9).
Section 7.4: Temperature Dependence of Thermal Properties
87
Figure 7.9: Test Structure to Measure Thermal Conductivity
The bridge section is heated by running a current through it. The tethers are designed to be
long and thin to prevent heat loss. Each tether is 2500 gm long, and 5 gm wide. At room
temperature the conductivity is 230 W/m-K, and the thermal resistivity of a tether is 2.17 x
1012 K/W. The overall resistive effect of the 10 tethers is approximately 2.17 x 1011 K/W.
The resistance of the heating bridge is, at room temperature, 191,000 K/W. The heat flow
difference between the tethers and the bridge will simply be the ratio of resistances; meaning only 8.8 x 10-5 percent of the heat will flow down the tethers. This is a negligible
amount, meaning almost no heat will flow down the tethers, assuring the uniform heating
of the bridge.
Properties
Chapter 7: Temperature Dependent Properties
88
Chapter 7: Temperature Dependent
88
1200
1000
800
e
600
E
400
2000
0
0.0001
0.0002
0.0003
0.0004
x-position (m)
Figure 7.10: Temperature Over the Bridge Structure
A voltage drop and resistance are measured between each tether. This resistance will
be compared to the results obtained in the previous section to determine the average temperature over that section being measured. A temperature profile similar to the following
can be created; and is shown in Figure 7.10. This plot is modeling the heating of the bridge
of the test device, assuming constant thermal conductivity of 230 W/m-K, and only serves
as an example to verify the analysis techniques used to determine k from the test structure.
From the experimentally measured profile the conductivity due to temperature can be
determine using the following method. The temperature profile between two points on a
bridge is represented by the following equation:
T(x) =
2k
x 2 +Ax+B
(7.8)
This equation is the same as the one used for tether modeling, and assumes a k constant.
Since Eq. 7.8 represents temperature changes over small sections of the chip, it assumes
that the temperature gradient is small enough to use Eq. 7.8 with a constant k. The q is the
power generated per unit volume dependent on temperature, since resistivity is also
Section 7.4: Temperature Dependence of Thermal Propete
89
dependent on temperature. For this model, the value of q will be determined from the temperature dependent resistance model determined in the previous section using the average
of the two boundary condition temperatures, and the known current. A and B are calculated from the boundary conditions: the boundary conditions are that the temperature at
both the ends of the bridge section are given, and are room temperature in for this example. Solving for A and B and substituting gives the following equation
T(x) =
2k
x2 +
I
(T2L T)
L
+
] x +T
2K_
I
(7.9)
where T, and T 2 are the boundary condition temperatures. L is the length of the section
being measured. Solving for k gives the following
[9 Lx - x2)2
k =
2+Tl)
x
T(x) -T
(T
(7.10)
From this equation and the experimental data an approximate relationship can be developed between k and T. Three adjacent measured data points are taken from the device. The
two outside boundary points are T, and T2 , and T(x) is the middle temperature. The value
x is the position of the measured data point. Since the structure is uniform in geometry,
this is 40 tm. With all values known, Eq. 7.10 will produce the average thermal conductivity, corresponding to the middle temperature measurement. This method was checked
by picking different boundary temperatures, T, and T 2 , and the middle temperature
between them, T(x), and calculating the appropriate k for each. The calculated thermal
conductivities matched with the constant 230 W/m-k used in the model for k.
Unfortunately, due to time constraints this device was not tested for this work. Future
work on this design should include the testing of this thermal conductivity measurement
method and use of the results in the modeling.
90
Chapter 7: Temperature Dependent Properties
7.5 Conclusions
Improvement of the modeling of the SiC micro-sensor must begin with better temperature
dependent modeling and data. The electrical property method used was a success, producing accurate and usable results. The results obtained indicate that operating temperature
ranges of the sensor stay within the saturation range of SiC. Good results using constant
resistivities can still be obtained from the sensor modeling since the mobility effect in the
saturation range is small, but for accurate results the temperature dependent resistivities
should be used. For temperature measurements of the micro-hotplate the mobility effect
on resistance becomes important and useful. Every wafer used should be tested for temperature dependent electrical properties, since resistivity is very sensitive to small variations between wafers.
The thermal conductivity model needs to be tested to collect accurate thermal conductivity data to be used in the model. The given data from the literature was used with some
success in the modeling, but more material specific data is needed. Variation in thermal
properties with temperature are much more significant in SiC than with electrical properties since these properties are not dominated by charge carrier effects. In semiconductors
the thermal properties are more dependent on lattice effects. More work needs to be done
with thermal conductivity to improve the modeling and designing of these sensor devices.
Chapter
8
Device Testing
8.1 Chapter Overview
This chapter will discuss the set-up and testing of the hotplate designs. Also covered is the
difference in material properties between the modeling case and the test wafers. Measurements are discussed, and results compared to the expected modeling effects. Finally, a discussion will follow outlining procedures for future testing and modeling work.
8.2 Experimental Set-Up
Each of the hotplates was metallized with the basic design shown in Fig. 8.1. Gold and
titanium are used as the contact metal. Titanium is used to react with the SiC to form a
good electrical contact between the metals and the semiconductor. This requires a high
temperature anneal. To determine the best contact, a test array of circular Transmission
Line Method (TLM) patterns is made on the wafer [21]. This method measures the resistance between two contacts for varying radius. Figure 8.2 shows a circular TLM pattern.
An array of TLM patterns is made with varying radii. Resistance can be measured
between the contacts for each pattern, and can be plotted as a function of radius. The result
is a linear relationship with a slope proportional to the sheet resistance of the semiconduc-
91
92
92
Charter 8: Device Testina
N-layer contact t
Small metal contacts
Metal
-
plateonnectors
Plate
Figure 8.1: Test plate layout
tor, and the y-intercept is twice the contact resistance of one of the contacts [21]. Using
this method the contact resistance is determined. This measurement technique is also used
to test different annealing methods. The contacts are Schottky before the annealing process, meaning they will only allow current flow for positive voltage and no current flow
for negative voltage. The ideal contact is an ohmic contact, producing a linear I-V plot.
Different TLM arrays were annealed at different temperatures and times. I-V plots were
taken for each and compared. The annealing process of 1000 degrees for 5 minutes produced the best ohmic contact of the annealing methods tested and was the method used to
anneal the actual test structures.
The design layout for the devices being tested is shown in Figure 8.1. The two positive
and negative contacts are connected by metal (gold) to a single large contact in each case.
This configuration makes only one connection to the positive and negative contacts.
Seven hotplates of three different geometries were made for the first experimental run.
Five of the hotplates that were tested are of the basic tether design discussed in Chapter 5.
93
93
Section 8.2: Experimental Set--Up
Section 8.2: Experimental Set-Up
Contacts
Radius
Figure 8.2: Circular TLM pattern
Of these, three have large, 4 x 4 gm, perforations in the hotplate section, while the other
two hotplates of the long tether design have small, 2x2 gm, perforations. The different
perforation sizes are to determine the perforations' effect on performance, such as local
heating and current density effects. The final two designs are both of the necking design
discussed in Chapter 6. The necking width is slightly smaller than the model; 4 gm instead
of 5 jim. These are the four geometries tested, using 7 devices.
The doping densities of these plates is 1019 cm- 3 , as opposed to the 1018 cm-3 used in
the modeling. This changes the resistivity of the plate. Instead of the 0.089 Ohm-cm the
plates should have a resistivity of 0.025 Ohm-cm. For this work the resistivity taken was
the measured resistivity at room temperature measured from experimentation of chip #1 as
discussed in the previous chapter. The resistivity value is 0.015 Ohm-cm. Rerunning the
modeling for the tether plates, as discussed in Chapter 5, with the new resistivity produces
an operating current of 4.5 mA. The resistivity of the new plate is 3500 Ohms, the operating power is 0.074 Watts, and the voltage is 16.4 V. These values will be the values used
for comparison to the long tethered structures tested.
94
Chapter 8: Device Testing
Figures 8.3-8.6 show one of the manufactured hotplate used in the testing, before metallization and addition of the contacts. The geometric features of the plates can be seen to
have a high degree of precision when compared to the desired dimensions.
a444.4*4 W
94444
4 4t
4
4444*0
44
4*444 44
4
44
4 S*
44
04W4W4a
4 *4
4
*0
*
1:4
0
4k4
4
4
4t
44
V444
4
4
#4
*4
4
4 *0 W
4*
4
V
44*
Figure 8.3: Manufactured hotplate
Figure 8.4: Micro-machined tethers
Section 8.2: Experimental Set-Up
95
Figure 8.5: Tether-hotplate junction
Figure 8.6: Tether hotplate junction and contact pad
These figures show the accuracy of the manufacturing of the device. Note the under etching of the plates and tethers, allowing the plate and tethers to hang free, isolating them
from the rest of the chip. This manufacturing process for single crystal SiC is unique to
96
n
8: Device
Chapter
Chanter 8: Device Teting
Expected
Test Plate Design
Resistance (1)
Long Tethers, Small Holes
3654
Long Tethers, Large Holes
3654
Long Tethers, Large Holes
3654
Necked Tethers
6285
Long Tethers, Large Holes
3654
Long Tethers, Small Holes
3654
Necked Tethers
6285
Measured
Resistance
4462
4686
5643
8576
13737
2485
11069
Table 8.1: Comparison of expected verses measured resistances
BMS and these devices.
8.3 Experiment Results
The first step in the analysis of the plate was a comparison of resistances and a check of
contact quality. Resistance was measured over the plate using the layout on Fig. 8.2. The
n-layer of the plate should have resistances comparable to those calculated using the measured resistivities from the experiments in the previous chapter. The Table 8.1 shows the
results for expected n-layer resistance vs measured n-layer resistance. The expected resistance is very close for the first four designs, but the final three designs did not correlate.
Upon close examination of the these devices it was found that the gold contact metal was
not adhering to the SiC, and was flaking off. This means that the contacts to these devices
failed during processing resulting in poor adhesion. For all of the chips, upon further
examination, it was found that the metallization between two of the direct plate contacts
(the contacts directly connected to the tethers) had not bonded, and, thus, one of the tethers
was not receiving current during the testing when the single, large contacts were being
used. Adjusting the calculations for the expected resistance by removing one tether from
the calculation gives the results in Table 8.2. The adjusted expected resistance gives a better correlation between the resistances. The remaining differences between the expected
and measured resistances can be correlated to the plate perforations. The results for the
Section 8.3: Experiment Results
Expected
Test Plate Design
Resistance (1)
Long Tethers, Small Holes
5408
Long Tethers, Large Holes
5408
Long Tethers, Large Holes
5408
Necked Tethers
9354
5408
Long Tethers, Large Holes
Long Tethers, Small Holes
5408
9354
Necked Tethers
97
Measured
Resistance
4462
4686
5643
8576
13737
2485
11069
Table 8.2: Adjusted resistance comparison
final three devices show that there are problems with the metallization of their contacts,
and their results will be neglected for this thesis.
Since the devices could not be repaired to allow both contacts to be tested, three of the
devices were tested with only three tethers. The necked design, the small perforation
design, and one of the large perforation designs. In each of these three designs, current
was run through the device until the tethers were glowing. In each design a voltage of 3540 volts, approximately 80 amps, was run through the device until the tethers were emitting light. At 10-15 volts the positive contacts began to glow blue. Blue light is an indication that there are electrons being injected into the p-layer. The light is emitted when the
electrons meet with holes in the p-layer forming a light emitting diode. These contacts are
forward biased when a positive voltage is placed on them. As voltage is progressively
increased, points on the negative junctions begin to glow white, as well as at spots along
the metal connectors that connect the contacts. The fact that they are glowing white is an
indication of a reverse bias breakdown across the p-n junction and breakdown of the
dielectric under the metal connectors. This is an unexpected behavior since a SiC p-n junction should not breakdown below approximately 100 V, but manufacturing and wafer
quality can both lower this value. Once enough current is forced through the hotplates the
tethers glowed for a short time, and then burned out.
Chapter 8: Device Testing
98
The fourth device was tested by placing four micro-probes on each small contact,
eliminating the problem with metal connectors. This method allows all four tethers to be
operating as designed. The same effect with the breakdown of the junction was observed
as in the previous three cases, with the positive glowing blue and the negative white. The
tethers did not glow until the current was 120 mA and the voltage was 50 V. The glowing
in the device only occurred in the middle of the two negative voltage tethers, not in the
plate or other two tethers as expected.
The operating voltages of all devices were much higher than expected, the operating
currents were also much higher then predicted, the breakdown voltage much lower than
expected, and the temperature distributions not as modeled. An investigation of why this
occurred will be discussed in the following section.
8.4 Analysis of Experiment
The main effects observed in this experiment related to the work of this paper are the high
operating voltages, currents, and power, and the heating of the center of the tethers, and
only in two tethers. Further analysis indicates why these effects occurred.
The heating effects seen in the middle span of the tethers, and not in the plate as
expected, can be explained by an additional conduction path being made by the touching
of the center plate section with the surrounding chip through the substrate. This extra conduction path is formed by the tethers deflecting into the chip due to thermal stresses created as the hotplate heats. A simple calculation was performed to verify this effect by
using the thermal analog to electrical circuits [11]. The plates with only three operating
tethers can be modeled as shown in Fig. 8.7.
Section 8.4: Analysis of Experiment
99
99
Section 8.4: Analysis of Experiment
RT= 3 4 8 00 K/W
T=1200 K
-eO T=298 K
T2
Rm/=17400
RP=1450 K/W
K/W
RT= 3 4 800 K/W
Figure 8.7: Basic modeling of experimental results
This model assumes that the glowing section of the middle of the tether is at 1200 K, since
it is glowing white hot. The resistances of each section are determined from the relation
R
(8.3)
L
kA
where the L is the length of the section considered and the A is its cross-sectional area.
From the two boundary conditions a heat flow, q, can be calculated from
AT
(8.4)
R
q
RT/ 2 +R
+-
This equation gives a heat flow of 0.01104 Watts. To determine Ti
,
or the approximate
temperature of the plate, the following equation can be used
1200 -T 1
(8.5)
q =
R T /2
This equation gives T, to be approximately 650 K. This model assumes there is no internal
heating in any part of the hotplate or tethers, which is technically incorrect, but represents
a worse case scenario. At 650 K it is believed that the rest of the tether and plate should be
glowing red, as this temperature is well above the temperature for emission of visible
Chapter 8: Device Testing
100
100Chte8:DvcTetn
RT= 3 4
RT/2=1 7 4 00 K/W
T=1200 K
80 0
K/W
T
- T2
-T=298
K
R =1450 K/W
RT/2 =1 7
4 00
K/W
RT= 3 4 8 00 K/W
Figure 8.8: Model of final device results
light.
The same method is used for the final device tested, where using two negative microprobes connected to the two smaller negative contacts forces allows all of the tethers to be
operating. The model is modified in the Fig. 8.8. Modeling in the same fashion produces a
plate temperature of 830 K. At this temperature the plate section should be glowing red.
The heat must have an additional conduction path in order to keep the plate temperature down. In fact, a simple calculation shows that a touch to the plate with a cross-section
as small as 3.5 x 3.5 pm is sufficient to reduce the plate temperature below the visible
region.
An examination of the device after testing was made that showed regions under the
plate section had a clearance as small as 2 tm. The examination also showed that the plate
section had deflected down into the chip, thermally shorting the device through the substrate. This deflection is presumed to be a result of the constrained thermal expansion of
the tethers, which would result in possible bending or buckling causing the plate to deflect
and making contact with the substrate n-layer. A critical buckling temperature of the tethers can be calculated by modeling them as clamped bridges, as shown in Fig. 8.9.
101
Section 8.4: Analysis of Experiment
h
L
*
Figure 8.9: Buckling model of tethers
The critical bucking temperature can be calculated from the critical buckling,
p
2
= 4n 2EI = EaAT A
cr
cr
L2
(8.6)
where E is the Young's modulus, I the inertia, a the coefficient of thermal expansion for
SiC, and A the cross-sectional area. Simplifying Eq. 8.6,
AT
cr
(8.7)
=
3L2a
where h is the height of the tether, L is the length. The following dimensions for the tether
and SiC are used: L = 240 gm, h = 3 gm, and a = 4 x 10-6 K- 1. After a temperature change
of only 128 K the tethers should buckle. The deflection of the tethers must also be considered. For a worst case analysis, the configuration in Fig. 8.10 is used. The tethers extension due to temperature change can be calculated from
AL = aLAT.
(8.8)
For a temperature change of 500 K, the tether will extend 0.48 gm. The vertical deflection
of the tether can be estimated assuming that the tether deforms into a circular arc as shown
in Fig. 11. The value of 0 can be found from
0 =
AL sinO
L0
'
(8.9)
From trial and error, 0 is calculated to be 0. 11 radians. The deflection of the tether is given
102
Charter 8: Device Testing
102
h
L
Figure 8.10: Deflection modeling of tethers
L
L+AL -
Figure 8.11: Modeling tether bending to determine the vertical deflection of the tether
by
6
L(1 - cos0)
(8.10)
sinO
From these equations it is calculated using the given tether dimensions and the thermal
expansion that the tether with deflect 13.2 gm down into the plate. Since the hotplate is
only under etched by 2 gm the plate will make contact with the substrate, thus electrical
Section 8.5: Conclusions10
103
and thermally shorting and producing the heating seen in the tethers.
8.5 Conclusions
The deflection of the plate, coupled with the significant current leakage to the p-layer,
explains the results obtained from the experiment. Improvements in the structure must be
made in order to prevent the thermal deflection of the tethers. Since additional structures
are already manufactured, awaiting metallization, a short term solution is needed to test
these chips. One method might be to excite the plate and tethers using an AC current to
their resonance frequency to cause the plate to deform away from the chip. This is one
potential solution.
For future designs, several possible solutions exist. The performance of the device is
dependent on cross-sectional area, not the actual width and thickness dimensions. Thus,
the dimensions could be adjusted to cause the device to be stiffer in the vertical direction,
causing more of the deformation to occur in plane. Such a design would lead the device to
twist, but with the current hotplate geometry some twisting can be accommodated.
Another solution would be to deepen the etch under the hotplate. This would require a significant increase in etching times, but might be worth the improvement. The third solution
would be a new layout. Creating the device as a circle for the center plate section with spirals for the tether would allow the device to twist, and prevent bending into the cavity
under the micro-hotplate.
The other area of concern is operating voltages. Because of the low breakdown voltage
of the junction a lower voltage is required. This experiment made clear the importance of
keeping the drive voltages low in the device. Solutions to this are no-necking, higher doping, larger scales, or shorter tethers. Any change of these parameters of the design will
cause a sacrifice in another one of the requirements. For example, shorter tethers lead to
104
Chapter 8: Device Testing
less temperature uniformity over the plate. The main design idea is to minimize both current and resistivity, while still achieving the design objectives.
The final change necessary is to work on increasing the breakdown voltage of the
junction. This can be done by rounding corners and minimizing cuts through the junction.
The breakdown voltage is also expected to be improved by using higher grade wafers,
manufactured using modern techniques. With these improvements, the next series of tests
should have devices working as designed.
Chapter
9
Conclusions
9.1 Design Overview
The design of the SiC micro-hotplates focused on several key design features outlined in
Chapter 1. These include manufacturability, electronics compatibly, temperature uniformity, fast time response, low power draw, and high operating temperature. These standards were the focus of the designs developed in this work. Several key design features
were identified as the modeling and design space of this work was investigated based on
these standards. The first key design point is the reduction of heat loss effects. The main
causes of heat loss are conduction, convection, and radiation; convection and radiation can
be neglected because the size of the device makes their effects negligible in comparison to
the conduction effect. Thus, focusing on conduction, several features become important.
Tethers should be used to reduce the conductivity of the thermal conduction paths to the
surrounding chip. Longer tethers act as insulators. Minimizing the width of the tethers
maximizes the electrical performance of the device. These three design features are important to minimizing the conductive heat loss effects.
The second key design feature is to maximize resistive heating effects, which minimizes the power needed to obtain the desired temperatures. This power improvement is
105
106
Chapter 9: Conclusions
accomplished based on the ratio of length to cross-sectional area. Tethers can increase
resistance by maximizing the length of the tether while minimizing the cross-sectional
area. Necking further enhances the power decrease by further increasing resistance and
resistive heating where is it is needed most, close to the plate section. The increased resistance of the tethers reduces the current necessary for heating, and thus reduces the power
dissipation in the plate, improving the power of the whole hotplate and reducing non-uniform plate heating.
The final, major design considerations was temperature distributions over the device.
The ideal device has no temperature change over the center plate section where the film
measurements are made. Maximizing heating off the plate and transferring this heat into
the plate through conduction is the best way to assure an ideal temperature distribution. A
design utilizing necking will keep the current low so that actual heating in the plate section
is minimized. It also localizes heating in the best position, close to the plate, to allow for
good conduction into the plate. The greater the ratio of tether resistance to plate resistance
the better the performance will be in regard to temperature distribution.
These three critical design features were all met by the tether and necking designs. The
tethers and necking addresses all of these design issues with the same solution, and tethers
with necking should be the design used for SiC micro-sensors.
9.2 Lessons
Every step of this design process brought with it lessons; lessons about design, MEMS
devices, SiC, and modeling tools. The most relevant conclusions came with the testing of
the device. Two conclusions that are both critical issues to the operation of a SiC chemical
sensor. This first conclusion is that not only is minimizing power important, but also the
minimization of voltage. The necking design minimizes power, but operates at a much
Section 9.3: Future Work
107
higher voltage then the plain tether design. A balance between power and voltage must be
made in the follow-on designs. Voltage must be minimized in order to prevent breakdown
of the p-n junction.
The second conclusion is a structural consideration. Manufacturing was thought to be
the important structural consideration, but in actual operations it was not. First, because of
the size of the device it was assumed thermal expansion would be small, and because of
the geometry it was assumed that there was plenty of room for the device to rotate. Secondly, the under etching depth, or the clearance between the plate section and the substrate, was thought to be greater than 2 jim. The small clearance allows even a small
deflection in the device to cause the plate to touch the substrate. Greater consideration
needs to be given to these thermal effects. Future designs need to be designed to operate
with thermal stresses and deflections.
9.3 Future Work
Future work on this device must embody work related to the two main and significant conclusions discussed in the previous section. First, a short term solution must be found to
allow for the testing of already manufactured structures, and second a long term solution
must be found for the next manufacturing run. The premise of the device operation as discussed in this work is proven to be sound, it is a matter of future work to determine solutions to the voltage and structural concerns to assure the operation of the micro-sensors.
The voltage issue can be addressed by several factors including doping density, tether
length, and manufacturing. Higher doping density will lower the resistivity and drop the
voltage while still maintaining all of the geometric advantages. Less or no necking will
also reduce the voltage. Larger devices of the same geometry have slightly lower voltages
that will help. Actively creating a reverse bias at all of the contacts by applying a voltage
108
Chapter 9: Conclusions
to the p-layer will help to increase the breakdown voltage. Using higher grade wafers will
also help to increase the breakdown voltage. And finally avoiding etching through the
junction and not using sharp angles will all improve the breakdown voltage.
The thermal expansion and structural problems can be addressed in the following
ways. Longer under-etching times to increase the clearance under the plate. Changing the
width, thickness, and length dimensions of the tethers, while maintaining the cross-sectional area to leave the power dissipation unchanged, to promote in-plane twisting of the
tethers, preventing the plate from deflecting into the substrate. Different geometries can
also be investigated using the same design concept of tethers and plate. For example, the
plate can be made circular with the tethers spiraling around it. The heating effect will be
the same, but the device will be more prone to twisting rather than bending.
With these solutions and the designs discussed in this thesis a successful device can be
developed. It will take some adjustments to the current design to address the testing problems as well as additional testing varying designs, but a functional design will be the
result.
Appendix
A
Finite Differencing of the Hotplate.
A.1 Overview
This appendix will cover the finite differencing techniques used to model temperature distributions over the sensors. The discussion will include an overview of the different equations used to model the plate, including corners, edge elements, boundary conditions, and
internal heat generation.
A.2 Finite Differencing Technique
In the finite difference modeling the plate is divided up into many different elements of the
same size, 2x2 gm for the analysis completed in this work, which are represented by a
point, or a node, in the center of the element. The analysis is in 2-d for this work, although
methods do exist for handling 3-d cases. The third dimension is accounted for in our
model in the internal heat generation equation. The node in each element represents the
temperature of that element. Several different mathematical techniques can be used to
determine the temperature of a specific node. Each method is dependent on the temperature of the nodes surrounding the specific node. Some of the main methods are forward
109
Appendix A: Finite Differencing of the Hotplate.
110
m, n+1
m-1, n
m, n
-
-om+1, n
Element
m, n-1
Figure A.1: Nodal layout for finite difference method
differencing, backward differencing, and center differencing [20]. The method used is
mainly dependent on the known boundary conditions of the model. If only the initial
boundary conditions are known, a backward differencing scheme would be used. For this
work, a centered differencing scheme was used because all of the surrounding boundary
conditions are assumed to be room temperature. In each design analyzed using this
method the contacts between the plate section and the chip are set to room temperature.
With these boundary conditions ,centered difference is an excellent method for design
modeling.
The plate is divided up in the Fig A.1 using a finite differencing scheme. The plate
section is evenly divided up into 10,000 2x2 gm (even more in the cases where tethers are
included). Each element is represented by a node at its center. A center differencing will
average each node with the surrounding nodes using the following equation from chapter
4 [11].
T
n
m, n
T
, n+
I+ Tm, n -
m 1, n
+ T m+
4
m- 1, n
(A.1)
This is a circular reference and can not be solved in one step, but can be solved iteratively
where an initial guess is applied to each node; in this case it is that the entire plate is at
I1I
Appendix A: Finite Differencing of the Hotplate.
room temperature. Each point is then calculated using the initial values and a new temperature is placed in for the node, a Ti+l, where Ti is the initial temperature. The process is
repeated until the error between each successive step is less than a hundredth of a degree.
The boundary conditions are placed in the representative nodes as constants.
Internal heat generation is an important addition to the model since it drives plate heating. Without this heat generation the calculations would yield a plate section that remains
at room temperature. Resistive heating is the mechanism used to heat the plate and tether
sections. To account for it the following is added to equation A. 1:
AT
m,
n
(A.2)
-
n
t -k
This equation determines the additional heat input to each node. P is the power, determined by the power density which is dependent on the geometry of the section producing
the power: tether, necked, or plate. This power density is then multiplied by the volume of
the element; giving P, the power generated in each element. The value k is simply the thermal conductance. It is not temperature dependent in this model. The value t is the thickness. The final equation used is the following:
T
m, n
= Tm, n + 1 +
m,
4
m+ 1, n
in1
m -,n
+
P
t -k
(A.3)
This is the equation used for all of the interior nodes. The edge nodes must be dealt with
with a different equation.
Elements at the edge of the plate and tethers are not governed by the boundary
condition nodes, and are missing one or more of the surrounding nodes in order to be able
to calculate the temperature. The Figures A.2 , A.3 and A.4 show examples of these elements.
1 12
Appendix A: Finite DifferencinvQ of th-e Hotniate
112
m,
Ay
m, n
m-1, n
4-Ax +
m, n-1
Figure A.2: Edge element for finite difference method
m, n+1
Ay
m, n
rn-i, n
rna
m+, n
4-
Ax
-0-
m, n-1
Figure A.3: Inside corner element for finite difference method
113
113
Appendix A: Finite Differencing of the Hottolate.
Appendix A: Finite Differencing of the Hotplate.
m, n
m -1, n
e
Ay
Ax
m, n-i
Figure A.4: Outside comer for finite differencing
Each of these figure are represented by the following equations, which include a convective component [11]. For the edge element:
T =
m, n
(2T
m-1, n
+T
m, n+ 1
+ T
mn, n - 1
)+2hAx T
k
0(A-4)
2 hAx
(k
(5
For the inside corner:
T
2(T mn-1,n +(T m,n+1 )+(T m
Tm
1n +T m,n-1))2hxhTk
k T
(A.5)
(k
For the outside corer:
m~nm,
n
(T
T
mn,n -1
=(A.6)
m, n
+T
m-1, n
)+2hAx T
k
2 hx+1I
k
These equations assume there is a convection effect. For the modeling in this work it is
assumed that the convection is negligible, and thus can be neglected from these equations.
The following are the equations neglecting convective effects, including the addition of
internal heating. For the edge element:
Appendix A: Finite Differencin
1 14
T
m, n
= 2Tm-1, n+ Tm, n+ 1+ Tm, n 4
1
)+
of the Hotplate.
(A.7)
P
t -k
For the inside corner:
2
T
=
(Tm
m, n
For the outside corner:
m - 1, n
Tmn
m, n
+nTm ~
)+(Tm
m, n+ 1
6
m+ 1, n
+nTm
)
m, n- 1 +
(Tm,n1 + Tm- 1, n) +P
2
t -k
t-k
(A.8)
(A.9)
These are the equations used to model the plate designs. Each geometry was constructed
using the appropriate form of these equations for each node in ExcelTM. Using Excel's
calculation feature to perform an iterative calculation solutions were computed, with a
convergence error set to a hundredth of a degree.
Finite Differencing is an effective modeling systems for less complex systems, but
it is computational intensive. Multiple nodes must be calculated for thousands of steps to
obtain the desired convergence. As complexity is added, so is computational time added,
both in additional nodes and addition iterations. The tethered design calculations took several hours to be performed by Excel. To improve the calculation time accuracy must be
sacrificed. Finite elements becomes a better method to use for complex geometries
because of its greater accuracy and reduced computational time.
Appendix
B
Finite Element Analysis and
ADINA
B.1 Overview
This appendix will cover in detail the derivation of the necessary FEM equations used in
the analysis of the tether and necking sensor designs. The appendix will discuss the mathematical model, the solution method, and the use of the finite differencing program
ADINA used to solve these equations. This explanation will cover the issues discussed in
chapter 5 in greater detail.
B.2 Mathematical Model using FEM
Finite element methods model the behavior of physical bodies. These bodies can be solid
materials or moving fluids. Finite elements can model the elastic properties of a material,
the electrical properties, or the heat transfer of a body (as is done in this work). The analysis begins by considering a body, such as the example in Chapter 5 and shown in Figure
B.l.
115
116
Annendix B: Finite Element Analvsis and AINA
116
~Sf
node
0'
SU
Figure B.1: General finite element body
Any body such as the one in figure B. 1, including the device designed in this work, is governed by the "principle of virtual work." This principle states that the body must remain in
equilibrium for any compatible, small virtual displacement (in this case temperature) [15].
Compatible means that the virtual displacements are zero at the prescribed displacements,
SU. This principle, called the "principle of virtual temperatures" when applied to heat
transfer, is represented by the following equation, discussed in chapter 5 [15,16].
f
V
s sdS +X
Tko'dv = JqBdv +
V
0Q
(B.1)
S
This equation was discussed in chapter 5, and represents the equilibrium between the
external virtual work on the right side and the internal virtual work on the left. Refer to
chapter 5 for the discussion of this equation.
117
Appendix B: Finite Element Analysis and ADINA
The body is broken up by meshing into several finite elements, as is shown in figure B. 1. Meshing is the griding system used to define each element. An element is represented by nodes. Figure B. 1 shows an 8 node element. Each node represents a temperature
and three directional temperature gradients. For any element such as the one in figure
B.ithe temperature and temperature changes can be represented by the following equations, already discussed in chapter 5 [15].
S(m)
((m)
_
(m)6
(B.2)
n(m)g
(B.4)
A brief review of these equations shows the right hand side temperature vector is a vector
of all nodal points. The left hand side of each equation represents the elemental temperature or temperature gradient.The H and B vectors are represented of the nodal position in
relation to the center of the element and are formed as discussed in chapter 5. S denotes
surface areas that are effected by heat flux, convection and radiation, and only apply to
nodes on the surface of the body.
Substituting these equations into the "principle of virtual temperatures" yields the
following equation[ 15].
fETkAdV+
V
hH THsdS
S
HT qBdV+
V
H sT sdS
(B.5)
Sq
This equation is only applied to individual elements, and now must account for all the elements forming the body, the sensor in this case. The following equation takes the summation of all elements[15]:
118
118
Appendix B:
Element Analysis
Analysis and
ADINA
and ADINA
Element
~
Appendix B: Finite
M
Sh(m)H s(m)TH s(m)ds(m)
()+
$( m)Tk (in)
V(m)
in
lj
S(m)
(B.6)
('( fH
m V(m)
HS (m)T qs(m) d(m)
+) '
m Sq(m)
(m)T qB (m) dV~m
This equation can be simplified to the following representation:
0
1k +c
(B.7)
The values are represented by the following:
k =
J
(m)Tk$
dV
(B.8)
m V(m)
c =
h(m)H s(m)T H S(m)dS()
S
)
(B.9)
mnS(m)
Y =
(B.10)
B -- Y S
The B and S value of Q represent internal heat generation and surface flux respectively, as
shown in the following equations[15]:
B =
(
m
H(m)T qB(m)dv(
J
))
(B.11)
V(m)
Hs(m)T s(m)dS (in)
S
(B. 12)
m Sq(m)
All of the convective terms can be eliminated since convection is neglected in this analy-
sis, yielding:
kg-_
(B. 13)
The critical component necessary to have in order to solve this equation is K, the conductivity matrix.
Q is based
on known internal and external heat generation. The critical com-
119
119
App~endix B: Finite Element Analysis and ADINA
ADpendix B: Finite Element Analysis and ADINA
y
A
Node 2
Node 1
1
Center
x
Node 3
Node 4
Figure B.2: Example finite element
ponents of each are the values of H and B. The following example shows the construction
of H and B based on a simple four node, 2-d element, for temperature.
Figure B.2 shows the layout of this element. This body has sides of length one. H
is a matrix that indicates the position of each node in relation to the reference frame, which
goes through the center in this case. H is given in the following:
H
I(1 + x) - (1 ±y)
(1 - x)
(1 + y) (1 -x)
(1
y) (1 + x) - (1
y)
(B.14)
B is the Jacobian times the derivative of H with respect to each direction. H' is the follow-
ing:
H' =
(1 + y) -( +
4 (1+ x) (1 -x)
( 1l-Y) ( -Y)
-(1 -x) -(1 +x)
(B.15)
The Jacobian operator is simply the identity matrix since the element is square and the
local and global coordinates are the same. This J gives:
120
B = H'
(B.16)
Using this method the values of H and B are determined for each element in the body.
These values help form the conductivity matrix, allowing the equation B. 14 to be solved
for by simultaneous equations. The boundary condition temperature is placed in the equations for the appropriate nodes; nodes that are on the chip's edge in this case. This provides the systems with enough known variables to allow for the reset of the unknown to be
solved for using the remain equations.
B.3 Transient Response Modeling
For the transient response in chapter 5 the model was modified to the following. First, the
equations are adjusted to the following:
t + At0 (m)
_
(m)t + At0
(B.17)
t+At S(m)
_
S(m)t + At,
(B.18)
-
(m)t + At0
(B.19)
t + At
(B.20)
t + At ,(m)
kt + At
In transient analysis, the heat capacity effects must also be added. The following is added
to the left hand side of the principle of virtual work:
f '
Tt + At t + At,1
k
0'dV
(B. 21)
V
The value of QB is also adjusted to include a heat capacitance effect.
t + At
OB =
Y j
M V(m)
fl(m)T(tAt B(m)
Fmq
t+At(pcf m)
(ldV
(m)t +At_)
(m)
(.2
AppDendix B: Finite Element Analysis and ADINA
121
Adjusting these parameters for the transient case a solution can be found for a time dependent model. A Euler method or Newton-Raphson method is used to solve these equations
in transient case. This modeling was used by ADINA to calculate the transient response of
the device.
B.4 ADINA modeling
ADINA modeling is completed using a CAD like system to define body geometries. Models can be calculated both 2-d and 3-d. For the designs discussed in this model, room temperature boundary conditions are placed on the edge surface areas around the chip.
Internal heat generation can be entered into the model by calculating a heat generation per
unit area and applying the heat generation to the appropriate volume. For example, the
heat generating for the necked tether is calculated, per unit area, and placed into the model
for the necked volume that this heat will be generated in. Material properties are entered,
originally as non temperature dependent, and later as temperature dependent properties.
122
Appendix B: Finite Element Analysis and ADINA
Appendix
C
Test Device Mask Sets
C.1 Overview
This appendix has the layouts of the designs developed for testing. The first three layouts
are the tested designs, and the final two layouts are design not yet tested.
C.2 Tested designs
Z
~
. .. . ....
Fiur
1
1li
...
U
. ...
2I 22CC1A
r.
iTest
N
il
1
1dl
..
1Z
J'
Dc
Figur .1: jTest1U..
D
h2C Z'A,
.1"
EsPoi
,LagD
efoain
123
124
Appendix: Test Device Mask Sets
a
G
r. i
____
...
-7'&L
l
. .15 ... ....
-
t
Z
9127
7
2:1=
.
i 5?*,
f d'ri
l
ri
...-....
--..
t7.'
1
-,
r
'
1j ,
1
r
r"
.J
.
1,t
--
-
1
.
-.1 1*,1^r
11.g 0
r
r
''
C~ ~ ~~ ~ ~ ~j C
N. 11cy
K
..
a)
, ' -,,
-:zi*
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111
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,,i'
n'~
.'.
,
-
t
'
r'
3
:,
5 ei
n
tio),
3*
;*
)t
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nV
.'1
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'
1
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-(i
r;
c;I
t
C
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..
21 f
l
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ro)co
( a (
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126
Appendix : Test Device Mask Sets
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