The Design of a High Precision, Wide Common
Mode Range Auto-Zero Comparator
by
Anders Wen-Dao Lee
S.B. EE, Massachusetts Institue of Technology (2014)
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2015
c Massachusetts Institute of Technology 2015. All rights reserved.
Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Department of Electrical Engineering and Computer Science
May 18, 2015
Certified by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Roger Zemke
Design Manager, Linear Technology
VI-A Company Thesis Supervisor
Certified by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charles G. Sodini
LeBel Professor of Electrical Engineering
MIT Thesis Supervisor
Accepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prof. Albert R. Meyer
Chairman, Masters of Engineering Thesis Committee
2
The Design of a High Precision, Wide Common Mode Range
Auto-Zero Comparator
by
Anders Wen-Dao Lee
Submitted to the Department of Electrical Engineering and Computer Science
on May 18, 2015, in partial fulfillment of the
requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
Abstract
This thesis discusses the design and analysis of a high common-mode input auto-zero
comparator for use in a Hot Swap controller. Comparators are essential building
blocks within the current limit detection schemes of Hot Swap controllers. However,
the current limit detection scheme places a sense resistor in the current path, burning static power. Reducing this power consumption while maintaining the overall
accuracy of the detector can be done by decreasing the full scale sense voltage across
the sense resistor, decreasing the size of the sense resistor, and increasing the overall
accuracy of the comparator. This is realized by using an auto-zero comparator designed in Linear Technology’s 0.6 µm BiCMOS process. The overall topology uses the
closed loop offset storage with an auxiliary amplifier scheme. The input and auxiliary
amplifier are based on the fully differential folded cascode topology with some key
changes. The comparator is a typical PMOS comparator with internal hysteresis and
additional circuitry added to maintain symmetry for as long as possible. A Widlar
bandgap-based circuit provides the necessary internal reference. The comparator was
designed and verified using LTspice and Linear Technologys in house models. The
resulting design has an absolute accuracy better than ±200 µV over temperature,
increasing the relative accuracy with the sense resistor value halved from previous
designs. Additionally, the comparator can handle inputs from zero to sixty volts and
settles to a new offset sample in less than 3 µs.
VI-A Company Thesis Supervisor: Roger Zemke
Title: Design Manager, Linear Technology
MIT Thesis Supervisor: Charles G. Sodini
Title: LeBel Professor of Electrical Engineering
3
4
Acknowledgments
I am eternally grateful to God for proving me with the opportunity, strength, and
wisdom to study at MIT for the past five years.
I would like to thank Roger Zemke, my VI-A company supervisor. Without his
guidance and patience, this project could not have happened. I appreciate the time
and effort he put into explaining concepts and circuits, building me up as a better
engineer. Bob Jurgilewicz was also a key figure in my time at Linear Technology. I
am very appreciative of the time he took to mentor me and to be available when I
needed help. To Sam Nork and the rest of the Boston design center team: thank you.
I would also like to thank Charlie Sodini for his guidance in the development and
writing of this thesis.
A very special thank you goes to Emily Seitz, my fiancée. I am thankful for your
patience and love as I finish my master’s program and am incredibly excited to spend
the rest of my life with you. Last but not least, I am thankful for my parents and
siblings. I would not be here if it werent for their love, support, and sacrifice. I am
indebted to how much they have done for me.
There are too many others to list by name who have been instrumental in my
life, whether it be mentoring, challenging, investing, or just being there for me. I am
extremely thankful for the roles you have played in my life.
5
THIS PAGE INTENTIONALLY LEFT BLANK
6
Contents
1 Introduction
17
1.1
Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.2
Existing Hot Swap Controller Limitations . . . . . . . . . . . . . . .
18
1.3
Thesis Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
1.4
Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
2 Theory of Auto-Zeroing
2.1
2.2
21
Auto-Zero Amplifier Configurations . . . . . . . . . . . . . . . . . . .
22
2.1.1
Open Loop Configuration . . . . . . . . . . . . . . . . . . . .
22
2.1.2
Closed Loop Configuration . . . . . . . . . . . . . . . . . . . .
23
2.1.3
Closed Loop Configuration with Auxiliary Amplifier . . . . . .
24
Auto-Zeroing and Noise . . . . . . . . . . . . . . . . . . . . . . . . .
26
3 Amplifiers
3.1
31
Input Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
3.1.1
Input Transistors . . . . . . . . . . . . . . . . . . . . . . . . .
31
3.1.2
Folded Cascode . . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.2
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3.3
Auxiliary Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.4
Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
4 Internal Comparator
4.1
41
Design and Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
7
41
4.2
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Voltage References
43
45
5.1
Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
5.2
Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
5.2.1
Classical Widlar Bandgap Reference . . . . . . . . . . . . . .
47
5.2.2
Thesis Bandgap and Resistor Sizing . . . . . . . . . . . . . . .
49
25mV Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
5.3
6 Switching
55
6.1
Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
6.2
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
6.3
Switch Construction . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
6.4
High Voltage Switching . . . . . . . . . . . . . . . . . . . . . . . . . .
59
6.4.1
Blast Signal Generators . . . . . . . . . . . . . . . . . . . . .
60
6.4.2
Voltage Clamp . . . . . . . . . . . . . . . . . . . . . . . . . .
61
7 Supplies
65
7.1
Low Voltage Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
7.2
Charge Pump Output
. . . . . . . . . . . . . . . . . . . . . . . . . .
66
7.3
VrailA andVrailD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
8 Final Design Verification and Conclusion
69
8.1
Offset Cancelation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
8.2
dV/dt Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
8.3
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
8.4
Closed Loop Step Response . . . . . . . . . . . . . . . . . . . . . . .
74
8.5
Capacitor Holding Time . . . . . . . . . . . . . . . . . . . . . . . . .
76
8.6
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
8.7
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
8.8
Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . .
79
8
A Tables of Transistors
81
B Threshold Accuracy Plots
85
9
THIS PAGE INTENTIONALLY LEFT BLANK
10
List of Figures
1-1 Comparator use scenario for the this thesis’s design . . . . . . . . . .
17
2-1 Open loop cancellation configuration . . . . . . . . . . . . . . . . . .
23
2-2 Closed loop cancellation configuration . . . . . . . . . . . . . . . . . .
24
2-3 Closed loop configuration with auxiliary amplifier . . . . . . . . . . .
25
2-4 The block diagram of the system designed for this thesis . . . . . . .
26
2-5 Typical noise spectral density of a MOS transistor [7] . . . . . . . . .
27
2-6 Auto-zero noise cancellation behavior modeled by an RC circuit [8] .
27
2-7 The effect of an auto-zero process on low passed noise with a bandwidth
five times larger than the sampling frequency [8] . . . . . . . . . . . .
28
2-8 The noise spectral density of the auto-zero amplifier with a sampling
period of 1ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
3-1 The input amplifier topology . . . . . . . . . . . . . . . . . . . . . . .
32
3-2 The bias cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3-3 The auxiliary amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3-4 The bode plot of auxiliary amplifier . . . . . . . . . . . . . . . . . . .
37
3-5 The transconductance effectiveness factor curve . . . . . . . . . . . .
39
4-1 The internal comparator’s topology . . . . . . . . . . . . . . . . . . .
42
4-2 The hysteresis loop of the internal comparator . . . . . . . . . . . . .
43
5-1 The first method of providing a 25 mV reference . . . . . . . . . . . .
46
5-2 The current implementation of the 25 mV reference . . . . . . . . . .
46
5-3 A classic Widlar bandgap cell . . . . . . . . . . . . . . . . . . . . . .
48
11
5-4 The bandgap cell used in the reference circuitry . . . . . . . . . . . .
49
5-5 The bandgap reference voltage versus temperature . . . . . . . . . . .
50
5-6 Generation of the 25mV reference from the bandgap . . . . . . . . . .
51
5-7 The 25 mV reference voltage versus temperature . . . . . . . . . . . .
53
6-1 The placement of switches around the the circuit . . . . . . . . . . .
55
6-2 The timing diagram of the switch logic . . . . . . . . . . . . . . . . .
56
6-3 The logic used to generate the proper clock signals
. . . . . . . . . .
57
6-4 A transmission gate . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
6-5 The circuitry used to level shift the logic signals . . . . . . . . . . . .
59
6-6 The half-monostable edge detectors used to generate the blast signals
60
6-7 The blast signal response of the edge detectors . . . . . . . . . . . . .
61
6-8 The voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
7-1 The implementation of the low voltage supplies . . . . . . . . . . . .
65
7-2 The charge pump modeling circuitry . . . . . . . . . . . . . . . . . .
66
7-3 The circuitry used to generate VrailA andVrailD . . . . . . . . . . . . .
67
8-1 simplified diagram showing testing . . . . . . . . . . . . . . . . . . .
70
8-2 The threshold error versus temperature in the typical-typical environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
8-3 The maximum dV/dt rejected versus the distance from the threshold
72
8-4 The quiescent analog supply current over temperature . . . . . . . . .
73
8-5 The quiescent charge pump current over temperature . . . . . . . . .
74
8-6 The closed loop step response over temperature . . . . . . . . . . . .
75
8-7 The time it takes to deviate 0.1% from the initial stored value . . . .
76
8-8 The leakage path of the storage capacitors . . . . . . . . . . . . . . .
77
8-9 The propagation delay versus overdrive . . . . . . . . . . . . . . . . .
78
B-1 The threshold accuracy measured in a typical-typical process . . . . .
86
B-2 The threshold accuracy measured in a fast-fast process . . . . . . . .
86
B-3 The threshold accuracy measured in a slow-slow process
87
12
. . . . . . .
B-4 The threshold accuracy measured in a slow-fast process . . . . . . . .
87
B-5 The threshold accuracy measured in a fast-slow process . . . . . . . .
88
13
THIS PAGE INTENTIONALLY LEFT BLANK
14
List of Tables
1.1
The core design goals for this thesis project
. . . . . . . . . . . . . .
19
3.1
The transconductances calculated using the EKV method . . . . . . .
39
8.1
The final design specifications . . . . . . . . . . . . . . . . . . . . . .
79
A.1 The N-channel devices used in the design . . . . . . . . . . . . . . . .
81
A.2 The P-channel devices used in the design . . . . . . . . . . . . . . . .
83
15
THIS PAGE INTENTIONALLY LEFT BLANK
16
Chapter 1
Introduction
1.1
Motivation
Hot Swap controllers are essential in many modern server and communication systems.
The inclusion of a Hot Swap controller allows circuit boards to be inserted or removed
into live system backplanes. The systems no longer have to be powered down for
system maintenance or load capacity adjustments. An essential function of the Hot
Swap controller is limiting the amount of current being passed to the load. This
current is sensed by placing a small resistor in the current path and comparing the
voltage drop across the resistor against a reference.
Figure 1-1: Comparator use scenario for the this thesis’s design
17
While this is a conceptually easy solution, there are several factors to take into
consideration while designing the current limit detecting circuitry. The accuracy of
the circuitry is constrained by the threshold voltages size and the absolute accuracy
of the comparator. The comparator must also be able to handle a wide range of
common-mode input voltages as the current sensing is done on the high side.
Auto-zeroing can be applied to the comparator to greatly increase its absolute
accuracy, reducing the necessary threshold voltage and increase the relative accuracy
of the system. An auto-zero comparator periodically samples its offset and then uses
a compensation network to drastically reduce its impact. As the offset changes due
to temperature, voltage, and time, the auto-zero comparator can recalibrate itself to
properly account for it. In addition to eliminating dc offsets, the auto-zero sampling
also greatly reduces 1/f noise. A precision trimmed comparator, while smaller, does
not have these advantages.
1.2
Existing Hot Swap Controller Limitations
There is a wide array of high voltage Hot Swap controllers on the market. These
controllers are able to take input voltages up to 80V, but none are able to ground
sense. They also have a current limit threshold voltages of at least 50mV with a typical
accuracy of only 10-20%. Linear Technologys only on-market Hot Swap controllers
that ground senses, meaning they can opperate with an input common mode voltage
of zero voltes, are the LTC4213 and the LTC4216. However, these controllers can
only handle voltages up to 6 volts. Their most accurate controller, the LTC4218, has
an accuracy of 5% on a 15mV threshold, but its voltage range only includes 2.9V to
26.5V. The most accurate high voltage control is the LTC4231, which has an accuracy
of 6% on a 50mV threshold and an input common mode range of 2.7V to 36V [1].
Texas Instruments’ TPS2490 Hot Swap controller has a common mode voltage range
of 9 V to 80 V with a threshold accuracy of 10% of 50 mV [2]. Maxim’s MAX5934
also has the same limitations as Texas Instrument’s part [3]. There are currently no
ground sensing high precision and high voltage controllers.
18
1.3
Thesis Goals
This thesis aims to develop an improved comparator for use in a Hot Swap controller
that satisfies or exceeds the core specifications in given in Table 1.1. The three
primary design objectives that must be met: the comparator is able to ground sense,
a 25mV threshold voltage used, and the system must be accurate within 1% of the
threshold voltage.
Input common-mode range
Maximum threshold error
Offset sampling blind time
Charge pump quiescent current
Propagation delay (response time)
0-60V
<1% of 25mV
<10 µs
<10 µA
<25 µs
Table 1.1: The core design goals for this thesis project
With an input common mode that includes ground, the current limiting circuitry
will be able to function if there is a short at the output. The 25mV threshold is half
the threshold of comparable devices on the market. This halves the power dissipated
by the sense resistor for a given current. With the increased accuracy, systems using
this chip do not have to be as conservatively designed.
The current specifications help to ensure that the comparator is still efficient and
does not impact the performance elsewhere on the chip. During the auto-zeroing
process, which is detailed in Chapter 2, there is a window where the comparator is
disconnected from the signal path. In order to minimize this time, the comparator
must be able to settle and calibrate within 10 µs. Propagation delay is the maximum
amount of time it takes for the comparator to signal an overcurrent situation. This
includes the blind time as the worst case scenario has the comparator offline right
when the current limit is breached. The comparator must also be able to hold this
calibration for a relatively long amount of time, on the order of a few milliseconds,
allowing for a small duty cycle. In addition to these requirements, design choices were
made to minimize quiescent current consumption off of the low voltage rails and to
minimize area consumption.
19
1.4
Thesis Outline
The rest of the thesis is organized as follows. Chapter 2 discusses the theory behind
the auto-zero circuitry, showing the basis for its advantages, limitations, and noise
behavior. The design, implementation, and performance of the amplifier stages is
presented in Chapter 3. Chapter 4 looks at the internal comparator design. The
voltage reference used to set the 25mV threshold is covered in Chapter 5. Chapter
6 includes the switch timing, switch construction, and logic level shifting circuitry.
The modeling and generation of the supplies and rails used in the design are detailed
within Chapter 7. Chapter 8 contains the testing setups, tests, and results that verify
the performance of the design. Finally, Chapter 9 summarizes the design and results
as well as providing suggestions for areas of further study.
The auto-zero comparator was designed using Linear Technologys 0.6 µm BiCMOS
process. This process has access to high voltage MOSFETs, some of which can
withstand voltages over 100V. Depletion-mode NMOS and PMOS devices are also
available. Depletion-mode NMOS and PMOS devices have negative and positive
threshold voltages, respectively, and pass current with zero Vgs . Tables detailing the
symbols, voltage ratings, and threshold voltages of the transistors used in the design
can be found in Appendix A.
The voltage rails used throughout the design are discussed in depth in Chapter
7, but are referred to throughout the rest of the design exposition. There are six
rails used throughout the system. The first are the low voltage analog and digital
supplies, PWRA and PWRD, which nominally are 2.5V. Next is the input voltage,
Vi , which can have a value from zero to sixty volts. A charge pump output, cpo,
sits twelve volts above Vi and analog and digital rails, VrailA and VrailD , maintain a
voltage approximately 4-5V above Vi .
20
Chapter 2
Theory of Auto-Zeroing
Although this thesis examines the implementation of an auto-zero comparator, the
core auto-zero circuitry is centered on an amplifier stage and, as such, this section
will deal mainly in the realm of auto-zero amplifier circuits.
The concept of an auto-zero amplifier is very simple: sample the offset of the
amplifier and then eliminate it from the input signal. While precision trimming a
device can be used to reduce its initial offset, there is no way to account for offset
shifts due to time, temperature, voltage stresses, and physical stress due to packaging.
An auto-zero circuit periodically adjusts for the offset, taking care of the initial offset
and its drift. Auto-zero circuits also heavily attenuate low frequency (1/f) noise
[4]. As long as the noise does not change much between the sampling phase and the
comparison phase, it will be reduced. Although the low frequency noise is attenuated,
the overall noise floor is raised due to the sampling aliasing of wideband noise.
The sampling nature of an auto-zero amplifier also causes the amplifier to be
offline during the sampling phase. Having the amplifier periodically offline is fine
in a discrete time circuit, but can be problematic in a continuous time application.
One way to address this issue is to use two amplifiers in parallel and ping-pong
between them, having one sample while the other is active. In the current sensing
application, it was determined that having a short blind time and small duty cycle
was less detrimental than the additional power and area that would be consumed
by adding a second amplifier. Additionally, this blind time can be wrapped into the
21
comparator response time specification. In the worst case scenario, the response time
is equal to the comparator’s blind time plus the propagation delay. If this is still less
than the desired response time, the comparator will be able to function unhindered
even with a window of blind time.
2.1
Auto-Zero Amplifier Configurations
An auto-zero amplifier can be implemented in three main ways: open loop cancellation, closed loop cancellation, and closed loop cancellation using an auxiliary amplifier
[5]. All of them act as normal amplifiers during the comparison phase but differ in how
they cancel and store the offset. Although these configurations could be implemented
as single-ended amplifiers, charge injection can become a dominant contributor to
error in an auto-zero circuit. By using at fully differential scheme, the impact of
charge injection is significantly reduced. The charge injection error is converted to a
common-mode term and then rejected by the differential architecture. In this section,
only the effect of auto-zeroing on DC offset will be explored. The next section will
discuss the impact auto-zeroing has on noise.
2.1.1
Open Loop Configuration
During the sampling phase, the open loop cancellation configuration, shown in
Figure 2-1, has its inputs shorted together and the outputs after the capacitors also
shorted. With the inputs shorted, the differential input voltage becomes only Vos and
the amplified version, Av · Vos , is stored on the capacitors. The shorts are removed
during the comparison phase and the input voltage consists of Vin + Vos . Because the
capacitors already have the amplified version of Vos stored, the voltage seen between
nodes X and Y is:
A(Vin + Vos ) − A(Vos ) = A(Vin )
22
(2.1)
Figure 2-1: Open loop cancellation configuration
A major limitation of this scheme is that the amplifiers gain must be low enough,
often less than 100 [5], so that it does not saturate when the offset is sampled. It is
possible to use several open loop auto-zero amplifiers in series to increase the overall
gain.
2.1.2
Closed Loop Configuration
The closed loop cancellation configuration, shown in Figure 2-2, uses a closed common
mode feedback loop to store the offset voltage on the input side of the amplifier. With
the inputs shorted together and the unity gain loop closed, the output, which is stored
on the input capacitors, is given as:
A
· Vos
A+1
(2.2)
During the comparison phase, the output seen is:
A
A Vin + Vos −
· Vos
A+1
23
Vos
= A Vin +
A+1
(2.3)
Figure 2-2: Closed loop cancellation configuration
The offset is reduced by the open loop gain of the amplifier! Storing the offset at the
input gives the distinct advantage over the open loop configuration of allowing the
amplifier to have extremely high gain. However, this configuration requires that the
amplifier to be unity gain stable [6]. Also, because the offset is stored at the input of
the closed loop cancellation configuration, it will be seeing the input common mode
voltage, which could be moving anywhere from ground all the way to sixty volts in
this application. Additionally, the thermal noise of the capacitors is no longer reduced
by the gain of the amplifier.
2.1.3
Closed Loop Configuration with Auxiliary Amplifier
This third topology is used as the basis for the auto-zeroing circuitry in this thesis.
By using a secondary amplifier and storing the offset in the feedback loop, as shown
in figure 2-3, the offset storage capacitors are no longer in the signal path or exposed
to moving high voltages and the amplifier is still able to have high gain. During the
sampling phase, the inputs are tied together and the loop is closed; ignoring Vos2 , the
24
Figure 2-3: Closed loop configuration with auxiliary amplifier
output voltage stored on the capacitors, can be derived as:
Vout1 = A1 Vos1 − A2 Vout1
Vout1 =
A1
· Vos1
1 + A2
(2.4)
(2.5)
During the comparison phase, the loop is broken but the auxiliary amplifier still
injects its offset correction into the output. The output referred offset voltage is:
Vout2 = A1 Vos1 − A2 Vout1
Vout2 = A1 Vos1 −
Vout2 =
A1 A2
· Vos1
1 + A2
A1
· Vos1
1 + A2
(2.6)
(2.7)
(2.8)
Which gives an equivalent input referred offset of:
Vos,ref =
1
· Vos1
1 + A2
(2.9)
The offset from the secondary amplifier is ignored in the calculations because it is
divided by the ratio of A1 /A2 when brought out to the input. By testing the system
25
beyond the expected Vos1 values, we can account for offsets from the auxiliary stage.
The amplifier gains were chosen such that A1 is large and A2 is still big, but smaller
than A1 . A large A2 is needed because the overall input referred offset is proportional
to the input offset divided by the gain of the second stage. A1 must be larger than A2
so that the sampled voltage is large enough that small fluctuations caused by charge
injection are negligible. Any offset from charge injection, the auxiliary stage, or the
internal comparator is reduced by A1 when input referred. A large A1 ensures that
the input stage dominates the offset.
The closed loop configuration with an auxiliary amplifier with a comparator block
added to the end is used in this thesis, as shown in Figure 2-4. The capacitors right
before the comparator block hold the signal during the sampling phase, preventing
the comparator’s output from varying uncontrollably.
Figure 2-4: The block diagram of the system designed for this thesis
2.2
Auto-Zeroing and Noise
Auto-zero amplifiers attenuate 1/f noise in addition to eliminating offset. However,
because they are under-sampled systems, wide band white noise is aliased back into
the baseband, raising the overall noise floor. Noise within the circuit is generated
26
by the transistors and capacitors. MOS devices have flicker (1/f) noise and thermal
noise. The 1/f noise is a result of traps near the silicon/oxide interface which randomly
capture and release carriers. Thermal, or Johnson-Nyquist, noise is caused by thermal
agitation of charge carriers and is approximately white. The storage capacitors also
generate thermal noise, which is proportional to kT/C, where k is the Boltzmann
constant and T is the temperature. A 1 pF capacitor can cause up 64 µV of noise but
because the storage capacitors are after the input amplifier, the kT/C noise becomes
much smaller when input referred.
Figure 2-5: Typical noise spectral density of a MOS transistor [7]
Figure 2-6: Auto-zero noise cancellation behavior modeled by an RC circuit [8]
The noise cancellation behavior can be modelled as subtracting a periodic sample
27
from a time varying noise source (made up of 1/f and white noise). DC and low
frequency noise do not change much from the sample and are attenuated while high
frequency noise is not; the circuit acts as a high pass filter. Figure 2-6 models this
behavior using and RC circuit. During the sampling phase, the switch is closed
and the noise source, VN , appears across the capacitor, assuming that the RC time
constant is much less than the sampling time. During the comparison phase, the
output voltage now becomes the difference between the current value of VN and the
sampled value on the capacitor. The capacitor, however, is storing information about
the high frequency noise at the sampled time, causing low frequency errors when it
is held and subtracted. The under-sampling of the system causes the wideband noise
of the replicas to alias back into the base band. While the DC offset and 1/f noise
are greatly attenuated, the overall noise floor is raised [8].
Figure 2-7: The effect of an auto-zero process on low passed noise with a bandwidth
five times larger than the sampling frequency [8]
The definition of white noise is noise that has equal power spectral density over
all frequencies. This is not a realistic representation of noise in a circuit because ideal
white noise has infinite power. To model the noise within the system, band-limited
28
white noise is used. Because the amplifier acts like a single pole system through its
0dB point, the noise bandwidth can be determined using the equation derived in [9]:
fN =
π
· f1 = 1.57f1
2
(2.10)
Where fN is the noise bandwidth and f1 is the -3dB frequency of the amplifier.
The input amplifier has a cutoff frequency (f1 ) of 8kHz, giving a noise bandwidth of
12.8kHz. Figure 2-8 shows the input, high-passed, and aliased output noise spectral
density of the auto-zero amplifier with a sampling period of 1ms. The RMS noise has
been reduced from 17.9 µVrms to 4.4 µVrms .
Figure 2-8: The noise spectral density of the auto-zero amplifier with a sampling
period of 1ms
29
THIS PAGE INTENTIONALLY LEFT BLANK
30
Chapter 3
Amplifiers
This chapter presents the requirements, design, and implementation of the amplifier
stages. The heart of the auto-zero comparator is an auto-zero amplifier. Two amplifiers are needed for the topology used in this thesis: the input amplifier and the
cancellation amplifier.
3.1
Input Amplifier
The input amplifier fulfills two main duties within the auto-zero comparator: level
shifting the input signal and providing a high gain input stage. By level shifting the
input immediately, the rest of the auto-zero circuitry can be done using well defined
voltage rails. It also eliminates the need for many high voltage tubs and reduces
the impact of common mode steps, which would be the case if the signal were level
shifted at the output. A PMOS input, fully differential folded cascode topology was
used to realize these requirements. Additionally, this topology also provides 720mV
of output swing.
3.1.1
Input Transistors
The differential pair of the input amplifier consists of six PMOS devices, mpi1 through
mpi6 . A PMOS input stage was used to meet the zero common-mode voltage require31
Figure 3-1: The input amplifier topology
ment. Although PMOS amplifiers common-mode voltage usually doesn’t include the
upper rail, the charge pump sitting on top of the input voltage eliminates any headroom issues.
The 5V PMOS, mpi1 through mpi4 , are isolated devices; as long as their terminals
stay within 5V of each other, they will not be damaged. This remains the case as
mpi5 , mpi6 , and mpi14 consume an excess voltages that could potentially harm the
inputs. The native devices mpi1 and mpi2 have a threshold voltage of -1.48V while
the enhancement devices mpi3 and mpi4 have a threshold voltage of -0.95V. They are
cascoded by tying their gates together. Provided that all of these devices remain in
saturation, the gm of the input amplifier is determined only by the gm of mpi1 and
mpi2 . By implementing noth mpi1 and mpi2 with two unit transistors with a W/L of
32
50/2, the input amplifier has a fairly large transconductance. Further discussion of
the sizing can be found later on in this chapter.
The high voltage transistors mpi5 and mpi6 are depletion mode PMOS devices and
do the brunt of the level shifting. The drains of mpi5 and mpi6 are tied to low voltage
nodes, which sit nominally at 400mV, in the transistor stack. Because depletion
mode PMOS devices have a positive threshold voltage, mpi5 and mpi6 are always
in saturation and do not affect the small signal performance of the amplifier. They
only consume any excess voltage, should any appear between the inputs and the low
voltage nodes.
3.1.2
Folded Cascode
The stack of transistors is based on the folded cascode topology but has been adapted
to meet the requirements of this application. The new topology also has a well biased
output, allows for input level shifting, and provides a low impedance node that can
be used for multiple inputs. This comes at the cost of the very high gain of a folded
cascode, however, the amplifier still has the gain similar to a basic active load.
The NMOS devices are still cascoded; mni1 and mni2 have a threshold voltage of
0.37V and mni3 and mni4 have a threshold voltage of 0.78V. The voltage on the nodes
that the input transistors feed into is a low impedance node and hence very stable.
This allows the secondary amplifier stage, which will be discussed in later on in this
chapter, to feed into there without impacting the performance of the input amplifier.
The PMOS transistors, however, are no longer cascoded.
The top PMOS, mpi7 and mpi8 , have their gates tied to an output, setting the
common-mode output voltage to a Vgs below the top rail. The drains of the mpi7 and
mpi8 are also tied together, allowing the output of the amplifier to still swing. By
having the drains tied, either mpi7 or mpi8 can be turned off due to its output swinging
high while the other supplies the current for both branches. With this topology, the
output resistance looking up into the PMOS is now only on the order of ro instead
of gm ro , reducing gain. If there were no short between the drains, mpi7 and mpi8
would effectively act as diode connected transistors, providing a small signal output
33
resistance 1/gm path to ground. This can also be explained on a larger scale: the
gate-source voltage of the diode connected transistor is relatively fixed as it passes
current. The differential current from the input transistors is only a few nanoamps
over the operating range of interest so a diode connection would provide almost no
differential voltage at the output.
The topology, sizing and biasing used provides a DC gain of 72dB, or a gain of
4000, and a gain-bandwidth product of 17.2MHz.
3.2
Biasing
Figure 3-2: The bias cell
The biasing cell provides the reference voltages and currents used throughout
34
the auto-zero comparator. Because the 0.6 µm BiCMOS process has depletion mode
devices, a low voltage depletion NMOS is used to produce the reference current. By
grounding the mnb2 s gate and placing a resistor between its source and ground, a
reference current inversely proportional to the resistor size is generated. This current
only fluctuates by ±10% over temperature.
The ouput current of the depletion NMOS biases a pair of cascoded PMOS devices
that are diode connected. The PMOS are cascoded to enhance the Vds matching as the
current is mirrored. The PMOS device current is then mirrored to set up the current
bias for the NMOS devices. These gate voltages are used to set the bias voltages in
the input amplifier and keeps the currents throughout the amplifier and comparator
stages relatively constant within the circuit. To scale the current, multiples of the
same transistors are used, i.e. 2 µA and 1 µA can be generated from the same reference
by using twice as many devices in parallel for the 2 µA mirror. This helps to ensure
that the currents are all properly ratioed. If the current ratios were set by resizing
the W/L ratios, the δW and δL error terms between devices would not track as
consistently. For example, using multiples proveds a width of 2 · (W + δW ), twice the
original size, W + δW . If the device width increased by a factor of 2, the new area
would be 2 · W + δW , which is no longer scales the error terms as well.
It is important that this same current is also sent through the input transistors,
although it must be taken off of VrailA . The current is mirrored using the NMOS
bias voltage and then sent up and mirrored with PMOS devices off of VrailA . To
protect the low voltage devices, mni5 is placed in the current translating path. The
gate of mni5 is tied to the low voltage supply, so mni6 and mni7 never see anything
above that. In earlier design iterations, the input transistors current was supplied
by a depletion mode PMOS. However, when process variations and temperatures
were tested, the PMOS and NMOS current sources would sometimes drift in opposite
directions. When the input transistor current decreased and NMOS current increased,
the gain of the input amplifier was drastically reduced.
35
3.3
Auxiliary Amplifier
Figure 3-3: The auxiliary amplifier
The offset cancellation amplifier consists of a PMOS differential pair that feeds
into the same low impedance node as the input differential pair. The differential
pair consists of cascoded devices to reduce any loading effect they may have on the
input amplifier. Transistors with low threshold voltages had to be used to prevent
the cascode from pushing the current mirror out of saturation. mpa1 and mpa2 have
a threshold voltage of -0.75V while mpa3 and mpa4 have a threshold voltage of -0.4V.
While the very thin low Vt devices used for mpa3 and mpa4 are not very consistent,
they are only used for providing increased resistance and do not affect the stages gm
while in saturation.
The storage capacitors, ca1 and ca2 , are tied to supply rather than ground because
PMOS devices are being used. Even if the voltage rail were to move, the Vgs on
36
Figure 3-4: The bode plot of auxiliary amplifier
the capacitors would still be relatively constant. If the storage caps were tied to
ground, the gate voltagess of mpa1 and mpa2 would be pinned while their source
voltages moved, creating a varying Vgs and reducing the effectiveness in the amplifier’s
cancellation.
The auxiliary amplifiers transfer characteristics must allow it to be stable when
a unity gain loop is closed around it during the sampling phase. No additional
compensation capacitors need to be added to the system because they are already
implemented with the offset storage capacitors. With these capacitors, the amplifier
acts like a single pole system and its closed loop bode plot can be seen in Figure
3-4. It has a DC gain of 58dB, a gain of around 800, a phase margin of around 90◦ ,
and a crossover frequency of 470kHz. The 90◦ of phase margin creates a very stable
system and while the 470kHz crossover frequency isnt very fast, it is fast enough for
the system to settle within 0.1% of its final value in less than 3 µs. [10] The bode
plots of the offset cancellation amplifier are shown in Figure 3-4.
37
3.4
Device Sizing
The sizing of the differential pairs is a key factor to the device offset, transconductance, and overall performance of the auto-zero comparator. The standard deviation
of the offset caused by mismatch between a pair of closely spaced devices can be
described using the Pelgrom model [11]:
An
σ=√
WL
(3.1)
As the area of the devices increases, they are more accurately matched. The
constant Ap is dependent on the fabrication process and is approximately 12 mV · µm
in the 0.6 µm BiCMOS process. The offset of the input pair of transistors has a
standard deviation of 0.85mV, meaning 99.9% of the devices produced will have a
mismatch of less than 5.6mV.
The EKV model was used to determine the transconductance of the differential
pairs. First the nominal transconductance is found using the equation:
gmo =
Id
nVt
(3.2)
Where Id is the drain current, n is a process parameter (equal to 1.4 in the 0.6 µm
BiCMOS process), and Vt is the thermal voltage. Then the transconductance is
multiplied by the transconductance effectiveness factor (TEF). The TEF is modeled
as a sigmoid curve defined by equation 3.3 and represents how far into strong or
weak inversion the device is. This curve is shown in Figure 3-5. The value of x is
determined by equation 3.4; the constant kx is process and device dependent. It is
approximated as 21 for a PMOS device in the 0.6 µm BiCMOS process. [12]
1
T EF = p
√
1 + 0.5 x + x
x=
kx Id
W/L
(3.3)
(3.4)
As derived in Chapter 2, the auxiliary amplifiers offset is reduced by a factor of
38
Figure 3-5: The transconductance effectiveness factor curve
Input Amp
Aux Amp
W/L
100
0.267
Id
x
TEF gmo
1 µA 0.21 .834 27.5
1 µA 78.8 .109 27.5
gm
22.9
2.99
Table 3.1: The transconductances calculated using the EKV method
gm1 /gm2 when input referred. By making gm1 much larger, any offset from sources
other than the input differential pair is negligible. Table 3.1 shows the values described
in this section for the input and auxiliary amplifiers.
39
THIS PAGE INTENTIONALLY LEFT BLANK
40
Chapter 4
Internal Comparator
After the input signal is compensated for offset and amplified, it is sent to the internal
comparator. The internal comparator’s purpose is to convert the differential signal
into a single-ended logic level output. It does not have to be extremely accurate as
its offset is divided by the gain of the first stage when input referred.
4.1
Design and Operation
The architecture of the comparator is based on a PMOS variant of the complete comparator with internal hysteresis found in [13]. The additional wrap around circuitry
was taken from a previous Linear Technology comparator design. The wrap around
circuitry allows the circuit, including the hysteresis, to be symmetric for as long as
possible. A PMOS variant was used to match the input amplifier stage because the
output of the input amplifier is biased relative to the supply rail using a PMOS device.
If an NMOS comparator were used, a low supply rail could cause the comparator’s
input Vgs to be below the threshold voltage, severly impacting performance. The
capacitors cc1 and cc2 hold the comparator’s input when the system is sampling the
input offset. This holds the comparator’s output value and prevents glitching during
the sampling phase. Because a PMOS comparator was used, the capacitors are tied
to the supply rail instead of ground to maintain a constant Vgs even if the rail moves.
To discuss the operation of the comparator, the hysteresis will be initially ignored
41
and then accounted for later.
When a positive differential signal is applied across the inputs, cip and cin , the
gates of mpc2 and mpc1 respectively, the current through mpc1 increases and the current
through mpc2 decreases. If the differential signal is large enough, all of the tail current
will flow through mpc1 . The increased current passes through mnc6 and causes the
gate of mnc6 to rise. mnc5 mirrors this increased current, pulling it through mpc3 .
When the comparator tries to mirror this current to mpc6 , there is no path for it to
flow. The decreased current through mpc2 has shut off the gate of mnc10 . mpc4 acts
as a short to the analog supply rail, pulling the drain of mpc6 up. The output is then
sent to a series of inverters providing a logic level output, Vco .
Figure 4-1: The internal comparator’s topology
When a negative differential signal is applied, mnc5 and mnc6 shut off, turning off
mpc3 through mpc6 . mnc4 , mnc9 , and mnc10 are now turned on; mnc10 acts as a short
to ground. This output is then sent through the inverters, providing Vco .
The circuit without hysteresis can also be thought of as a 1/gm loaded stage
feeding into an actively loaded common source amplifier. The first stage is the PMOS
42
differential pair loaded with diode connected transistors, providing a gain of around
1. The second stage consists of mnc4 and mnc10 acting as an NMOS in a common
source amplifier loaded by the cascode of mpc4 and mpc6 . This provides a high gain
stage whose output is sent to the inverters.
4.2
Hysteresis
Figure 4-2: The hysteresis loop of the internal comparator
The comparators hysteresis is generated by mnc7 and mnc8 . When the comparator
is in its low state, mnc7 is off while mnc8 is on. The drain of mnc8 is connected to the
negative input current path and wants to be pulling 3/2 the current through mnc9 .
As the differential voltage heads towards the positive trip point, mpc1 turns on. Once
it is able to supply enough current such that id,mnc8 = 1.5 · id,mnc9 , the comparator
trips. The same process occurs when transition from high to low. mnc7 wants to draw
1.5 · id,mnc6 and the comparator will only trip once mpc2 is able to source that much
current. The hysteresis of the comparator is ±50 mV. When referred to the input
43
of the input amplifier, this hysteresis becomes less than 15 µV. Because the overall
system is slow to respond to low overdrive situations, input referred hysteresis is not
of much concern. However, the internal hysteresis helps to suppress output errors
caused by random and coherent noise.
44
Chapter 5
Voltage References
The 25 mV reference needs to be accurate. Even if the rest of the design has nanovolt
accuracy, a bad reference can completely destroy accuracy.
5.1
Approach
One approach to implementing the 25 mV threshold is injecting the offset into a low
impedance node. The amplifier topology used already has the auxiliary amplifier
injecting an offset cancelling current. If a second auxiliary current is controlled to
equal a 25 mV offset, then the reference can be generated completely with a low
voltage reference and low voltage devices. The gm of the input stage is controlled by
the dimensions of mpi1 and mpi2 in Figure 3-1 as well as their bias currents. Generating
a 25 mV differential signal as well as matching the widths and lengths are both fairly
simple, but matching current becomes an issue with a high voltage input. As the input
voltage increases, the leakage from the high voltage transistors also increases. If the
currents are going to be mirrored and matched, there will have to be at least one high
voltage transistor within the current mirror path as the current is translated from
the low voltage rail up to the charge pump. This high voltage transistor can have up
to 10 nA of leakage current out of a total 1 µA at high voltage and high temperature.
The mismatch in current limits the amount of matching between the input stage and
the offset injection stage and limits the overall accuracy of the comparator.
45
Figure 5-1: The first method of providing a 25 mV reference
The second approach to generating the 25 mV offset reference is to place a reference
voltage on top of the input rail. The voltage cannot be placed 25 mV below the rail
as the common-mode input voltage range needs to include ground. Approaching the
reference with this method provides some distinct benefits. Firstly, the bias current
of the input differential pair no longer needs to precisely match any other currents
throughout the system. It also allows for the offset voltage sampling conditions to
match the trip point. In the first approach, the comparator trips when the negative
input is 25 mV below the positive input. With the second approach, the comparator
can be set to trip right when the positive input becomes greater than the negative
input, identical to the sampling phase environment.
Figure 5-2: The current implementation of the 25 mV reference
46
5.2
Bandgap Reference
The reference voltage is first generated using a bandgap voltage reference, providing good stability over temperature. The bandgap reference used in this thesis was
taken from a previous Linear Technology design and is based on the classical Widlar
bandgap reference.
5.2.1
Classical Widlar Bandgap Reference
A bandgap reference generates its stable output voltage by combining a temperature
coefficients that are complementary and proportional to absolute temperature (CTAT
and PTAT, respectively). If sized correctly, they will cancel each other out, resulting
in minimal temperature drift [14].
VREF = VCT AT + VP T AT
(5.1)
δVCT AT
δVP T AT
=−
δT
δT
(5.2)
δVCT AT
δVP T AT
δVREF
=
+
=0
δT
δT
δT
(5.3)
During the operation of a Widlar bandgap cell, shown in Figure 5-3, the ∆VBE
between Q1 and Q2 can be expressed as:
∆VBE = VBE1 − VBE2 = I2 R3
∆VBE = Vt ln
I1
Is1
− Vt ln
I2
Is2
(5.4)
(5.5)
If VBE1 is assumed to be approximately equal to VBE3 , the following relationships
develop:
I1 R1 = I2 R2
I2 =
∆VBE
R3
I1
R2
=
I2
R1
Vt
I1 Is2
Vt
Is2 R2
=
ln
=
ln
R3
I2 Is1
R3
Is1 R1
47
(5.6)
(5.7)
(5.8)
Figure 5-3: A classic Widlar bandgap cell
The output voltage, VREF , of the Widlar cell can now be defined as:
VREF
R2
= VBE3 + I2 R2 = VBE3 +
ln
R3
Is2 R2
Vt = VBE3 + KVt
Is1 R1
δVBE3
δVt
δVREF
=
+K
δT
δT
δT
(5.9)
(5.10)
The temperature coefficient of a NPNs base-emitter junction is approximately −2 mV/◦ C
[15] while the temperature coefficient of Vt is around 0.085 mV/◦ C. The values of Is1
and Is2 are directly proportional to the areas of their respective BJTs. By properly
sizing the transistors and resistors, the two temperature coefficients can cancel each
other out. The reference voltage at this point is nominally 1.2-1.3 V.
Although the Is and resistor values have some temperature dependence, these are
cancelled out to the first order by being used in ratios. As temperature begins to
48
drift away from the initial bias point, To , the temperature coefficients start to move,
changing VREF by up to a few millivolts.
5.2.2
Thesis Bandgap and Resistor Sizing
Figure 5-4: The bandgap cell used in the reference circuitry
The major difference between the Wildar reference and the reference used in this
thesis is the presence of rbg4 . The output voltage now appears on top of rbg4 instead of
rbg1 and rbg2 . By including rbg4 , rbg1 and rbg2 can now be matched and less resistance
is used overall. If rbg4 were not used, both rbg1 and rbg2 would have to be increased by
122 kΩ. VREF can now be set by trimming a single resistor without altering the bias
49
condition in the rest of the cell. The new expression for VREF is given by equation
5.11
VREF = VBE3 + I2 Rbg2 + 2I2 Rbg4
Rbg2 + 2Rbg4
ln
= VBE3 +
Rbg3
Is2
Is1
Vt
(5.11)
The output of the bandgap reference, shown in Figure 5-5, varies by 3.5 mV over
temperatures ranging from -55◦ C to 125◦ C. This movement gets reduced by a factor
of 50 when scaled to the 25 mV reference, resulting in 70 µV of movement at the
reference. This change in reference voltage is the small enough that the auto-zero
comparator can still meet the accuracy specification.
Figure 5-5: The bandgap reference voltage versus temperature
rbg4 was sized by iterating through many resistor values and plotting the reference voltage versus temperatures from -55◦ C to 125◦ C. The circuitry that transposes
the bandgaps output to a 25mV reference also has some fluctuations due to increased
leakage current with increased temperature. Sizing the resistor in the bandgap refer50
ence properly helps mitigate the impact of these leakages.
5.3
25mV Reference
The output of the bandgap reference must be scaled down to 25 mV and translated on
top of the input voltage. This is accomplished by generating a current proportional
to the bandgaps output voltage and then mirroring it off of the charge pump output,
as shown in Figure 5-6.
Figure 5-6: Generation of the 25mV reference from the bandgap
The bandgaps output is sent to one terminal of an actively loaded differential pair,
which drives the NMOS mnr3 . The current flowing through mnr3 is determined by
51
the bandgaps voltage and the resistance of rr3 ; its value of 1.252 MΩ sets a nominal
current of 1 µA. This current is then mirrored off of the charge pump output using
transistors mpr1 through mpr4 and sent down through rr1 to the load. The voltage
that appears on rr1 is the bandgap voltage scaled by the factor rr1 /rr3 . Although
the differential pair will have a systemic offset of up to 2mV due to non-infinite gain,
the offset is also scaled down with the overall voltage resulting in less than 50 µV
of movement at the 25 mV reference. Because the systemic offset is also relatively
constant over temperature, its impact can be reduced when either rr1 or rr3 are
trimmed.
The bias current through mnr1 and mnr2 is set by the resistor rr4 . The common
source node is a Vgs below the output of the bandgap reference, about 500mV. With
a resistance of 250 kΩ, rr4 sets a total bias current of around 2 µA.
The charge pump output was used instead of VrailA to provide headroom for
the cascoded diode connected PMOS transistors. The cascode was created this way
(instead of tying the gates of mpr2 and mpr4 together) because references accuracy is
critical to the performance of the entire system and depends on the current matching
between the two branches.
The high voltage NMOS, mnr3 , was implemented using a depletion mode device.
When an enhancement mode transistor was used, the differential pair began to have
headroom issues. The output of the differential pair was set to approximately 1.25 V
+ Vgs,mnr3 . With the low voltage supply being only 2.5 V, mpr5 was being pushed
out of saturation. A depletion mode NMOS has a negative threshold voltage and
eliminates this problem. It does run the risk of trying to pull the output too low;
rr2 was placed to prevent that. rr2 provides a fixed voltage bump over temperature
for the same reason the 25 mV drop across rr1 is fixed, its ∆R tracks that of rr3 .
Additionally, the depletion-mode NMOS was sized near minimum size to reduce its
parasitic capacitance. As the input common-mode voltage changes, the charging and
discharging of mnr3 ’s parasitic capacitances is the leading contributor to threshold
errors.
The resulting DC reference voltage versus temperature relationship is shown in
52
Figure 5-7. It has the characteristic upside down parabola shape found in bandgap
references.
Figure 5-7: The 25 mV reference voltage versus temperature
53
THIS PAGE INTENTIONALLY LEFT BLANK
54
Chapter 6
Switching
There are three sets of switches, S1, S2, and S3, that must be properly timed for
the auto-zero comparator to switch states and settle quickly. S1 determines whether
the internal comparator is connected to the input signal path, S2 determines whether
the inputs are sampling the reference or monitoring the input, and S3 determines
whether the offset cancelation loop is open or closed. The placement of the switches
throughout the circuit can be seen in Figure 6-1
Figure 6-1: The placement of switches around the the circuit
55
6.1
Switch Timing
Although the auto-zero comparator has two main states, the sampling and comparison
phases, the switches also have intermediary states. The sequence in which the switches
are connected and disconnected can impact the overall performance of the system.
The timing diagram showing the switch controlling signals is shown in Figure 6-2
Figure 6-2: The timing diagram of the switch logic
When transitioning from the comparison phase to the offset sampling phase, S1 is
first turned off, disconnecting the internal comparator from the input signal path. The
internal comparator only sees the inputs stored on its capacitors and the transients
and changing values from the cancellation phase do not reach the output. S2 is
then turned off, turning on S2B, and the inputs of the auto-zero comparator are tied
together. After the inputs are tied together, S3 turns on and the offset cancellation
loop is closed.
When transitioning from the offset sampling phase to the comparison phase, S3 is
the first switch to be turned off. This breaks the offset cancellation loop, stores the
offset, and prevents this stored offset from being affected by the rest of the switching
sequence. S2 then reconnects the inputs to monitor the voltage drop across the sense
resistor. As the output of the input amplifier approaches its final value, the internal
56
comparator is reconnected. The short delay, t21 , between switching the input transistors and reconnecting the internal comparator prevents the discrepancy between the
closed and open loop values from incorrectly tripping the comparator.
6.2
Clock Circuitry
The entire switching system is controlled by a single enable signal. When the signal
is low, the auto-zero comparator is in its sampling phase. When the signal changes
to a high level, the auto-zero comparator transitions out of the sampling phase to
the comparison phase. The clock circuitry, shown in Figure 6-3, contains a series of
logic gates and delays that properly spaces out the transitions of the different clock
signals.
Figure 6-3: The logic used to generate the proper clock signals
57
6.3
Switch Construction
The majority of the switches used throughout the auto-zero comparator are simple
transmission gates, as shown in Figure 6-4. Transmission gates allow for conduction
in both directions, even as the signal approaches the rail voltages. The MOS devices
are minimum sized to reduce gate area, minimizing the amount of charge injected as
the switch turns on and off. No compensation for charge injection, such as dummy
MOS devies, is needed as nearly the whole design is fully differential and symmetric.
The signals and the capacitors they are being stored on are also large enough that
mismatch due to charge injection has a minimal impact.
Figure 6-4: A transmission gate
The only switches that are not implemented as transmission gates are the main
input switches, controlled by S2 and S2 in Figure 6-1. These switches are implemented
using back-to-back NMOS devices. Even though the input voltage may reach 60 V,
low voltage devices can be used by placing them in tubs connected to the input
voltage. NMOS switches had to be used as PMOS switches cannot be turned on if
the common-mode input voltage is at ground. The input switches are controlled by
versions of S2 and S2B level shifted to switch between the input voltage and VrailA .
58
Figure 6-5: The circuitry used to level shift the logic signals
6.4
High Voltage Switching
While all of the clock circuitry and most of the switching is done using the low voltage
digitally supply, which lies between 2.5 V and 5 V, the input switches ride a rail that
can be anywhere from zero to sixty volts. To control the input switches, the logic
must be level shifted to the necessary levels. The level shifted logic lies between
Vi and VrailD . VrailD is generated off of the charge pump and provides a voltage
approximately 4.5 V above Vi . These voltage levels make it possible to use the low
voltage devices sitting in tubs as switches. The low voltage devices take up much less
area and also reduce the amount of leakage current. The reduced leakage current in
the input switches as a significant impact on the overall accuracy of the comparator
as a few nanoamps can cause up to 100 µV of shift in the 25 mV reference.
Because the level shifted logic signals use VrailD , current is ultimately being pulled
59
Figure 6-6: The half-monostable edge detectors used to generate the blast signals
off of the charge pump. To minimize the charge pump current used, the level shifter
uses a latch. While a large but brief blast of current is used during transitions, only
a very light quiescent current is needed to hold the logic levels.
The circuitry used to shift the logic signal is shown in Figure 6-5. When S2 turns
on, mns18 is turned on and mns19 is turned off. mns21 is hit by the voltage pulse
and pulls a large current through mns18 , pulling HVo down to the clamp voltage.
mns19 is turned off and mps9 is turned on, setting the other output node up to VrailD
and turning off mps8 . After the blast pulse has passed, mns18 still passes a 50 nA
trickle current and the logic levels are held. When S2 transitions low, the same thing
happens but to the opposite branches. The output of the system is taken from a
single side and passed through inverters to sharpen the transitions. mps10 and mns16
are medium voltage devices, as the clamp voltage lies between six and seven volts to
ensure that the inverter does not pass current outside of the transitions. The second
inverter only sees Vi and VrailD and can be implemented using 5 V devices.
6.4.1
Blast Signal Generators
Half-monostable edge detectors are used to generate the blast current signal pulses.
Both the rising edge and falling edge detectors, shown in Figure 6-6, are made up
of an RC high pass filter and inverters. When the rising edge detector is hit with a
pulse, the voltage across the resistor spikes up and then exponentially decays to zero
with a time constant of τ = RC. This spike is converted to a clean pulse with a width
60
of approximately 0.69τ by feeding into a series of inverters. 15V devices were used for
mps5 and mns13 as they must be able to withstand a Vgs greater than 2·PWRD. This
voltage difference is created when the falling edge pulls the gates of these transistors
to a PWRD below ground. The RC value used in the edge detectors generates a
pulse with a width of approximately 70 ns. The falling edge detector functions the
same way except the resistor is now connected to the positive rail. When the falling
edge hits, the output of the RC filter is pulled low and then exponentially rises to the
positive rail. The response of the edge detector circuitry is shown in Figure 6-7
Figure 6-7: The blast signal response of the edge detectors
6.4.2
Voltage Clamp
The clamp used in this circuit was borrowed from a previous Linear Technology design
and is shown in Figure 6-8. The clamp forces the voltage of VN to be no more than
61
Figure 6-8: The voltage clamp
62
four diode connected PMOS drops, 6-7 V, below the input voltage, VP . The current
pulled off of VP is limited by the size of R1 . Once the voltage across R1 is enough
to turn on M6 , M6 will supply the rest of the current required by VN . Within this
application the drain of M6 is tied to VP but is kept so that the diode drops across
M1 through M4 is relatively constant, even when a large amount of current needs to
be supplied to VN .
63
THIS PAGE INTENTIONALLY LEFT BLANK
64
Chapter 7
Supplies
This chapter details the generation and modelling of the different power supplies and
rails used within the auto-zero comparator design. The supplies include the digital
and analog low voltage supplies as well as the output of a charge pump. In addition
to these supplies, rails are generated between the input voltage and the charge pump.
7.1
Low Voltage Supplies
Figure 7-1: The implementation of the low voltage supplies
The low voltage analog and digital supplies provide the majority of the power
to the auto-zero comparator. The low voltage rails can have a value of somewhere
between 2.5 and 5 volts. The analog supply feeds all of the low voltage current
65
sources, mirrors, amplifiers, and references. The digital supply powers the clocking
and switching circuitry. Both of the supplies have their own return paths, RTNA
and RTND. The seperate analog and digital supplies help prevent the noisy digital
transitions from interacting and interfereing with the analog supply. These supplies
are implemented using voltage sources in series with small resistances and their return
paths consist of a small resistor to ground.
7.2
Charge Pump Output
Figure 7-2: The charge pump modeling circuitry
The auto-zero comparator was designed around using it to measure the voltage
across a sense resistor in an NMOS power path controller. This power path controller
has a charge pump used to drive the gates of the power FETs. The output of the
charge pump sits around twelve volts above the input to the auto-zero comparator.
However, charge pumps are inefficient and weak; drawing too much current from it
will diminish the output voltage and impact the performance of the power FETs.
The auto-zero comparator is also not the only device that will want to use the charge
66
pump output. Therefore, 10 µA was set as the maximum amount of quiescent charge
pump current the comparator can use.
Because the charge pump is already present on the chip, no actual charge pump
was implemented for this design. Instead, it was modeled as a twelve volt supply in
series with a resistor and a Schottky diode sitting on top of the input voltage. A
large capacitor was also placed between the output of the Schottky diode and the
input voltage to act as a reservoir. The charge resevoir allows the charge pump to
ride through large transients, such as the the blast current pulled during the high
voltage switching. The resistance models the finite output resistance of the charge
pump, assumed to be 100, and decreases the charge pump voltage if too much current
is pulled off of it.
7.3
VrailA and VrailD
Figure 7-3: The circuitry used to generate VrailA and VrailD
Another set of voltage rails, VrailA and VrailD , were generated to sit around 5 V
67
above the input voltage, Vi . Although voltages above Vi are needed for the auto-zero
comparator to operate, twelve volts above Vi is excessive for most of the circuitry and
forced the use of medium voltage devices. By creating a rail 5 V above Vi , low voltage
devices sitting in tubs can be used instead.
VrailA and VrailD are generated using the circuitry shown in Figure 7-3. The resistor
r1 is sized and used in conjunction with the depletion PMOS, mp1 , to generate 1 µA
current. mp1 feeds into the zener diode, zd1 , which is sitting on Vi , setting its cathodes
voltage to 5.5V above Vi . This voltage is sent to mn1 and mn2 , whose sources create
VrailA and VrailD . The voltages of VrailA and VrailD are now set to Vi + 5.5 − Vgs , or
approximately five volts. Low pass filters are placed between the cathode of zd1 and
the gates of mn1 and mn2 to isolate the VrailA from switching noise that will appear
on VrailD .
68
Chapter 8
Final Design Verification and
Conclusion
This chapter presents the tests and results used to verify the design.
8.1
Offset Cancelation
The primary design goal for this thesis is the improved accuracy of the comparator.
The maximum threshold error allowable is less than 1% of 25 mV, or less than 250 µV.
The threshold voltage of the comparator is defined as the average value of the rising
and falling thresholds.
A testing sequence, visualized in Figure 8-1, was used to verify the accuracy of the
comparator. Initially the inputs to the auto-zero comparator is held in the sampling
mode for a while. This allows the startup transients to settle out and the system
to reach its normal operating point. The auto-zero comparator then switches into
the comparison phase and a differential signal 5 mV than the expected threshold is
applied. The 5 mV step is then removed and the differential voltage applied is just the
expected threshold value. If the output of the comparator does not go low, then the
lower threshold is incremented down until the comparator trips. The same process
was initially used to find the upper threshold (except the input was stepped up and
the threshold incremented upwards) but because the hysteresis is a constant 50 µV,
69
the threshold voltage could be found by finding the lower threshold and shifting it up
25 µV.
The test thresholds were incremented at 25 µV steps. The step size was chosen
because it was small enough to give some inclination as to how the system deals
with offset but large enough that simulation time was not wasted on unnecessary
resolution.
Figure 8-1: simplified diagram showing testing
Figure 8-2: The threshold error versus temperature in the typical-typical environment
The threshold tests were run for input offsets ranging from −50 mV to 50 mV
at 5 mV increments, input common-mode voltages of 0 V and 60 V, and at -55◦ C,
70
27◦ C, and 125◦ C. In addition to these parameters, the tests were run over all of the
process corner models, typical-typical, fast-fast, slow-slow, fast-slow, and slow-fast.
The threshold error in microvolts versus input offset in millivolts for the typical-typical
process is shown in Figure 8-2. The entire collection of corner data is in Appendix
B. All of the corners met the threshold specification for offsets of up to ±50 mV
over temperature and input common-mode voltage. In fact, none of the tests had
threshold errors that exceeded ±200 µV. This is extremely good as the 6.6σ value of
the input pair is only 5.6 mV, much less than the ±50 mV tested.
8.2
dV/dt Rejection
In addition to being able to handle high common-mode input voltages, the comparator
must also be able to reject movements in the common-mode input voltage. The
voltage on the load capacitance begins to ramp up once it is connected to the source
and should not falsely trip the comparator. Fortunately, the Hot Swap controller
limits the rate of change in voltage to prevent the load from seeing sparks and glitches
caused when the board is connected. The change in voltage is limited to a rate of
1 V/µs and this will only be seen for a maximum of 60 µs. The design goal provided
was that the comparator must not falsely trip if it is sitting 1mV away from the
threshold.
To quantify how well the common-mode dV/dt is rejected, the comparators was
set a fixed value away from the threshold and the common-mode voltage was swept
up to 60 V over 60 µs several times. The distance from the threshold voltage was
increased until the comparator no longer tripped due to the change in input voltage.
The plot of the maximum dV/dt rejected versus the distance from the threshold can
be seen in Figure 8-3.
Although the comparator is fully differential and would be expected to have very
good common mode dV/dt rejection, it barely meets the required specification. The
changing input voltage affects the 25 mV reference. The capacitance between the
drain and bulk of the high voltage depletion NMOS, mnr3 in Figure 5-6, fluctuates
71
Figure 8-3: The maximum dV/dt rejected versus the distance from the threshold
with the input voltage, changing the amount of current being pulled through the
reference mirror. The NMOS was decreased in size to reduce the overall capacitance,
but it will still draw an extra 20 nA during high dV/dt periods. Other attempts
at compensating for the extra current were ineffective. Placing a matching dummy
NMOS in the other side of the mirror did not help, as its source being near Vin caused
too much mismatch between it and the original depletion NMOS. The issue in the
reference will always be present as long as a low voltage signal is being translated
up on top of Vin . The only way to avoid it would be to place the whole reference
generation circuit between Vin and VrailA . Moving the reference between these two
rails would double the total current being pulled off of the charge pump, making this
solution impractical.
72
8.3
Current Consumption
To measure the current from the analog rail, the circuit was allowed to reach its steady
state and then the total current from the analog voltage source was measured. Measurements were taken over temperatures ranging from -55◦ C to 125◦ C. The current
consumed from the low voltage analog supply increased linearly with temperature
and had a maximum total consumption of 19 µA.
Figure 8-4: The quiescent analog supply current over temperature
The charge pump current is the more critical design parameter. Because the
charge pump is weak, inefficient, and used by other circuit blocks, the auto-zero
comparator was designed to use less than 10 µA of charge pump current. The charge
pump current measurement was taken by allowing the circuit to reach its operating
point and then reading the current passing through the charge pump source and
subtracting any current being used by the charge pump model (e.g. the current
charging the capacitor). The charge pump current was measured over temperatures
73
ranging from −55◦ C to 125◦ C and with the input voltage at 0 V and 60 V. The
maximum current drawn from the charge pump was less than 6.5 µA and occurred at
125◦ C. The changes in the input voltage had a negligible impact on the charge pump
current, increasing it less than 100 nA with voltage. The blast current from the high
voltage level shifter also has an insignificant impact on current consumption as the
blast window is extremely short.
Figure 8-5: The quiescent charge pump current over temperature
8.4
Closed Loop Step Response
The performance of the closed loop step response is critical to the performance of the
auto-zero comparator. If the loop rings or does not settle quickly enough, the stored
offset value will be incorrect and hinder the offset cancellation. To test the response
of the closed loop to a step, an input offset was applied to the auto-zero comparator
and stored. The comparator then was placed into the comparison phase and the offset
74
was stepped. When the comparator switched back to the sampling phase, the loop
was hit with the stepped offset and the response was captured.
Figure 8-6: The closed loop step response over temperature
The auxiliary amplifier was designed to have approximately 90◦ of phase margin,
eliminating spikes and ringing. However, Figure 8-6 clearly shows some overshoot.
This overshoot is caused by the switching between phases. The closed loop not only
has to respond to the step, but also to a change in transfer function when connected.
The loop responds quickly, taking less than 3 µs to settle from an input offset step
of 5 mV. This 5 mV jump is much larger than any change in offset the comparator
is likely to see between two adjacent sampling periods so it provides a conservative
estimate as to how much time the loop needs to settle.
75
Figure 8-7: The time it takes to deviate 0.1% from the initial stored value
8.5
Capacitor Holding Time
The length of time charge can be held on the offset cancellation storage capacitors sets
an upper limit for the auto-zero comparators period length. Once the voltage deviates
too far from the initial value, it must be refreshed. To help quantify this behavior, a
voltage corresponding to 5 mV of input offset was held on the offset storage capacitors
and monitored until it fell more than 0.1% away from its initial value. It consistently
takes around 8.5 ms for the differential stored voltage to deviate more than 0.1%
from its initial value across the temperature range. This long storage time is not too
surprising due to the systems differential nature. The single ended 0.1% hold time
is on the order of 10’s of milliseconds and is inversely proportional to temperature.
The long hold time is due to a much larger voltage being stored. The relationship
to temperature, however, is eliminated when the system is measured differentially.
As the sample is stored, the capacitors only available discharge path is through the
76
Figure 8-8: The leakage path of the storage capacitors
gates of the PMOS transistors in the auxiliary amplifier and the transmission gate
switches which are closed, as shown in Figure 8-8. Because this design was done in
Linear Technologys 0.6 µm BiCMOS process, the devices are big enough that drain to
source leakage and gate tunneling are small. The 0.1% hold times are shown against
temperature in Figure 8-7.
8.6
Propagation Delay
Propagation delay is an important factor when designing a comparator. If the comparator takes too long to register and pass the signal, the overcurrent could damage
the system. The worst case propagation delay for the auto-zero comparator occurs
when the threshold is passed right when the sampling phased is engaged. In that
case, total time it takes for the signal to reach the output is the sampling time plus
the actual propagation time of the comparison phase.
77
Figure 8-9: The propagation delay versus overdrive
To measure the propagation time of the comparison phase, the inputs of the
comparator were set within 100 µV of the threshold voltage. The differential input
was then stepped up by a certain amount and the propagation time of the step
was recorded. The size of the step was increased from 25 µV to several millivolts,
giving the relationship between overdrive voltage and propagation delay. By 10 mV
of overdrive, the delay is less than a microsecond. This is advantageous as it allows
small, brief violations of the threshold, such as glitches, to not trip the comparator
while larger violations will trigger the comparator.
8.7
Noise
The noise of the system does not have a significant impact on its performance after
the auto-zeroing has taken place. The input referred noise is decreased by the large
input transistors, the relatively big gm of the input stage, and the filtering done by
78
the auto-zero circuitry. The in depth analysis of how the auto-zero circuitry impacts
noise can be found in Chapter 2. LTspice was used to produce an initial input
referred noise spectral density plot of the system. The auto-zero circuitry treated
like the RC network detailed in Section 2.2 with a sampling period of 1ms. The
initial noise spectral density has an RMS noise value of 17.9 µVrms and the autozeroed noise spectral density has an RMS noise value of 4.4 µVrms , a reduction of
over 75%. To get the peak-to-peak amplitude span of 99.9% of the noise waveform,
the RMS value is multiplied by a factor of 6.6. The resulting peak-to-peak voltage
is 29 µVpp , approximately 6% of the peak-to-peak spread allowed by the threshold
accuracy design requirement.
8.8
Conclusion and Future Work
Input common-mode range
Maximum error
dv/dt rejected 1mV from threshold
Offset sampling blind time
Charge pump quiescent current
Analog supply quiescent current
Propagation delay (no blind time)
Propagation delay (with blind time)
RMS noise
0.1% offset storage time
Design Goal
0-60V
<250 µV
1 V/µs
<10 µs
<10 µA
<25 µs
-
Final Design
0-60V
<200 µV
1 V/µs
<5 µs
6.5 µA
20 µA
<1.5 µs
<6.5 µs
4.4 µV
8.5ms
Table 8.1: The final design specifications
The comparator presented in this thesis meets all the primary and secondary
design goals using a closed loop configuration with an auxiliary amplifier. The verification tests run are detailed within this chapter. Table 8.1 presents the design goals
and the final characteristics of the design. In a typical-typical process, the comparator is accurate withing 0.5% of the 25 mV threshold, functions with inputs ranging
from ground to sixty volts, samples in less than 5 µs, and consumes less than 6.5 µA
of current from the charge pump.
Although the comparator met and exceeded all the design requirements, there
79
is still room for improvement. The dV/dt rejection only just met the specification.
Further exploration of other methods of translating the reference voltage or reducing
the gate-source capacitence of the high voltage device could result in large improvements. The input common mode range could also be improved. The comparator is
currently designed to handle iputs of up to 60 V. This limitation is set by the charge
pump output being twelve volts above the input and intrinsic device breakdown voltages. Using different charge pump configurations or devices may improve the upper
bound. Linear Technology currently has comparators that handle inputs up to 80 V.
By adapting some of the design choices and processes, this thesis’s comparator may
be able to have an input common-mode range of 0 to 80 V.
80
Appendix A
Tables of Transistors
Table A.1: The N-channel devices used in the design
Symbol
Voltage Rating
Typcial Vt
2.5 V
−1.00 V
5V
0.78 V
Comments
Depletion mode device
This device also appears
without the bulk node
5V
0.37 V
81
Native device
15 V
0.61 V
40 V
0.71 V
80 V
0.68 V
80 V
−1.1 V
82
Depletion mode device
Table A.2: The P-channel devices used in the design
Symbol
Voltage Rating
Typcial Vt
5V
−0.95 V
Comments
This device also appears
without the bulk node
This device also appears
without
−0.75 V
5V
the
optional
bulk node; used in the
current mirrors as the
cascode device
−1.48 V
5V
Native device
Used
as
the
cascode
device for the auxiliary
−0.40 V
5V
ampiflier’s
input
pair
and in the comparator’s
wraparound circuitry
−0.70 V
15 V
83
22 V
−0.87 V
80 V
1.70 V
84
Depletion mode device
Appendix B
Threshold Accuracy Plots
This appendix contains plots displaying the accuracy of the auto-zero comparator
as simulated across process corners, input common mode voltage, and temperature
in LTspice. Each data set it labelled with its corresponding temperature and input
voltage. For instance, a data set labeled ”27◦ C, 0V” was simulated at 27◦ C with an
input common mode voltage of zero volts.
85
Figure B-1: The threshold accuracy measured in a typical-typical process
Figure B-2: The threshold accuracy measured in a fast-fast process
86
Figure B-3: The threshold accuracy measured in a slow-slow process
Figure B-4: The threshold accuracy measured in a slow-fast process
87
Figure B-5: The threshold accuracy measured in a fast-slow process
88
References
[1] Linear Technology Corporation. Parametric Search for Hot Swap Controllers.
http://www.linear.com/parametric/hot_swap_controllers, 2015. Accessed
02-24-2015.
[2] Texas Instruments Inc. TPS2490/1 Positive High-Voltage Power-Limiting
Hotswap Controller (Rev. D). http://www.ti.com/lit/ds/symlink/tps2490.
pdf, 2012. Accessed 04-30-2015.
[3] Maxim Integrated Products Inc. MAX5934 Datasheet. http://datasheets.
maximintegrated.com/en/ds/MAX5934-MAX5934A.pdf, 2001. Accessed 05-012015.
[4] T. Yoshida, Y. Masui, T. Mashimo, M. Sasaki, and A. Iwata. A 1V Supply
√
50nV/ Hz Noise PSD CMOS Amplifier Using Noise Reduction Technique of
Autozeroing and Chopper Stabilization. Symposium on VLSI Circuits Digest of
Technical Papers, 2005.
[5] R. Wu, J. H. Huijsing, and K. A.A. Makinwa. Precision Instrumentation Amplifiers and Read-Out Integrated Circuits. Analog Circuits and Signal Processing.
Springer, Verlag, New York, first edition, 2013.
[6] I. Mehr and D. Dalton. A 500-MSample/s, 6-But Nyquist-Rate ADC for
Disk-Drive Read-Channel Applications. IEEE Journal of Solid-State Circuits,
34(7):912–920, July 1999.
[7] P. Wilson and H. A. Mantooth. Model-Based Engineering for Complex Electronic
Systems. Newnes, Waltham, Massachusetts, first edition, 2013.
[8] C. C. Enz and G C. Temes. Circuit Techniques for Reducing the Effects of OpAmp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization. Proceedings of the IEEE, 84(11):1584–1614, November 1996.
[9] P. R. Gray and R. G. Meyer. Analysis and Design of Analog Integrated Circuits.
John Wiley & Sons, Inc., New York, New York, second edition, 1990.
[10] R. I. Demrow. Settling Time of Operational Amplifiers. Analog Dialogue: A
Journal for the Exchange of Analog Technology, 4(1):1–15, June 1970.
89
[11] M. J.M. Pelgrom, A. C.J. Duinmaijer, and A. P.G. Welbers. Matching Properties
of MOS Transistors. IEEE Journal of Solid-State Circuits, 24(5):1433–1440,
October 1989.
[12] Bob Jurgilewicz. EKV discussion. Personal communication, June 17 2014.
[13] P.E. Allen. Comparators. http://www.aicdesign.org/SCNOTES/2006notes/
Chap08%288_7_06%29.pdf, 2006. Accessed 09-29-2014.
[14] T. C. Carusone, D. A. Johns, and K. W. Martin. Analog Integrated Circuit
Design. John Wiley & Sons, Inc., Hoboken, NJ, second edition, 2012.
[15] P.E. Allen. Georgia Institute of Technology, ECE4430 Lecture 390 - Bandgap
Voltage Reference.
http://www.ece.gatech.edu/academic/courses/
ece4430/Filmed_lectures/BandgapSources/L390-BandgapRefs.pdf, 2001.
Accessed 12-04-2014.
90