Flash Memory with Nanoparticle Floating Gates
Sanjay Banerjee
Director, Microelectronics Research Center
Cockrell Chair Professor of Electrical & Computer Engineering
University of Texas at Austin
• Why Nanoparticles in Flash Memory
• Self-assembly schemes
• Device Performance
Acknowledgements: DARPA MARCO, NSF NIRT, Micron
The Scale of Things – Nanometers and More
Things Natural
Things Manmade
10-2 m
Ant
~ 5 mm
Dust mite
Red blood cells
with white cell
~ 2-5 μm
The Challenge
1,000,000 nanometers =
1 millimeter (mm)
MicroElectroMechanical
(MEMS) devices
10 -100 μm wide
10-4 m
0.1 mm
100 μm
-5
0.01 mm
10 μm
O
10 m
Pollen grain
Red blood cells
Infrared
Fly ash
~ 10-20 μm
Microworld
200 μm
Human hair
~ 60-120 μm wide
Head of a pin
1-2 mm
Microwave
10-3 m
1 cm
10 mm
1,000 nanometers =
1 micrometer (μm)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
S
S
S
S
S
S
S
S
Zone plate x-ray “lens”
Outer ring spacing ~35 nm
Visible
10-6 m
P
O
~10 nm diameter
ATP synthase
0.1 μm
Ultraviolet
Nanoworld
10-7 m
10-8 m
Self-assembled,
Nature-inspired structure
Many 10s of nm
Nanotube electrode
1 nanometer (nm)
Soft x-ray
Atoms of silicon
spacing ~tenths of nm
100 nm
Smaller is
different
0.01 μm
10 nm
10-9 m
DNA
~2-1/2 nm diameter
Fabricate and combine
nanoscale building
blocks to make useful
devices, e.g., a
photosynthetic reaction
center with integral
semiconductor storage.
10-10 m
More is
different
0.1 nm
Quantum corral of 48 iron atoms on copper surface
positioned one at a time with an STM tip
Corral diameter 14 nm
Carbon nanotube
~1.3 nm diameter
Carbon
buckyball
~1 nm
diameter
Office of Basic Energy Sciences
Office of Science, U.S. DOE
Version 10-07-03, pmd
Moore’s Law
No exponential is forever!
But can we delay “forever”?
source
drain
Flash memory applications
Markets
Consumer Electronics
Networking
Wireless
Industrial Control
Automotive
Control Gate
Floating gate
Tunnel dielectric
NAND Flash Market Segmentation
Digital Settop Box
0%
Others
5%
*Others include GPS, games, emerging applications, etc
MP3 players
(Flash based)
22%
2005 NAND Demand
TAM Percentage
$468 M
iSupply: Q3. 2005
$2124 M
$5230 M
USB Flash Drive
17%
$1667 M
Rem ovable Solid
State Flash Cards
53%
$244 M
$70 M
Mobile Handset
(Em bedded)
2%
Digital Still
Cam era
(Em bedded)
1%
NOR Flash had TAM of 7B$, mostly in wireless cell phones.
Very high growth rates!!!
Flash Technology Scaling History
1986 / 1.5μm
1988 / 1.0μm
1991 / 0.8μm
1993 / 0.6μm
1996 / 0.4μm
1/~1
000
1998 / 0.25μm
2000 / 0.18μm
2002 / 0.13μm
10X
2004 / 90nm
2006 / 65nm
10X
10X
Volume Production Year / Technology Generation
Source: Intel
• Flash Invented in mid 1980’s
• NOR flash evolved from EPROM
• NAND started as poly-poly erase cell later evolving to present structure
• ~20 years & 10 Generations of ETOX® (Intel NOR) High Volume
Production
• 8+ years & 5 Generations of MLC: 2bit / cell
NVM- Long Term Requirements (ITRS 2006)
Nanoparticle Gate Flash Memory
Gate
Gate
Source
Source
Drain
Drain
Conventional Flash Memory
Nano-floating Gate Memory
A defect totally discharges the floating gate
A defect discharges only one dot
– Thick tunnel oxide
– High voltage/ power
– Low reliability/ speed
High-k tunnel oxide
„ Speed/ power/ density better
„ Reliability improved
„ New phenomena- self-assembly,
Coulomb blockade, multi-level cells
„
SiGe Nanocrystals on High-K Dielectrics
HfO2
SiO2
AFM scans (1 micron x 1micron) showing SiGe dots grown at
~ 500ºC for 90 s with 0.75 gas ratio of GeH4 to Si2H6.
Kim., Banerjee, Growth of germanium quantum dots on different dielectric substrates by chemical-vapor deposition,
J VAC SCI TECHNOL B 19 (4): 2001
Band diagram of HfO2 and SiO2 dielectric at low program voltage
Nanocrystal Dots
Si Ec
SiGe Ec
Channel
Channel
Dot
gate
Dot
gate
Interface
oxide
Tunneling oxide
(SiO2)
(HfO2)
2
10
SiO2
HfO2
1
10
Jg [A/cm2]
Tunneling oxide
(HfO2)
0
10
F-N tunneling
(due to small φb)
E.O.T 4nm
-1
Direct
tunneling
10
-2
10
Direct tunneling
-3
10
-4
10
0
2
4
6
VG [V]
8
10
(SiO2)
Program & Erase Transient Characteristics
0.4
Program
HfO2 2.5V
0.6
SiO2 4V
0.5
0.2
0.0
SiO2 4V
With SiGe dots
0.4
0.3
0.2
Erase
-0.2
HfO2 tunneling oxide
SiO2 tunneling oxide
Without dots
0.7
ΔVth(V)
Threshold Voltage shift (V)
HfO2 tunneling oixde =4.8nm
SiO2 tunneling oxide = 3.6nm
Without dots
0.1
HfO2 2.5V
0.0
-0.4
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
3
4
5
6
Program/Erase Time (s)
VCG(V)
Kim DW, Kim T, Banerjee SK, ELECTRON DEV 50 (9): 1823-1829 SEP 2003
The Bio-nanometer Perspective
Atom
DNA
Virus
Protein
Cells
Fish
egg
Hair
Bacterium
Human
eye
Water
10-1
1
nm
10
102
103
μm
Nanomaterials:
Nanotubes
Dendrimers
Nanopores
Quantum dots
Nanoshells
Nanoparticles
Transistor
Gate/
dielectrics/substrate
Interconnect
104
105
106
107
108
mm
Integrated circuit
Microprocessor
Slide by C. Li
Yamashita, IEDM 2006, p. 447 (Ferritin)
Ishii, Nature Vol. 423, 2003 (Chaperonin)
Protein assembly of Metal (Co, Au,..) and Semiconductor (PbSe, CdSe, Ge ..) NCs
Schematic structure of
Chaperonin 60 (GroEL)
STEM images of PbSe nanocrystals on SiO2
50 nm
Without chaperonin template
50 nm
With chaperonin template
Various semiconductor and metal nanocrystals self-assembled, including Co
Density~ 10 12 cm-2
ΔVFB comparison of
protein-mediated PbSe
NC MOS capacitor and
control samples
TaN
PbSe NCs
SiO2
TaN Gate
NCs
Control Oxide
10 nm
Tunnel Oxide
Si
Si Substrate
A
×
B
C
×
D
×
ΔVFB(V)
PbSe NCs
Protein Template
(Annealed)
0.8 P ro g ram /E rase tim e= 1s
A
0.6
B
0.4
0.2
C ,D
0.0
×
4
5
6
7
8
9
10
P ro g ram V o ltag e (V )
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
PbSe -10V 200ms
PbSe 10V 200ms
Co -8V 200ms
Co 8V 200ms
VFB (V)
VFB(V)
Endurance and Retention Characteristics
0
1
2
3
4
10 10 10 10 10 10
Number of Cycles
Devices survived 105 cycles of
program/erase operation; no
sign of window closure
5
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
10
PbSe -10V 200ms
PbSe 10V 200ms
0
10
1
10
2
Co -8V 200ms
Co 8V 200ms
10
3
10
Retention Tim e (s)
Devices have good retention.
4
Heat Shock Proteins (Trent, NASA)
Coulomb Blockade in SiGe dot on SiO2 and HfO2
-5
2.0x10
SiGe on SiO2 @ 520 ºC
Drain Current (A)
-5
1.5x10
-5
1.0x10
n=0
n=1
-6
5.0x10
0.0
SiO2 tunneling oxide = 3.6nm
0
1
2
3
4
5
Gate Voltage (V)
6
7
8
9
Vertical Flash Memory
Sidewall
channels
Nanocrystal
floating gate
Drain contact
Gate
Source
Gate poly
Source contact (outside view)
Device
mesa
n+ Source/Drain
Schematic side view
Scanning Electron Micrograph
Vertical Flash Retention at 300K
± 9 V, 100 ms tunneling P/E
10 nm
E1237 PCL_070104002_VFR5W4_04_3DFlash_Nanocrystals.dm3
MAG: 295kX
Nanoparticle Self-Assembly Using PS-b-PMMA Copolymer
Process Flow
Employing a sandwich of organic/ inorganic/ organic layers (Polyimide/ SiO2/ PS-b-PMMA) to engineer the aspect ratio of the patterns
Material Characterization
100 nm
nm
100
(b)
Normalized Count
(a)
100 nm
(c)
(d)
100 nm
10nm
glue
6
Nickel Nanocrystals
Si Substrate
SEM micrographs of (a) Copolymer template, (b) transferred polymer
Histogram of the copolymer pore size distribution
patterns into the underlying SiO2 layer, (c) ultimate array of Ni nanoparticles. shown in Fig. (a)
(d) Cross-sectional image of the embedded nanoparticles within SiO2.
Characteristics of MOSCAP Memory Devices
1.2
2.0
Control Sample - w/ o Ni dots
10V
8V
6V
±10V, 100 msec
±8V , 100 msec
1.0
1.6
ΔVFB (V)
0.8
0.6
1.2
0.8
0.4
0.4
0.2
0
0
-4
-3
-2
-1
0
10-6
1
10-4
10-3
10-2
10-1
100
Write/ Erase time (s)
Gate Voltage (V)
High frequency C-V
Characteristics @ 1MHz
10-5
Memory window for
different program voltages
Transient characteristics of
the memory device
Molecular Memories, Misra,
IEDM p.537 2003; IEDM p. 707 2004.
Variability, DOS ?
SONOS trap densities ~1019 cm-3 eV-1
For ~3 nm layer, ~3X1012 cm-2 traps
spatially and energetically distributed
Non-MOS Memory Contenders (adapted from Fazio, Intel)
MRAM
FeRAM
Phase Change
Cell Size λ2
CMOS
Integration
Large ~40 Æ 20
Large ~25
Small ~6.5
<200C Post Magnetic
Tight MJT control
Fe reduces in hydrogen
Etching difficult for Fe
Compatible with backend
CMOS metal processing
Read
Non-Destructive, Fast, Low
Power
Power constrained, Scales
poorly; half select issue
Theoretically Infinite
Destructive: Endurance
limited read
Low power capacitive
Theoretically good speed
1e-8 Æ 1e12; claims made,
but limited data
Non-Destructive, Moderate
speed, Scales poorly
Power constrained, large
drivers, Improves with scaling
~1e12; claims made, but
limited data; Erratic failures
Write current increases
with scaling, materials
engineering required at
each scaling node;
superparamagnetic limit?
Embedded
Working Memory
Low Density
3D cell required sub 90nm.
Material engineering required
at each scaling node
No material changes, No
physical limits known down to
~5nm
Embedded
Low Power
Low Density
Stand Alone or Embedded
High Density
Low Cost
Write
Cycling
Endurance
Scalability
Application
Color Code
Poor
OK
Good
Data Storage Region
Chalcogenide
Poly Crystalline
Amorphous
Heater
Phase Change
Material
Resistive
Electrode
1R
Nanocrystal Dots
Channel
Dot
gate
Tunneling oxide
• End-of-roadmap (2020, L=6 nm) NAND F= 14 nm, Tox= 6
nm, Cell area ~ 1000 nm2; (3X for NOR)
• NC spacing ~ tunnel oxide thickness ~ 4 nm
• Spacing & NC size/DOS affects charge capture crosssection & Read
• Optimal spacing depends on dielectric & NC band diagram,
retention (108 s), Erase/Write times (10-6 s)Æ Ebarr= 1eV
• For NC densities of ~ 1012 cm-2, room for ~10 NC
• Variability is a challenge for NC & trap-based cells
• Self-assembly and non-planar structures?
There is plenty of room at the bottom!
Feynman
• Will these devices make it? The answer is a very definite…..
Maybe!!