!"#$%&'%$ !)*+,- ./%01 2,+1,3**3'#) !)$3##%43$%+0 5)## 6)780+#+1M.N. Kozicki1,2,*, N.E. Gilbert3, C. Gopalan1, M. Balakrishnan1, C. Ratnakumar1, and M. Mitkova1,2
1
Center for Solid State Electronics Research, Box 876206, Arizona State University, Tempe, AZ 85287, USA
2
Axon Technologies Corp., 7702 E Doubletree Ranch Road, Suite 300, Scottsdale, AZ 85258, USA
3
Desert Microtechnology Associates, Inc., 16611 N 91st Street, Suite 103, Scottsdale, AZ 85260, USA
*Corresponding author: Phone (480) 965-2572; fax (480) 965-8118; e-mail michael.kozicki@asu.edu
I. PURPOSE OF THE WORK
There is a mounting need for multiple function discrete and
embedded memories. The ideal multi-function memory would
combine all the desirable qualities of current memory
incumbents, including fast programming, low voltage/current
operation, non-volatility, high endurance, excellent scalability,
and compatibility with CMOS logic processes. In addition, to
achieve high storage density and low cost, multi-bit operation
is a growing requirement. Several emerging memories claim
the potential to become the “universal memory” for discrete
and embedded applications but among the drawbacks of these
technologies is significant process and design complexity and
relatively high power operation. This paper describes the
design and operation of a multi-level cell (MLC) technology
demonstrator based on Programmable Metallization Cell
(PMC) memory elements. These elements posses the desirable
characteristics listed above but MLC operation of CMOS
integrated PMC has not been reported until now.
II. ADVANCES IN THE ART
PMC is a novel memory cell consisting of a thin solid
electrolyte film of Cu- or Ag-doped Ge-S or Ge-Se between
two electrodes; Cu or Ag is used as an oxidizable electrode on
the electrolyte and the lower electrode can be the W via plug
in a standard CMOS process. PMC is embeddable as only one
additional mask over logic is required to determine which vias
are memory elements and which are through connections (see
Fig. 1). Fig. 2 and Fig. 3 show typical low power currentvoltage and resistance-voltage characteristics respectively for
a 240 nm diameter Ag-Ge-S electrolyte device. The device
transitions from its high resistance state to the on state at 450
mV and the erase initiation occurs at -250 mV. The on state
resistance is defined by the programming current limit by Ron
= Vte/Iprog, where Vte is the threshold voltage for the
electrodeposition process (approx. 220 mV for this material
combination). Note that it is this simple relationship between
Ron and Iprog that facilitates multi-level storage in PMC devices.
Fig. 4 shows the room temperature retention characteristics of
a device programmed at 10 !A and read at 200 mV,
illustrating the high level of non-volatility of both on and off
states with time. In order to design a technology demonstrator
chip, we developed an accurate Spice macro model for PMC
devices. Figs. 5 and 6 show outputs from our model and
compare them with measured signals from actual devices.
Lab_in and Sim_in are measured and simulated input signals
and Lab_out and Sim_out are the corresponding outputs. As
may be seen in both the case of the write operation (Fig. 5)
and the erase operation (Fig. 6), the model fits the measured
data with a high degree of accuracy. Also evident from this is
the speed of both the write and erase operations; the device
switches within the 20 ns rise time of the input signals. The
above data shows that PMC represents a unique low power,
fast, non-volatile, embeddable element that has inherent MLC
characteristics and as such clearly advances the art in memory
technology, however, if the technology is to be widely adopted,
demonstration of performance in a CMOS circuit is necessary.
III. NEW RESULTS AND SIGNIFICANCE
We developed a technology demonstrator chip on a
standard (foundry) 180 nm CMOS process with PMC cells
integrated between metal 2 and metal 3 to show that MLC
operation was possible with simple write, read, and erase
circuitry. The floorplan of the MLC memory array module is
given in Fig. 7. The array size is 1024 memory cells, each
containing one PMC device and one MOS transistor, which is
sufficient to demonstrate storage cell/circuit operation. The
basic design, illustrated in Fig. 8, was crafted to exploit the
property described by the equation for Ron above, i.e., to use
discrete currents to program distinct, widely spaced resistance
states in the device. A common current source is used to set
the base current level I1 and the other current levels, I2, I3, are
simply created by two more transistors sized to twice and
three times the base transistor respectively. These are selected
by the control logic to create the resistance values in the cell
for the 01 (25 k!), 10 (12.5 k!), and 11 (8.3 k!) states
respectively (Roff is 00). The general schematic of the read
circuitry is given in Fig. 9. The sense amplifier detects the
resistance of the selected device by forcing a half-threshold
bias, generated by a unique high-accuracy circuit involving a
PMC element, across the bit and comparing the generated
current to half the programming current. This is easily
achieved with transistors one half the size of the write
transistors. This scheme avoids read disturbs in the low
voltage cells and can theoretically be expanded to more levels
per cell. The voltage signals are decoded to output a 2 bit word.
A demonstration of circuit operation is shown in Fig. 10. For
each write cycle, the write current is increased by one
increment by the input write command. Each subsequent read
shows an increment in the output data word from 00 to 11.
These results are significant as they demonstrate that we can
integrate low voltage non-volatile PMC elements with CMOS
to produce a MLC array using simple peripheral circuitry
which leads to low overhead and the possibility of both
discrete and embedded multiple function applications.
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Metal 3
Ag or Cu
0.6
Solid electrolyte
Metal 2
Oxide
W via
W via
Metal 2
Metal 2
Fig. 1. Schematic of PMC device integration between two
levels of metal in a standard CMOS process.
0.4
Voltage (V)
W via
Lab_IN
Lab_OUT
Sim_in
0.2
Sim_out
0
-0.2
-0.4
0
100
200
300
400
500
Time (ns)
Fig. 5. Simulated (Sim_in, out) and measured (Lab_in,
out) device write operation showing model fit.
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0.2
Fig. 2. Current-voltage plot of a 240 nm diameter device
with a 60 nm Ag-Ge-S solid electrolyte (Iprog = 10 !A).
Voltage (V)
0
-0.2
Lab_in
-0.4
Lab_out
Sim_out
-0.6
Sim_in
-0.8
0
100
200
300
400
500
Time (ns)
Fig. 6. Simulated (Sim_in, out) and measured (Lab_in,
out) device erase operation showing model fit.
Fig. 3. Resistance-voltage plot of the device of Fig. 2
showing Roff > 1010 " and Ron = 22 k" for Iprog = 10 !A.
Test
Array
Row Decode
Bias
Column Decode
Write
Erase
Fig. 4. Roff (upper) and Ron (lower) measured at 200 mV as
a function of time at room temperature for Iprog = 10 !A.
Read
Write
Erase
Fig. 7. Floorplan of MLC memory module in technology
demonstrator showing main functional sub-blocks.
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Fig. 8. Schematic of the design architecture for multi-level
storage in the PMC testbed. Logic switched transistors of
different size produce the write current levels I1, I2, I3.
Fig. 9. Read circuit for MLC illustrating use of simple
current comparators with transistors of half the write size.
Control voltage, Vcon, used to show resistance of programmed cell, Rcell = Roff/(Roff.Vcon+1)
Ron=8.3 k!#11
Ron=12.5 k!#10
Ron=25 k!#01
Roff>1010 ! # 00
Valid Data
Valid Data
Valid Data
MSB
LSB
Read
Write level 3
Write level 2
Write level 1
Erase
Fig. 10. Demonstration of multi-level operation in which the four levels for two bit per cell operation are defined by
the off state (>1010 ") and the three on state resistances defined by the selectable current sources.