ITC Special Section
Carnegie Mellon University
LSI Logic
Editor’s note:
Defect density and size distributions are difficult to characterize, especially if you have little or no access to test vehicles specifically designed for the purpose. The authors propose a new methodology for extracting that information directly from production test data on actual products.
—Ken Butler, Texas Instruments
D EFECTS FREQUENTLY OCCUR during IC manufacture. Modeling the resulting yield loss is an important part of any design-for-manufacturability strategy. Of the many mechanisms that cause yield loss, some have sufficiently accurate models and are well understood, whereas others are unpredictable and difficult to characterize. Current yield-related research focuses mainly on systematic defects. In contrast, this article addresses random spot defects, which affect all processes and currently require a heavy silicon investment to characterize. We propose a new approach for characterizing random spot defects in a process. This approach enables accurate measurement of parameters for the critical-area yield model—the workhorse of modern yield-learning strategies.
IC manufacturers often neglect the need to tune the yield model—that is, to continuously update yield model parameters—because of the silicon area required to characterize a process. But the inherently stochastic nature of yield makes frequent process characterization necessary for accurate yield models. We present a system that overcomes the obstacle of silicon area overhead by using available wafer sort test results to measure critical-area yield model parameters. We use only wafer sort test results, so no additional silicon area is required. Our strategy uses the most realistic characterization vehicle for the product IC—the product itself—rather than memory or specialized test structures that waste silicon area and often do not represent the product’s design style.
Defect density and size distributions
(DDSDs) are important parameters for characterizing spot defects in a process. A DDSD tells us what the defect density is for a given defect radius— that is, the number of defects per unit area. The distribution gives this information for all defect radii. Typically, though, as defect radius increases, defect density quickly decreases. Thus, we can generally curtail the distribution and measure only defect density for a range of defect radii, because larger defects have a density approaching zero. This inherent feature becomes useful in attempting to discretize the DDSD.
We can subdivide the distributions characterizing a process beyond defect size. Each metal layer of the process can potentially have a different DDSD. Ideally, we’d like to measure each layer’s DDSD rather than attempt to characterize all layers simultaneously with a single distribution. These distributions are parameters for the critical-area yield model.
1-3
IC manufacturers measure DDSDs primarily with specialized test structures on a wafer. Test structures contain geometries specifically designed to observe defects.
When a defect occurs in a particular region of a test structure, that structure observes the defect, making it easy for the process engineer to identify what the defect mechanism is, where it occurred, and to learn about the defect’s size. The price we pay for this convenience is that test structures consume silicon area on the wafer.
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Thus, test structures impose a trade-off between area cost and defect observability.
Consider the three wafers in Figure 1. In Figure 1a, the entire wafer is dedicated to test structures. This configuration allows excellent defect observability, but the obvious drawback is that no product can be manufactured from it—product volume is zero. Manufacturers typically use a full wafer of test structures only during the earliest yield-learning phase, when the yield improvement realized from these structures significantly outweighs manufacturing cost.
In Figure 1b, products have replaced many of the test structures, raising volume to a medium level. However, observability has decreased because now there is a significant amount of area where defects can occur with no direct ability to characterize them. The wafer in
Figure 1b also contains test structures in the scribe lines.
This configuration is a compromise between defect observability and volume. Manufacturers typically use it during yield ramp, when volume is necessary, but the ability to characterize defects—particularly systematic defects—is still required.
Finally, the wafer configuration shown in Figure 1c uses the entire silicon area to manufacture products.
The scribe lines still contain test structures because they don’t affect product volume. As in the Figure 1b configuration, this configuration provides limited area to observe defects, but it is even more extreme because it relegates the test structures to the scribe lines. This configuration is used most during the volume phase of yield ramp, when characterization of random spot defects is most important for predicting yield.
The observability-versus-area trade-off has led to research that seeks the best of both worlds: high observability and low (or no) area overhead. In particular, researchers have used SRAMs to extract DDSDs.
4 This technique requires no additional overhead, because the characterization vehicle (the SRAM) is a useful product itself. SRAMs, however, have undesirable characterization characteristics, such as confinement to a few metal layers, which limits the scope of observable defects. SRAMs’ extremely regular structure means that if the replicated cell has a narrow scope of geometric features for defect observation, this limitation will extend over the entire chip. These limitations are only noteworthy when the memories are extracting DDSDs for yield-loss prediction for random-logic circuits. A preferable defect characterization vehicle in such cases is a random-logic product.
Other researchers have suggested using a random-
(a)
(b)
(c)
Figure 1. Wafers with different test structure configurations and varying levels of defect observability (gray areas and scribe lines represent test structures): all test structures and no products (a), some test structures replaced by products (b), and entire area used for products, with test structures in scribe lines only (c).
logic product to estimate the defect pareto in a process using only test results.
5 That work, in conjunction with the SRAM work, inspired the initial idea that we could extract a DDSD for each process layer using a randomlogic product IC as a virtual test structure.
6 The first publication describing an investigation of this idea appeared in March 2006.
7 Here, we elaborate on that publication and present new findings from an experiment conducted on test data from silicon wafers provided by LSI Logic.
Our system accurately characterizes spot defects that contribute to yield loss by measuring defect density in each metal IC layer, without the silicon overhead required by current techniques. The various geometries and line spacing in a typical layout lead to defects of different sizes with varying effects on the IC (some small
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μ
E
1
μ E
4
μ E
6 b technique that relates the analyzed IC’s test responses to defect characteristics that could cause such test responses. We will describe two mappings: one between defect probabilities and fault probabilities, and one between faults and test responses.
μ
E
2 b c
μ
E
3 c
Figure 2. Sample layout with six microevents: four in metal layer 1 (a), and two in metal layer 2 (b). Microevents
μ
E
1 to
μ
E
3 have radius r
1
(solid boxes) and
μ
E
4
(dashed boxes), where r
1 to
μ
E
6 have radius r
< r
2
. Spot defects are circles.
2
A spot of extra conducting material deposited in a metal layer can introduce an extra, unwanted bridge connection between nonequipotential metal regions in the layer. In most cases, a bridge will affect the circuit’s electrical behavior. An instance of a bridge that connects two or more nonequipotential metal islands is called a microevent.
4 Each microevent involves a set of circuit nodes, S = { n
1
, n
2
,
…
, n m
}, that are bridged by the spot defect of a specific radius. We can calculate the probability of a single, independent microevent using the critical-area yield model.
7 Equation 1 shows the probability that microevent i will occur, where C i is the microevent’s critical area, and D j
( r i
) is the defect density for defects of radius r i
(the same radius as microevent i ) in layer j , the layer in which microevent i occurs.
defects may have a negligible impact). Therefore, in addition to defect density, we must measure the distribution of defect sizes.
The strategy for achieving this goal is straightforward.
6-8 By nature, each spot defect affects only a small subset of nodes in close proximity to one another. Each spot defect leads to a unique, defective circuit response.
Likewise, given a circuit response, there are some potential spot defects that cause that response. Using results from structural testing, we can estimate the probability of a particular circuit response and consequently the probabilities of defect occurrence. By grouping responses according to specific characteristics, such as the size of a defect necessary to cause that circuit response, we can determine the occurrence probabilities of defects of that size.
Using a modeling strategy to predict faulty circuit responses as a function of defect characteristics in the process, we can mathematically derive defect characteristics that minimize the difference between the modeled test response probabilities and the estimated test response probabilities. Thus, the calculated defect characteristics must represent the actual defect characteristics in the process. Of course, for this to be true, certain conditions must be met. We propose a defect characterization methodology based on this concept. That is, we develop and apply a modeling strategy that predicts probabilities of test responses depending on a DDSD, and then we find the DDSD that leads to agreement between circuit test responses measured by a tester and test responses predicted by the model.
To accomplish this, we have developed a modeling p i
= e
−
( )
Here, we define microevent
μ
E i as a bridge, thus limiting our scope to spot defects causing bridges. We do this for two reasons: First, it is important that the physics of the investigated yield loss mechanism be well understood, which is indeed the case for bridges. Second, spots of extra conducting material are still a major reason for IC malfunctions in many processes.
An IC’s vulnerability to random spot defects greatly depends on the layout. The critical-area concept was developed to provide a metric of design sensitivity to defects.
1,9 Critical area is the layout region where, if a spot defect of radius r occurs, a circuit can fail. Figure
2 shows a small portion of a sample layout with signal lines in metal 1 and metal 2. The figure illustrates six microevents: four in metal 1 and two in metal 2. Four sample spot defects demonstrate how a microevent can occur. Each microevent has an associated critical area for a specific defect radius. For example, microevents
μ
E
1 to
μ
E
3 have critical area for a defect of radius r
1
, represented by the solid boxes associated with each microevent label. Likewise, microevents
μ
E
4 to
μ
E
6 have critical area for radius r
2
, represented by the dashed boxes. This example shows that even within a single metal layer, microevents involving the same circuit node set S can occur in several discrete regions. In this
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case, S = { b , c }. Each discrete region of critical area represents a separate microevent. In addition, microevents involving the same set of circuit nodes can exist in different metal layers.
Critical-area measurement occurs in steps. First, we measure critical area for all potential microevents in a layout for a given radius, r start
. In each subsequent step, the defect radius is incremented by a small amount and the first step repeated for the new radius. This process repeats, continuing over a specified range of defect radii until reaching r end
.
We can now define a macroevent as the set of all microevents that exist for the same set of circuit nodes
S . As mentioned, many microevents involving S can exist in different layers for different defect radii. So, a collection of independent microevents describes each macroevent. Figure 2 shows a single macroevent, occurring between lines b and c, which consists of microevents 1 through 6. Because a macroevent is a set of independent microevents, the probability of a macroevent involving S is one minus the product of the probabilities of each microevent involving S not occurring. Thus, in this example, the probability of the macroevent involving b and c occurring is one minus the product of the probabilities of each of the six microevents not occurring.
Critical-area extraction for a range of defect radii provides a list of microevents and their associated critical areas. With those measurements, we can calculate microevent probabilities, and thus macroevent probabilities, as a function of defect densities. Because a macroevent represents a multiline bridge, we have in fact extracted a list of potential bridge defects along with their occurrence probability. This results in the first mapping between defects and faults.
The final modeling stage necessary for mapping defect characteristics to test responses is a mapping between the macroevent list and the test responses. This mapping is embodied by the T matrix, which we calculate by simulating the entire test set against each macroevent. Because simulation time for a large number of macroevents (even a small circuit can have hundreds of thousands) can be enormous, we model them as logiclevel faults, making efficient simulation possible. To maintain accuracy when simulating at the logic level, we first derive an accurate gate-level model of the circuit.
Typical standard-cell representations obscure the cell’s internal workings, causing the omission of important signal lines from the logic-level netlist. This netlist includes only standard-cell ports, even if the standard cell contains several CMOS logic gates. Therefore, we map a standard-cell layout to a logic-level description that captures the structure of static CMOS gates in the cell, using the gate primitives NAND, NOR, and NOT.
This change lets us consider gate outputs routed in metal 1 in a standard cell during microevent extraction and tie them to logic signals in the netlist.
An AND-gate standard cell illustrates this issue.
Typically, an AND gate is implemented in CMOS by a
NAND gate followed by an inverter, with the connection between the two routed in metal 1. Microevents involving the internal metal 1 routing might occur, but without the layout-to-logic mapping used here, we have no basis for forming a logic-level fault model that includes this metal line. With our mapping, we can efficiently handle critical area that involves all metal lines in a standard cell (which can account for a significant portion of the chip’s total critical area).
However, some standard cells might still contain metal structures that are not mapped to the logic level.
These polygonal structures are metal lines that don’t correspond to a CMOS logic gate’s output (these structures do not include power and ground, which easily map to logic 1 and 0). They are typically in complex
CMOS gates such as AND-OR-INVERT gates, multiplexers, and other complex logic functions. Although we could ignore macroevents involving these polygons, they will become an additional source of error. We developed a technique to handle the polygons by mapping their logic functions to standard cell ports, and we used this technique in the silicon experiment that we describe later.
The extracted macroevents represent bridges that can involve two or more signal lines. Test engineers commonly use bridge faults 10 to model two-line bridge defects, but because macroevents can involve more than two lines, more-advanced fault models are necessary. We use the voting-bridge fault model, 11 in which pull-up and pull-down network drive strengths determine the erroneous lines.
We form a voting model for each macroevent by separately summing the drive strengths of all lines in the macroevent driven to logic 0 and logic 1. We then compare the two sums to determine which logic value will be imposed on the other lines. An error occurs on each line with the weaker logic value. To implement the voting model described here, we use fault tuples, a generalized fault representation mechanism.
12 Despite the
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ITC Special Section
394 complex models we use, the behavior of real spot defects is unpredictable and therefore can be a source of error.
To simulate the macroevents modeled as votingbridge faults, we use FATSIM, a concurrent fault simulator for fault tuples.
12 To determine which test vectors detect which macroevents, we use no fault dropping during simulation. The resulting data is stored in the T matrix, which has the following form: cretely using some number of points, we can concatenate all the DDSDs’ defect densities into a single vector.
The linear regression’s output will be this vector, which can then be split into a DDSD for each metal layer. We present a detailed mathematical description of these steps elsewhere.
9,10
T
=
⎢
⎣
⎢
⎡ t
M t t
V , 1 t
V , 2
L
L t t
1 , M
M
⎥
⎦
⎥
⎤ where V is the number of test vectors simulated, M is the total number of macroevents, and t s , i is a 1 (0), indicating that macroevent i is detected (undetected) by test vector s . The T matrix provides the mapping between logic-level faults and circuit test responses.
We have verified qualitatively that an inaccurate T matrix can significantly decrease the overall accuracy of our DDSD extraction approach. When we use a random T matrix, the resulting DDSDs have no resemblance to the expected distribution. Therefore, it is critical that macroevents be modeled precisely and simulated correctly; otherwise, the T matrix’s quality will be questionable. Simulation techniques that are more detailed than a logic-level model (for example, transistor-level Spice simulation) could possibly lead to greater accuracy, but they would increase the required simulation time considerably.
As discussed earlier, we can measure DDSDs by minimizing the difference between the predicted and the observed probability of passing tests (yield per test). We have described the various components necessary to predict probability p i of test i passing. We adapt the critical-area yield model for this task, using critical-area functions of macroevents, and the DDSD per layer as parameters of the model. After measuring the T matrix and critical-area functions of macroevents, the DDSDs are the only unknown parameters of the model. We can p i from tester results as the ratio of the number of chips that pass test i to the total number of chips manufactured.
We can find the DDSDs that minimize the error between p i p i by using linear regression. The key idea is to abandon the concept of individual DDSDs per layer. Because we will capture each distribution dis-
To evaluate the proposed approach, we performed an experiment based on a simulated, artificial process.
We assumed DDSDs for each layer of the artificial process and inserted defects into the process based on these distributions. We measured the estimated yield per test vector by emulating a tester. We then applied the DDSD extraction strategy to the circuit and compared the extracted DDSDs with the inserted DDSDs.
For this experiment, we used circuit c3540 from the
1985 International Symposium on Circuits and Systems
(ISCAS) benchmark suite.
13 We logically optimized the c3540 implementation and technology-mapped it to a
0.18-micron commercial standard-cell library. The final layout was routed in five metal layers and used approximately 100
μ m
×
100
μ m of area.
In modern manufacturing processes, a design of this size would typically be free of defects because of relatively low defect densities. To ease the simulation burden, we assumed that a single die consisted of 10,000 parallel instances of c3540, with each instance retaining its original controllability and observability. As a result, each die had an area of approximately 1 cm 2 and could still be tested with a test set for a single instance of c3540. Although this die had a total critical area comparable to typical chips, it lacked the diverse geometrical features that a die would normally exhibit. However, the impact of design diversity on the DDSD extraction technique was not the experiment’s focus.
After preparing the demonstration circuit, we extracted macroevents, modeled them using fault tuples, and simulated them with FATSIM to generate the T matrix.
The production test set consisted of 155 stuck-at test patterns. During macroevent extraction, we determined critical area for a range of defect sizes to build a critical-area function for each macroevent. For metal layers 1 through
4, the critical-area function domain was 0.2 micron to 2 microns, and for metal layer 5, it was 0.34 micron to 2 microns, with samples spaced at 50-nm intervals.
This resulted in 182 critical-area points. We determined the limits on the basis of minimum line spacing for the
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lower bound and selected the upper bound to capture a sufficient portion of the DDSD’s tail. Figure 3 shows the total discretized critical-area function (sum of critical area functions of all microevents involving the layer) for each of the five metal layers for one instance of c3540.
12,000
10,000
1 2 3 4 5 Metal
182 bins
19 bins
8,000
In the proposed DDSD extraction methodology, we measure the yield per test from the structural test results of a real tester. In the simulation experiment, we substituted tester emulation for actual test results. We generated defects according to a stochastic Poisson process in which each potential defect is an independent event. The assumed
DDSD followed the well-known power law, with the defect densities shown in
Table 1. We increased defect densities to levels well beyond realistic figures to reduce the simulation time required for test emulation.
6,000
4,000
2,000
0
0.2
0.3
0.5
1
Defect radius (
μ m)
2
Figure 3. Critical-area functions (white symbols) extracted from all metal layers of a single instance of circuit c3540 from the ISCAS 85 benchmark
We consider each macroevent’s occurrence an independent Poisson process because we assume that each defect’s occurrence is independent of all suite. Black symbols represent critical-area functions after combining a range of defect sizes.
others. As a result, each macroevent occurs with a frequency dictated by a Poisson process at a rate determined from the critical-area function of the macroevent and the DDSDs. Table 2 shows the percentage of dies
Table 1. Injected defect density and size distributions
(DDSDs) following the power law distribution, with power parameter p and peak-probability parameter X
0
= 0.05
μ m for each metal layer. D
0
[cm –2 ] represents defect density.
containing zero, one, two, or three macroevents in a sample size of 50,000 for this experiment. From this table, we reach two conclusions: Parameter
Metal layer
1 2 3 4 5
■
D
0
(cm –2 ) p
1
3
2
4
2
3
1
2
3
3
■
Because the occurrence rates of the number of macroevents per die align with the theoretical occurrence rates, 50,000 dies are sufficient.
Of the simulated dies, multiple macroevents affect only a small percentage.
Table 2. Occurrence rates for the number of macroevents per die for a sample size of 50,000.
From the artificial process simulation, we knew which macroevents occurred on each faulty die. We then obtained the yield per test by inspecting the T matrix. The yield per test varied slightly around an average of 98% for each test. We assume that no masking effects occur for dies affected by multiple macroevents.
Thus, if a test detects any of the individual macroevents, we assume that the test will fail. Table 2 shows that the
Parameter Occurrence rate
No. of macroevents per die
Percentage of dies
0
94.17
1
5.67
2
0.15
3
0.01
assumption that no masking occurs applies to about
0.16% of all dies; thus, any impact from this assumption is minimal.
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396
We formulated the DDSD extraction process as a minimization problem to be solved using linear regression analysis. Here, we detail the regression procedure for the demonstration circuit.
As already mentioned, the total number critical-area points from the critical-area analysis for all layers is 182.
It is natural to likewise want to discretize the DDSDs by solving for their values at the same points as the critical area points. Each of these is referred to as a bin. The individual defect densities in the 182 bins comprise the
DDSD vector we wish to derive. However, given that there are only 155 test vectors, we can obtain only 155 yields per test. Consequently, there are more unknowns than equations, which means the minimization is an undetermined problem with an infinite number of solutions.
To reformulate the problem so that it is solvable, we grouped sample points for defect size ranges into fewer, wider bins, thus reducing the overall number of densities to be derived. Figure 3 shows the 19 bins used for this experiment. We recalculated critical-area functions for the new bin arrangements, represented by the black symbols in Figure 3. This reconstruction doesn’t affect the T matrix, so there is no need to resimulate the faults. We used principal component regression to find the values for the 19 bins that make up the DDSDs. We obtained 95% confidence intervals for the extracted DDSDs, using standard bootstrapping techniques.
14
Figure 4 shows the final extracted results of the analysis for all five metal layers. The triangles represent the
19 extracted DDSD vector components, and the small circles represent the assumed DDSD components.
Although the results aren’t perfect, the inserted DDSD and the extracted DDSD correlate well—a positive and promising result. Figure 4 also shows the 95% confidence intervals for each DDSD component. Some of the confidence intervals are quite large. The source of this variance can be traced to the properties of the criticalarea functions and the T matrix. Specifically, criticalarea functions that contribute to one test’s failing correlate strongly with critical-area functions contributing to other test patterns.
After the success of the simulation experiment, we conducted a similar experiment on a chip manufactured in a commercial facility. The chip is an array of
64-bit ALUs manufactured in a 0.11-micron process. LSI
Logic designed the chip as a process development and silicon-debugging vehicle closely mimicking the design style of the company’s other digital-logic products.
Hence, the chip is ideally suited for testing and validating our DDSD extraction strategy. Each die contains 384
ALUs, each independently controllable and observable
(similar to the assumption made in the simulation experiment).
The chip’s structure is convenient from the perspective of scale because the die is partitioned into many small blocks, each a single ALU. Although not all designs are this regular, large designs are frequently partitioned into smaller blocks and tested separately with scan chains. Analyzing each block independently or limiting the analysis to just a handful of blocks is one strategy for coping with the large number of macroevents associated with an industrial design.
We performed the experiment in almost the same manner as that of the simulation experiment. We adjusted the critical-area bins to account for the smaller feature size. The bin edges were 0.1, 0.2, 0.4, 1, and
2 microns. The silicon chip was routed in six layers rather than five and thus required 23 bins (like metal layer 5, metal layer 6 was captured with only three bins). Another difference in this experiment was that we used real test results for a test set containing 262 patterns provided by the manufacturer. We extracted the results using 451 failing ALUs; the part’s yield is IP, so we don’t disclose the total number of manufactured ALUs.
Figure 5 shows the extracted DDSDs for the six metal layers. We did not simply parameterize an assumed model, yet the extracted curve for each layer follows a power law distribution, a DDSD shape typically found in manufacturing processes. This strongly indicates that these results are meaningful. Additionally, the plots indicate that although the distributions don’t vary widely, there are differences in defect densities from layer to layer. The y -axis in each graph has the same range, making plot comparisons easier. Finally, the large confidence intervals for the smallest defect sizes in metal layers 5 and 6 occur because there is very little critical area for small defects in the higher metal layers, as Figure 6 shows. This can be the result of either design rules that force lines to be farther apart or simply the decreased routing density in those layers. Either way, there is limited ability to observe small defects in those layers—hence, the large confidence intervals.
The results of the experiment on chips fabricated in
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1.0
1 2
0.8
0.6
3
Metal 1
4
Extracted defect density
Presumed defect density
1.0
5 6
0.8
0.6
7
Metal 2
8
0.4
(a)
0.2
0
0.2
0.5
1
Defect radius (
μ m)
Metal 3
1.0
9 10 11 12
0.8
95% confidence interval
0.6
2
0.4
(b)
0.2
0
0.2
0.5
1
Defect radius (
μ m)
Metal 4
1.0
0.8
14 15 16
(c)
0.4
0.2
0
0.2
0.5
1
Defect radius ( μ m)
1.0
17
0.8
2
18
0.6
(d)
0.4
0.2
0
0.2
0.5
1
Defect radius ( μ m)
Metal 5
19
2
2
0.6
0.4
0.2
0
0.3 0.5
1
Defect radius (
μ m)
2
(e)
Figure 4. Assumed and extracted DDSDs for all metal layers and corresponding 95% confidence intervals: metal 1 (a), metal 2 (b), metal 3 (c), metal 4 (d), and metal 5 (e).
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1 2 3
Metal 1
4 5 6 7
Metal 2
8 9 10 11
Metal 3
12
(a)
0.2
0.5
1
Defect radius (
μ m)
14 15
Metal 4
16
2
(b)
0.2
0.5
1
Defect radius (
μ m)
18 19
Metal 5
20
2
(c)
0.2
0.5
1
Defect radius (
μ m)
21 22
Metal 6
23
2
(d)
0.2
0.5
1
Defect radius ( μ m)
2
(e)
0.2
0.5
1
Defect radius ( μ m)
2
(f)
0.2
0.5
1
Defect radius ( μ m)
2
Figure 5. Extracted DDSDs for all metal layers in a fabricated 64-bit ALU test chip, and corresponding 95% confidence intervals. Defect densities are hidden to protect IP, but the scale of all plots is identical. Metal 1 (a), metal 2 (b), metal 3 (c), metal 4 (d), metal 5 (e), and metal 6 (f).
398 silicon confirm the results of the simulation experiment:
We can measure DDSDs that characterize a process in ordinary digital circuits using only slow, structural test results from the product.
R ATHER THAN DISCARDING pass/fail test results once a part has been sorted, we can derive valuable process characteristics from the test data. Our strategy extracts
DDSDs consistent with those we’d expect to see for a modern manufacturing process—an achievement not previously accomplished without using additional silicon area. Our ongoing research is looking for ways to improve accuracy by using high-fidelity fault models and greater data volume, as well as by accounting for yield loss due to other defect types such as open circuits.
Many manufacturers continue to rely on inspection techniques whose quality degrades with every new process generation. Our approach to extracting process characteristics doesn’t suffer from the same degradation. Although manufacturers stand to gain much from using this approach, our strategy also offers an opportunity for fabless companies to gain insight into the fabrication of their chips. For the first time, such companies can independently compute their products’ defect characteristics and improve design yield by tuning designs for a given fabline.
■
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5.E+04
4.E+04
Metal 1
Metal 2
Metal 3
Metal 4
Metal 5
Metal 6
3.E+04
2.E+04
1.E+04
0.E+00
0 0.5
1.0
Defect radius (
μ m)
1.5
2.0
Figure 6. Total critical-area functions per layer extracted from all metal layers of a 64-bit ALU.
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Jeffrey E. Nelson is a PhD candidate in the Department of Electrical and Computer Engineering at
Carnegie Mellon University. His research interests include process characterization and testing of digital systems. He has a
BS and an MS in electrical and computer engineering from Rutgers University and Carnegie Mellon University, respectively. He is a member of the IEEE.
Thomas Zanon is a PhD candidate in the Department of Electrical and
Computer Engineering at Carnegie
Mellon University and a yield ramping consulting engineer at PDF Solutions, in San Jose, California. His research interests include defect and process characterization based on test results. Zanon has a Dipl. Ing. degree in electrical engineering and information technology from the
Technische Universitaet Muenchen. He is a member of the IEEE and EDFAS.
include test and diagnosis of integrated, heterogeneous systems. He has a BS in engineering from Calvin College, an MS in electrical engineering from the University of Arizona, and a PhD in computer science and engineering from the University of Michigan, Ann Arbor.
Wojciech Maly is the Whitaker Professor of Electrical and Computer
Engineering at Carnegie Mellon University. His research interests focus on the interfaces between VLSI design, testing, and manufacturing, with emphasis on the stochastic nature of phenomena relating these three VLSI domains. Maly has an MSc in electronic engineering from the Technical University of Warsaw and a PhD from the Institute of Applied Cybernetics, Polish Academy of Sciences.
Jason G. Brown is a PhD candidate in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include defect-based test, inductive fault analysis, and layout-driven diagnosis.
He has a BS in electrical engineering from Worcester
Polytechnic Institute and an MS in computer engineering from Carnegie Mellon University.
Brady Benware is a staff engineer in the Product Engineering group at
LSI Logic, where his current focus is on developing defect-based test methods to achieve very low defective-parts-per-million levels. Benware has a PhD in electrical engineering from Colorado State University.
Chris Schuermyer is an engineer in the Advanced Defect Screening group at LSI Logic. His research interests include test for yield and defect learning, defect-based testing, and logic diagnosis. He has a BS in physics and a BS and an MS in electrical engineering, all from Portland State
University.
Osei Poku is a PhD candidate in the
Department of Electrical and Computer Engineering at Carnegie Mellon
University. His research interests include various aspects in test and diagnosis of VLSI circuits, such as automatic test pattern generation, volume diagnosis, and diagnosisbased yield learning. Poku has a BS in electrical engineering from Hampton University and an MS in electrical and computer engineering from Carnegie
Mellon University.
Direct questions or comments about this article to
R.D. Blanton, Dept. of Electrical and Computer
Engineering, Carnegie Mellon University, 5000 Forbes
Ave., Pittsburgh, PA 15213; blanton@ece.cmu.edu.
R.D. (Shawn) Blanton is a professor in the Department of Electrical and
Computer Engineering at Carnegie
Mellon University, where he is the associate director of the Center for Silicon
System Implementation (CSSI). His research interests
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