The Track-Finding Processor for
the Level-1 Trigger of the CMS
Endcap Muon System
D.Acosta, A.Madorsky, B.Scurlock, S.M.Wang
University of Florida
A.Atamanchuk, V.Golovtsov, B.Razmyslovich
St. Petersberg Nuclear Physics Institute
Muon Track-Finding
• Perform 3D track-finding from trigger primitives
• Measure PT , ϕ, and η
• Transmit highest PT candidates to Global Level-1
θ
ϕ
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
2
Track-Finder Requirements
• High efficiency with low PT threshold
• Single muon trigger rate < few kHz at L=1034 cm-2s-1
– Should have large safety factor
• PT resolution ≈ 20%
– Require ϕ, η information from 3 muon stations
• Multi-muon capability
– ≤ 3 muons per 60° azimuthal sector
– Best 4 muons overall sent to Global Level-1 Trigger
• Pipelined and deadtime-less
– 40 MHz B.X. frequency
• Minimal latency
– < 16 B.X. (400 ns)
• Programmable
– FPGA and RAM implementation
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
3
Trigger Regions in η
Overlap
Drift-Tube system
1.2 > η > 0.9
Cathode Strip
Chamber
System
• 4 muon stations in each endcap
• Each station contains 6 layers of CSC chambers
• PT measured from fringe field of 4 T solenoid using
3D track segments in each station
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
4
Trigger Regions in ϕ
Track-Finding
performed in
independent
60° sectors
ME1/3
MB2/2
MB2/1
Illustration of
overlap region
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
5
Why Two Muon Track-Finders?
• The Barrel Track-Finder:
– intrinsically 2D
• road-finding in ϕ only (expect low rates)
• uniform magnetic field in central region
– large number of neighbor interconnections
• chambers are staggered, non-projective
• The Endcap Track-Finder:
– intrinsically 3D
• road-finding in ϕ and η to reduce backgrounds
• non-uniform magnetic field in endcap
– No interconnections between trigger sectors
• chambers are projective in ϕ
• small bending in endcap
• Therefore, different needs in each region imply two
different designs
• Must ensure that fake double triggers do not occur in
region of overlap
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
6
Level-1 Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver Sector Processor
OPTICAL
FE
SR
TMB
PC
2µ / chamber
3µ / port card
SP
LCT
FE
Wire FE cards
3µ / sector
Wire LCT card
36µ
In counting house
CSC Muon Sorter
RPC
On chamber
On periphery
4µ
DT
4µ
4µ
Global µ Trigger
Global L1
4µ
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
7
Track-Finder Architecture
• Track-Finder implemented as 12 Sector Processors
• Each Sector Processor:
– Implemented on a 9U VME card
– Processes 15 CSC segments and 8 DT segments
– Identifies ≤ 3 muons per 60°
• CSC data received by 3 Sector Receiver cards
–
–
–
–
Each receives 6 track segments on optical links
Reformats data to ϕ, ϕb , η
Applies alignment corrections
Communicates to Sector Processors via custom
point-to-point backplane
– Presently under development at UCLA
• DT data sent to transition board at back of crate
• Custom point-to-point backplane:
– Delivers ~600 bits every 25 ns (3 GB/s)
– Operates at 280 MHz to reduce connections:
• National Channel Link 28:4 serialization
– Presently being prototyped in Florida
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
8
Sector Processor Layout
Custom
Backplane
D. Acosta, University of Florida
P1
Control
Logic
CCB
SR
4 st.
Channel Links
Global Buffer (FIFOs)
Extrapolation Units
TAU2
(endcap)
VME
Interface
2 Bunch Crossing Analyzer
FPGA
Download
Logic
Final
Selection
Unit
TAU1
(overlap)
Pt-assignment
Units(LUTs)
Channel Links
Output
Data
Storage
Pt-assignment Units (FPGAs)
LED
Drivers
Control Logic
(Clock distribution, SRAM read/write
and other devices)
Transition
Module
LEB99 Workshop, September 21, 1999
SR
1,3 st.
SR
1,2 st.
SR
Barrel
9
Sector Processor Logic
• Latch input and hold for possibly more than one B.X.
– Allows for timing errors from trigger primitives
• Perform all possible station-to-station extrapolations
in parallel
– Simultaneously search roads in ϕ and η
• Assemble 3- and 4-station tracks from 2-station
extrapolations
• Cancel redundant short tracks if track is 3 or 4
stations in length
• Select the three best candidates
• Calculate PT , ϕ, η and send to CSC muon sorter
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
10
Two Bunch Crossing Mode
• Input data can be latched for 2 B.X. to accommodate
timing errors from trigger primitives
• Sector Processor still reports trigger at correct B.X.
Title:
(dblecnt.eps)
Creator:
Adobe Illustrator(R) 8.0
Preview:
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with a preview included in it.
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D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
11
Extrapolation Unit
η road finder
Q2
Q1
η2
η1
φ2
φ1
ψ2
ψ1
Amb2
Amb1
Global
Clock
FF
3
FF
3
FF
6
FF
6
FF
10
LUT
64x2
FF
2
FF
2
LUT
64x1
FF
1
FF
1
SB
η 1− η2
FF
7
LUT
64x1
FF
1
LUT
64x7
ηhigh
FF
7
LUT
64x7
ηmed
FF
7
LUT
64x7
η low
FF
7
ABS
FF
10
SB
φ 1−φ 2
FF
10
LUT
32x5
ψ2max
FF
5
FF
5
FF
1
FF
1
1Bx
D. Acosta, University of Florida
LUT
128x1
FF
1
FF
1
FF
5
LUT
32x5
ψ 2min
FF
5
LUT
32x5
ψ1max
FF
5
LUT
32x5
ψ1min
FF
5
NOT
AND
FF
1
SB
η h−∆ φ
FF
1
SB
η m−∆
φ
FF
1
SB
η l−∆φ
FF
1
LUT
8x1
FF
1
SB
∆ φ−ψ2
FF
1
SB
∆ φ−ψ2
FF
1
SB
∆ φ−ψ1
FF
1
SB
∆ φ−ψ1
FF
1
Course Pt assign
enable
LUT
32x2
enable
FF
2
Extrapolation
Quality
ϕ road finder
6input
AND
ϕ
Xilinx Virtex
FPGA
XCV150
FF
1
1Bx
Z
3input
AND
FF
1
1Bx
LEB99 Workshop, September 21, 1999
12
Track Assembly Procedure
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D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
13
3 ME33 – ME4
3 ME33 – ME2
12 ME33 – ME1
LINK
33
9
6
3 ME32 – ME4
3 ME32 – ME2
12 ME32 – ME1
LINK
32
9
6
3 ME31 – ME4
3 ME31 – ME2
12 ME31 – ME1
LINK
31
9
6
3 ME23 – ME4
3 ME23 – ME3
12 ME23 – ME1
LINK
23
9
6
3 ME22 – ME4
3 ME22 – ME3
12 ME22 – ME1
LINK
22
9
6
3 ME21 – ME4
3 ME21 – ME3
12 ME21 – ME1
LINK
21
9
6
6 ME23 – ME1
4 ME23 – MB2
8 ME23 – MB1
LINK
23
9
6
6 ME22 – ME1
4 ME22 – MB2
8 ME22 – MB1
LINK
22
9
6
6 ME21 – ME1
4 ME21 – MB2
8 ME21 – MB1
LINK
21
9
6
Extrapolation output
small enough to
address SRAM for
quick decision
D. Acosta, University of Florida
SRAM
256Kx16
IDT
LEB99 Workshop, September 21, 1999
To Final Selection Unit
From Extrapolation Units
Track Assembler Unit
6 bit Ranking &
9 bit hit i.d. :
14
Station MB1
Station MB2
Station ME1
Station ME2
Station ME3
Station ME4
1
MUX
1
1
AND
1
4 bits:
1st stub Bx ID – 1 bit;
2nd stub Bx ID – 1 bit;
3rd stub Bx ID – 1 bit;
4th stub Bx ID – 1 bit.
1
To prohibit
Double Count
Select
1
MUX
1
1
AND
1
AND
1
MODE
0 – no µ
1 – a Match bit unset
(only for 3-stn)
2 – 1-2-3
3 – 1-2-4
4 – 1-3-4
5 – 2-3-4
11 – MB1-MB2-ME2
6 – 1-2
12 – MB1-ME1-ME2
7 – 1-3
13 – MB2-ME1-ME2
8 – 2-3
14 – MB1-ME2
9 – 2-4
10 – 3-4 15 – MB2-ME2
1
Select
1
MUX
1
1
1
MUX
9
Converter 4
Enable
13
Converter 4
9
Enable
9
13
Converter 4
9
Enable
9
9
Converter 17
9
9
9
9
9
9
9
9
Track 9
Track 8
Track 7
Track 6
Track 5
Track 4
Track 3
Track 2
Track 1
Hit Number Comparators
(36 Units)
9
4
4
Converter 17
4
Converter 17
36
Final
Decisio
n Unit
17 bits:
1st stub number – 5 bits;
2nd stub number – 5 bits;
3rd stub number – 5 bits;
2-stn or 3-stn mode – 1 bit;
overlap or endcap track – 1 bit.
6
6
6
5
6
6
6
6
6
Extrapolations Quality
Comparators
(36 Units)
Stream 1 Stream 2 Stream 3
13
9
Sel1 Sel2 Sel3
Stream 1 – ME2 key station
Stream 2 – ME2 key station
Stream3 – ME3 key station
Stream 1 Stream 2 Stream 3
9
Track 9
Track 8
Track 7
Track 6
Track 5
Track 4
Track 3
Track 2
Track 1
9
Extrapolation Quality Part
From Track Assembler Unit
Hit Number Part
Select
To Assignment
Unit (FPGAs)
4
4
6
3
3
3
36
To select
3 best tracks
out of 9
“Final Selection Unit”
FPGA XCV50 (XILINX)
6
D. Acosta, University of Florida
To Assignment
Unit (FPGAs)
Bunch crossing ID
From 2 Bx Analyzer
The Final Selection Unit
A Sorter with Cancellation Logic
LEB99 Workshop, September 21, 1999
VHDL
code
written
15
Assignment Unit
• Determines ϕ, η, PT of the selected 3 best muons
• PT assignment uses ϕ, η measurements from 2 or 3
stations
– δPT/PT ~ 30% with only 2 stations
– δPT/PT ~ 20% with 3 stations ⇒ improves Level-1 rate
reduction
• Implemented with FPGA preprocessing followed by
large SRAM look-up table
2Mb×16 SRAM
FPGA
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
16
Summary of CSC Track-Finder
• Conceptual design complete
• 12 Sector Processors cover CSC and CSC/DT
overlap
– 1.0 < η < 2.4 and ∆φ = 60° on one board
• Track-finding algorithms are three-dimensional
– Improves background suppression
• PT assignment includes φ,η measurements from 3
stations
– δPT/PT ~ 20%
(30% with only 2 stations)
– Significantly improves rate reduction at Level-1
• Inputs can be latched for 2 B.X.
– Tolerates timing errors from trigger primitives
•
•
•
•
Latency expected to be only 14 B.X.
Fully re-programmable
Xilinx Virtex FPGAs and SRAM used
Board layout and backplane design started
D. Acosta, University of Florida
LEB99 Workshop, September 21, 1999
17