Substrate Noise Analysis Tool User’s Guide
Nisha Checka
May 5, 2006
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Platform Support
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Download
SNAT can be downloaded from the following password protected website.
http://www-mtl.mit.edu/researchgroups/icsystems/subnoise
SNAT is available free to MARCO and DARPA researchers. Please refer to the website for information on obtaining access to SNAT.
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Requirements
An HSPICE license is required to run SNAT. SNAT uses HSPICE in the library characterization
to extract current profiles. In addition, HSPICE is used to solve the simplified macromodel netlist.
If the starting circuit is extremely complex (i.e 100K gates or greater), the resultant macromodel
netlist can be quite large. In this case, Nanosim can be used to solve the netlist.
A Nanosim license is also required. Nanosim is used to extract capacitance data at each node of
all standard cells. If the user provides the capacitance of each node of each standard cell, then
Nanosim is not required.
If the circuit input description is a verilog/VHDL description, then the description must be synthesized so that a listing of the standard cells used in the design is available. SNAT will need this
information to complete the simulation.
SNAT is compatible with Cadence and just about any layout tool. A Cadence license is not required.
If, however, the user wishes to generate a substrate model from a layout, an extraction function
must be available to correlate the relevant nodes of the substrate model with the designed circuit.
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Overview
The simulation of large digital systems to predict the substrate noise performance is a computationally complex task. Full transistor level SPICE simulations yield the most accurate results;
however, the technique is impractical for most circuits as the run-time increases rapidly with circuit complexity. For typical circuits, full transistor level simulations take on the order of weeks to
simulate a few clock cycles and most often do not converge.
It has been demonstrated that abstracting the noise behavior into an equivalent linear noise macromodel greatly improves simulation speed without much expense in accuracy. SNAT uses a macromodelling based approach.
Figure 1 shows a high level block diagram. SNAT requires two inputs: a circuit description and a
technology description. Refer to Section 5.1 for more information on the valid input files. SNAT
decomposes the circuit into equivalent noise macromodels. The noise macromodels together with
the event model for each node in the circuit are used to construct the noise signature. The noise
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signature is then simulated with the substrate model and power grid (optional) to compute the
substrate noise profile. The outputs are a time domain representation and noise spectrum.
Technology Information
Circuit Description
Decompose
into noise
macromodels
Noise injection
pattern
Event
model
Noise Information
Figure 1: Flow of Substrate Noise Analysis Tool.
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5.1
Usage
Input Files
SNAT works with a broad spectrum of information for both the circuit and technology descriptions.
This allows SNAT to be used at any stage in the design cycle. The different input descriptions that
SNAT can work with are detailed in Figure 2 and Figure 3.
Circuit Description
SNAT works by trading off accuracy for speed. The more descriptive the input file (i.e. SPICE
netlist with extracted parasitics), the better the noise modeling is, and as a result, the more
accurate the result is. However, more elements are required to accurately model the noises sources,
consequently the run time is longer. Figure 2 details the various circuit description granularity
levels.
Short Run Time
Least Descriptive
Long Run Time
Most Descriptive
Increasing Accuracy
Gate level netlist
SPICE netlist
SPICE netlist
w/parasitics
Figure 2: Circuit Description Granularity Levels.
If the input file is a verilog/VHDL netlist, the verilog/VHDL simulator is used to generate the event
model. This information is typically generated during the regular design phase. The the rise/fall
times of the signals predicted by the simulation will be less accurate than a SPICE simulation. The
verilog/VHDL netlist
must
then be synthesized so that SNAT canLong
generate
Short
Run Time
Run Time the equivalent noise
Least
Descriptive
Most
Descriptive
macromodels. The synthesized netlist and the event model are required for SNAT to generate the
Increasing Accuracy
Substrate resistivity
(no layout)
SNAT generated
2 resistivity
Substrate
(w/ contacts layout)
SNAT generated
Substrate doping
profile (full layout)
SubstrateStorm
noise signature.
If the input file is a SPICE netlist, SPICE or Nanosim or some equivalent SPICE-level simulator
can be used to generate
the event model. The SPICE netlist andLong
event
model are then used by
Short Run Time
Run Time
Least noise
Descriptive
Most Descriptive
SNAT to generate the
signature.
Increasing Accuracy
Technology Description
Gate level netlist
SPICE netlist
SPICE netlist
SNAT is not meant to be used for accurate substrate modeling. w/parasitics
Several tools are available for
this function. Cadence’s SubstrateStorm is one such tool. It requires a layout and the substrate
doping profile to generate the substrate model. For final verification simulations, it is recommended
that the user generate the substrate model using an external tool. The resultant netlist can be
incorporated into SNAT. If, however, a full substrate doping profile is not available or if a faster
run time is desired, SNAT can be used to generate the substrate model. Refer to Figure 3 for a
listing of the various technology description granularity levels.
Short Run Time
Least Descriptive
Long Run Time
Most Descriptive
Increasing Accuracy
Substrate resistivity
(no layout)
SNAT generated
Substrate resistivity
(w/ contacts layout)
SNAT generated
Substrate doping
profile (full layout)
SubstrateStorm
Figure 3: Technology Description Granularity Levels.
To generate the substrate model from a layout using SNAT, the input SPICE netlist must be generated using the extract function in Cadence or an equivalent layout editor. This is required so
that the SNAT can match the substrate nodes of the various devices in the design to the layout.
The layout must be in CIF format. GDS2 is a binary format and as a result is unable to be read
by SNAT. The underlying substrate resistivity must be entered in the layout configuration file.
If no layout information is available, a bound on the die size must be entered so that SNAT can
generate a very coarse model.
5.2
Configuration Files
BSIM model file
‘technologyname’.char
‘technologyname’.v
‘technologyname’.cdl
5.3
Library Characterization
The first step in the noise simulation is to perform a library characterization. The user must
provide four files that describe the library. The first is the model file that contains the BSIM
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models of the devices. The second is a technology characterization file. The name of the file must
be ‘technologyname’.char. This file contains information about the technology such as the power
supply voltage. The format of the file must be as follows:
vdd,segmenttime,steptime,rlat,cwell
path to BSIM model file
Sample files are included with the SNAT download. In addition, sample files can be found in the
Example section of this document. segmenttime corresponds to the time span for the extracted
current profiles in nanoseconds. If you’re unsure as to what value to set this, set it high and then
reduce if the file sizes are too large.
steptime is the time step used in spice simulations. This should be based on the operating frequencies of interest. If the simulation is to be run over a long time span, a small time step will
result in a long simulating time. However, if the time step is set too large, then the accuracy of the
simulation will suffer.
rlat is the lateral resistance of the substrate.
cwell is the capacitance of the nwell.
The third file is a verilog file containing a verilog description of all the standard cells. The naming
convention of this file must be ‘technologyname’.v where ‘technologyname’ is the name of the technology. The last file is a SPICE description of all the standard cells. The name of this file must be
‘technologyname’.cdl.
Two additional files must be provided that describe the characterization. These two files, cap.list
and rt.orig, describe the rise and fall times and capacitance values over which the library will
be characterized. cap.list contains 12 capacitances values (in fF) over which each cell will be
characterized. A nominal list is provided with the download but can be changed by the user. These
nominal values are appropriate for a 0.18µm technology. These values should scale down with decreasing technology node.
rt.orig contains 11 rise/fall time values (in ns) over which each cell will be characterized. A nominal file is provided with download and can be changed by the user. These values will depend on
the frequencies of interest and are appropriate for high frequency operation in a 0.18µm technology.
The purpose of the library characterization is to extract the noise behavior of the standard cells.
This step need only be performed once per technology library. To run the library characterization,
type the following line at the prompt. Replace ‘technologyname’ with the name of the technology.
SNAT % libchar ‘technologyname’
For example, for the TSMC 0.18 µm technology, the technology name is tsmc18. To run the library
characterization, the following line executes the characterization.
SNAT % libchar tsmc18
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The entire standard cell library is characterized during this step and takes roughly 18 hours to
characterize 471 standard cells on a dual processor 1.2 GHz SunFire 280r machine. If the user
wishes to reperform the library characterization or delete the results, SNAT must be reinitialized.
To do so, run the following command:
SNAT % reinit
5.4
Noise Simulation
For the actual noise simulation, SNAT is run with two command line arguments. The main input
is the circuit description:
SNAT % snat ‘circuitdescription’.‘fileextension’ ‘technologydescription’
If the input file is a SPICE netlist, the file extension must be sp. If the input file is a verilog or
VHDL netlist, the file extension will be v and vhd respectively. The file extension is limited to
these formats and must follow this convention. SNAT invokes the correct netlist parser based on
the file extension. An example command for a SPICE netlist is as follows:
SNAT % snat mycct.sp tsmc18
The second command line option describes the library. It must be the same as the library name
used during characterization.
When SNAT is invoked, the user is prompted to supply substrate model information as well as
other run-time parameters. When first invoked, SNAT chooses the appropriate netlist parser and
constructs the skeleton of the individual macromodels. It then generates the event model. The
user is then prompted to enter the substrate type:
What type of substrate is used (e.g. epi, nonepi, soi)?
The options are epi, non-epi, and SOI. The substrate model depends on the substrate type. If
an epi substrate is used, a common substrate node is assumed. For non-epi and SOI substrates,
a more complex model is required. If the user selects an epi substrate, SNAT requires values for
resistivities of both the epi layer and the bulk in Ωcm:
Enter the resistivity of the epi layer (ohmcm):
Enter the resistivity of the bulk (ohmcm):
If the user selects either a non-epi substrate or SOI, SNAT asks for information on the substrate
model.
Do you have a substrate model (y/n)?
If the user has a substrate model, SNAT prompts for the path to that model. If the user does not
already have a substrate model, SNAT will be used to generate the model. SNAT can generate the
model using one of two methods. First, if a layout is available, SNAT generates the model from
the layout. In the layout file, the bulk nodes of the devices should be labeled with the following
convention:
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‘instancenumber’_‘cellname’_bulk‘devicenumber’
For example, the bulk node of the device M2 in instance X2 of a NAND gate should be labeled as
follows:
X2_NAND_bulkM2
The only layout format that SNAT is able to accept is a .cif file. GDS files can easily be converted
to CIF format using any layout program. SNAT prompts the user for the path to the layout file.
SNAT requires also requires the value of the substrate resistivity to generate the substrate model.
Finally, if a layout is not available, SNAT generates a coarse substrate model from the die size
and substrate resistivity information. The user must enter the die length and width in the units of
microns.
SNAT generates the substrate model that is used to interconnect the substrate nodes of the individual macromodels based on the user-supplied information. The last step in the simulation is the
incorporation of a power grid.
Do you have a model for the power grid (y/n)?
If the user has a power grid, SNAT prompts the user to enter the path:
Enter the filename:
After the power grid information has been entered, information on the package parasitics must be
provided. SNAT requires values of the resistance (Ω), inductance (nH), and capacitance (pF) of
the package.
Package parasitics, Rpar (ohm):
Lpar (nH):
Cpar (pF):
Finally, the user can choose whether to use the isolation plug-in. Currently, the plug-in only works
with guard ring isolation. In order to determine the isolation provided by the guard ring, key
parameters of the structure must be entered. First, the guard ring type affects the isolation. The
possible types are an n+ guard ring, a p+ guard ring, and a dual n+/p+ guard ring. If a single
guard ring is used, the width of the guard ring must be entered. this denoted by w in Figure 4(a).
If the dual guard ring is used, the width of the individual rings (w1 and w2 ) must be entered as
well as the spacing. This is denoted by sg in Figure 4(b). The user must also enter the spacing
between the active circuitry and the innermost ring. This distance is usually defined as being the
distance between the center of the active circuits to the innermost ring. This is denoted by s in
Figures 4(a) and 4(b). The length and width of the structure must be entered. This is denoted by
ltot and wtot in Figures 4(a) and 4(b). Finally, to determine the substrate noise profile as a result
of the guard ring, a sensing location must be defined. This location is fixed along the center axis
of the active circuits. Refer to Figures 4(a) and 4(b) for all relevant guard ring parameters.
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Unused silicon area
tot
Dual n+/p+
guard rings
Single n+ or
p+ guard ring
tot
w1
Active
circuits
tot
Active
circuits
Sense
location
tot
Unused silicon area
Unused silicon area
Sense
location
w2
g
(a) Single guard ring (n+ or p+).
(b) Dual guard ring (n+ and p+).
DualFigure
n+/p+ 4: Guard ring geometries and parameters.
guard rings
tot
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Example
w1
This section runs through a sample
SNAT simulation.
6.1
Active
Files circuits
tot
Sense
location
Sample files are included in the Example directory of the download. The Example directory has
seven files. A description of each of these files is given below. This sample library was designed in
a 0.18-µm technology and includes three standard cells.
Unused silicon area
w2
sample.char
Description: contains
g library characterization information such as power supply voltage, segment
length, time step, lateral resistance of the substrate, capacitance of the n-well, and the path to the
BSIM models.
File:
1.8,3,5e-12,5,50e-15
~/SNAT/Example/modelfile.l
sample.cdl
Description: contains SPICE descriptions of standard cells.
File:
.subckt XOR2X1 Y A B
M0 net29 net21 net37 VDD P l=0.18u w=0.792u
M1 net29 A net38 VDD P l=0.18u w=0.792u
M2 net29 A net37 VSS N l=0.18u w=0.528u
M3 net29 net21 net38 VSS N l=0.18u w=0.528u
M4 Y net29 VSS VSS N l=0.18u w=0.66u
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M5 VDD net29 Y VDD P l=0.18u w=0.99u
M6 net21 A VSS VSS N l=0.18u w=0.33u
M7 VDD A net21 VDD P l=0.18u w=0.462u
M8 net37 net38 VSS VSS N l=0.18u w=0.528u
M9 VDD net38 net37 VDD P l=0.18u w=0.792u
M10 net38 B VSS VSS N l=0.18u w=1.32u
M11 VDD B net38 VDD P l=0.18u w=1.804u
.ends XOR2X1
*.SCALE meter
.GLOBAL GND VSS VDD
.subckt CLKBUFXL Y A
M0 Y net7 VSS VSS N l=0.18u
M1 VDD net7 Y VDD P l=0.18u
M2 net7 A VSS VSS N l=0.18u
M3 VDD A net7 VDD P l=0.18u
.ends CLKBUFXL
*.SCALE meter
.GLOBAL GND VSS VDD
w=0.32u
w=1.02u
w=0.32u
w=0.32u
.subckt INVX1 Y A
M0 Y A VSS VSS N l=0.18u w=0.66u
M1 VDD A Y VDD P l=0.18u w=0.99u
.ends INVX1
*.SCALE meter
.GLOBAL GND VSS VDD
sample.v
Description: contains verilog descriptions of standard cells.
File:
‘celldefine
module XOR2X1 (Y, A, B);
output Y;
input A, B;
xor I0(Y, A, B);
endmodule // XOR2X1
‘timescale 1ns/10ps
‘celldefine
module CLKBUFXL (Y, A);
output Y;
input A;
buf I0(Y, A);
endmodule // CLKBUFXL
‘timescale 1ns/10ps
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‘celldefine
module INVX1 (Y, A);
output Y;
input A;
not I0(Y, A);
endmodule // INVX1 ‘endcelldefine
modelfile.l
Description: contains BSIM models.
multicell.sp
Description: example SPICE circuit netlist to be simulated by SNAT.
pgmodel.sp
Description: example power grid model for multicell.sp.
submodel.sp
Description: example externally generated substrate model for multicell.sp.
cifconv.table
Description: CIF names for diffusion, p implant, and n well layers. The second column represents
the CIF name for the corresponding layer in the first column. For example, if the CIF name for
the diffusion layer is L1. The first line says DIFF L1. This file is only required if using SNAT to
generate a substrate model from a layout.
6.2
Running SNAT
First, copy the files sample.char, sample.v, and sample.cdl to the home directory.
SNAT % cp Example/sample.* .
The first step is to run the library characterization on the library sample. This will characterize
the three cells in the library.
SNAT % libchar sample
When the library characterization is finished, the message Library Characterization Finished
is displayed. The library characterization data can be used for all designs that use this library.
If the user wishes to re-perform the library characterization or delete the library characterization
results, SNAT must be re-initialized. Use the following command to reinitialize SNAT:
SNAT % reinit
The next step is to perform the actual substrate noise simulation. For this example, the SPICE
netlist described in multicell.sp will be simulated for its substrate noise performance. To invoke
the simulation, use the following command:
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SNAT % snat multicell.sp sample
The user will be prompted to enter more information to complete the simulation. SNAT generates
a macromodel-based equivalent circuit netlist with the format ‘originalspice’ snat.sp. For
this example, the file is called multicell snat.sp. All the different simulation possibilities will be
discussed in this section.
If a simulation has been run previously, SNAT can reuse that event model. This is particularly
useful if the user wishes to see the effect of substrate type and layout granularity levels on the
simulation results without changing the circuit netlist itself. If, however, the topology of the circuit
has changed or the input has changed, then the simulation must be re-run. If SNAT detects that a
simulation has been run previously, it asks the user whether he or she wishes to use the same event
model. Reusing the event model can save a considerable amount for very large designs.
Has the event model changed since the last simulation (y/n)? y
The user will not be asked this question, if this is the first time the simulation is being run.
Epi Substrate
First the user is prompted to enter the substrate type.
What type of substrate is used (e.g. epi, nonepi, soi)? epi
Type epi and press enter. The user is then prompted for the resistivity of the epi layer in units of
Ωcm. Enter 10 and press enter. The user must then enter the resistivity of the bulk in Ωcm. Enter
.001 and press enter.
Enter the resistivity of the epi layer (ohmcm): 10
Enter the resistivity of the bulk (ohmcm): .001
The user is then prompted for a power grid model. If no power grid is available, then common
power supply nodes are assumed. A sample power grid model is provided in the Example directory. We will run the simulation with this sample model. At the prompt, enter y. Then, enter
Example/pgmodel.sp as the path to the power grid model.
Do you have a model for the power grid (y/n)? y
Enter the filename: Example/pgmodel.sp
To complete the base simulation, a model for the package must be entered. SNAT requires the
resistance, inductance, and capacitance of the package. For this example, we will assume a simple
bond wire connection. Enter 3 Ω, 2 nH, and 10 pF for Rpar , Lpar , and Cpar respectively.
Package parasitics, Rpar (ohm): 2
Lpar (nH): 3
Cpar (pF): 10
Finally, SNAT prompts the user to use the isolation plug-in. Guard rings are ineffective for epi
substrates so we will skip using guard rings for this example.
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Would you like to use the isolation plug-in (y/n)? n
From the entered information, SNAT performs the simulation. The output can be viewed using
any waveform viewer such as Awaves.
Non-epi/SOI substrates with an externally generated substrate model
At the substrate type prompt, enter nonepi. This section is the same for SOI also.
What type of substrate is used (e.g. epi, nonepi, soi)? nonepi
This example demonstrates simulation with an externally generated substrate model. When asked
if a substrate model is available, enter y.
Do you have a substrate model (y/n)? y
Then, enter the path to the substrate model. The sample substrate model is provided in the
Example directory and is called submodel.sp.
Enter the filename: Example/submodel.sp
The user is now prompted for a power grid model. Since the epi simulation above shows how to
incorporate a power grid model, we will skip it here.
Do you have a model for the power grid (y/n)? n
Enter the same bond wire parasitics as above.
Package parasitics, Rpar (ohm): 2
Lpar (nH): 3
Cpar (pF): 10
We will use the isolation plug-in in the last example.
Would you like to use the isolation plug-in (y/n)? n
Non-epi/SOI substrates with a SNAT-generated model from layout
At the substrate type prompt, enter nonepi. This section is the same for SOI also.
What type of substrate is used (e.g. epi, nonepi, soi)? nonepi
This example uses SNAT to generate the substrate model from a layout. When asked if a substrate
model is available, enter n.
Do you have a substrate model (y/n)? n
A layout is available so enter y when prompted. A sample layout file is provided in Example/multicell.cif.
Enter this filename when asked.
Do you have a layout (y/n)? y
Enter the layout file (filename.cif): Example/multicell.cif
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To construct the model, SNAT needs to know the underlying substrate resistivity. A standard
non-epi substrate has a resistivity between 10-15 Ωcm. Enter 12.5 as the resistivity.
Enter the substrate resistivity (ohmcm): 12.5
We will again skip the power grid model. Enter the same bond wire parasitics:
Do you have a model for the power grid (y/n)? n
Package parasitics, Rpar (ohm): 2
Lpar (nH): 3
Cpar (pF): 10
We’ll skip the isolation plug-in for now.
Would you like to use the isolation plug-in (y/n)? n
Non-epi/SOI substrates with a SNAT-generated model and no layout
At the substrate type prompt, enter nonepi. This section is the same for SOI also.
What type of substrate is used (e.g. epi, nonepi, soi)? nonepi
This example uses SNAT to generate the substrate model knowing only the die size. When asked
if a substrate model is available, enter n.
Do you have a substrate model (y/n)? n
There is no layout available so enter n when prompted.
Do you have a layout (y/n)? n
To construct the model, SNAT needs to know the underlying substrate resistivity. Enter 12.5 as
the resistivity. The die size must be entered to generate the coarse model. Enter 100 as both the
length and width in microns.
Enter the substrate resistivity (ohmcm): 12.5
Enter die length (um): 100
Enter die width (um): 100
We’ll skip the power grid and enter the same bond wire parasitics. We will again skip the power
grid model. Enter the same bond wire parasitics:
Do you have a model for the power grid (y/n)? n
Package parasitics, Rpar (ohm): 2
Lpar (nH): 3
Cpar (pF): 10
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We will now demonstrate the isolation plug-in. SNAT currently works with guard ring isolation.
SNAT informs the user of this fact and asks if the user wishes to continue. Figures 4(a) and 4(b)
are useful to refer to when entering the guard ring parameters.
The first piece of information that is required is the guard ring type. This example will use a dual
n+/p+ guard ring. For a single n+ or p+ guard ring, the values in Figure 4(a) are entered.
Enter the guard ring type (n+,p+,n+p+): n+p+
Next, the various guard ring geometries must be entered. In parentheses, the label corresponding
to either Figures 4(a) or 4(b) are listed. d is the distance between the center of the active circuits
and the sensing location.
Enter the guard ring type (n+,p+,n+p+): n+p+
Enter the width of the n+ guard ring (w1) (um): 10
Enter the width of the p+ guard ring (w2) (um): 10
Enter the space between the n+ and p+ rings (s_g) (um): 5
Enter the distance between active circuitry and the innermost guard
ring (d) (um): 50
Enter the length of the ring structure (l_tot) (um): 100
Enter the width of the ring structure (w_tot) (um): 100
Enter the distance to the sense location (d) (um): 100
Finally, information on the biasing of the guard ring must be provided. Does the guard ring have
dedicated supplies? For this example, both the n+ and p+ guard ring have dedicated supplies.
Is there a dedicated guard ring VDD (y/n)? y
Is there a dedicated guard ring GND (y/n)? y
The sensing location is labeled sense in the SNAT-generated netlist.
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