International Journal of Engineering Trends and Technology (IJETT) –volume 4 issue 7 July 2013
Implementation of Digital Frequency Synthesizer in
Communication System on FPGA
1
Anupama B R, 2M C Chandrashekhar, 3Dr. M Z Kurian
1
PG Student [DE], Dept. of E&C, SSIT, Maralur, Tumkur, Karnataka, India
2
Associate Prof., Dept. of E&C, SSIT, Maralur, Tumkur, Karnataka, India
3
Dean & HOD, Dept. of E&C, SSIT, Maralur, Tumkur, Karnataka, India
Abstract: Digital Frequency Synthesizer (DFS) is used in communication system to generate a sampled sinusoidal carrier wave. The major
advantages of DFS method is that precisely and rapidly manipulate its output frequency, phase and amplitude under the control of a DSP
compare to Coordinate Rotation Digital Computer (CORDIC) technique, which uses an iterative computation method to generate carrier
frequency. But circuit complexity and distortions will be generated, when memory compression methods are employed in CORDIC and
also ROM size becomes fairly large as it grows exponentially with the width of the phase accumulator whereas a large phase accumulator
width is desirable in order to achieve fine frequency tuning. DFS has the ability to tune with extremely fine frequency and phase
resolution and to rapidly hop between the different frequencies. Modulation is carried out using DFS, which has multiplier less structure,
utilizes less resource on FPGA and in demodulation same architecture is used to obtain the digital data back. Signal processing tasks
implemented using digital circuits do not suffer from the effects such as thermal drifts, component variations and aging associated as in
analog counterparts. High degree of system integration can be achieved by implementing the digital functional blocks.
Keywords: DFS, CORDIC, ROM, IC, CMOS, DSP
I.
INTRODUCTION
Modulation and demodulation are the most important aspect in the communication, so have to choose an effective method
to implement. CORDIC algorithm is the one of the technique generate carrier wave in communication system, algorithm is a unique
technique for performing various complex arithmetic functions using shift-add iterations. The algorithm provides low power and
area efficient implementation of complex arithmetic operations in many digital signal processing applications. CORDIC algorithm
used for computing a wide range of functions including certain trigonometric, linear, logarithmic and hyperbolic functions.
CORDIC is also known as the digit-by-digit method and Volder's algorithm [1], is a simple and efficient algorithm to calculate
hyperbolic and trigonometric functions. It is commonly used when no hardware multiplier is available (e.g., simple microcontrollers
and FPGAs) as the only operations it requires are addition, subtraction, bitshift and lookup table. CORDIC is generally faster than
other approaches when a hardware multiplier is not available (e.g., a microcontroller), or when the number of gates required to
implement the functions it supports should be minimized (e.g., in an FPGA).
The following equations used to perform trigonometric functions using just shift and add.
x i 1  x i  y i  di  2i
yi 1  y i  x i  di  2 i
z i 1  z i  di  tan 1 2i 
In CORDIC there are two modes one is rotation mode and another one is vector mode. Rotation by Volder, rotates the
input vector by a specified angle (given as an argument). In vectoring mode, rotates the input vector to the x axis while recording the
angle required to make that rotation. In rotation mode
di= -1 if zi < 0, +1 otherwise
In case of vector mode the value of d become
di= +1 if yi < 0, -1 otherwise
But circuit complexity and distortions will be generated, when memory compression methods are employed in CORDIC
and also ROM size becomes fairly large as it grows exponentially with the width of the phase accumulator whereas a large phase
accumulator width is desirable in order to achieve fine frequency tuning. If the phase accumulator output is truncated introduces
spurious harmonics. DFS is the best method to generate a sampled sinusoidal carrier wave. The major advantage of DFS is that its
phase, amplitude and output frequency can be precisely and rapidly manipulated under the control of a DSP.
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International Journal of Engineering Trends and Technology (IJETT) –volume 4 issue 7 July 2013
II.
BASICS OF DFS
Simplified form of DFS is shown in Fig. 2.1. It consists of a phase accumulator and a phase to amplitude converter
(conventionally a sine ROM) [2]. The phase accumulator consists of a j bit frequency register, which stores a digital phase
increment word followed by a j bit full adder and a phase register. The digital phase increment input word is entered in the
frequency register. This data is added to the data previously held in the phase register at each clock pulse. The phase increment word
represents a phase angle step that is added to the previous value at each ( 1 / f clk ) second to produce a linearly increasing phase
value. The phase is generated by modulo 2 j overflowing property of a phase accumulator. The rate of overflow is consider as the
output frequency, which is expressed as
f out 
Pf clk
2j
 f out 
f clk
,
2
where P is the phase increment word, j is the number of phase accumulator bits, f out is the output frequency and f clk is the
clock frequency. The constraint in the above equation comes from the sampling theorem. Frequency resolution is found by setting
P =1 as the phase increment word is an integer, as
f 
f clk
.
2j
Digital phase information is converted into the values of a sine wave from the ROM, which is the look-up table.
̂
Phase
P
j
Frequency
Register
Phase Register
Amplitude
Phase To
Amplitude
Converter
k
m
j
PHASE ACCUMULATOR
f clk
Phase Accumulator output
Phase to Amplitude converter output
1.5
1
phase
Amplitude
0.5
0
-0.5
-1
sample index n
-1.5
0
50
100
150
200
250
300
350
400
450
n
1/f clk
Fig. 2.1 DFS block diagram and wave shapes
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International Journal of Engineering Trends and Technology (IJETT) –volume 4 issue 7 July 2013
BLOCKS OF DIGITAL FREQUENCY SYNTHESIZER
PHASE ACCUMULATOR
A clock with frequency f clk is the synthesizer’s only time reference. The phase accumulator’s output is a ramp value, as it
overflows to 0 periodically. For an N-bit accumulator, the frequency of the ramp is given by
A.
1.
f out  f clk 
frequency control word
2N
Every value at the output of the phase accumulator is converted to approximated sine amplitude by a phase-to-sine
amplitude converter.
2.
PHASE TO AMPLITUDE CONVERTER
The spectral purity of the DFS is estimated by the values stored in the sine table ROM. Hence can increase the resolution of
the ROM. But as ROM storage increases lower the speed, increased power consumption and greatly increased costs. By storing only
/2 radians of sine wave information compression can be achieved and to generate the ROM samples for the full range of 2  by
exploiting the quarter wave symmetry of the sine function. One of the approaches to the phase-to-sine amplitude mapping is the
CORDIC algorithm, which is an iterative computation method. But there is increased circuit complexity, cost and distortions that
will be generated, when the methods of memory compression are employed.
msb
2nd msb
2
P
j
k
Phase
Accumulator
k2
Complementor
k2
 / 2 sine
Look - up
m
Complementor
m 1
2
phase

2
0
n
Amp
0
2
2
1.5
1.5
1
1
0.5
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
-1.5
-2
2nd msb
-2
50
100
150
1
0
200
250
300
350
400
n
50
100
150
200
250
300
350
400
1
msb
0
Fig. 2.2 Detailed diagram of DFS
B. EXPLOITATION OF SINE FUNCTION SYMMETRY
Technique to store only  / 2 radians of sine information and to generate the sine look-up table samples for the full range
of 2 quarter-wave symmetry of the sine function is used. The decrease in the look-up table capacity is paid for by the additional
logic necessary to generate the complements of the accumulator and the look-up table output, as shown in Fig. 2.2. The two Most
Significant Bit (MSB) s are used to decode the quadrant, remaining k-2 bits are used to address a one-quadrant sine look-up table.
MSB determines whether the amplitude is increasing or decreasing. The accumulator output is used “as is” for the first and the third
quadrants. The bits must be complemented so that the slope of the saw-tooth is inverted for the second and fourth quadrant. The
sampled waveform at the output of the look-up table is a full wave rectified version of the desired sine wave as shown in Fig. 2.2.
The final output sine wave is then generated by multiplying the full wave rectified version by -1, when the phase is between  and
2 .
C. CONCEPT OF THE ARCHITECTURE USED
Instead of a ROM LUT, a hardware-optimized phase-to-sine amplitude converter used to approximate the first quadrant of
the sine function with eight equal-length piecewise linear segments [3]. The main goal is to maintain low system complexity and
reduce power consumption and chip area requirements. The second aim is to achieve a specified spectral purity, where spectral
purity is defined as the ratio of the power in the desired frequency to the power in the greatest harmonic, across tuning bandwidth of
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) –volume 4 issue 7 July 2013
the synthesizer. Spectral purity is an essential design parameter in communication systems for synthesizer, ensuring that undesired
in-band signals remain below a given threshold and are not detected.
In order to achieve the first goal, approximation of a sinusoid as a series of eight equal-length piecewise continuous linear
segments s i is done, where
i
s i ( x )  mi  ( x  )  y i ,
8
i  [0,7]
is the slope of each segment and is carefully selected to eliminate the requirement for multiplication by representing each one as a
sum of at the most two powers of two. Precision of slope representation, i.e., the difference between the smallest and the largest
powers of two used can restrict, by putting an upper bound on the adder’s width. To reduce the control system circuitry costs equal
length segments are selected. In order to obtain desired spectral purity, different sets of mi and y i coefficients are evaluated and the
best one meeting the requirements is selected.
D. DESCRIPTION OF THE ARCHITECTURE
Complete DFS architecture is shown in Fig. 2.3. The coefficients are given in Table 2.1. The phase to sine amplitude
converter [4] block includes a 1’s complement to exploit quarter wave symmetry. This architecture is significantly less complex. It
does not include a ROM, no multipliers or squaring circuits are required. To simplify the control circuitry equal length segments are
used. Only three integers need to be added and multiplexers.
The phase accumulator is of 20 bits wide, truncated to 12 bits. The two MSBs are used for quadrant symmetry. Segment is
identified by the next three bits. The remaining seven bits identify different sub-angles. The two upper multiplexers shift these
remaining seven bits according to the slopes mi , listed in Table 2.1.
Table 2.1: Linear segment coefficients
i
mi
0 1+½
1 1+½
2 1+¼
3 1 + 1/8
4
1
5 ½+¼
6
½
7
1/8
yI
2/1024
191/1024
384/1024
552/1024
697/1024
819/1024
909/1024
971/1024
The notation {>>n} shown in Fig.2.3 signifies a right shift by n bits, means division by 2 n. The lower multiplexer selects
the appropriate y i approximation listed in the table. The output from the multiplexers is of 13 bits wide, to account for the whole
dynamic range of possible values. The three-operand adder sums the multiplexer outputs together and rounds the result to 7 bits.
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International Journal of Engineering Trends and Technology (IJETT) –volume 4 issue 7 July 2013
MSB1
MSB2
P 16
Phase
12 10
accumulato
16
̂
3 MSBs
1s
comp.
7
m
u
x
1
7
>>1
0
13
7
>>1
7
m
u
x
2
>>2
0
7
>>3
y0
y1
y2
y3
y4
y5
y6
y7
m
u
x
3
13
15
Format
converte
r
15
13
Figure 2.3 DFS architecture
III.
RESULTS
DFS architecture can be used to perform modulation & demodulation in communication system [5]. To verify the
architecture, the design was coded in VHDL. Fig. 3.1 shows the simulation result of DFS architecture for offset value 111111.
Fig. 3.1 Simulation result of DFS architecture
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International Journal of Engineering Trends and Technology (IJETT) –volume 4 issue 7 July 2013
IV.
ADVANTAGES
The main advantage of this architecture is that it does not depend upon the extensive use of ROM, as is normally the case
with other commonly available architectures. Hence, it fits into a very small area on the chip. Fine frequency and phase resolution
can be achieved using DFS.
V.
CONCLUSION
Architecture for digital frequency synthesizer is presented. DFS architecture can be used to perform modulation &
demodulation in communication system [5]. DFS has the ability to tune with extremely fine frequency and phase resolution and to
rapidly hop between the frequencies. The DFS has less complex architecture compared to CORDIC.
REFERENCES
[1]
Deprettere, E., Dewilde, P., and Udo, R., "Pipelined CORDIC Architecture for Fast VLSI Filtering and Array Processing," Proc. ICASSP'84, 1984, pp.
41.A.6.1-41.A.6.4.
[2]
J. M. P Langlois and D. Al-Khalili, “Hardware Optimized Direct Digital Frequency Synthesizer Architecture with 60 dB Spectral Purity” Proc.
IEEE International Symposium On Circuits and Systems, May 2002.
Charoensak, C., Abeysekera, S. S.: FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulation,
SOC Conference Proceedings, IEEE International Volume, pp. 137-138, 12-15 Sept. (2004).
[3]
[4]
[5]
K. R. Nataraj , Dr S. Ramachandran and Dr B. S. Nagabushan “Development of Algorithm, Architecture and FPGA Implementation of Demodulator for
Processing Satellite Data Communication” IJCSNS International Journal of Computer Science and Network Security, VOL.9 No.7, July 2009.
Anupama B R, M C Chandrashekhar, Dr. M Z Kurian, “Implementation of a GMSK Communication System on FPGA Using Distributed Algorithm”,
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering ,Vol. 2, Issue 6, June 2013.
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