IBM T. J. Watson Research Center
Device Technology and the
Future of Computing
Thomas N. Theis,
Director, Physical Sciences, IBM Research
Frontiers of Extreme Computing, October 25 2005
© 2005 IBM Corporation
IBM Research
My view…
 Moore’s Law is an observation about the number of devices that can
be placed on a chip at a given time.
 There is no fundamental physical reason why device densities
cannot follow the Moore’s Law trend for many more decades.
– Lithographic dimensions will eventually be shrunk to atomic scale and
lithographic processes can seamlessly combine with synthesis.
– New devices can circumvent the scaling limits of FETs.
Frontiers of Extreme Computing, October 25, 2005
2
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IBM Research
Topics
 Making devices smaller is not the problem!
 Silicon CMOS Technology will be extended for at least a decade
 The “ultimate” FET may not be made of silicon
 Non-silicon memory devices will scale to very small dimensions.
 New devices may enable adiabatic computing and reversible logic.
Frontiers of Extreme Computing, October 25, 2005
3
© 2005 IBM Corporation
IBM Research
Minimum machined dimension (microns)
A Brief History of Miniaturization
1000
100
Moore’s Law (1965)
10
1
90 nm Manufacturing
(2004)
193 nm immersion
EUV
0.1
0.01
industry roadmap
2004 commercial
niche lithographies
0.001
2004 best lab practice
0.0001
1800
1850
Frontiers of Extreme Computing, October 25, 2005
1900
1950
2000
2050
4
2100
© 2005 IBM Corporation
IBM Research
The silicon transistor in manufacturing …
35 nm
Gate Length
90 nm technology generation
Frontiers of Extreme Computing, October 25, 2005
5
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IBM Research
… and in the lab.
Gate
Source
TSi=7nm
Lgate=6nm
Frontiers of Extreme Computing, October 25, 2005
Drain
B. Doris et al., IEDM , 2002
6
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Power Density (log scale)
Still, we are approaching some limits.
1.0
1.0
0.1
0.1
Gate Length (microns)
Frontiers of Extreme Computing, October 25, 2005
0.01
0.01
7
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IBM Research
Active Power Can Better Managed!
Thermal Mapping of Fully Operating IBM Microprocessor
(2 GHz, 1.4 V) in a System Environment
Filmstrip during bootup:
Thermal images
during bootup:
max
min
H. Hamann (IBM), ISSCC 2005
Frontiers of Extreme Computing, October 25, 2005
IBM
Confidential
0.4 s per frame
Total ~ 80s
8
© 2005 IBM Corporation
IBM Research
Better Information for Layout and High-level Design
Access to data cache
Access to memory controller
Power map
Temperatures
max
data
cache
data
cache
memory
controller
memory
controller
min
H. Hamann (IBM), ISSCC 2005
Frontiers of Extreme Computing, October 25, 2005
9
© 2005 IBM Corporation
IBM Research
The Problem with Passive Power Dissipation:
You Can’t Scale Atoms!
Gate
Source
Drain
1.2 nm oxynitride
Field effect transistor
 Direct tunneling through the gate insulator will be the dominant cause of
static power dissipation.
 Single atom defects can cause local leakage currents 10 – 100x higher
than the average current, impacting reliability and generating unwanted
variation between devices.
Frontiers of Extreme Computing, October 25, 2005
10
© 2005 IBM Corporation
IBM Research
The Work-Around: High-k Insulator / Metal Gate Stack
High-k/Metal Gate Stack
90nm
SiON
10S
Tox=11A
Metal gate electrode
High-k material
Oxide interlayer
90nm Gate Dielectric:
Tinv = 19A
ToxGL = 11A
Frontiers of Extreme Computing, October 25, 2005
High-k/Metal Gate Stack:
Tinv = 14.5A
ToxGL = 16A
11
© 2005 IBM Corporation
Relative Gain in Performance
IBM Research
Improving Performance
 No longer possible by scaling alone
– New Device Structures
100
80
60
Innov ation
Scaling
40
20
0
0.18um
– New Device Design point
– New Materials
1
H
Device Elements:
2
He
boron
5
Beyond 2005
carbon
6
C
silicon
14
Si
scandium titanium vanadium chromium
22
22
23
21
24
Ti
Ti
V
Cr
Sc
strontium
38
Sr
yttrium
39
Y
barium
56
Ba
barium
71
Lu
lanthanium
57
La
zirconium niobium molybdenum
42
40
41
Mo
Zr
Nb
tantalum Tungsten
tungsten Rhenium
hafnium Tantalum
73
74
73
74
75
72
Ta
W
Ta
W
Re
Hf
cerium
58
Ce
Praeseo
dymium
59
Pr
neodymium
60
Nd
Frontiers of Extreme Computing, October 25, 2005
cobalt
27
Co
65nm
helium
B
calcium
20
Ca
90nm
Before the 90’s
Since the 90’s
hydrogen
0.13um
Technology Generation
nickel
28
Ni
zinc
30
Zn
nitrogen
oxygen
fluorine
7
8
O
F
N
9
phosphorus
15
P
germanium
arsenic
32
Ge
33
Bromine
35
35
Br
Br
As
Ruthenium rhodium palladium
43
45
45
Ru
Rh
Pd
iridium
77
Ir
bismuth
83
Bi
platinum
78
Pt
samarium europlum gadollinium terbium dysprosium holmium
64
63
65
66
62
67
Gd
Eu
Tb
Dy
Sm
Ho
erbium
68
Er
thullium ytterbium
69
70
Tm
Yb
12
© 2005 IBM Corporation
IBM Research
Innovation Will Continue:
Transistor Roadmap Options
2004 2007 2010 2013 2016 2020
Physical Gate
Ultrathin SOI
doped channel
raised source/drain
37 nm 25 nm 18 nm 13 nm 9 nm
High k gate dielectric
6 nm
FinFET
Double-Gate CMOS
Strained Si, Ge, SiGe
Gate
halo
buried oxide
depletion layer
buried oxide
isolation
Silicon Substrate
isolation
Silicon Substrate
Source
Drain
In general, growing power dissipation and increasing process variability will be addressed by
introduction of new materials and device structures, and by design innovations in circuits
and system architecture.
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Memory may be easier to shrink than logic.
SL
m+1
SL
m
SL
m-1
WL
n-1
WL
n
WL
n+1
 Everyone is looking for a dense (cheap) cross-point memory.
 It is relatively easy to identify materials that show bistable hysteretic
behavior (easily distinguishable, stable on/off states).
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Technology Champions
(Companies)
Relative Maturity of Nonvolatile Memory Technologies
20
18
16
14
12
10
8
6
4
2
0
Product
Sampling
Frontiers of Extreme Computing, October 25, 2005
Development
Single Cell
Demo
Charts, No
Parts
15
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IBM Research
16Mbit Magnetic Random Access Memory (MRAM) Demo
Pads / peripheral circuits
Cross-section:
Chip image:
• 4 active bits / block
• Good power supply
distribution
4 active 128Kb blocks
• Write currents
trimmed by block
140
120
100
MTJ
8Mb
unit
8Mb
unit
80
Redundancy control &
Write current trimming
60
40
20
Pads / peripheral circuits
0
Materials-2000
Advances
-1500 -1000 -500
0
500
2.40
140
1995
120
400
2005
350
TMR(%)
(%)
TMR
2.00
80
1.80
1.60
60
1.40
40
1.20
20
0
-150
-200
290K
300
100
Resistance (a.u.)
MR(%)
(%)
TMR
2.20
1000
-100
0
50
0
100
FieldField
(Oe)(Oe)
Field (Oe)
150
50
a258-03 J4
1.00
-50
200
100
Prior to Anneal
Anneal 360°C
-100
250
Frontiers of Extreme Computing, October 25, 2005
150
100
200
0
-150
-100
-50
0
50
Field
Field(Oe)
(Oe)
16
100
150
© 2005 IBM Corporation
IBM Research
Post-Silicon CMOS: The Quest for the Ultimate FET
W
200n
m
Self-Aligned Carbon Nanotube FET:
Extension Contacts Based on
Charge-Transfer Chemical Doping
Frontiers of Extreme Computing, October 25, 2005
Vertical Transistor
Based on Semiconductor Nanowires
17
© 2005 IBM Corporation
IBM Research
Intrinsic Performance of Cabon Nanotube FETs
Output Characteristics
Simple back-gated CNTFET
20
Vds = -1.6 V
Pd
|Id| [A]
Pd
15
-1.2 V
10
-0.8 V
-0.4 V
5
nanotube
0V
0
Subthreshold Characteristics
-1.2
0.4 V
-0.8
Vds [V]
-0.4
0.0
Temperature dependence
1
10
0
12
-1
10
-2
gm[S]
|Id| [A]
10
Vds
10
-0.7 V
-0.5 V
-0.3 V
-0.1 V
-3
10
-4
10
-5
10
-2
-1
0
Vgs [V]
1
Frontiers of Extreme Computing, October 25, 2005
2
8
4
0
-2.0
90 K
300 K
-1.0
0.0
1.0
Vgs [V]
Yu-Ming Lin et al. (IBM), EDL 2005
18
© 2005 IBM Corporation
IBM Research
Intrinsic Switching Speed of CNFETs
fT 
Cut-off Frequency
gm
2 Cg
Cg : gate capacitance
Lin et al.
(IBM)
Javey et al.
(Stanford)
Seidel et al.
(Infineon)
~ 1.8 nm
~ 1.7 nm
~ 1.1 nm
10-nm SiO2
8-nm HfO2
12-nm SiO2
Maximum gm
12.5 S
27 S
3.5 S
Cg/L
38 pF/m
120 pF/m
32 pF/m
fT @ Lg = 65 nm
800 GHz
550 GHz
260 GHz
Diameter
Gate Dielectric
Yu-Ming Lin et al. (IBM), EDL 2005
Frontiers of Extreme Computing, October 25, 2005
19
© 2005 IBM Corporation
IBM Research
Steep Sub-threshold Slopes for Low-Voltage Operation
Bulk switching
10
10
Dual-Gate
CNTFET
Id (A)
10
10
10
10
10
10
-1
S=63 mV/dec
-2
-3
-4
-5
-6
-7
Vgs-Si = -2.5 V
-8
-1.2
-0.8
-0.4
0.0
Vg-Al (V)
Sub-thermal S through band-to-band tunneling
Frontiers of Extreme Computing, October 25, 2005
20
© 2005 IBM Corporation
IBM Research
Adiabatic Computing and Reversible Logic
Can we operate FETs at or below the “kT” limit?
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Adiabatic Computing
How much energy must be dissipated to charge a capacitor?
Trade-off depends
strongly on
device physics!
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Frontiers of Extreme Computing, October 25, 2005
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IBM Research
Applications of Adiabatic Charging
 Drive specific capacitances which cause large dissipation.
– Power supplies
– Energy conserving data bus drivers
 Broadly implement reversible logic.
– Retractile cascade, reversible pipelines
– High-efficiency regenerative power supply (very complex)
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Reversible Logic: Implementation with FETs
 It is conceptually possible to build general purpose reversible computers
with energy dissipation per operation going asymptotically to zero as
frequency goes to zero.
 But, frequency must be reduced by about 1/1000 to achieve benefits with
respect to conventional approaches to CMOS logic.
Dissipation of 4 bit ripple counter (D. J. Frank, 1995)
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Recent Optimized Power vs Frequency Assessment
DJ Frank, MIT Workshop on Reversible Computation, February 14, 2005
Frontiers of Extreme Computing, October 25, 2005
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IBM Research
Qualitative Overall Comparison
Conventional CMOS
with fixed supply
TSPC (a fast non-energy
recovering dynamic CMOS
logic family)
Scaled static
CMOS (estimate)
2N-2N2P (an energy-recovering logic family)
Highly reversible
DJ Frank, MIT Workshop on Reversible Computation, February 14, 2005
Frontiers of Extreme Computing, October 25, 2005
27
© 2005 IBM Corporation
IBM Research
Are there devices that are better suited
than FETs for the implementation of
reversible logic?
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation
IBM Research
Beyond Charged-Based Logic?
 Spins
 Nanomechanics
Magnetic Field
EF
e-
Ga As
q ua ntum well
CoFe
MgO
Luminescence
AlGaAs
p + -GaAs
substrate
AlGaAs
Collec tor
A
VT
IC
 Photons
Frontiers of Extreme Computing, October 25, 2005
 DNA Chemistry
29
© 2005 IBM Corporation
IBM Research
Nanoelectronics Research Initiative (NRI)

AMD, Freescale, Micron, TI, IBM, Intel
 Joint Industry funding of University Research

Leveraging existing NSF and new (joint NSF/NRI) funding

Promoting both
– Invention / Discovery (distributed research, “let many flowers bloom”)
– Proof of Concept (focused university consortia with outstanding facilities)

“Extend the historical cost/function reduction, along with increased
performance and density … orders of magnitude beyond the limits of CMOS”
– Non-charge-based logic
– Non-equilibrium systems
– Novel energy transfer mechanisms for device interconnection
– Phonon engineering
– Directed self-assembly of complex structures
Frontiers of Extreme Computing, October 25, 2005
30
© 2005 IBM Corporation
IBM Research
Conclusions
 Silicon CMOS logic will be extended at least another 10 years.
– New materials and transistor structures
– Cooperative circuit and device technology co-design
 The “ultimate FET” may not contain silicon.
 New, dense, cheap memory devices are on the way.
 Reversible logic is possible, but may be practical only with
devices that are “beyond the FET”.
 The search for logic devices “beyond the FET” is underway,
(but there should be more focus on devices suitable for
adiabatic computation and reversible logic)
Frontiers of Extreme Computing, October 25, 2005
31
© 2005 IBM Corporation
IBM Research
Thanks!
Frontiers of Extreme Computing, October 25, 2005
32
© 2005 IBM Corporation
IBM Research
Non-Si FET
 The potential of carbon nanotubes (CNT)
– Metallic & semiconducting nanotubes: interconnects (up to ~109A/cm2)
& switches.
– 1D transport (low elastic and inelastic scattering low energies, ballistic
or quasi-ballistic transport, fT≤1THz.
– Low energy dissipation (power density problem, no electromigration)
– Good control of electrostatics (“thin body devices”, no mobility
degradation).
– Inert (no dangling bonds to passivate, wide choice of gate insulators –
high k materials)
– Direct band-gap materials (integrate electronic & opto-electronic
devices using the same material).
Frontiers of Extreme Computing, October 25, 2005
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© 2005 IBM Corporation