ASIC Design Interview Questions
Summarized by Chong Yao
----------------No commerical use is allowed-------------1. Why Reset?
A Reset is required to initialize a hardware design for system operation and to force an ASIC into a
known state for simulation.
A reset simply changes the state of the device/design/ASIC to a user/designer defined state. There are two
types of reset, what are they? As you can guess them, they are Synchronous reset and Asynchronous reset.
Synchronous Reset
A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock.
The reset signal is applied as is any other input to the state machine.
Advantages:



The advantage to this type of topology is that the reset presented to all functional flip-flops is
fully synchronous to the clock and will always meet the reset recovery time.
Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with
the logic generating the d-input. But in such a case, the combinational logic gate count grows, so
the overall gate count savings may not be that significant.
Synchronous resets provide some filtering for the reset signal such that it is not effected by
glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some
types of designs where the reset is generated by a set of internal conditions. As the clock will
filter the logic equation glitches between clock edges.
Disadvantages:




The problem in this topology is with reset assertion. If the reset signal is not long enough to be
captured at active clock edge (or the clock may be slow to capture the reset signal), it will result
in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset
pulse is wide enough to be present during the active clock edge.
Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the
reset signal from any other data signal. So proper care has to be taken with logic synthesis, else
the reset signal may take the fastest path to the flip-flop input there by making worst case timing
hard to meet.
In some power saving designs the clocked is gated. In such designed only asynchronous reset will
work.
Faster designs that are demanding low data path timing, cannot afford to have extra gates and
additional net delays in the data path due to logic inserted to handle synchronous resets.
Asynchronous Reset
An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the
clock signal is. This is considered as high priority signal and system reset happens as soon as the reset
assertion is detected.
Advantages:



High speeds can be achieved, as the data path is independent of reset signal.
Another advantage favoring asynchronous resets is that the circuit can be reset with or without a
clock present.
As in synchronous reset, no work around is required for logic synthesis.
Disadvantages:


The problem with this type of reset occurs at logic de-assertion rather than at assertion like in
synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or
near the active clock edge of a flip-flop, the output of the flip-flop could go metastable.
Spurious resets can happen due to reset signal glitches.
Conclusion
Both types of resets have positives and negatives and none of them assure fail-proof design. So there is
something called "Asynchronous assertion and Synchronous de-assertion" reset which can be used for
best results. (which will be discussed in next post)
2.Non-blocking/blocking assignment
The blocking assignment statement (= operator) acts much like in traditional programming languages.
The whole statement is done before control passes on to the next statement.
The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the
left-hand sides at the end of the time unit.
For several assignment, if they were the blocking assignment, they would be evaluated and assigned in
sequence; if they were the non-blocking assignment, they would be evaluate d simultaneously and
assigned at the same time, therefore, the delays overlap.
Moreover, the blocking assignment are usually used in the continuous assignment (combinational circuit)
"assign", and non-blocking assignment are typically utilized in the procedure assignment (sequential
circuit) "initial, always, task, function".
2.1) How re blocking and non-blocking statements executed?
In the blocking statement, the RHS will be evaluated and the LHS will be then updated without any
interruptions.
In the non-blocking statement, RHS will be evaluated at the beginning of the time step. Then the LHS
will be updated at the end of the time step. Within the whole period, the other process can run in parallel.
2.2) 1: Active Evens ( blocking statements, RHS of NBA, continuous assignement, $display)
2: Inactive Events ( #1 delays, etc)
3: Non-Blocking Assign updates ( LHS of non-blocking statements )
4: Monitor Events ($strobe, $monitor, etc )
2.3) Encounter Files
The Design Import form is used to load the
Verilog netlist (.syn.v);
physical libraries (.LEF);
process technology libraries;
timing libraries (.tlf);
timing constraints.
2.4) Encounter
extracted RC
Pre-CTS optimize to fix setup violation
CTS
Post-CTS optimize to fix hold violation
2.5) What files are required for PrimeTime to run?
PrimeTime needs four types of files before you can run it:
1. Netlist file: Verilog, VHDL, EDIF
2. Delay file: SPEF(standard parasitic format, it's from STARRC or place&route tool), SPF,
SDF(standard delay format)
3. Library file: DB ( From library vendors)
4. Constrains file: Synopsys Design Constraints(SDC) include 3 min requirement, clock, input delay and
output delay.
2.6) In prime time, use best case and min lib to check hold violation. use worst case and max lib to check
setup violation
3. Setup/hold time
The setup time is the amount of time that an input signal (to the device) must be stable (unchanging)
before the clock ticks in order to avoid possible Metastability.
The hold time is the amount of time that an input signal (to a sequential device) must be stable
(unchanging) after the clock tick in order to avoid possible Metastability
setup equation
Tclk > Tc2q_L_max + Tlogic_max + Tsetup_C + Tskew + Tjitter
Tskew should be negative
hold equation
Tc2q_L_min + Tlogic_min > Thold_C + Tskew
Tskew is the positive skew
key things to note from above equations
a) Setup violation check
1. Vdd ↑ Id↑ Tlogic↓
2. Temperature ↓ Tlogic↓
3. Period ↑
4. Using faster DFF Tc2q↓
5. Tskew↓ by powerful driver, CTS (clock tree synthesis)
6. Pipeline/minimize number of logic levels Tlogic↓
7. Process
b) Hold time violation
1.Vdd↓ Tlogic↑
2. Temperature↑ Tlogic↑
3.Using slower DFF Tc2q↑
4. Tskew↑
5.Adding Inverter pairs, buffers, delay cells, Tlogic↑ , by CTS
4.Skew
Positive skew occurs when the launch register receives the clock earlier than the capture register. Positive
skew helps the setup violation.
Negative skew helps the hold time violation.
Here, tskew should be negative.
Here, Tskew is the positive skew.
b) PLL jitter (Tjitter ) is not used in hold time equation , since hold time violation is based on same clock
edge . (whereas setup time violation depends on 2 consecutive clock edges)
c) above equations have clock skew in pessimistic directions . U can play around with clock skews to get
extra margin by skewing them in favorable direction to decrease violation .
5.STA
1)
Timing constraints, as Synopsys Design Constraints(SDC), are how the designer tells the STA tool about
the timing behavior of the ASIC. The three minimum constraints are defining the clock, input delay, and
output delay. There are four types of timing paths are available. They are :




Input to Register (Sync),
Register to Register (Sync),
Register to Output (Sync) and
Input to Output(Async). Each path has a start and endpoint
When the clocks are defined, all Register to Register paths are assumed to be constrained in one clock
cycle. A path originates from either an Input port or a Register clock pin, while an end point is either an
Output port or a Register data pin. All start and end point must be timing constrained.
6. Verilog common questions
6.1)
(1)casez treats all z and ? as "Don't care". If expression is "zzzz", satisfied all the conditions, so the first
statement will be executed.
(2)casex treat all z or x or ? as "Don't care". if expression is "zzzz" or "xxxx", fist statement executed.
(3)case pass all z or x to the result as xxxx or zzzz.
(4) CASEZ should be used for case statements with wildcard don't cares, otherwise use of CASE is
required; CASEX should never be used.
This is because:
Don't cares are not allowed in the "case" statement. Therefore casex or casez are required. Casex will
automatically match any x or z with anything in the case statement. Casez will only match z -- x require
an absolute match
e.g
always @(select)
casez(select)
4'b???1: out = a;
4'b??1?: out = b;
4'b?1??: out = c;
endcase
/////////////simulation result//////////////
select = xxxx, out = xx;
select = zzzz, out = a;
select = xx1x, out = b;
///////////////////////////////////////////
if using casex
select = xxxx, out = a;
6.2)What is difference between Verilog full case and parallel case?
A "full" case statement is a case statement in which all possible case-expression binary patterns can be
matched to a case item or to a case default. If a case statement does not include a case default and if it is
possible to find a binary case expression that does not match any of the defined case items, the case
statement is not "full."
A "parallel" case statement is a case statement in which it is only possible to match a case expression to
one and only one case item. If it is possible to find a case expression that would match more than one case
item, the matching case items are called "overlapping" case items and the case statement is not "parallel."
6.3) How can I model a bi-directional net with assignments influencing both source and destination?
The assign statement constitutes a continuous assignment. The changes on the RHS of the statement
immediately reflect on the LHS net. However, any changes on the LHS don't get reflected on the RHS.
System Verilog has introduced a keyword alias, which can be used only on nets to have a two-way
assignment. For example, in the following code, any changes to the rhs is reflected to the lh s , and vice
versa.
module test ();
wire rhs,lhs;
alias lhs=rhs;
6.4) An AND gate and OR gate are given inputs X & 1 , what is expected output?
AND Gate output will be X;
OR Gate output will be 1
6.5) Tell something about modeling delays in verilog?
Verilog can model delay types within its specification for gates and buffers. Parameters that can be
modelled are T_rise, T_fall and T_turnoff. To add further detail, each of the three values can have
minimum, typical and maximum values
T_rise, t_fall and t_off
Delay modelling syntax follows a specific discipline;
gate_type #(t_rise, t_fall, t_off) gate_name (paramters);
When specifiying the delays it is not necessary to have all of the delay values specified. However, certain
rules are followed.
and #(3) gate1 (out1, in1, in2);
When only 1 delay is specified, the value is used to represent all of the delay types, i.e. in this example,
t_rise = t_fall = t_off = 3.
or #(2,3) gate2 (out2, in3, in4);
When two delays are specified, the first value represents the rise time, the second value represents the fall
time. Turn off time is presumed to be 0.
buf #(1,2,3) gate3 (out3, enable, in5);
When three delays are specified, the first value represents t_rise, the second value represents t_fall and the
last value the turn off time.
Min, typ and max values
The general syntax for min, typ and max delay modelling is;
gate_type #(t_rise_min:t_ris_typ:t_rise_max, t_fall_min:t_fall_typ:t_fall_max,
t_off_min:t_off_typ:t_off_max) gate_name (paramteters);
Similar rules apply for th especifying order as above. If only one t_rise value is specified then this value is
applied to min, typ and max. If specifying more than one number, then all 3 MUST be scpecified. It is
incorrect to specify two values as the compiler does not know which of the parameters the value
represents.
An example of specifying two delays;
and #(1:2:3, 4:5:6) gate1 (out1, in1, in2);
This shows all values necessary for rise and fall times and gives values for min, typ and max for both
delay types.
Another acceptable alternative would be;
or #(6:3:9, 5) gate2 (out2, in3, in4);
Here, 5 represents min, typ and max for the fall time.
N.B. T_off is only applicable to tri-state logic devices, it does not apply to primitive logic gates because
they cannot be turned off
6.6)Gray to binary
Dec Gray Binary
0 000 000
1 001 001
2 011 010
3 010 011
4 110 100
5 111 101
6 101 110
7 100 111
Gary to Binary: assign binary = { gray[2], (gray[1] ^ binary[2]),(gray[0] ^ binary[1]) }
Binary to Gray: assign gray = { binary[2], (binary[2] ^ binary [1]),( binary [1] ^ binary [0]) }
6.7) What is the difference between unary and logical operators?
Unary operators have only one operand, where as logical operators are of two operands.
6.8) What is the difference between transport delay and inertial delay?
Transport delay is the delay caused by the wires connecting the gates. Wire do delay the signal they carry,
this is due to the wire resistance, capacitance, and inductance. Simply transport delay is propagation delay
on a wire. It models the devices with infinite switching speed; input glitches propagate to the output. In
verilog transport delay is modeled as follows: a< = #5 b;
Inertial delay (inter-statement) is the time taken by a gate to change its output, which is the gate delay. No
input glitches propagated. In verilog inertial delay is modeled as follows: assign #5 a = b;
Answer:
#5 a=b, Inertial delay (inter-statement), gate delay. NO glitches. Wait 5 time units before doing the action
for "a=b".
a<= #5 b; Transport delay.(Intra-statement) Propagation delay on a wire. Glitches passing. The value of b
is calculated and stored in an internal temp register. After 5 time units, assign this stored value to a.
6.9) Different Coding fashion
Write code for 2:1 MUX using different coding methods?
Use assign statement:
7 module mux_using_assign(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //-----------Input Ports--------------14 input din_0, din_1, sel ;
15 //-----------Output Ports--------------16 output mux_out;
17 //------------Internal Variables-------18 wire mux_out;
19 //-------------Code Start----------------20 assign mux_out = (sel) ? din_1 : din_0;
21
22 endmodule //End Of Module mux
Use if statement
7 module mux_using_if(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //-----------Input Ports---------------
14 input din_0, din_1, sel ;
15 //-----------Output Ports--------------16 output mux_out;
17 //------------Internal Variables-------18 reg mux_out;
19 //-------------Code Starts Here--------20 always @ (sel or din_0 or din_1)
21 begin : MUX
22 if (sel == 1'b0) begin
23 mux_out = din_0;
24 end else begin
25 mux_out = din_1 ;
26 end
27 end
28
29 endmodule //End Of Module mux
Use Case statement
7 module mux_using_case(
8 din_0 , // Mux first input
9 din_1 , // Mux Second input
10 sel , // Select input
11 mux_out // Mux output
12 );
13 //-----------Input Ports--------------14 input din_0, din_1, sel ;
15 //-----------Output Ports--------------16 output mux_out;
17 //------------Internal Variables-------18 reg mux_out;
19 //-------------Code Starts Here--------20 always @ (sel or din_0 or din_1)
21 begin : MUX
22 case(sel )
23 1'b0 : mux_out = din_0;
24 1'b1 : mux_out = din_1;
25 endcase
26 end
27
28 endmodule //End Of Module mux
6.10) What's the difference between === and ==?
"a===b" a equal to b, including x and z (Case equality)
"a==b" a equal to b, result may be unknown (logical equality)
The equality operators ( = = , ! = ) will yield an x if either operand has x or z in its bits. Whereas the case
equality operators ( = = = , ! = = ) compare both operands bit by bit and compare all bits, including x and
z.
6.11) Write code for a parallel encoder and a priority encoder?
module pri_encoder_using_assign (
8 binary_out , // 4 bit binary output
9 encoder_in , // 16-bit input
10 enable // Enable for the encoder
11 );
12
13 output [3:0] binary_out ;
14 input enable ;
15 input [15:0] encoder_in ;
16
17 wire [3:0] binary_out ;
18
19 assign binary_out = ( ! enable) ? 0 : (
20 (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
21 (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
22 (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
23 (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
24 (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
25 (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
26 (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
27 (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
28 (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
29 (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
30 (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
31 (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
32 (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
33 (encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
34 (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
35
36 endmodule
module encoder_using_case(
8 binary_out , // 4 bit binary Output
9 encoder_in , // 16-bit Input
10 enable // Enable for the encoder
11 );
12 output [3:0] binary_out ;
13 input enable ;
14 input [15:0] encoder_in ;
15
16 reg [3:0] binary_out ;
17
18 always @ (enable or encoder_in)
19 begin
20 binary_out = 0;
21 if (enable) begin
22 case (encoder_in)
23 16'h0002 : binary_out = 1;
24 16'h0004 : binary_out = 2;
25 16'h0008 : binary_out = 3;
26 16'h0010 : binary_out = 4;
27 16'h0020 : binary_out = 5;
28 16'h0040 : binary_out = 6;
29 16'h0080 : binary_out = 7;
30 16'h0100 : binary_out = 8;
31 16'h0200 : binary_out = 9;
32 16'h0400 : binary_out = 10;
33 16'h0800 : binary_out = 11;
34 16'h1000 : binary_out = 12;
35 16'h2000 : binary_out = 13;
36 16'h4000 : binary_out = 14;
37 16'h8000 : binary_out = 15;
38 endcase
39 end
40 end
41
42 endmodule
6.12) What is the difference between
I) c = select? a:b;
II) if(select) c=a; else c=b;
Answer:
The ? merges answers if the condition is "x", so for instance if select = 1'bx, a=2'b10 and b=2'b11,
you'd get c=2'b1x. On the other hand, "if" treats Xs and Zs as FALSE, so you'd always get c=b.
6.13) what's difference between $monitor and $display?
$monitor: display every time one of its parameters changes, in Postponed region.
$display : display once every time they are executed, in Active region.
$strobe: display only at the end of the current simulation time, in Postponed region, usually used for
non-blocking assignment.
6.14) What's the differenece between wire and reg data type?
Wire is a net data type, represents connections between hardware elements. It's default value is z.
Reg is a register data type, which represent data storage elements. Registers retain value until another
value is placed onto them. It's default value is x.
6.15) What is defparam used for?
Defparam is used to pass a new set of parameters during instantiation
1 module secret_number;
2 parameter my_secret = 0;
3
4 initial begin
5 $display("My secret number is %d", my_secret);
6 end
7
8 endmodule
module defparam_example();
secret_number U0();
secret_number U1();
defparam U0.my_secret = 11;
defparam U1.my_secret = 22;
endmodule
6.16) What is the difference between a latch and a flip lop.
Latch:
I) level-sensitive "sequential" element. The output captures the input when the clock signal is high, so as
long as the clock is logic 1, the output can change if the input also changes.
II) faster than Flip-flop.
III) it takes less gates to implemented ( less area).
IV) But it's sensitive to glitches on enable pin. It also can be clocked or clock less.
Flip-flop
I)edge sensitive "sequential" element.
II)Flip flop will store the input only when there is a rising or falling edge of the clock.
III)FF is immune to glitches.
IV)D-FF is built from two latches. They are in master slave configuration.
7) What is the difference between a task and a function in verilog?
Function
Timing-Control statements
No, shall execute in zero time
Cannot call tasks, can call
Call function or tasks
functions
at least 1 input type argument and
input type argument
shall not have an output or inout
type argument
return value
return a single value
Task
Yes
Can call both tasks and functions
can have 0 or more arguments of
any type
shall not return a value
8) What happens if there is connecting wires width mismatch?
For examples:
RHS[7:0] = LHS[15:0]
The end result is LHS[7:0] = RHS[7:0];
The assignments starts from LSBs of the signals, and ends at the MSB of smaller width signal.
9) What are different options that can be used with $display statement in Verilog?
%b - binary
%c - ASCII character
%d - Decimal
%h - Hexadecimal
%m - Hierarchical name
%o - Octal
%s - Steing
%t - Time
%v - Net signal strength
10) A Moore state machine is more
efficient than a Mealy state machine Because of Moore state machine has synchronous outputs
– no glitches
– one cycle “delay”
– full cycle of stable output
And Mealy machine has asynchronous outputs
– if input glitches, so does output
– output immediately available
– output may not be stable long
enough to be useful -> If output of Mealy FSM
goes through combinational logic before being
registered, the CL might delay the signal and it could
be missed by the clock edge.
11) What are different types of timing verifications?
Dynamic timing:
a. The design is simulated in full timing mode.
b. Not all possibilities tested as it is dependent on the input test vectors.
c. Simulations in full timing mode are slow and require a lot of memory.
d. Best method to check asynchronous interfaces or interfaces between different timing domains.
Static timing:
a. The delays over all paths are added up.
b. All possibilities, including false paths, verified without the need for test vectors.
c. Much faster than simulations, hours as opposed to days.
d. Not good with asynchronous interfaces or interfaces between different timing domains.
12) How do you implement the bi-directional ports in Verilog HDL?
module bidirec (oe, clk, inp, outp, bidir);
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule
13) Difference between inter statement and intra statement delay?
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
14) Suggest some ways to increase clock frequency?
1)Check critical path and optimize it.
2) Add more timing constraints (over constrain).
3)pipeline the architecture to the max possible extent keeping in mind latency req's.
15) What is the difference between LVS and DRC?
The layout must be drawn according to certain strict design rules. DRC helps in layout of the designs by
checking if the layout is abide by those rules.
After the layout is complete we extract the netlist. LVS compares the netlist extracted from the layout
with the schematic to ensure that the layout is an identical match to the cell schematic.
16) What is DFT ?
DFT means design for testability. 'Design for Test or Testability' - a methodology that ensures a design
works properly after manufacturing, which later facilitates the failure analysis and false product/piece
detection
Other than the functional logic, you need to add some DFT logic in your design. This will help you in
testing the chip for manufacturing defects after it come from fab. Scan, MBIST, LBIST, IDDQ testing etc
are all part of this. (this is a hot field and with lots of opportunities)
16.1) Contamination delay is also called tmin and Propagation delay is also called tmax in many data
sheets.
16.2) When there are multiple non-blocking assignments made to the same reg variable in a sequential
always block, then the last assignment is picked up for logic synthesis. For example
always @ (posedge clk) begin
out <= in1^in2;
out <= in1 &in2;
out <= in1|in2;
17) Dynamic vs Static Timing Analysis
Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not
timing! Timing analysis can be static or dynamic. Dynamic timing analysis verifies functionality of the
design by applying input vectors and checking for correct output vectors whereas Static Timing Analysis
checks static delay requirements of the circuit without any input or output vectors.
Dynamic timing analysis has to be accomplished and functionality of the design must be cleared before
the design is subjected to Static Timing Analysis (STA). Dynamic Timing Analysis (DTA) and Static
Timing Analysis (STA) are not alternatives to each other. Quality of the Dynamic Timing Analysis (DTA)
increases with the increase of input test vectors. Increased test vectors increase simulation time. Dynamic
timing analysis can be used for synchronous as well as asynchronous designs. Static Timing Analysis
(STA) can’t run on asynchronous deigns and hence Dynamic Timing Analysis (DTA) is the best way to
analyze asynchronous designs. Dynamic Timing Analysis (DTA) is also best suitable for designs having
clocks crossing multiple domains.
Example of Dynamic Timing Analysis(DTA) tool is Modelsim (from mentor Graphics), VCS (from
Synopsys). DTA is also carried out on post layout netlist to verify that functionality of the design has not
changed. Test vectors remain same for both
17.1) Advantages of STA:
 All timing paths are considered for the timing analysis. This is not the case in simulation.
 Analysis times are relatively short when compared with event and circuit simulation.
 Timing can be analyzed for worst case, best case simultaneously. This type of analysis is not
possible in dynamic timing analysis.
 Static Timing Analysis (STA) works with timing models. STA has more pessimism and thus
gives maximum delay of the design. DTA performs full timing simulation. The problem
associated with DTA is the computational complexity involved in finding the input patterns
(vectors) that produce maximum delay at the output and hence it is slow.
17.2) Disadvantages of STA:
 All paths in the design may not run always in worst case delay. Hence the analysis is pessimistic.
 Clock related all information has to be fed to the design in the form of constraints.
 Inconsistency or incorrectness or under constraining of these constraints may lead to disastrous
timing analysis.
 STA does not check for logical correctness of the design.
 STA is not suitable for asynchronous circuits.
18. FPGA vs ASIC
FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable
logic components called "logic blocks", and programmable interconnects. Logic blocks can be
programmed to perform the function of basic logic gates such as AND, and XOR, or more complex
combinational functions such as decoders or mathematical functions. For complete details click here.
ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed for a particular
use, rather than intended for general-purpose use. Processors, RAM, ROM, etc are examples of ASICs.
Speed
ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can be
optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have high speed
clocks.
FPGA is difficult to route.
Cost
FPGAs are cost effective for small applications. But when it comes to complex and large volume designs
(like 32-bit processors) ASIC products are cheaper.
Size/Area
FPGA are contains lots of LUTs, and routing channels which are connected via bit streams(program). As
they are made for general purpose and because of re-usability. They are in-general larger designs than
corresponding ASIC design. For example, LUT gives you both registered and non-register output, but if
we require only non-registered output, then it's a waste of having a extra circuitry. In this way ASIC will
be smaller in size.
Power
FPGA designs consume more power than ASIC designs. As explained above the unwanted circuitry
results wastage of power. FPGA wont allow us to have better power optimization. When it comes to
ASIC designs we can optimize them to the fullest.
Time to Market
FPGA designs will consume less time, as the design cycle is small when compared to that of ASIC
designs. No need of layouts, masks or other back-end processes. It's very simple: Specifications -- HDL +
simulations -- Synthesis -- Place and Route (along with static-analysis) -- Dump code onto FPGA and
Verify. When it comes to ASIC we have to do floor planning and also advanced verification. The FPGA
design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis,
and mask / re-spin stages of the project since the design logic is already synthesized to be placed onto an
already verified, characterized FPGA device.
Type of Design
ASIC can have mixed-signal designs, or only analog designs. But it is not possible to design them using
FPGA chips.
19. What is the difference between cycle and event based Verilog simulators ?


Cycle based Simulator :Cycle simulation is a technique (i.e. an algorithm) for digital circuit
simulation. It does not simulate detailed circuit timing, but instead computes the steady state
response of a circuit at each clock cycle. The user cannot see the glitch behavior of signals
between clock cycles. Instead the user observes circuit signals once per clock cycle. Cycle based
simulators work only with synchronous designs.
Event based Simulator: Simulation based on events in logic means that whenever there is change
in a input event, the output is evaluated. This makes the simulation very slow compared to Cycle
based simulators. Verilog-XL is an event based simulator.
Consider the circuit below: if a cycle based simulator runs a simulation on the circuit below, then it will
evaluate B, C, D and E only at each cycle. In the case of an event based simulator, B, C, D and E are
evaluated not only at clock cycle, but also when any of the events at the input of gates and flip-flops
occurs.
20. Difference between blocking, non-blocking, and delayed
assignment.
Reference:
1.
2.
3.
http://www.asic-world.com/
http://www.testbench.in/TS_00_INDEX.html
University of Southern California EE577B lectures.
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