CS612 Algorithms for Electronic Design Automation Partitioning Mustafa Ozdal CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 1 © KLMH MOST SLIDES ARE FROM THE BOOK: VLSI Physical Design: From Graph Partitioning to Timing Closure MODIFICATIONS WERE MADE ON THE ORIGINAL SLIDES Chapter 2 – Netlist and System Partitioning Original Authors: VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 2 Lienig Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu © KLMH Chapter 2 – Netlist and System Partitioning 2.1 Introduction 2.2 Terminology 2.3 Optimization Goals 2.4 Partitioning Algorithms 2.4.1 Kernighan-Lin (KL) Algorithm 2.4.2 Extensions of the Kernighan-Lin Algorithm 2.4.3 Fiduccia-Mattheyses (FM) Algorithm 2.5 Framework for Multilevel Partitioning 2.5.1 Clustering 2.5.2 Multilevel Partitioning System Partitioning onto Multiple FPGAs VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 3 Lienig 2.6 Introduction © KLMH 2.1 System Specification Partitioning Architectural Design ENTITY test is port a: in bit; end ENTITY test; Functional Design and Logic Design Chip Planning Circuit Design Placement Physical Design DRC LVS ERC Physical Verification and Signoff Clock Tree Synthesis Signal Routing Fabrication Timing Closure Packaging and Testing VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 4 Lienig Chip Divide and Conquer Strategy for Chip Design Partition the design. Then, work on each partition separately Advantages: Parallel implementation of each part by different designers Tool capacity issues avoided Disadvantages: Potentially less room for optimization Inter-dependency between different partitions Difficulty of combining partitions at the end CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 5 Introduction © KLMH 2.1 Circuit: Cut cb 1 3 2 7 4 5 8 6 Cut ca 8 7 Block B Block A 3 4 1 6 5 2 Cut ca: four external connections VLSI Physical Design: From Graph Partitioning to Timing Closure 8 7 Block B 5 4 1 6 3 2 Cut cb: two external connections Chapter 2: Netlist and System Partitioning 6 Lienig Block A Terminology © KLMH 2.2 Block (Partition) Graph G1: Nodes 3, 4, 5. 4 4 1 1 3 5 6 3 5 6 2 2 Cells Graph G2: Nodes 1, 2, 6. Collection of cut edges Cut set: (1,3), (2,3), (5,6), VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 7 Lienig cut edge: connects nodes in different partitions Optimization Goals Given a graph G(V,E) with |V| nodes and |E| edges where each node v V and each edge e E. Each node has area s(v) and each edge has cost or weight w(e). The objective is to divide the graph G into k disjoint subgraphs such that all optimization goals are achieved: Number (or total weight) of connections between partitions is minimized Partition sizes are balanced NP-hard problem Efficient heuristics are developed in the 1970s and 1980s. They are high quality and in low-order polynomial time. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 8 Lienig © KLMH 2.3 © KLMH Chapter 2 – Netlist and System Partitioning 2.1 Introduction 2.2 Terminology 2.3 Optimization Goals 2.4 Partitioning Algorithms 2.4.1 Kernighan-Lin (KL) Algorithm 2.4.2 Extensions of the Kernighan-Lin Algorithm 2.4.3 Fiduccia-Mattheyses (FM) Algorithm 2.5 Framework for Multilevel Partitioning 2.5.1 Clustering 2.5.2 Multilevel Partitioning System Partitioning onto Multiple FPGAs VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 9 Lienig 2.6 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm Given: A graph with 2n nodes where each node has the same weight. Goal: A partition (division) of the graph into two disjoint subsets A and B with minimum cut cost and |A| = |B| = n. 1 5 2 6 Block A Block B 3 7 4 8 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 10 Lienig Example: n = 4 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology Gain D(v) of a node v 1 5 D(v) = |Ec(v)| – |Enc(v)| , 2 6 3 7 4 8 High gains (D > 0) indicate that the node should move, while low gains (D < 0) indicate that the node should stay within the same partition. VLSI Physical Design: From Graph Partitioning to Timing Closure Node 3: D(3) = 3-1=2 Node 7: D(7) = 2-1=1 Chapter 2: Netlist and System Partitioning 11 Lienig where Ec(v) is the set of v’s incident edges that are cut by the cut line, and Enc(v) is the set of v’s incident edges that are not cut by the cut line. © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology Gain of swapping a pair of nodes a and b 1 5 g = D(a) + D(b) - 2* c(a,b), 2 6 3 7 4 8 where • D(a), D(b) are the respective gains of nodes a, b • c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here 1), otherwise, c(a,b) = 0. The gain g indicates how useful the swap between two nodes will be VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 12 Lienig The larger g, the more the total cut cost will be reduced © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology Node 7: D(7) = 2-1=1 g = D(a) + D(b) - 2* c(a,b), where • D(a), D(b) are the respective gains of nodes a, b • c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here 1), otherwise, c(a,b) = 0. g (3,7) = D(3) + D(7) - 2* c(a,b) = 2 + 1 – 2 = 1 => Swapping nodes 3 and 7 would reduce the cut size by 1 VLSI Physical Design: From Graph Partitioning to Timing Closure 1 5 2 6 3 7 4 8 1 5 2 6 3 7 4 8 Node 3: D(3) = 3-1=2 Chapter 2: Netlist and System Partitioning 13 Lienig Gain of swapping a pair of nodes a und b © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology Node 5: D(5) = 2-1=1 g = D(a) + D(b) - 2* c(a,b), where • D(a), D(b) are the respective gains of nodes a, b • c(a,b) is the connection weight between a and b: If an edge exists between a and b, then c(a,b) = edge weight (here 1), otherwise, c(a,b) = 0. g (3,5) = D(3) + D(5) - 2* c(a,b) = 2 + 1 – 0 = 3 => Swapping nodes 3 and 5 would reduce the cut size by 3 VLSI Physical Design: From Graph Partitioning to Timing Closure 1 5 2 6 3 7 4 8 1 5 2 6 3 7 4 8 Node 3: D(3) = 3-1=2 Chapter 2: Netlist and System Partitioning 14 Lienig Gain of swapping a pair of nodes a und b © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology Gain of swapping a pair of nodes a and b VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 15 Lienig The goal is to find a pair of nodes a and b to exchange such that g is maximized and swap them. © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology Maximum positive gain Gm of a pass The maximum positive gain Gm corresponds to the best prefix of m swaps within the swap sequence of a given pass. These m swaps lead to the partition with the minimum cut cost encountered during the pass. Gm is computed as the sum of Δg values over the first m swaps of the pass, with m chosen such that Gm is maximized. Gm m g i VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 16 Lienig i 1 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm Kernighan-Lin Algorithm Step 0: – – V = 2n nodes {A, B} is an initial arbitrary partitioning Step 1: – – i=1 Compute D(v) for all nodes vÎV Step 2: – – Choose ai and bi such that Dgi = D(ai) + D(bi) – 2 * c(aibi) is maximized Swap and fix ai and bi Step 3: – – – – If all nodes are fixed, go to Step 4. Otherwise Compute and update D values for all nodes that are connected to ai and bi and are not fixed. i=i+1 Go to Step 2 Step 4: – Find the move sequence 1...m (1 £ m £ i), such that Gm = – å m i =1 Δg i is maximized If Gm > 0, go to Step 5. Otherwise, END Step 5: Execute m swaps, reset remaining nodes Go to Step 1 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 17 Lienig – – 1 5 2 6 3 7 4 8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 18 Lienig Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 1 5 2 6 3 7 4 8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 gains D(v) of each node: D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 Nodes that lead to maximum gain VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 19 Lienig D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 1 5 2 6 3 7 4 8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 gains D(v) of each node: D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 Nodes that lead to maximum gain Gain after node swapping Gain in the current pass VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 20 Lienig D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 1 5 1 5 2 6 2 6 3 7 3 7 4 8 4 8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 Nodes that lead to maximum gain Gain after node swapping Gain in the current pass VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 21 Lienig D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 1 5 1 5 2 6 2 6 3 7 3 7 4 8 4 8 Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example Cut cost: 6 Not fixed: 1,2,4,6,7,8 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 22 Lienig g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 1 5 1 5 2 6 2 6 3 7 3 7 4 8 4 8 Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example Cut cost: 6 Not fixed: 1,2,4,6,7,8 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 D(1) = -1 D(2) = -1 D(4) = 3 D(6) = 2 D(7)=-1 D(8)=-1 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 23 Lienig g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 1 5 1 5 1 5 2 6 2 6 2 6 3 7 3 7 3 7 4 8 4 8 4 8 D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 Cut cost: 6 Not fixed: 1,2,4,6,7,8 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 D(1) = -1 D(2) = -1 D(4) = 3 D(6) = 2 D(7)=-1 D(8)=-1 g2 = 3+2-0 = 5 Swap (4,6) G2 = G1+g2 =8 VLSI Physical Design: From Graph Partitioning to Timing Closure Nodes that lead to maximum gain Gain after node swapping Gain in the current pass Chapter 2: Netlist and System Partitioning 24 Lienig Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example 1 5 1 5 1 5 1 5 2 6 2 6 2 6 2 6 3 7 3 7 3 7 3 7 4 8 4 8 4 8 4 8 D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 Cut cost: 6 Not fixed: 1,2,4,6,7,8 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 D(1) = -1 D(2) = -1 D(4) = 3 Cut cost: 1 Not fixed: 1,2,7,8 D(6) = 2 D(7)=-1 D(8)=-1 g2 = 3+2-0 = 5 Swap (4,6) G2 = G1+g2 =8 VLSI Physical Design: From Graph Partitioning to Timing Closure D(1) = -3 D(2) = -3 Cut cost: 7 Not fixed: 2,8 D(7)=-3 D(8)=-3 g3 = -3-3-0 = -6 Swap (1,7) G3= G2 +g3 = 2 Nodes that lead to maximum gain Gain after node swapping Gain in the current pass Chapter 2: Netlist and System Partitioning 25 Lienig Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example 1 5 1 5 1 5 1 5 1 5 2 6 2 6 2 6 2 6 2 6 3 7 3 7 3 7 3 7 3 7 4 8 4 8 4 8 4 8 4 8 D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 Cut cost: 6 Not fixed: 1,2,4,6,7,8 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 D(1) = -1 D(2) = -1 D(4) = 3 Cut cost: 1 Not fixed: 1,2,7,8 D(6) = 2 D(7)=-1 D(8)=-1 g2 = 3+2-0 = 5 Swap (4,6) G2 = G1+g2 =8 VLSI Physical Design: From Graph Partitioning to Timing Closure D(1) = -3 D(2) = -3 Cut cost: 7 Not fixed: 2,8 D(7)=-3 D(8)=-3 g3 = -3-3-0 = -6 Swap (1,7) G3= G2 +g3 = 2 D(2) = -1 Cut cost: 9 Not fixed: – D(8)=-1 g4 = -1-1-0 = -2 Swap (2,8) G4 = G3 +g4 = 0 Chapter 2: Netlist and System Partitioning 26 Lienig Cut cost: 9 Not fixed: 1,2,3,4,5,6,7,8 © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 D(1) = -1 D(2) = -1 D(4) = 3 D(6) = 2 D(7)=-1 D(8)=-1 g2 = 3+2-0 = 5 Swap (4,6) G2 = G1+g2 =8 D(1) = -3 D(2) = -3 D(7)=-3 D(8)=-3 g3 = -3-3-0 = -6 Swap (1,7) G3= G2 +g3 = 2 D(2) = -1 D(8)=-1 g4 = -1-1-0 = -2 Swap (2,8) G4 = G3 +g4 = 0 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 27 Lienig Maximum positive gain Gm = 8 with m = 2. © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Example D(1) = 1 D(2) = 1 D(3) = 2 D(4) = 1 D(5) = 1 D(6) = 2 D(7) = 1 D(8) = 1 g1 = 2+1-0 = 3 Swap (3,5) G1 = g1 =3 D(1) = -1 D(2) = -1 D(4) = 3 D(6) = 2 D(7)=-1 D(8)=-1 g2 = 3+2-0 = 5 Swap (4,6) G2 = G1+g2 =8 D(1) = -3 D(2) = -3 D(7)=-3 D(8)=-3 D(2) = -1 g3 = -3-3-0 = -6 Swap (1,7) G3= G2 +g3 = 2 D(8)=-1 g4 = -1-1-0 = -2 Swap (2,8) G4 = G3 +g4 = 0 Since Gm > 0, the first m = 2 swaps (3,5) and (4,6) are executed. Since Gm > 0, more passes are needed until Gm 0. VLSI Physical Design: From Graph Partitioning to Timing Closure 1 5 2 6 3 7 4 8 Chapter 2: Netlist and System Partitioning 28 Lienig Maximum positive gain Gm = 8 with m = 2. Kernighan-Lin Algorithm © KLMH 2.4.1 Kernighan-Lin (KL) Algorithm – Complexity Analysis n: # of nodes in each partition Step 0: – – O(n) – – i=1 Compute D(v) for all nodes vÎV Step 2: O(n2) – – O(n2) Choose ai and bi such that Dgi = D(ai) + D(bi) – 2 * c(aibi) is maximized Swap and fix ai and bi Step 3: – – – – If all nodes are fixed, go to Step 4. Otherwise Compute and update D values for all nodes that are connected to ai and bi and are not fixed. i=i+1 Go to Step 2 Step 4: – O(n) Find the move sequence 1...m (1 £ m £ i), such that Gm = – If Gm > 0, go to Step 5. Otherwise, END Step 5: – – Execute m swaps, reset remaining nodes Go to Step 1 VLSI Physical Design: From Graph Partitioning to Timing Closure å m i =1 Δg i is maximized O(n) 1-pass runtime: O(n3) Optimized implementation: O(n2lgn) Chapter 2: Netlist and System Partitioning 29 Lienig n times V = 2n nodes {A, B} is an initial arbitrary partitioning Step 1: © KLMH 2.4.2 Extensions for Kernighan-Lin (KL) Algorithm Unequal partition sizes Unequal cell sizes or unequal node weights VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 30 Lienig k-way partitioning (generating k partitions) Fiduccia-Mattheyses (FM) Algorithm Single cells are moved independently instead of swapping pairs of cells. Thus, this algorithm is applicable to partitions of unequal size or the presence of initially fixed cells. Cut costs are extended to include hypergraphs, i.e., nets with two or more pins. While the KL algorithm aims to minimize cut costs based on edges, the FM algorithm minimizes cut costs based on nets. The area of each individual cell is taken into account. Nodes and subgraphs are referred to as cells and blocks, respectively. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 31 Lienig © KLMH 2.4.3 Fiduccia-Mattheyses (FM) Algorithm © KLMH 2.4.3 Given: a graph G(V,E) with nodes and weighted edges VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 32 Lienig Goal: to assign all nodes to disjoint partitions, so as to minimize the total cost (weight) of all cut nets while satisfying partition size constraints Fiduccia-Mattheyses (FM) Algorithm – Terminology FS(c): the # of cut nets connected only to cell c in c’s partition “moving force” c FS(c) = 1 CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 33 Fiduccia-Mattheyses (FM) Algorithm – Terminology TE(c): the # of uncut nets connected to cell c “retention force” c TE(c) = 1 CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 34 Fiduccia-Mattheyses (FM) Algorithm – Terminology Δg(c) = FS(c) – TE(c) “gain of moving c” c Δg(c) = 0 CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 35 Fiduccia-Mattheyses (FM) Algorithm – Terminology © KLMH 2.4.3 Gain g(c) for cell c 3 2 b g(c) = FS(c) – TE(c) , a where the “moving force“ FS(c) is the number of nets connected to c but not connected to any other cells within c’s partition, i.e., cut nets that connect only to c, and the “retention force“ TE(c) is the number of uncut nets connected to c. 4 1 Cell 2: FS(2) = 0 e c d 5 TE(2) = 1 g(2) = -1 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 36 Lienig The higher the gain g(c), the higher is the priority to move the cell c to the other partition. Fiduccia-Mattheyses (FM) Algorithm – Terminology © KLMH 2.4.3 3 2 g(c) = FS(c) – TE(c) , where the “moving force“ FS(c) is the number of nets connected to c but not connected to any other cells within c’s partition, i.e., cut nets that connect only to c, and the “retention force“ TE(c) is the number of uncut nets connected to c. b a 4 1 c d FS(1) = 2 TE(1) = 1 g(1) = 1 Cell 2: FS(2) = 0 TE(2) = 1 g(2) = -1 Cell 3: FS(3) = 1 TE(3) = 1 g(3) = 0 Cell 4: FS(4) = 1 TE(4) = 1 g(4) = 0 Cell 5: FS(5) = 1 TE(5) = 0 g(5) = 1 VLSI Physical Design: From Graph Partitioning to Timing Closure 5 3 2 Cell 1: e b a e 4 1 c d 5 Chapter 2: Netlist and System Partitioning 37 Lienig Gain g(c) for cell c Fiduccia-Mattheyses (FM) Algorithm – Terminology © KLMH 2.4.3 Maximum positive gain Gm of a pass The maximum positive gain Gm is the cumulative cell gain of m moves that produce a minimum cut cost. Gm is determined by the maximum sum of cell gains g over a prefix of m moves in a pass Gm m g i VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 38 Lienig i 1 Fiduccia-Mattheyses (FM) Algorithm – Terminology © KLMH 2.4.3 Ratio factor The ratio factor is the relative balance between the two partitions with respect to cell area. It is used to prevent all cells from clustering into one partition. The ratio factor r is defined as area( A) r area( A) area( B) VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 39 Lienig where area(A) and area(B) are the total respective areas of partitions A and B Fiduccia-Mattheyses (FM) Algorithm – Terminology © KLMH 2.4.3 Balance criterion The balance criterion enforces the ratio factor. To ensure feasibility, the maximum cell area areamax(V) must be taken into account. A partitioning of V into two partitions A and B is said to be balanced if VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 40 Lienig [ r ∙ area(V) – areamax(V) ] ≤ area(A) ≤ [ r ∙ area(V) + areamax(V) ] Fiduccia-Mattheyses (FM) Algorithm – Terminology © KLMH 2.4.3 Base cell A base cell is a cell c that has maximum cell gain g(c) among all free cells, and whose move does not violate the balance criterion. Cell 1: FS(1) = 2 TE(1) = 1 g(1) = 1 Cell 2: FS(2) = 0 TE(2) = 1 g(2) = -1 Cell 3: FS(3) = 1 TE(3) = 1 g(3) = 0 Cell 4: FS(4) = 1 TE(4) = 1 g(4) = 0 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 41 Lienig Base cell Fiduccia-Mattheyses (FM) Algorithm – Terminology Pin distribution of a net: The pair (A(net), B(net)) where A(net): # of pins in partition A B(net): # of pins in partition B Critical net: A net that contains a cell c whose move changes the cut state of the net Either: The net has 1 cell in partition A and all others in B Or: The net has all cells in a single partition For a critical cell, one of the following should hold: A(net) = 0 or A(net) = 1 or B(net) = 0 or B(net) = 1 CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 42 Fiduccia-Mattheyses (FM) Algorithm – Critical Nets Critical nets simplify the gain calculations Only the cells belonging to critical nets need to be considered for gain calculations CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 43 Fiduccia-Mattheyses (FM) Algorithm © KLMH 2.4.3 Fiduccia-Mattheyses Algorithm Step 0: Compute the balance criterion Step 1: Compute the cell gain Dg1 of each cell Step 2: i = 1 – Choose base cell c1 that has maximal gain Dg1 , move this cell Step 3: – – Fix the base cell ci Update all cells’ gains that are connected to critical nets via the base cell ci Step 4: – – – If all cells are fixed, go to Step 5. If not: Choose next base cell ci with maximal gain Dgi and move this cell i = i + 1, go to Step 3 Step 5: – Determine the best move sequence c1, c2, .., cm (1 £ m £ i) , so that Gm = – å m i =1 Δgi is maximized If Gm > 0, go to Step 6. Otherwise, END Step 6: Execute m moves, reset all fixed nodes Start with a new pass, go to Step 1 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 44 Lienig – – Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 A 3 2 b a B e 4 1 c d 5 Given: Ratio factor r = 0,375 area(Cell_1) = 2 area(Cell_2) = 4 area(Cell_3) = 1 area(Cell_4) = 4 area(Cell_5) = 5. Step 0: Compute the balance criterion [ r ∙ area(V) – areamax(V) ] ≤ area(A) ≤ [ r ∙ area(V) + areamax(V) ] VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 45 Lienig 0,375 * 16 – 5 = 1 area(A) 11 = 0,375 * 16 +5. Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 A 3 2 b a B e 4 1 c d 5 Step 1: Compute the gains of each cell FS(Cell_1) = 2 FS(Cell_2) = 0 FS(Cell_3) = 1 FS(Cell_4) = 1 FS(Cell_5) = 1 TE(Cell_1) = 1 TE(Cell_2) = 1 TE(Cell_3) = 1 TE(Cell_4) = 1 TE(Cell_5) = 0 VLSI Physical Design: From Graph Partitioning to Timing Closure g(Cell_1) = 1 g(Cell_2) = -1 g(Cell_3) = 0 g(Cell_4) = 0 g(Cell_5) = 1 Chapter 2: Netlist and System Partitioning 46 Lienig Cell 1: Cell 2: Cell 3: Cell 4: Cell 5: Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 A 3 2 b a B e 4 1 c d Cell1: Cell 2: Cell 3: Cell 4: Cell 5: FS(Cell_1) = 2 FS(Cell_2) = 0 FS(Cell_3) = 1 FS(Cell_4) = 1 FS(Cell_5) = 1 TE(Cell_1) = 1 TE(Cell_2) = 1 TE(Cell_3) = 1 TE(Cell_4) = 1 TE(Cell_5) = 0 g(Cell_1) = 1 g(Cell_2) = -1 g(Cell_3) = 0 g(Cell_4) = 0 g(Cell_5) = 1 5 Step 2: Select the base cell Possible base cells are Cell 1 and Cell 5 Balance criterion after moving Cell 1: area(A) = area(Cell_2) = 4 Balance criterion after moving Cell 5: area(A) = area(Cell_1) + area(Cell_2) + area(Cell_5) = 11 Both moves respect the balance criterion, but Cell 1 is selected, moved, VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 47 Lienig and fixed as a result of the tie-breaking criterion. Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 A 3 2 b a B e 4 1 c d 5 Step 3: Fix base cell, update g values Cell 2: FS(Cell_2) = 2 TE(Cell_2) = 0 g(Cell_2) = 2 Cell 3: FS(Cell_3) = 0 TE(Cell_3) = 1 g(Cell_3) = -1 Cell 4: FS(Cell_4) = 0 TE(Cell_4) = 2 g(Cell_4) = -2 Cell 5: FS(Cell_5) = 0 TE(Cell_5) = 1 g(Cell_5) = -1 VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 48 Lienig After Iteration i = 1: Partition A1 = 2, Partition B1 = 1,3,4,5, with fixed cell 1. Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 A 3 2 b a e 4 1 c d B Iteration i = 1 Cell 2: FS(Cell_2) = 2 TE(Cell_2) = 0 g(Cell_2) = 2 Cell 3: FS(Cell_3) = 0 TE(Cell_3) = 1 g(Cell_3) = -1 Cell 4: FS(Cell_4) = 0 TE(Cell_4) = 2 g(Cell_4) = -2 Cell 5: FS(Cell_5) = 0 TE(Cell_5) = 1 g(Cell_5) = -1 5 Iteration i = 2 Cell 2 has maximum gain g2 = 2, area(A) = 0, balance criterion is violated. Cell 3 has next maximum gain g2 = -1, area(A) = 5, balance criterion is met. Cell 5 has next maximum gain g2= -1, area(A) = 9, balance criterion is met. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 49 Lienig Move cell 3, updated partitions: A2 = {2,3}, B2 = {1,4,5}, with fixed cells {1,3} Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 A e b a 1 Iteration i = 2 3 2 c d 4 B Cell 2: g(Cell_2) = 1 Cell 4: g(Cell_4) = 0 Cell 5: g(Cell_5) = -1 5 Iteration i = 3 Cell 2 has maximum gain g3 = 1, area(A) = 1, balance criterion is met. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 50 Lienig Move cell 2, updated partitions: A3 = {3}, B3 = {1,2,4,5}, with fixed cells {1,2,3} Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 B 3 2 e b a 1 c d 4 A Iteration i = 3 Cell 4: g(Cell_4) = 0 Cell 5: g(Cell_5) = -1 5 Iteration i = 4 Cell 4 has maximum gain g4 = 0, area(A) = 5, balance criterion is met. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 51 Lienig Move cell 4, updated partitions: A4 = {3,4}, B3 = {1,2,5}, with fixed cells {1,2,3,4} Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 B 3 2 A Iteration i = 4 e b a 1 c d 4 Cell 5: g(Cell_5) = -1 5 Iteration i = 5 Cell 5 has maximum gain g5 = -1, area(A) = 10, balance criterion is met. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 52 Lienig Move cell 5, updated partitions: A4 = {3,4,5}, B3 = {1,2}, all cells {1,2,3,4,5} fixed. Fiduccia-Mattheyses (FM) Algorithm – Example © KLMH 2.4.3 Step 5: Find best move sequence c1 … cm B G1 = g1 = 1 3 2 A e G2 = g1 + g2 = 0 b a G3 = g1 + g2 + g3 = 1 G4 = g1 + g2 + g3 + g4 = 1 G5 = g1 + g2 + g3 + g4 + g5 = 0. 1 c d 4 5 m Maximum positive cumulative gain Gm g i 1 i 1 found in iterations 1, 3 and 4. The move prefix m = 4 is selected due to the better balance ratio (area(A) = 5); the four cells 1, 2, 3 and 4 are then moved. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 53 Lienig Result of Pass 1: Current partitions: A = {3,4}, B = {1,2,5}, cut cost reduced from 3 to 2. © KLMH Chapter 2 Supplemental: Difference between KL & FM Component dependency of partitioning algorithms KL is based on the number of edges FM is based on the number of nets Time complexity of partitioning algorithms KL has cubic time complexity VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 54 Lienig FM has linear time complexity © KLMH Chapter 2 – Netlist and System Partitioning 2.1 Introduction 2.2 Terminology 2.3 Optimization Goals 2.4 Partitioning Algorithms 2.4.1 Kernighan-Lin (KL) Algorithm 2.4.2 Extensions of the Kernighan-Lin Algorithm 2.4.3 Fiduccia-Mattheyses (FM) Algorithm 2.5 Framework for Multilevel Partitioning 2.5.1 Clustering 2.5.2 Multilevel Partitioning System Partitioning onto Multiple FPGAs VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 55 Lienig 2.6 Clustering © KLMH 2.5.1 To make things easy, groups of tightly-connected nodes can be clustered, absorbing connections between these nodes Size of each cluster is often limited so as to prevent degenerate clustering, i.e. a single large cluster dominates other clusters VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 56 Lienig Refinement should satisfy balance criteria Clustering © KLMH 2.5.1 a d d a d e b c,e a,b,c b c e Possible clustering hierarchies of the graph VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 57 Lienig © 2011 Springer Initital graph Multilevel Partitioning VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 58 Lienig © 2011 Springer Verlag © KLMH 2.5.2 FPGA Applications: Programmability Instead of fabricating a chip, we can program an FPGA Advantages: Avoid non-recurring engineering (NRE) costs of IC design Enable later changes easily (e.g. in case of a new media format) Disadvantages: Larger area, more power, slower speed CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 59 FPGA Applications: System Prototyping Typical design cycle: Hardware design Arch RTL PD Litho Fab Firmware Drivers Apps Reduce time to market with system prototyping: Arch RTL PD Litho Fab Firmware CS 612 – Lecture 3 Drivers Apps Mustafa Ozdal Computer Engineering Department, Bilkent University 60 System Partitioning onto Multiple FPGAs © KLMH 2.6 FPGA FPGA FPGA FPIC FPIC FPIC FPIC RAM FPGA Logic © 2011 Springer Verlag FPGA FPGA Logic VLSI Physical Design: From Graph Partitioning to Timing Closure Mapping of a typical system architecture onto multiple FPGAs Chapter 2: Netlist and System Partitioning 61 Lienig Reconfigurable system with multiple FPGA and FPIC devices System Partitioning onto Multiple FPGAs Challenges: Partitioning formulations: Low utilization of FPGA resources (due to hard I/O pin limits) Low performance (due to interconnect delays between FPGAs) Long runtimes of system partitioning process Hard upper bound for total area of each partition Hard upper bound for the cut size 3rd dimension for FPGA mapping: time CS 612 – Lecture 3 Mustafa Ozdal Computer Engineering Department, Bilkent University 62 Circuit netlists can be represented by graphs or hypergraphs Partitioning a graph means assigning nodes to disjoint partitions © KLMH Summary of Chapter 2 Total size of each partition (number/area of nodes) is limited Objective: minimize the number connections between partitions Basic partitioning algorithms Incremental changes organized into passes KL swaps pairs of nodes from different partitions FM re-assigns one node at a time FM is faster, usually more successful Multilevel partitioning Clustering FM partitioning Refinement (also uses FM partitioning) Application: system partitioning into FPGAs VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 63 Lienig Each FPGA is represented by a partition