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G0495506124
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校 輔仁大學
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所 電子工程學系
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舊
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稱
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495506124
號
研
究
蔡宗達
生
(中
)
研
究
Tsung Ta Tsai
生
(英
)
論
文 克服短雜脈衝與過早傳輸效應以抵擋電力分析攻擊
名
稱
(中
)
論
文
名 Overcoming Glitches and Early Propagation Effect to Counteract DPA Attacks
稱
(英
)
其
他
題
名
指
導
教 林寬仁
授
(中
)
指
導
教 Kuan Jen Lin
授
(英
)
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學
位 碩士
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別
畢
業
96
學
年
度
出
版 97
年
語
文 英文
別
關
鍵
DPA
字
(中
)
關
鍵
差異電力分析
字
(英
)
不同邏輯電路形式被用以設計密碼演算電路以抵擋差異電力分析(differential
power analysis)攻擊。 然而它們大多花費大量的硬體成本使電路沒有短雜脈
衝(glitch)與移除訊號過早傳輸(early propagation)之效應。在一個最近發表的
摘 做法 iMDPL (improved Masked Dual-Rail Pre-charge logic)，即使已經使用了五
倍以上的硬體，我們仍然發現存在漏洞，可能降低安全強度。在本論文
要 中，我們研究兩種方法來克服短雜脈衝與訊號過早傳輸(early propagation)之
(中 效應。第一種方法 並未企圖消除短雜脈衝與訊號過早傳輸(early propagation)
) 之效應，而在於將它們的效應平均分配給不同電位之輸出，如此可以抵擋
差異電力分析攻擊，並節省大量硬體。我們提出等量(equivalence)性質之觀
念，來證明其安全性，並以實驗模擬驗證其安全性。第二中方法則是使用
亂數產生器來混亂訊號到達時間，以致攻擊者無法利用短雜脈衝與訊號過
早傳輸現象。我們也實作並評估此一方法。
Various logic styles have been proposed to counteract DPA (Differential Power
Analysis) attacks. However, large area penalty must be incurred to make circuits
glitch-free and to eliminate the early propagation effects. We found that a most recent
摘 design iMDPL still has leakage to DPA attacks in spite of using over 5 times area
overhead. In this thesis, we study two countermeasures to overcome the glitch and
要 early propagation effects. The first approach does not attempt to make the whole
(英 circuit glitch-free and no early propagation effect. On the other hand, it equalizes the
) glitches and early propagation effects for different-level outputs. We propose a new
property called equivalence property to prove its security. The second approach
applies an RNG (Random Number Generator) to insert random delays into the key
path to make glitches and early propagation effects independent of intermediate data
which are processed. Therefore, an attacker cannot exploit them to reveal a key.
Abstract (in
Chinese) .…...………………………………………………….……………i
文
Abstract .………….…..………….………………………………….……………
目
……...ii
次
Acknowledgement …………………………………………………………………
論
…...iii
Contents …...………………………………………………………………..……
…..…iv List of
Tables ……........…………………………………………………………….…..vi
List of
Figures ……….....…...…………………………………………...….………….vii
1
Introduction ……………………………………………………………………….1
1.1 Differential Power Analysis Attack …………..……..……...….………….….1
1.2 Countermeasures………………………………………………………………2
1.3 Purpose of This thesis....…………………..…………………..…...………….3
1.4 Organization ……………………...…………………..….……...…………....4
2 AES Algorithm and Hardware Implementation …............................................5 2.1
Finite Fields…………………………………………………................…….5 2.2
AES Algorithm …..…….......……………….…………………...........……..9 2.3
AES Key Expansion ...……………………..……………………….……….12 2.4
The AES Hardware Implementation ………..……………………...……….13 3
DPA Attacks and PMRML Countermeasure…………………………………..17 3.1
DPA Attacks ...………….…………………………………..……….....……17 3.2
Countermeasures……...…..…………………………………………………22 3.3
Glitches and Early Propagation Effect….…………………………………...24 4
PMRML and Equivalence Property…………...……………..…………………26
4.1 Pre-charge Masked Reed-Muller Logic (PMRML)..................................…..26 4.2
Equivalence Property……………….........................................................…29 4.3
Security Evaluation of the PMRML .………………………………………..31 4.4
Security Evaluation of the iMDPL………………..………………………...33 5
Countermeasure using Randomized Delay …………………..……………… 35 5.1
Random Delay Insertion …………………………………………………….35 5.2
TRNG and PRNG ……………………………………...……………………37 5.3
Evaluation of RNG…………………………………………………………..38 6
Experimental Results...........................................................................42 6.1 PMRML
Evaluation using SPICE…..……………………………………….42 6.2
Experimental Results………………………………………………………...44 7
Conclusion………………………………………………......................................47
References ….………………………………………………………………………
….48
參
考
文
獻
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