Chapter 5
Computer
Organization
OBJECTIVES
After reading this chapter, the reader should
be able to:
Distinguish between the three components of a computer
hardware.
List the functionality of each component.
Understand memory addressing and calculate the number of
bytes for a specified purpose.
Distinguish between different types of memories.
Understand how each input/output device works.
Continued on the next slide
OBJECTIVES (continued)
Understand the systems used to connect different
components together.
Understand the addressing system for input/output
devices.
Understand the program execution and machine cycles.
Distinguish between programmed I/O, interrupt-driven
I/O and direct memory access (DMA).
Understand the two major architectures used to define
the instruction sets of a computer: CISC and RISC.
Figure 5-1
Computer hardware (subsystems)
5.1
CENTRAL
PROCESSING
UNIT
(CPU)
Figure 5-2
•
CPU
CPU performs operations on data.
1. ALU
2. Control Unit
3. A set of registers
ALU
• Arithmetic operations:
–
–
–
–
–
–
Increment
Decrement
Add
Subtract
Multiply
Divide
• Logical operations:
–
–
–
–
NOT
AND
OR
XOR
Registers
Fast stand-alone storage locations
that hold data temporarily in CPU.
– PC (Program Counter)
• Keep track of the instruction currently being executed.
• Incremented after execution of the instruction.
– Instruction Register
• Store the instruction currently being executed
– Data Registers
• Hold data before it can be processed
Register
• A, special, high-speed storage area within the CPU.
All data must be represented in a register before it
can be processed.
– For example, if two numbers are to be multiplied, both
numbers must be in registers, and the result is also
placed in a register.
• The power and speed of a CPU determined by
– the number of registers that a CPU has and
– the size of each (number of bits)
– For example a 32-bit CPU is one in which each register
is 32 bits wide. Therefore, each CPU instruction can
manipulate 32 bits of data.
Control Unit
• Like the part of the human brain that
control the operation of each part of the body.
• Controlling is achieved through wires (form
Control unit to ALU) that can be on/off.
• 4 wires  16 operations
1.
2.
3.
4.
5.
6.
I ← M[PC]
PC++
R1 ← A
R2 ← B
R3 ← R1 + R2
C ← R3
1.
2.
3.
4.
5.
I ← M[PC]
PC++
.
.
.
10
20
30
ADD
2000 CA+B
2004 CC-5
CA+B
10
2000
20
30
A
B
C
5.2
MAIN MEMORY
Main Memory
• Main memory –
– a collection of storage locations,
– each with a unique identifier called the address.
• Word– Data are transferred to and from memory in groups
of bits called words.
– The number of bits that can be stored in one CPU
register in a computer.
Figure 5-3
Main memory
Address Space
• Although programmers use a name to identify a word,
at the hardware level, each word is identified by an
address.
• Address space – The total number of uniquely identifiable locations in memory.
– For example:
a memory with 64KB and a word size of 1 byte has an
address space that range from 0 to 65535.
Table 5.1 Memory units
Unit
-----------KB-kilobyte
MB-megabyte
GB-gigabyte
TB-terabyte
PB-petabyte
EB-exabyte
Exact Number of bytes
Approximation
-----------------------210 bytes
220 bytes
230 bytes
240 bytes
250 bytes
260 bytes
-----------103 bytes
106 bytes
109 bytes
1012 bytes
1015 bytes
1018 bytes
Address as Bit Pattern
• Because computers operate by storing
numbers as bit patterns, the address itself is
also represented as a bit pattern.
• If a computer has N words of memory, you
need an unsigned integer of size log2N bits to
refer to each memory location.
Note:
Memory addresses are defined using
unsigned binary integers.
Example 1
A computer has 32 MB (megabytes) of memory. How
many bits are needed to address any single byte in
memory?
Solution
The memory address space is 32 MB, or 225 (25 x 220).
This means you need
log2 225 or 25 bits, to address each byte.
Example 2
A computer has 128 MB of memory. Each word in
this computer is 8 bytes. How many bits are
needed to address any single word in memory?
Solution
The memory address space is 128 MB, which
means 227. However, each word is 8 (23) bytes,
which means that you have 224 words. This
means you need log2 224 or 24 bits, to address
each word.
Memory Types
• RAM (Random Access Memory)
– Volatile
– R/W by user
– Two categories:
• DRAM(Dynamic RAM)
– Refresh
– used in most PCs
• SRAM(Static RAM)
– No refresh
– faster 、more reliable
– more expensive
– often used only as a memory cache
Memory Types
• ROM (Read Only Memory)
– Nonvolatile
– Written by manufacture
– Hold the booting program
– Categories:
• ROM
• PROM(Programmable ROM)- Write once by
user
• EPROM(Erasable PROM)- physical removal
and reinstallation by special device
• EEPROM(Electronically EPROM)- without
being removed from computer
Figure 5-4
Memory hierarchy
Speed
Secondary Memory
Cost Space
Cache Memory
• Cache memory at any time contains a copy of a
portion of main memory.
1. CPU checks the cache
2. If exist, copy the word,
otherwise
1) access main memory and copy a block of memory
starting with the desired word.
2) CPU accesses cache and copies the word.
Figure 5-5
Cache
• It is very probable that the CPU, in next cycle,
needs to access the words following the first word.
• The existence of the cache speeds processing.
• 80-20 rule
Most computers typically spend 80% of the time
accessing only 20% of the data.
• Same data are accessed over and over again.
5.3
INPUT / OUTPUT
Input/Output Subsystem
• I/O subsystem allows a computer to
– Communicate with the outside world
– Store programs and data
even when the power is off.
Nonstorage devices
• allows the CPU/memory to
communicate with the outside world
• Keyboard – provides input
• Monitor
– display output
– Echoes the input typed on the keyboard
• Printer
Storage devices
• can store large amount of information to be
retrieved at a later time.
• Cheaper than main memory
• Nonvolatile
• Auxiliary storage device (Secondary memory)
• Categories:
– Magnetic
– optical
Magnetic Storage devices
• Use magnetization to store bits of data
• If a spot is magnetized  1
• If a spot is not magnetized  0
• Magnetic Disk
– Random access device
• Magnetic Tape
– Sequential access device
Physical layout of a magnetic disk
• Performance depends on several factors
 Rotational speed
 Seek time – the time to move the R/W head
to desired track
Transfer time – the time to move data from
the disk to the CPU/Memory
Figure 5-6
Surface organization of a disk
• Each surface is divided into tracks
• Each track is divided into sectors
• Sectorthe smallest storage area that can be accessed
at one time.
• Blockcan be stored in one or more sectors and
retrieved together.
Figure 5-7
Figure 5-8
Mechanical configuration of a tape
•
•
•
•
Surface organization of a tape
Sequential access
Slower
Cheaper
Backup large amount of data
• 9 vertical spots
 8 bits of information
 1 bit for error detection
Figure 5-9
Optical Storage devices
• Use light (laser) to store and retrieve data.
• CD-ROM(Compact disc read-only memory)
– Same technology as CD
• CD-R (Compact disc recordable)
– WORM(Write Once, Read Many)
• CD-RW (Compact disc rewritable)
– Also called Erasable optical disc
• DVD(Digital Versatile Disc)
– Higher capacity
74分42秒
•
•
•
•
CD (Compact Disc)
讀取CD的雷射光-美國貝爾實驗室的發明
新力(SONY)與飛利浦(Philips)合作研發
新力總裁大賀典雄所定下直徑12公分、錄音時間74分42秒的版本。
• 錄音長度剛好可以完整收錄貝多芬的第九號交響
曲「合唱」(終樂章:「快樂頌」)
Figure 5-10
Creation and use of CD-ROM
Table 5.2 CD-ROM speeds
Speed
Data Rate
Approximation
-----------1x
2x
4x
6x
8x
12x
16x
24x
32x
40x
-----------------------153,600 bytes per second
307,200 bytes per second
614,400 bytes per second
921,600 bytes per second
1,228,800 bytes per second
1,843,200 bytes per second
2,457,600 bytes per second
3,688,400 bytes per second
4,915,200 bytes per second
6,144,000 bytes per second
-----------150 KB/s
300 KB/s
600 KB/s
900 KB/s
1.2 MB/s
1.8 MB/s
2.4 MB/s
3.6 MB/s
4.8 MB/s
6 MB/s
52X
7.8 MB/s
Figure 5-11
CD-ROM format
Figure 5-12
Making a CD-R
Figure 5-13
Making a CD-RW
Table 5.3 DVD capacities
Feature
Capacity
--------------------------------single-sided, single-layer
single-sided, dual-layer
double-sided, single-layer
double-sided, dual-layer
-----------4.7 GB
8.5 GB
9.4 GB
17 GB
Memory hierarchy
Speed
Secondary Memory
• Hard disk
• Floppy disk (Diskette)
•Flash memory
• CD-R/CD-RW/DVD
• Magnetic tape
Cost Space
5.4
SUBSYSTEM
INTERCONNECTION
Connecting CPU and memory using three buses
• Data bus# of wires depends on the size of the word.
• Address bus# of wires depends on the address space of memory.
• Control bus# of wires depends on the total number of control
commands a computer needs.
Figure 5-14
Connecting I/O devices
• The CPU and memory are electronic devices.
• The I/O devices are eletromechanical, magnetic,
or optical devices.
– Much slower speed
– Need for an intermediary- I/O controller (or interface)
• Serial controlleronly one wire connection to the device
• Parallel controllerseveral connections to the device
Figure 5-15
Connecting I/O devices to the buses
SCSI controller
• SCSI(Small Computer System Interface)
Parallel (8/16/32 bits)
Daisy chained connection
Unique ID for each device
Figure 5-16
FireWire controller
• IEEE 1394 (iLink)
 serial
 High speed up to 50MB/sec (400Mbps)
 Daisy-chain/Tree connection
 1394b (800Mbps)
Figure 5-17
USB controller
• USB(Universal Serial Bus)
serial
1.0 (12 Mbps)
2.0 (480 Mbps)
Figure 5-18
Addressing I/O devices
• The CPU use the same bus to R/W memory
and I/O devices.
The only difference is the instruction.
• Two methods to handle the addressing of
I/O devices
– Isolated I/O
– Memory-Mapped I/O
Isolated I/O addressing
• Different instructions
• The I/O addresses can overlap with memory
addresses without any ambiguity because
the instruction itself is different.
Figure 5-19
Memory-mapped I/O addressing
• Same instructions
• The CPU treats each register in the I/O controller as
a word in memory.
• Adv. – smaller # of instructions
• Disadv. – part of the address space allocated for I/O
Figure 5-20
5.5
PROGRAM
EXECUTION
Program Execution
•
•
•
•
General–purpose computers use a set of
instructions called a program to process data.
Both the program and the data are stored in
memory.
The CPU uses repeating machine cycles to
execute instructions in the program, one by one.
A simplified cycle consists of:
1. Fetch
2. Decode
3. Execute
Figure 5-21
Steps of a cycle
Machine Cycle
1.Fetch
– IRMemory[PC]
– PC++
2.Decode
– [IR] gets decoded by control unit
3.Execute
– Control unit sends the task-orders to other
components.
Figure 5-22
Contents of memory and register before execution
 IRMemory[070]
PC++
Figure 5-23.a
 R1Memory[200]
 IRMemory[071]
PC++
Contents of memory and
registers after each cycle
Figure 5-23.b
 R2Memory[201]
 IRMemory[072]
PC++
Contents of memory and
registers after each cycle
Figure 5-23.c
 R3R1+R2
 IRMemory[073]
PC++
Contents of memory and
registers after each cycle
Figure 5-23.d
 Memory[202]R3
 IRMemory[074]
PC++
Contents of memory and
registers after each cycle
Synchronization
between CPU and I/O device
• Programmed I/O –
CPU waits for the I/O device.
• Interrupt-driven I/O –
The I/O device informs(interrupts) CPU.
• DMA (Direct Memory Access) –
DMA controller transfer data between I/O
device and memory (without through CPU)
Figure 5-24
Programmed I/O
• CPU does nothing until the
data transfer is complete.
• CPU constantly checks the
status of I/O device.
• CPU time is wasted by
status checking.
Figure 5-25
Interrupt-driven I/O
• CPU can do other jobs
until I/O device is ready and
interrupt it.
• CPU does not constantly
checks the status of I/O
device.
• Transfer data:
Memory – CPU – I/O device
DMA (Direct Memory Access)
• Transfer a large block of data between a high-speed
I/O device (disk) and memory directly (without
passing data through CPU)
• DMA controller relieves the CPU of some of its
functions.
• DMA controller has registers to hold a block of data.
• CPU is available for other jobs.
• CPU is idle only (stops using the buses for a short
time) during the data transfer between DMA and
memory.
• Transfer data:
CPU is idle
Memory – DMA – I/O device
Figure 5-26
DMA connection to the general bus
Figure 5-27
DMA input/output
5.6
TWO DIFFERENT
ARCHITECTURES
CISC
Complex Instruction Set Computer
• Have a large set of instructions, including the
complex ones.
• Easer programming
• Complicated circuitry of CPU and control unit.
• Intel Pentium series
RISC
Reduced Instruction Set Computer
• Have a small set of simple instructions.
• Programming is more difficult and longer
• PowerPC series (Apple Computers)