DAAD Projekt „ESSNBS“
Technical University of Sofia
An Educational Electronic Prototype System
for Phase-Locked Loop Based Circuits
Eltimir Stoimenov(1), Ivаilo Pandiev(2)
e_stoimenov@tu-sofia.bg(1), ipandiev@tu-sofia.bg(2)
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
Our objective:
To develop a laboratory stand which helps students
to understand the basics of the PLL circuits.
Why?
Because PLL circuits are widely applied in
communication, electronics and computer
sciences. In this order students should possess a
high level of knowledge in the PLL theory.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
What we have done:
We have designed a versatile educational PLL
stand which incorporates the most important
applications of the PLL circuits:
- phase locking;
- frequency synthesis with integer and
non-integer coefficients;
- frequency demodulation.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
FM
generator
LPF_1
R3
PWM_OUT
DEM_OUT
LPF_2
R4
FM generator:
AllowsFrequency
frequencydividers:
demodulation
Pass
Filter:
PLL
circuit:
AllowsLow
frequency
synthesis
- Central frequency: 0-1MHz;
- Lag-lead
type (one
pole,ICone zero);
-Based
on 4046
- Programmable
coefficients
- Adjustable deviation;
thecan
students
set the
capture
--Allows
Students
setresolution
thetoVCO
parameters
-9bits
- Adjustable
data
signal frequency.
range
by external
components
-Based
on MSP430G2553
-Data signal
PWM output
- Based on MSP430F5310
P CPOUT
P C3OUT
VCOIN
VCOOUT
OUTPUT
C1B
COMPIN
PLL
PC 4046 VCO
C1A
SIGIN
OUT
P C2OUT
FREQUENCY
DIVIDER 1
0 - 512
R2
IN
R1
INPUT
P C1OUT
C2
R1 R2
C1
OUT
Niš, November 4th – 7th, 2012
FREQUENCY
DIVIDER 2
0 - 512
IN
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DAAD Projekt „ESSNBS“
Experimental results
FM
generator
PWM_OUT
DEM_OUT
INPUT
IN
FREQUENCY
DIVIDER 1
0 - 512
LPF_2
LPF_1
OUT
SIGIN
VCOIN
P COUT
LPF_3
PLL
4046
COMPIN
OUT
FREQUENCY
DIVIDER 2
0 - 512
VCOOUT
OUTPUT
IN
2. Frequency synthesis
demodulation - PWM output
1.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
Laboratory stand part -1
Niš, November 4th – 7th, 2012
Laboratory stand part -2
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DAAD Projekt „ESSNBS“
Exercise set, part 1:
1. Study the Phase-Loop-Locked circuit realized with 4046 IC. Consider the following
input parameters:
- VCO central frequency – fO = 100 kHz for VVCOIN = 1/2VCC;
- Lock range - 2fL = 100 kHz;
- Settling time – tset = 1 ms for maximum ripples ≤ 5% ;
- Overshoot ≤ 20% and settle to within 5% at wnt = 5.
2.Calculate all the external VCO components – R1, R2 and C1. Calculate the values of
the LPF_1 components - R3, R4 and C2. For the calculation use the nomograms and
formulas given 4046 datasheet from Philips.
3. Set the components values according the calculation you made in the previous point.
Apply a square wave signal of 5 V magnitude and frequency of 100 kHz. The frequency
dividers and the FM generator should not be connected to the circuit.
- Measure the VCO controle voltage – VCOIN;
- Use an oscilloscope to observe the input and the output signals. Measure the
frequencies of the signals;
- Determine the width of the lock range. Find the fMIN and fMAX frequencies and measure
the corresponding VCO control voltages. Compare the values with the input parameters.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
Exercise set, part 2:
4. Synthesize output signals with frequencies of 90 kHz to 110 kHz with step of
1 kHz. In this order connect the two frequency dividers to the PLL circuit and
change the division coefficients appropriately. Apply a square wave input signal
of 5V magnitude and frequency of 1 kHz. The FM generator should not be
connected to the circuit.
5. Realize a frequency demodulator using the PLL circuit. For this purpose
connect the FM generator to the input and by using the rotary encoder adjust
the signal as follows: carrier signal central frequency: 100 kHz; deviation: ±40%;
data signal frequency: 100 Hz. Connect the VCOIN signal to LPF_2 input and
observe the demodulated signal in the LPF_2 point. The original data signal is
also PWM modulated and after filtering it can be observed in PWM_OUT point.
Compare the two signals. The frequency dividers should not be connected to the
circuit.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
THE PILOT TEST
The pilot test of the developed educational
prototype system will be performed in 2012 with
hundred of 3rd year regular students within 24
learning hours. In particular the educational system
is a part of the laboratory practice of the Mixedsignal system course. The evaluation of the system
will be focused on usability of the learning material,
instructional effectiveness and learners’ attitudes.
The chosen block structure provides possibilities
for future extension of the developed system with
additional elements and functionality.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
CONCLUSIONS
The developers’ team achieved the following results
of the of the :
- Development of a procedure for PLL circuits study;
- Development of an educational electronic prototype
system based on monolithic PLL 4046. The created system
allows to study some of the basic PLL circuit applications,
such as phase locking process, frequency synthesis and
frequency demodulation;
- Creating students’ guide and assignments for
supporting the created educational prototype system.
Niš, November 4th – 7th, 2012
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DAAD Projekt „ESSNBS“
Thank you for your
attention
For more information please contact us on:
e_stoimenov@tu-sofia.bg
Niš, November 4th – 7th, 2012
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