Advanced Microprocessors
PS02CINS02
Unit
1
Comparison between 8085 and 8086
8085
8086
8-bit
16-bit
16-bit/64kB
20-bit/1MB
Instruction Queue
NO
6 byte
Pipeline
NO
2 stage
Multiprocessor support
NO
YES
IO
256
64K
Co-Processor Interface
NO
Yes
Integer and BCD
Integer,BCD,ASCII
No instruction
Instructions are there
3,5,6MHz
5,8,10MHz
Less Requirement
Large
Normal
Maximum & Minimum
5
9
Memory
Single Block
Segmented
Interrupts
5HW & 8SW
2HW & 256SW
Size
Address Bus and Memory
Arithmatics
Mul/Div
Speed
External HW
Modes
Addressing modes
Architecture of 8086
 parallel processing
 processing units:
 Bus Interface Unit (BIU)
 Execution Unit (EU)
 both operate at the same time
 fetch and execution independent operations
8086 Architecture
BIU
EU
Bus Interface Unit
 Facilitates comm. between the EU and the memory
or I/O circuits.
 Perform bus operation such as inst. fetching,
reading/writing of data for memory or i/o
peripherals.
 Transmit address, data, and the control signals on
the buses.
 Contains CS, DS, ES, SS and IP registers, address
generation adder, bus control logic, and an
instruction queue.
Bus Interface Unit
 An internal bus connects the EU and BIU.
 While the EU is executing an instruction the BIU




fetches up to six bytes of next instruction in the
instruction queue
Perform instruction queuing and data acquisitions.
8-bit (16-bit) bi-directional data bus for 8088
(8086).
20-bit address bus
Instruction queue to implement a pipelined
architecture
Execution Unit
 Responsible for decoding and executing
instruction.
 Contains: ALU, Flags, general purpose and
temporary register.
 The EU has eight registers AX, BX, CX, DX, SI, DI,
BP and SP.
 In addition EU has temporary registers for holding
operands for CPU, and the FLAGS registers
Execution Unit
 EU accesses the instruction from the instruction
queue and data from general-purpose register.
 It reads one instruction at a time, decodes it,
generates operand address if necessary, passes
them to BIU and requests to perform the
read/write cycle to memory or I/O, and performs
the operation specified by the instruction on
operand.
 During execution, EU may test the flags and
update these flags based on the results of
execution.
Software Model
8086 P
IP
CS
DS
SS
ES
AX
BX
CX
DX
SP
BP
SI
DI
SR
External Memory
Address Space
00000
Code Segment(64kB)
Data Segment(64kB)
Stack Segment(64kB)
Extra Segment(64kB)
FFFFF
Input/ Output
Address Space
OOOO
Input /
Output
Map
FFFF
Software Model
 Various Registers and their purposes, functional
capability and limitations.
 External memory and I/O devices’ organization.
 Less likely to change with new generation
Data Organization
 8086 supports 1 MB of external memory
 Individually located bytes from 00000H to FFFFFH
 Byte wise organization
 Can access byte, word or double word (little endian)
 Even and odd address boundaries
 Aligned word (starts from even add.)
 Aligned double word (starts from add. multiple of 4)
Data Organization
00008
• Byte 8
00008
• Byte 8
00007
• Byte 7
00007
• Byte 7
00006
• Byte 6
00006
• Byte 6
00008
• Byte 5
00008
• Byte 5
00004
• Byte 4
00004
• Byte 4
00003
• Byte 3
00003
• Byte 3
00002
• Byte 2
00002
• Byte 2
00001
• Byte 1
00001
• Byte 1
00000
• Byte 0
00000
• Byte 0
Data Types
 Sizes:
 Byte(8 bits)
 Word(16 bits)
 Double Word(32 bits)
8 bit
16 bit
32 bit
 Integer: Signed and Unsigned
 -128 to +127
S 7 bit data
 -32768 to +32767
S 15 bit data
 -(231) to + (231-1)
S 31 bit data
 BCD No.s:
 Unpacked
 Packed
 ASCII Codes:
O O O O
BCD Digit O
BCD Digit 1
BCD Digit O
ASCII CODE
Segment Registers
 1 MB memory can not be
accessed at a time
 64kB partitions (Segments)
 Only 4 segments active
CS




Code Segment (Program)
Data Segment (Data)
Stack Segment (Stack)
Extra Segment (Data)
 16 bit segment registers
form base address of each
segment.
 User accessible
SS
DS
ES
Code Segment
Stack
Segment
Data Segment
Extra
Segment
Memory Segmentation




Data Segment B
Code Segment E
Stack Segment H
Extra Segment J
 Each segment starts from a
16-byte boundary. e.g.
00000H, 00010H, 00020H
 Can be contiguous, adjacent,
disjoint or overlapping.
A
B
Data: DS =
B
Code: CS =
E
C
D
E
F
G
Stack: SS =
H
Extra: ES =
J
H
J
k
I
Dedicated, Reserved & General use Memory
 00000H to 00013H Dedicated
Memory

Memory
For user defined interrupts(27x4)
 FFFFCH to FFFFFH Reserved
Memory

For use with future products
 FFFF0H to FFFFBH Dedicated
Memory


Reserved
For internal interrupts and
exceptions (5x4)
 00014H to 0007FH Reserved

• FFFFFH
Storage of HW reset JUMP
FFFF0H is the RESET location
• FFFFBH
Dedicated
8086
Memory
Address
Space
(00000H
to
FFFFFH)
• FFFF0H
• 0007FH
Reserved
• 00013H
Dedicated
• 00000H
8086 Registers
Instruction
Pointer
Stack
Pointers
Base
Pointer
Index
Registers
•
•
•
•
16 bit
Identifies offset address of next instruction
CS:IP= 20-bit physical address
Normally increments in step of 2
• Identifies offset address of top of STACK
• SS:SP= 20-bit physical address
• For data access in Stack segment
• Used with base addressing mode
• Used to pass argument to subroutine
•
•
•
•
SI and DI
Used with DS and ES as offset for data
Used with indexed addressing mode
Used for string operations
Data Registers
A
• AX: Word Multiply, Divide, I/O
• AL: Byte Multiply, Divide, I/O, Translate,
BCD Arithmatic
• AH: Byte Multiply, Divide
B
• BX: Translate
C
• CX: String Operations, Loops as counter
• CL: Variable shift and rotate
D
• DX: Word Multiply, Divide, Indirect I/O
Status Register
X
X
X
X
OF DF
IF
TF
SF
ZF
X
AF
X
PF
X
CF
CF
• Carry Flag: set if carry out or borrow in for MSB of
result
PF
• Parity Flag: sit if the result has even parity
AF
• Auxiliary Carry: set if carry out or borrow in at bit D3
for 8 bit operation or at bit D7 for 16 bit operation
ZF
• Zero Flag: set if the result of the last instruction is
Zero
SF
• Sign Flag: MSB of the Result
OF
• Over Flow Flag: Set if the signed operation result is
out of range
Status Register
X
X
X
X
OF DF
IF
TF
SF
ZF
X
AF
X
PF
X
CF
TF
• Trap Flag: If set the 8086 goes into single step mode
• Used for debugging the program
IF
• Interrupt Flag: If set enables maskable HW
interrupts. If reset the interrupts at INT pin will be
ignored
DF
• Direction Flag: Used for string operations
• If set the string instructions decrements address
Memory Address Generation
Effective
Address (IP)
16-bit Logical Address
0 0 0 0
16-bit Segment Address
Segment
Address (CS)
20-bit Physical Address
Stack
 Within memory map
 Used for temporary storage of data/address
 CALL, PUSH, POP, RET
 Organized as words (32k words)
 At startup SP=FFFEH making
 Stack bottom SS:FFFEH
 Top of stack: SS:SP
 End of stack: SS:0000H
SS:FFFE
Stack
Bottom
SS: SP
Stack Top
SS
SP
Stack
Segment
SS:0000
Stack End
 Data transferred word wide
 Stack decrements by 2 and stores a word (PUSH)
 Multiple stacks allowed with only one active at a time
Input / Output Address Space
 Separate memory and IO space.
 Range: 0000H to FFFFH
 Byte wide
Input/ Output
Address Space
OOOO
 Page 0: 0000H to 00FFH
 (Specific instructions)
 Reserved: 00F8H to 00FFH
Input /
Output
Map
FFFF
Addressing modes
 Way of locating data or operand
 An instruction may belong to one or more addressing
modes or to neither of the modes.


Depending on data types used in instruction
Depending on memory addressing modes
 Describes type of operand and way to access it for
instruction execution
Instruction types
 Sequential control flow
 After execution of instruction passes control to next
instruction
 e.g. arithmatic, logical, data transfer and processor control
instructions.
 Control transfer
 After execution of instruction passes control to some
predefined address or address specified in the instruction
 e.g. branch instructions, JUMP, CALL , RET, INT etc.
Addressing modes for sequential control
transfer Instructions
 Immediate
 Immediate data/operand is part of instruction, appearing on
successive byte/bytes
 e.g. MOV AX,9080H,
MOV BL,7FH
 Direct
 A 16-bit address(offset) is provided as a part of instruction
 e.g. MOV AX,[1080H],
MOV BL,[127FH]
 Here data resides in data segment, therefore, the effective
address for the instructions are ((DS)x10H) + 1080H and
((DS)x10H) + 127FH respectively.
Addressing modes for sequential control
transfer Instructions
 Register
 In this type of operation operand is stored in register and referred
to by register name
 All registers except IP can be used.
 e.g. MOV AX,BX,
MOV BL,AH
 Register Indirect
 In this mode the registers are holding the address of operand.
Using address from register content the operand is accessed
indirectly.
 Registers BX, DI or SI can be used with DS or ES.
 Default segment is DS
 e.g. MOV AX,[BX],
MOV CL,[BX]
 Here data resides in data segment, therefore, the effective address
for the instructions are ((DS)x10H) + BX and ((DS)x10H)+BX
respectively.
Addressing modes for sequential control
transfer Instructions
 Indexed
 In this mode the index registers are holding the address of
operand. In case of string instructions DS and ES are default
segments for DI and SI respectively
 Default segment is DS
 e.g. MOV AX,[SI],
MOV [DI],CL
 Here data resides in data segment, therefore, the effective address
for the instructions are ((DS)x10H) + SI and ((DS)x10H)+DI
respectively.
 Register Relative
 In this type of operation operand address is formed by adding 8bit or 16-bit offset with the content of any of the registers BX, BP,
SI and DI in default (DS or ES) segment.
 e.g. MOV AX,50H[BX],
MOVAH,1234H[DI]
 Effective addresses are ((DS)x10H) + BX + 50H and
((DS)x10H)+DI + 1234H respectively.
Addressing modes for sequential control
transfer Instructions
 Base Indexed
 In this mode the address of operand is formed by addition of
content of a base register (BX/BP) to the content of index
register (SI/DI). In case of such instructions DS and ES are
default segments.
 e.g. MOV AX,[BX][SI]
 The effective address for the instruction is ((DS)x10H) +
BX+SI
 Relative Base Indexed
 The effective address is formed by adding 8-bit or 16-bit
displacement with sum of content of a base register (BX/BP)
and an index register (SI/DI).
 e.g. MOV AX,50H[BX][SI]
 Effective addresses are ((DS)x10H) + BX + SI +50H.
Addressing modes for control transfer
Instructions
 Intra-segment & Inter-segment
 Method of passing destination address to processor
Intersegment direct
Intersegment
Intersegment indirect
Modes for
control transfer
instructions
Intrasegment indirect
Intrasegment
Intrasegment direct
Addressing modes for control transfer
Instructions
 Intra-segment Direct
 Destination lies in the same segment as the instruction lies.
 Immediate displacement value is defined in the instruction
 The displacement is calculated relative to the IP.
 Effective address = CS:(IP+8/16 bit displacement)
 8-bit displacement= short jump


JMP SHORT LABEL
16-bit displacement= long jump

JMP NEAR PTR LABEL
 Intra-segment Indirect
 Here the displacement is passed indirectly by either a register
or memory location
JMP[BX]
 JMP[BX + 2340H]

Addressing modes for control transfer
Instructions
 Inter-segment Direct
 Destination is in the different segment.
 New segment as well as Immediate displacement value is
defined in the instruction
 JMP 5555H:2222H
 Jump to effective address 2222H in segment 5555H
 Inter-segment Indirect
 Here the displacement is passed indirectly by either a
register or memory location
 JMP[2000]
 It seeks 2 consecutive words from the location defined
in the DS and that becomes new CS and IP respectively.