Introduction to asynchronous
circuit design:
specification and synthesis
Jordi Cortadella, Universitat Politècnica de Catalunya, Spain
Michael Kishinevsky, Intel Corporation, USA
Alex Kondratyev, Theseus Logic, USA
Luciano Lavagno, Università di Udine, Italy
Outline
• I: Introduction to basic concepts on
asynchronous design
• II: Synthesis of control circuits from STGs
• III: Advanced topics on synthesis of control
circuits from STGs
• IV: Synthesis from HDL and other synthesis
paradigms
Note: no references in the tutorial
Outline
•
•
•
•
•
•
•
What is an asynchronous circuit ?
Asynchronous communication
Asynchronous logic blocks
Micropipelines
Control specification and implementation
Delay models
Why asynchronous circuits ?
Synchronous circuit
R
CL
R
CL
CLK
Implicit synchronization
R
CL
R
Asynchronous circuit
Ack
R
CL
R
CL
R
CL
Req
Explicit synchronization: Req/Ack handshakes
R
Synchronous communication
1
1
0
0
1
0
• Clock edges determine the time instants
where data must be sampled
• Data wires may glitch between clock edges
(set-up/hold times must be satisfied)
• Data are transmitted at a fixed rate
(clock frequency)
Dual rail
1
1
1
0
0
0
• Two wires per bit
– “00” = spacer, “01” = 0, “10” = 1
• n-bit data communication requires 2n wires
• Each bit is self-timed
• Other delay-insensitive codes exist
Bundled data
1
1
0
0
1
0
• Validity signal
– Similar to an aperiodic local clock
• n-bit data communication requires n+1 wires
• Data wires may glitch when no valid
• Signaling protocols
– level sensitive (latch)
– transition sensitive (register): 2-phase / 4-phase
Example: memory read cycle
Valid address
Address
A
A
Valid data
Data
D
• Transition signaling, 4-phase
D
Example: memory read cycle
Valid address
Address
A
A
Valid data
Data
D
• Transition signaling, 2-phase
D
Outline
•
•
•
•
•
•
•
What is an asynchronous circuit ?
Asynchronous communication
Asynchronous logic blocks
Micropipelines
Control specification and implementation
Delay models
Why asynchronous circuits ?
Asynchronous modules
DATA
PATH
Data IN
start
Data OUT
done
req in
ack in
req out
CONTROL
ack out
• Signaling protocol:
reqin+ start+ [computation] done+ reqout+ ackout+ ackin+
reqin- start[reset]
done- reqout- ackout- ackin(more concurrency is also possible, e.g. by overlapping the return-tozero phase of step i-1 with the evaluation phase of step i)
Completion detection
C
•
•
•
done
•
•
•
Completion detection tree
Asynchronous latches: C element
Vdd
A
A
C
B
Z
B
B
Z
A
Z
A
0
0
1
1
B
0
1
0
1
Z+
0
Z
Z
1
B
A
Z
A
B
Gnd
Bundled-data logic blocks
logic
•
•
•
•
•
•
start
delay
done
Conventional logic + matched delay
Outline
•
•
•
•
•
•
•
What is an asynchronous circuit ?
Asynchronous communication
Asynchronous logic blocks
Micropipelines
Control specification and implementation
Delay models
Why asynchronous circuits ?
Control specification
A+
A
B+
A-
B-
B
A input
B output
Control specification
A+
B+
A
A-
B-
B
Control specification
A+
B+
A
C+
C
A-
B-
C-
B
C
Control specification
Ri
Ro
FIFO
cntrl
Ao
Ai
Ri+
Ro+
Ao+
Ai+
Ri-
Ro-
Ao-
Ai-
Ri
Ao
C
C
Ro
Ai
A simple filter: specification
Ain Rin
y := 0;
loop
x := READ (IN);
WRITE (OUT, (x+y)/2);
y := x;
end loop
IN
filter
Aout Rout OUT
A simple filter: block diagram
+
x
IN
Rin
Ain
Rx
OUT
y
Ax
Ry
Ay
control
Ra
Aa
Rout
Aout
• x and y are level-sensitive latches (transparent when R=1)
• + is a bundled-data adder (matched delay between Ra and Aa)
• Rin indicates the validity of IN
• After Ain+ the environment is allowed to change IN
• (Rout,Aout) control a level-sensitive latch at the output
A simple filter: control spec.
+
x
IN
Rin
Ain
Rx
OUT
y
Ax
Ry
Ay
Ra
Aa
control
Rout
Aout
Rin+
Rx+
Ry+
Ra+
Rout+
Ain+
Ax+
Ay+
Aa+
Aout+
Rin-
Rx-
Ry-
Ra-
Rout-
Ain-
Ax-
Ay-
Aa-
Aout-
A simple filter: control impl.
Rx Ax
Ay Ry
Ra Aa
Aout
C
Ain
Rout
Rin
Rin+
Rx+
Ry+
Ra+
Rout+
Ain+
Ax+
Ay+
Aa+
Aout+
Rin-
Rx-
Ry-
Ra-
Rout-
Ain-
Ax-
Ay-
Aa-
Aout-
Outline
•
•
•
•
•
•
•
What is an asynchronous circuit ?
Asynchronous communication
Asynchronous logic blocks
Micropipelines
Control specification and implementation
Delay models
Why asynchronous circuits ?
Taking delays into account
z+
x+
xy+
x
z
z-
x’
z’
y
yDelay assumptions:
• Environment: 3 times units
• Gates: 1 time unit
events: x+  x’-  y+  z+  z’-  x-  x’+  z-  z’+  y- 
time: 3
4
5
6
7
9
10
12
13
14
Taking delays into account
z+
x+
xy+
x
z
z-
y-
x’
z’
y
very slow
Delay assumptions: unbounded delays
events: x+  x’-  y+  z+  x-  x’+  ytime: 3
4
5
6
9
10
11
failure !
Gate vs wire delay models
• Gate delay model: delays in gates, no delays in wires
• Wire delay model: delays in gates and wires
Delay models for async. circuits
• Bounded delays (BD): realistic for gates and wires.
– Technology mapping is easy, verification is difficult
• Speed independent (SI): Unbounded (pessimistic)
delays for gates and “negligible” (optimistic) delays for
wires.
– Technology mapping is more difficult, verification is easy
• Delay insensitive (DI): Unbounded (pessimistic) delays
for gates and wires.
– DI class (built out of basic gates) is almost empty
• Quasi-delay insensitive (QDI): Delay insensitive
except for critical wire forks (isochronic forks).
– Formally, it is the same as speed independent
– In practice, different synthesis strategies are used
BD
DI
SI  QDI
Motivation (designer’s view)
• Modularity
– Plug-and-play interconnectivity
• Reusability
– IPs with abstract timing behaviors
• High-performance
– Average-case performance (no worst-case delay
synchronization)
– No clock skew (local timing assumptions
instead)
• Many interfaces are asynchronous
– Buses, networks, ...
Motivation (technology aspects)
• Low power
– Automatic clock gating
• Electromagnetic compatibility
– No peak currents around clock edges
• Robustness
– High immunity to technology and environment
variations (in-die variations, temperature,
power supply, ...)
Problems
• Concurrent models for specification
– CSP, Petri nets, ...
• Difficult to design
– Hazards, synchronization
• Complex timing analysis
– Difficult to estimate performance
• Difficult to test
– No way to stop the clock
But we have some success stories...
•
•
•
•
•
•
Philips
AMULET microprocessors
Sharp
Intel (RAPPID)
IBM (interlocked pipeline)
Start-up companies:
– Theseus Logic, Cogency, ADD
• ...
Introduction to
asynchronous circuit design:
specification and synthesis
Part II:
Synthesis of control circuits
from STGs
Outline
•
•
•
•
•
•
Overview of the synthesis flow
Specification
State graph and next-state functions
State encoding
Implementability conditions
Speed-independent circuit
– Complex gates
– C-element architecture
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
x
y
x
z
y
z
z+
x+
x-
y+
z-
y-
Signal Transition Graph (STG)
xyz
000
x+
z+
x+
z+
xy+
y-
z-
y-
x-
100
y+
101
110
y+
z+
001
111
y+
x-
011
z-
010
xyz
000
Next-state functions
x+
x  z (x  y)
y  zx
z  x  y z
z+
y-
x-
100
y+
101
110
y+
z+
001
111
y+
x-
011
z-
010
Next-state functions
x  z (x  y)
y  zx
z  x  y z
x
y
z
Outline
•
•
•
•
•
•
Overview of the synthesis flow
Specification
State graph and next-state functions
State encoding
Implementability conditions
Speed-independent circuit
– Complex gates
– C-element architecture
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
VME bus
Bus
DSr
Data
Transceiver
LDS
LDTACK
Device
D
DSr
DSw
LDS
VME Bus
Controller LDTACK
D
DTACK
DTACK
Read Cycle
STG for the READ cycle
DSr+
LDS+
LDTACK+
DTACK-
D+
DTACK+
LDTACK-
LDS-
D
DSr
DTACK
VME Bus
Controller
LDS
LDTACK
DSr-
D-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Choice: Read and Write cycles
LDTACK-
LDS-
DSr+
DSw+
LDS+
D+
LDTACK+
LDS+
D+
DTACK-
DTACK-
LDTACK+
DTACK+
D-
DSr-
DTACK+
D-
DSw-
LDTACK-
LDS-
Circuit synthesis
• Goal:
– Derive a hazard-free circuit
under a given delay model and
mode of operation
Outline
•
•
•
•
•
•
Overview of the synthesis flow
Specification
State graph and next-state functions
State encoding
Implementability conditions
Speed-independent circuit
– Complex gates
– C-element architecture
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
STG for the READ cycle
DSr+
LDS+
LDTACK+
DTACK-
D+
DTACK+
LDTACK-
LDS-
D
DSr
DTACK
VME Bus
Controller
LDS
LDTACK
DSr-
D-
Binary encoding of signals
DSr+
LDS+
LDTACKDSr+
LDS-
LDTACK+
DSr+
D+
DTACK-
LDTACKDTACK-
LDS-
LDS-
DTACK-
DDTACK+
DSr-
LDTACK-
Binary encoding of signals
DSr+
10000
LDS+
LDTACK-
LDTACK-
DSr+
10010
LDS-
LDTACK+
DTACK-
LDS-
DSr+
10110
D+
DTACK-
10110
LDTACK-
01100
LDS-
DTACK-
01110
00110
D-
DTACK+
DSr-
(DSr , DTACK , LDTACK , LDS , D)
Excitation / Quiescent Regions
ER (LDS+)
LDS+
QR (LDS-)
LDS-
QR (LDS+)
LDS-
LDS-
ER (LDS-)
Next-state function
01
LDS+
11
00
LDS-
LDS-
LDS-
10
10110
10110
Karnaugh map for LDS
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
1
1
1
10
0
0
-
0
10
0
0
- 0/1?
Outline
•
•
•
•
•
•
Overview of the synthesis flow
Specification
State graph and next-state functions
State encoding
Implementability conditions
Speed-independent circuit
– Complex gates
– C-element architecture
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Concurrency reduction
DSr+
LDS+
DSr+
LDSDSr+
10110
10110
LDS-
LDS-
Concurrency reduction
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK-
DTACK+
LDS-
DSr-
D-
State encoding conflicts
LDS+
LDTACK+
LDTACK-
LDS-
10110
10110
Signal Insertion
CSC+
LDS+
LDTACK+
LDTACK-
LDS-
101101
101100
D-
DSr-
CSC-
Outline
•
•
•
•
•
•
Overview of the synthesis flow
Specification
State graph and next-state functions
State encoding
Implementability conditions
Speed-independent circuit
– Complex gates
– C-element architecture
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Complex-gate implementation
LDS  D  csc
DTACK  D
D  LDTACKcsc
csc  DSr  (csc  LDTACK )
• Under what conditions does a hazard-free
implementation exist?
Implementability conditions
• Consistency
– Rising and falling transitions of each signal
alternate in any trace
• Complete state coding (CSC)
– Next-state functions correctly defined
• Persistency
– No event can be disabled by another event
(unless they are both inputs)
Implementability conditions
• Consistency + CSC + persistency
• There exists a speed-independent circuit
that implements the behavior of the STG
(under the assumption that any Boolean function
can be implemented with one complex gate)
Persistency
100
a-
000
c+
001
b+
b+
a
c
b
a
c
b
is this a pulse ?
Speed independence  glitch-free output behavior under any delay
Speed-independent implementations
• How can the implementability conditions
– Consistency
– Complete state coding
– Persistency
be satisfied?
• Standard circuit architectures:
– Complex (hazard-free) gates
– C elements with monotonic covers
– “Standard” gates and latches
a+
0000
a+
b+
1000
b+
1100
a-
a-
0100
c+
c+
0110
d+
d+
0111
a+
a+
1111
b-
b-
1011
a-
a-
cd-
0011
c-
1001
c- a-
0001
d-
ab
cd
00
00
0
01
0
11
0
0000
10
a+
1000
0
b+
1100
01
11
1
0
1
1
1
1
a-
0100
c+
ER(d+)
0110
d+
10
0111
1
a+
1111
b-
1011
a-
0011
ER(d-)
c-
1001
c- a-
0001
d-
ab
cd
00
00
01
0
0
11
0
10
0
0000
a+
1000
b+
1100
01
11
1
0
1
1
1
1
a-
0100
c+
0110
d+
10
1
0111
a+
1111
d  ad  a c
b-
1011
a-
0011
Complex gate
c-
1001
c- a-
0001
d-
Implementation with C elements
S
R
C
z
• • •  S+  z+  S-  R+  z-  R-  • • •
• S (set) and R (reset) must be mutually exclusive
• S must cover ER(z+) and must not intersect ER(z-)  QR(z-)
• R must cover ER(z-) and must not intersect ER(z+)  QR(z+)
ab
cd
00
00
0
01
0
11
0000
10
0
a+
1000
0
b+
1100
01
11
1
0
1
1
a-
0100
c+
1
1
0110
d+
10
0111
1
a+
1111
b-
c
ac
1011
S
R
C
d
a-
0011
c-
1001
c- a-
0001
d-
0000
a+
1000
b+
1100
a-
but ...
0100
c+
0110
d+
0111
a+
1111
b-
c
ac
1011
S
R
C
d
a-
0011
c-
1001
c- a-
0001
d-
Assume that R=ac has an unbounded delay
Starting from state 0000 (R=1 and S=0):
0000
a+
1000
b+
1100
a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;
a-
0100
c+
R+ disabled (potential glitch)
0110
d+
0111
a+
1111
b-
c
ac
1011
S
R
C
d
a-
0011
c-
1001
c- a-
0001
d-
ab
cd
00
00
0
01
11
0
0000
10
0
a+
1000
0
b+
1100
01
11
1
0
1
1
a-
0100
c+
1
1
0110
d+
10
0111
1
a+
1111
b-
c
S
ab c
R
1011
C
d
Monotonic covers
a-
0011
c-
1001
c- a-
0001
d-
C-based implementations
c
S
ab c
R
c
c
d
C
b
a
weak
d
a
b
generalized C element (gC)
C
d
Introduction to
asynchronous circuit design:
specification and synthesis
Part III:
Advanced topics on synthesis of control
circuits from STGs
Outline
• Logic decomposition
– Hazard-free decomposition
– Signal insertion
– Technology mapping
• Optimization based on timing information
– Relative timing
– Timing assumptions and constraints
– Automatic generation of timing assumptions
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
No Hazards
abcx
1000
b+
1100
a0100
c+
0110
11 0 0
01 1 1
00 0 1
a
b
c
x
0
Decomposition May Lead to Hazards
abcx
1000
b+
1100
a0100
0100
c+
0110
111000
011111
001110
a
z
b
000011
c
x
000010
Decomposition
• Acknowledgement
• Generating candidates
• Hazard-free signal insertion
– Event insertion
– Signal insertion
Global acknowledgement
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
b
a
z
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
b
a
z
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
z
b
a
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c 0
b
0 z
a
a
b
d
y
How about 2-input gates ?
d-
b+
d+
y+
a-
y-
c+
d-
c-
d+
z-
b-
z+
c+
a+
c-
c
z
a
b
y
d
Strategy for logic decomposition
• Each decomposition defines a new internal signal
• Method: Insert new internal signals such that
– After resynthesis, some large gates are decomposed
– The new specification is hazard-free
• Generate candidates for decomposition using
standard logic factorization techniques:
– Algebraic factorization
– Boolean factorization (boolean relations)
Decomposition example
1001
zy+
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
1011
w+
x+
0101
x+ z-
0011
0100
x-
x+ y+
y-
z+
0111
wxyz
z-
w-
w+
y+
x+
x-
z+
1001
z-
y+
1010
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
yz=0
1011
x+
0011
0100
x-
z+
0111
yz=1
w
y
z
w+
0101
x+ z-
x+ y+
x
y
z
x
w
w
z
x
y
z
y
C
y
C
z
s=1
z-
y+
1010
1000
s- y+
1001
s- z1000
y-
y1011
s1001
w-
0001
w- zx+
1010
0000
0101
w- y+
x+ z-
0010
x+ y+
s=0
0110
s-
w+
0100
z+
0011
z-
w-
w+
y+
x+
x-
x0111
s+
0111
z+
s+
s=1
z-
y+
1010
1000
s- y+
1001
s- z1000
x
y1011
s1001
w+
0001
w- zx+
x+ y+
s=0
0110
s
y
z
w-
1010
0000
0101
w- y+
x+ z-
0010
w
0100
z+
w
0011
x-
x
w
z
0111
s+
x
0111
y
z
y
C
y
C
z
z-
y+
1010
1001
1001
yw-
1000
0001
w- z-
w- y+
0010
0000
0110
yz=0
1011
x+
0100
z+
w
y
z
w+
0101
x+ z-
x+ y+
x
y
z
x
w
0011
w
z
x0111
yz=1
x
y
z
y
C
y
C
z
s=1 1001
s-
zy+
1000
1001
y-
w-
0001
w- zx+
x+ y+
s=0
0110
s-
w+
1010
0000
0101
w- y+
x+ z0010
y-
1011
0100
z+
0011
z-
w-
w+
y+
x+
x-
x0111
s+
0111
z+
z- is delayed by the new transition s- !
s+
s=1 1001
s-
zy+
1000
1001
w+
w-
0001
w- zx+
x+ y+
s=0
0110
w
1011
1010
0000
0101
w- y+
x+ z0010
x
y-
0100
z+
y
z
0011
x0111
s+
0111
x
w
w
z
y
x
y
z
C
y
C
z
Decomposition
(Algebraic, Boolean relations)
F
Sr
C
D
C
C
D
Sr
Sr
C
NO
D
Hazard-free ?
(Event insertion)
C
YES
Decomposition
(Algebraic, Boolean relations)
F
Sr
C
D
until no more progress
Sr
C
NO
D
Hazard-free ?
(Event insertion)
C
YES
Boolean decomposition
x1
F
xn
f = F (x1,…,xn)
f
x1
xn
h1
H
G
hm
f = G(H(x1,…,xn))
Our problem: Given F and G, find H
f
h1
h2
state
s1
s2
s3
s4
dc
C
f
f
0
0
1
1
-
next(f)
0
1
0
1
-
(h1,h2)
(0,-) (-,0)
(1,1)
(0,0)
(-,1) (1,-)
(-,-)
This is a Boolean Relation
ya+
c-
a
c
d
d-
ac+
F
acd  y(c  d )
y
a+
S
y+
Rs
cad+
c+
R
y
ya+
c-
a
c
d
d-
a-
acd  y(c  d )
y
c+
a+
y+
cad+
c+
a
c
d
c
d
Rs
y
ya+
c-
a
c
d
d-
a-
acd  y(c  d )
y
c+
a+
a
y+
cad+
c+
cd  yc
Rs
y
ya+
c-
a
c
d
d-
a-
acd  y(c  d )
y
c+
a+
a
y+
cad+
c+
d
c
D
Rs
y
Technology mapping
• Merging small gates into larger gates introduces
no new hazards
• Standard synchronous technique can be applied,
e.g. BDD-based boolean matching
• Handles sequential gates and combinational
feedbacks
• Due to hazards there is no guarantee to find
correct mapping (some gates cannot be
decomposed)
• Timing-aware decomposition can be applied in
these rare cases
Specification
(STG)
Reachability analysis
State Graph
State encoding
Design
flow
SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Gate netlist
Timing assumptions in design flow
• Speed-independent: wire delays after a fork
smaller than fan-out gate delays
• Burst-mode: circuit stabilizes between
two changes at the inputs
• Timed circuits: Absolute bounds on gate / environment
delays are known a priori (before physical design)
Relative Timing Circuits
• Assumptions: “a before b”
– for concurrent events: reduces reachable state space
– for ordered events: permits early enabling
– both increase don’t care space for logic synthesis =>
simplify logic (better area and timing)
• “Assume - if useful - guarantee” approach: assumptions are
used by the tool to derive a circuit and required timing
constraints that must be met in physical design flow
• Applied to design of the Rotating Asynchronous Pentium Processor(TM)
Instruction Decoder (K.Stevens, S.Rotem et al. Intel Corporation)
Relative Timing Asynchronous Circuits
Speed-independent C-element
b
a
Timing assumption (on environment):
b
a
c
a- before bc
RT C-element: faster,smaller; correct only under
timing constraint: a- before b-
State Graph (Read cycle)
DSr+
LDS+
LDTACKDSr+
LDS-
LDTACK+
DSr+
D+
DTACK-
LDTACKDTACK-
LDS-
LDS-
DTACK-
DDTACK+
DSr-
LDTACK-
Lazy Transition Systems
ER (LDS+)
LDS+
LDS-
LDSDTACK-
LDS-
FR (LDS-)
ER (LDS-)
Event LDS- is lazy: firing = subset of enabling
Timing assumptions
• (a before b) for concurrent events:
concurrency reduction for firing and enabling
• (a before b) for ordered events:
early enabling
• (a simultaneous to b wrt c) for triples of events:
combination of the above
Speed-independent Netlist
DSr+
LDS+
LDTACK+
D+
DTACKDTACK+
LDTACK-
D-
LDSD
DTACK
LDS
map
DSr
DSr-
csc
LDTACK
Adding timing assumptions (I)
DSr+
LDS+
LDTACK+
D+
DTACKDTACK+
LDTACK-
D-
LDSD
DTACK
SLOW
LDTACK- before DSr+
LDS
map
DSr
DSr-
csc
FAST
LDTACK
Adding timing assumptions (I)
DSr+
LDS+
LDTACK+
D+
DTACKDTACK+
LDTACK-
D-
LDSD
DTACK
LDTACK- before DSr+
LDS
map
DSr
DSr-
csc
LDTACK
State space domain
DSr+
LDTACK- before DSr+
LDTACK-
State space domain
DSr+
LDTACK- before DSr+
LDTACK-
State space domain
DSr+
LDTACK- before DSr+
LDTACK-
Two more unreachable states
Boolean domain
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
1
1
1
10
0
0
-
0
10
0
0
- 0/1?
Boolean domain
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
1
1
1
10
0
0
-
-
10
0
0
-
1
One more DC vector for all signals
One state conflict is removed
Netlist with one constraint
DSr+
LDS+
LDTACK+
D+
DTACKDTACK+
LDTACK-
D-
LDSD
DTACK
LDS
map
DSr
DSr-
csc
LDTACK
Netlist with one constraint
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK
DTACKDTACK+
DSr-
D-
LDSD
TIMING CONSTRAINT
LDTACK- before DSr+
DSr
LDS
LDTACK
Timing assumptions
• (a before b) for concurrent events:
concurrency reduction for firing and enabling
• (a before b) for ordered events:
early enabling
• (a simultaneous to b wrt c) for triples of events:
combination of the above
Ordered events: early enabling
b
a
F
b
a
c
G
a
a
b
b
c
c
Logic for gate c may change
c
Adding timing assumptions (II)
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK
DSr
DTACKDTACK+
DSr-
D-
LDSD
D- before LDS-
LDS
LDTACK
Boolean domain
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
1
1
1
10
0
0
-
-
10
0
0
-
1
Boolean domain
LDS = 1
LDS = 0
D
LDTACK
DTACK
DSr
00
01
11
10
D
LDTACK
DTACK
DSr
00
01
11
10
00
0
0
-
1
00
-
-
-
1
01
-
-
-
-
01
-
-
-
-
11
-
-
-
-
11
-
-
1
1
10
0
0
-
-
10
0
0
-
1
One more DC vector for one signal: LDS
If used: LDS = DSr, otherwise: LDS = DSr + D
Before early enabling
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK
DSr
DTACKDTACK+
DSr-
D-
LDSD
LDS
LDTACK
Netlist with two constraints
DSr+
LDS+
LDTACK+
D+
LDTACK-
DTACK
DSr
DTACKDTACK+
DSr-
D-
LDSD
TIMING CONSTRAINTS
LDTACK- before DSr+
and D- before LDS-
LDS
LDTACK
Both timing assumptions are used for optimization and become constraints
Backannotation of Timing Constraints
• Timed circuits require post-verification
• Can synthesis tools help ?
– Report the least stringent set of timing constraints
required for the correctness of the circuit
– Not all initial timing assumptions may be required
• Petrify reports a set of constraints for order of
firing that guarantee the circuit correctness
Design Flow with Timing
Specification
(STG + user
assumptions)
Reachability analysis
Lazy State Graph
Timing-aware state encoding
Automatic Timing Assumptions
Lazy SG with
CSC
Boolean minimization
Next-state
functions
Logic decomposition
Decomposed
functions
Technology mapping
Required Timing Constraints
Gate netlist
VME bus spec after transforms
ldtack+
p2+
ldtack+
p1-
p8-
d+
lds+
p11-
p3+
lds+
D+
dtack+
p1+
dsr+
p2-
p7-
dsr-
p9+
ldtack-
p9-
p4+
p10-
dsr+
ldtack-
p8+
dtack+
lds-
dtack-
Reductions
Transforms
d-
p3p11+
p5+
p9-
p6-
lds-
dtack-
p10+
p7+
dsr-
p4-
p6+
p9+
D-
p5-