CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
JULY15
ASSESSMENT_CODE BCA2050_JULY15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10920
QUESTION_TEXT
Explain the features of microprogramming & discuss the various
applications of microprogramming.
SCHEME OF
EVALUATION
Features (page 295)
Each point 1 mark(1*5)=5 marks
Applications (page297)
Microprogramming …..predecessors [1 mark]
This technique…..microprocessors[1 mark]
Microprogramming is used …..etc[1 mark]
In order……chip-[2 marks]
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10921
QUESTION_TEXT
Explain contention problems in multiprocessor systems. Discuss
different types of contention.
SCHEME OF
EVALUATION
Contention:
The contention ratio in ….. will be lower-[2 mark]
A shared memory multiprocessor …..system-[2 mark]
Types of contention
1) Memory-[2 mark]
2) communication contention :[2 mark]
3) Hot spot contention: [2 mark]
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
10922
QUESTION_TEXT
Explain multiprocessing in brief. Discuss its advantages and
disadvantages.
SCHEME OF
EVALUATION
Multiprocessing: multiprocessing is concerned with …. same
progress(page 272) (3 mark)
Advantages(page 273)
Three point- Each[1mark]=>(1*3)=[3 marks]
Disadvantages (page 274)
Four points –Each[1 mark}=>(1*4)=[4 marks]
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72891
QUESTION_TEXT
Explain the classification of memory systems based on the following
a. Location
b. Access Method
c. Performance
SCHEME OF
EVALUATION
a. Location:
• CPU: The CPU requires its own local memory in the form of registers
and also the control unit requires local memories which are fast and
accessible. (1 mark)
• Internal: It is often equated with the main memory. There are other
forms of internal memory. (0.5 mark)
• External: It consists of peripheral storage devices like hard disks,
magnetic disks, tapes, CDs etc. (0.5 mark)
b. Access Methods:
• Sequential: Tape units have sequential access. Data are generally
stored in units called “records”. Data is accessed sequentially; the
records may be passed until record that is searched for is found. The
access time to a certain record is highly variable.(1 mark)
• Direct: Individual blocks or records have a unique address based on
physical location. A block may contain a group of data. Access is
accomplished by direct address to reach general vicinity, plus sequential
searching, counting or waiting to reach the final location. Disks units
have direct access. (1 mark)
• Random: Each addressable location in the memory has a unique
physically wired-in addressing mechanism. The time to access a given
location is independent of the sequence of prior access and constant.
Any location can be selected at random and directly addressed and
accessed. (1 mark)
• Associative: This is a random- access type of memory that enables
one to make a comparison of desired bit locations within a word for a
specified match, and do it for all words simultaneously. Thus a word is
retrieved based on a portion of its contents rather than its address.
Some cache memories may employ associative access. (1 mark)
c. Performance:
• Access time: For random access memory, this is the time it takes to
perform a read or write operation. That is, the time from the instant
that an address is presented to the memory to the instant that data
have been stored or made available for use. For non- random-access
memory, access time is the time it takes to position the read-write
mechanism at the desired location. 1.5M
• Cycle time: Applied to random access memory. It consists of the
access time plus any additional time required before a second access
can commence. (0.5 mark)
• Transfer rate: this is the rate at which data can be transferred into
or out of a memory unit. For random-access memory, it is equal to
(1/< cycle-time >)
For non-random-access memory,
Tn=Ta+N/R
Where Tn=Average time to read or write N bits
Ta=Average access time
N=number of bits
R=transfer rate in bits per second. (2 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72892
QUESTION_TEXT
Write a note on instructions format.
SCHEME OF
EVALUATION
Instruction Formats
Instruction Format is defined as the layout of bits in an instruction in
terms of its constituent parts. An Instruction Format must include
opcode implicitly or explicitly and one or more operand(s). For, most
instruction sets have usually more than one instruction format.
Instruction Length
Most important design issue is the length of an instruction. It is affected
by and affects Memory size, Memory organization, Bus structure, CPU
complexity, CPU speed. There is a trade off between powerful
instruction repertoire and saving space.
Number of addressing modes: Some times addressing mode is implicit
in the instruction or may be certain opcodes call for indexing.
Number of operands: Typically today’s machines provide two
operands. Each operand may require its own mode indicator or the use
of indicator is limited to one of the address fields.
Register versus memory: A machine must have registers so that the
data can be brought into the CPU for processing.
Number of register sets: Almost all machines have a set of general
purpose registers, with typically 8 or 16 registers in it.
Address range: For addresses that refer to the memory locations, the
range of addresses is related to the number of address bits.
Address granularity: It is concerned with addresses that refer to the
memory other than registers.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
125691
QUESTION_TEXT
Discuss Replacement Algorithms for Write policy, Write through, Write
back, Write once problem, and Line size.
Write Policy: Before a block that is resident in the cache can be replaced,
it is necessary to consider whether it has been altered in the cache but not
in the main memory. (2 marks)
Write through: All write operations are both directly done to main
memory and to cache. Main memory always contains valid content. (2
marks)
SCHEME OF
EVALUATION
Write back: Writes are only done to cache. There is an UPDATE bit is
set, its content is written to main memory. Problem is that portions of
main memory are invalid for certain period of time. If other devices
access those locations, they will get wrong contents. Therefore access to
main memory by I/O modules can only be allowed through the
cache. (2 marks)
Write once problem: if there are other cache’s in the system (e.g.
multiprocessor system sharing the same main memory), even in “write
through”, other cache’s may contain invalid content.
(2 marks)
Line size: Greater the size more hit (+) but also more line
replacements (–). Too big line size less chance of hot for some
parts of the block. Researchers suggest that 2 to 8 words seem
reasonably close to optimum. (2 marks)