HDL Co-Simulation
This material exempt per Department of Commerce license exception TSU
© 2005 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
• Identify the blocks necessary for HDL co-simulation
• Describe the steps involved in performing HDL co-simulation
© 2005 Xilinx, Inc. All Rights Reserved
Outline
• Introduction
• Co-Simulation Support Blocks
– Black Box
– Simulation Multiplexer
– ModelSim
• HDL Co-Simulation Process
• Summary
• Lab 2: MAC FIR Filter Verification Using
HDL Co-Simulation
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-Simulation
Supports Legacy Code
• Being able to include legacy code is essential for many DSP
system designers
• Legacy (or new) HDL code can be imported into the Simulink
tool
– A new black box function allows designers to import legacy HDL code
– Legacy code can be simulated in the Simulink tool to significantly reduce
development time
• HDL is co-simulated transparently
– Legacy HDL can be simulated by using the industry-standard Mentor Graphics
ModelSim or Xilinx ISE Simulator (ISIM) simulation tools directly from the Simulink
framework
• A single HDL simulator for multiple black boxes
• The time scale in the ModelSim/ISIM tool matches that in the Simulink
tool
© 2005 Xilinx, Inc. All Rights Reserved
Using Black Box for
HDL Co-Simulation
Legacy
HDL
Simulation
ISIM
© 2005 Xilinx, Inc. All Rights Reserved
Real-Time Verification
Outline
• Introduction
• Co-Simulation Support Blocks
– Black Box
– Simulation Multiplexer
– ModelSim
• HDL Co-Simulation Process
• Summary
• Lab 2: MAC FIR Filter Verification Using HDL CoSimulation
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-Simulation
Support Blocks
• System Generator libraries provide both high-level functions and basic functions
for building systems
• You may, however, have IP blocks or have a need to build IP blocks with your HDL
modules. These HDL modules must be simulated in conjunction with other System
Generator library blocks
• Supported blocks for performing HDL co-simulation
– Black Box block
– ModelSim block
– Simulator Multiplexer block
• The Black Box block provides an interface between the Simulink model and the
structural HDL source code
• The ModelSim block provides a means to invoke the ModelSim simulator and the
data exchange between the Simulink simulator and the ModelSim simulator
© 2005 Xilinx, Inc. All Rights Reserved
Black Box Block
• The Black Box block provides a way to incorporate non-Xilinx
blockset functions into a System Generator model
• It is needed to incorporate hardware description language (VHDL
or Verilog) models into System Generator
• The block is used to specify both the simulation behavior in the
Simulink tool and the implementation files to be used during code
generation with System Generator
• It assumes the interface (ports and parameters) of the function it
implements, and its ports produce and consume the same types of
signals as other System Generator blocks
• Black box HDL code can be co-simulated with the Simulink tool by
using either ModelSim or ISIM simulator
© 2005 Xilinx, Inc. All Rights Reserved
Black Box Requirements
• An HDL component associated with a black box must adhere to
the following System Generator requirements and conventions
– The entity name must not collide with any other entity name in the design
– Bidirectional ports are not allowed on the top-level black box entity
– For Verilog black boxes, the module and port names must be lower case
and must follow standard VHDL naming conventions
– Any port that is not a clock or clock enable must be of type
std_logic_vector. (For Verilog black boxes, ports must be of vector type;
e.g., input[3:0] din; input [0:0] dout)
– Any port that is a clock or clock enable must be of type std_logic (for
Verilog black boxes, ports must be of non-vector inputs; e.g., input clk)
• Every non-combinational HDL must have a separate clock and
clock enable port for each associated sample rate in the Simulink
tool
© 2005 Xilinx, Inc. All Rights Reserved
Black Box Requirements
• Clock and clock enable ports in black box HDL should be
expressed as follows
– Clock and clock enables must appear as pairs (i.e., for every clock, there is
a corresponding clock enable, and vice-versa)
– Although a black box can have more than one clock port, a single clock
source is used to drive each clock port
– Only the clock enable rates differ
– Each clock name (and clock enable name) must contain the substring CLK
(and CE)
– The name of a clock enable must be the same as that for the corresponding
clock, but with CE substituted for CLK. For example, if the clock is named
src_clk_1, then the clock enable must be named src_ce_1
• Clock and clock enable ports are not visible on the black box block
© 2005 Xilinx, Inc. All Rights Reserved
Black Box M-Configuration File
• A black box must describe its interface through a MATLAB M-function
– For example, ports and generics, its implementation, and optionally, its simulation model
through an HDL co-simulator
• The name of this function must be specified in the block parameter
dialog box under the Block Configuration M-Function parameter
• The configuration M-function is generated automatically by the system
generator and performs the following:
– Specifies the top-level entity name of the HDL component that should be associated with
the black box
– Selects the language (i.e., VHDL or Verilog)
– Describes ports, including type, direction, bit width, binary point position, name, and
sample rate
– Defines any generics required by the black box HDL
– Specifies the black box HDL and other files (e.g., EDIF) that are associated with the block
– Defines the clocks and clock enables for the block
– Declares whether the HDL has any combinational feed-through paths
© 2005 Xilinx, Inc. All Rights Reserved
Configuration M File
function fir_blackbox_config(this_block)
% Revision History:
%
% 03-Mar-2006 (07:07 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% R:\training\dsp_flow\labs\lab3\fir_blackbox.vhd
%
Specify HDL Language
%
this_block.setTopLevelLanguage('VHDL');
this_block.setEntityName('fir_blackbox');
Specify top-level entity
% System Generator has to assume that
yourcombinatorial
entity has a combinational
feed through;
Pure
path
% if it doesn't, then comment out the following line:
this_block.tagAsCombinational;
© 2005 Xilinx, Inc. All Rights Reserved
Configuration M File
this_block.addSimulinkInport('reset');
this_block.addSimulinkInport('din');
this_block.addSimulinkOutport('dout');
dout_port = this_block.port('dout');
dout_port.setType(‘UFix_27_0');
Specify data format for ports
% ----------------------------Port error checking
if (this_block.inputTypesKnown)
% do input type checking, dynamic output type and generic setup in this code block.
if (this_block.port('reset').width ~= 1);
this_block.setError('Input data type for port "reset" must have width=1.');
end
end % if(inputTypesKnown)
© 2005 Xilinx, Inc. All Rights Reserved
Configuration M File
if (this_block.inputRatesKnown)
setup_as_single_rate(this_block,'input_clk','input_ce')
end % if(inputRatesKnown)
% Add addtional source files as needed.
% |------------% | Add files in the order in which they should be compiled.
% | If two files "a.vhd" and "b.vhd" contain the entities
% | entity_a and entity_b, and entity_a contains a
% | component of type entity_b, the correct sequence of
% | addFile() calls would be:
Design files including HDL, netlists,
% | this_block.addFile('b.vhd');
Memory initialization files, etc.
% | this_block.addFile('a.vhd');
% |------------this_block.addFile('coregen\fir.edn');
this_block.addFile('coregen\COEF_BUFFER.mif');
this_block.addFile('coregen\fir.mif');
this_block.addFile('coregen\fir.vhd');
this_block.addFile('fir_blackbox.vhd');
© 2005 Xilinx, Inc. All Rights Reserved
Black Box Block Parameters
• Specify the name of the
Configuration M-Function that is
associated with the black box
• Indicate the Simulation Mode
(Inactive or Use HDL CoSimulation)
–
When the mode is Inactive, the
black box ignores all input data and
writes zeroes to its output ports
– Usually for this mode, the black
box should be coupled, using a
Simulation Multiplexer block, with a
parallel simulation model
• Indicate the helperblock to be used
during HDL Co-Simulation
© 2005 Xilinx, Inc. All Rights Reserved
Black Box Block Parameters
• Two simulators support
– Xilinx ISIM Simulator
• No helper block needed
– ModelTech ModelSim
Simulator
• Set Simulation mode to
External Simulator
• Requires ModelSim helper
block
• List helper block name
© 2005 Xilinx, Inc. All Rights Reserved
Simulation Multiplexer
• The Simulation Multiplexer is a System
Generator block that allows two portions of a
design to work in parallel, with simulation
results provided by the first portion and
hardware providing the second
– This is useful when a subsystem is defined in the
usual way with Simulink blocks, but black box HDL is
used to implement the subsystem in hardware or black
box HDL is used with the HDL Co-Simulator and the
simulator is made inactive
– Another use of the multiplexer is to switch between
black boxes that incorporate different types of HDL.
One black box might provide behavioral HDL to be
used in simulation, and the other might provide RTL to
be used for implementation
© 2005 Xilinx, Inc. All Rights Reserved
Simulation Multiplexer
Block Parameters
• The For Simulation, Pass
Through Data from Input Port
parameter determines which
input port (either 1 or 2) is used
for simulation
• The For Generation, Pass
Through Data from Input Port
parameter determines which
input port (either 1 or 2) is used
for generation
© 2005 Xilinx, Inc. All Rights Reserved
ModelSim Block
• The ModelSim HDL co-simulation block configures and controls co-simulation
for one or several black boxes
• The block performs the following
– Constructs the additional VHDL required to allow black box HDL to be simulated
inside the ModelSim tool
– Spawns a ModelSim session when a Simulink simulation starts
– Mediates the communication between the Simulink and ModelSim tools
– Reports whatever errors are detected when black box HDL is compiled
– Terminates ModelSim, if appropriate, when the simulation is complete
• During a simulation, each ModelSim block spawns one copy of ModelSim, and,
therefore, uses one ModelSim license
• If licenses are scarce, several black boxes can share the same block. Except for
minor reductions in flexibility, nothing is lost with this approach
• The time scale in ModelSim matches that in Simulink; i.e., one second of
Simulink simulation time corresponds to one second of ModelSim simulation
time
© 2005 Xilinx, Inc. All Rights Reserved
ModelSim Block Parameters
• The ModelSim block is started in the
directory named by this field
– The directory is created, if necessary
– The directory can be specified as an
absolute or relative path
• When this checkbox is selected, the
ModelSim waveform window opens
automatically, displaying a standard
set of signals
• When this checkbox is selected, the
ModelSim session is left open after
the Simulink simulation has finished
• To use Verilog Unisim library check
this box
• To specify the script, select Add
Custom Scripts and enter the
script name (e.g., myscript.do) in
the Script to Run After “vsim” field
© 2005 Xilinx, Inc. All Rights Reserved
Outline
• Introduction
• Co-Simulation Support Blocks
– Black Box
– Simulation Multiplexer
– ModelSim
• HDL Co-Simulation Process
• Summary
• Lab 2: MAC FIR Filter Verification Using HDL CoSimulation
© 2005 Xilinx, Inc. All Rights Reserved
HDL Import Flow
Top-level HDL file to be imported
HDL has
clk, ce and ports that match
requirements
Yes
No
Create HDL wrapper for the toplevel HDL which satisfies black box
requirements.
Import top-level HDL as Sysgen
black box
Add HDL, EDN, NGC, MIF files
required by the HDL for simulation
and implementation to black box
configuration function
Co-simulate black box using
ModelSim or ISE Simulator
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-simulation Flow
HDL black box to be co-simulated
ISE Simulator
ModelSim
Add ModelSim token to desgin
Specify the ModelSim token name
as the external co-simulator
Specify ISE Simulator
as the black box
simulation mode
Co-simulate HDL black box
In Sysgen
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-Simulation (Step 1)
Drag a black box
into the model
The Configuration Wizard
detects HDL files and
customizes the block
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-Simulation (Step 2)
ModelSim
Drag a ModelSim
block into the model
Select the ModelSim
Simulation Mode
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HDL Co-Simulation (Step 2)
ISE Simulator
Select the ISE Simulator
Simulation Mode
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-Simulation (Step 3)
ModelSim Simulator
Select the External
co-simulator
Simulation Mode
Simulink opens
ModelSim and
co-simulates
© 2005 Xilinx, Inc. All Rights Reserved
HDL Co-Simulation (Step 3)
ISE Simulator
Select the ISE Simulator
Simulation Mode
© 2005 Xilinx, Inc. All Rights Reserved
Outline
• Introduction
• Co-Simulation Support Blocks
– Black Box
– Simulation Multiplexer
– ModelSim
• HDL Co-Simulation Process
• Summary
• Lab 2: MAC FIR Filter Verification Using HDL CoSimulation
© 2005 Xilinx, Inc. All Rights Reserved
Knowledge Check
• Why HDL co-simulation?
• Name supported blocks for HDL co-simulation using ModelSim
• List the steps involved in performing HDL co-simulation using ISIM
© 2005 Xilinx, Inc. All Rights Reserved
Answers
• Why HDL co-simulation?
– It provides designers a means to incorporate legacy code in a Simulink-based
system DSP design
– Legacy code can be simulated in the Simulink tool to significantly reduce
development time
• Name supported blocks for HDL co-simulation using ModelSim
– Black Box
– Simulation Multiplexer
– ModelSim
• List the steps involved in performing HDL co-simulation using ISIM
– Drag a Black Box block into a design and assign the legacy code to it
– Select ISE Simulator in simulation mode option
– Run the Simulink simulation, which will invoke the ISIM simulator in the
background and feed result back to the scope
© 2005 Xilinx, Inc. All Rights Reserved
Summary
• Black box block provides a means to incorporate HDL model
• Black box allows ModelSim and ISE Simulator (ISIM) be invoked
to simulate HDL model
• ModelSim simulation flow requires ModelSim helper block
• A black box must describe its interface through a MATLAB Mfunction
• ISE simulator is run in background when invoked through black
box
• An HDL component associated with a black box may not have bidirectional ports at the top-level of hierarchy
• Any port that is a clock or clock enable must be of type std_logic
© 2005 Xilinx, Inc. All Rights Reserved
Outline
• Introduction
• Co-Simulation Support Blocks
– Black Box
– Simulation Multiplexer
– ModelSim
• HDL Co-Simulation Process
• Summary
• Lab 2: MAC FIR Filter Verification Using HDL
Co-Simulation
© 2005 Xilinx, Inc. All Rights Reserved
Lab 2
• You will perform the following steps:
– Create a MAC FIR using CORE Generator™
– Incorporate the MAC FIR into a System Generator
design by using black box.
– Simulate the MAC FIR in Simulink™.
– Create a hardware co-simulation block and perform
both hardware and software HDL co-simulation
© 2005 Xilinx, Inc. All Rights Reserved