ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 35: December 5, 2012
Transmission Lines
Implications
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Penn ESE370 Fall2012 -- DeHon
Transmission Line Agenda
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Where arise?
General wire formulation
Lossless Transmission Line
See in action in lab
Impedance
End of Transmission Line?
Termination
Implications
Discuss Lossy
Penn ESE370 Fall2012 -- DeHon
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Transmission Line
• Data travels as waves
• Line has Impedance
• May reflect at end of line


Penn ESE370 Fall2012 -- DeHon
1
c0
w

LC
 r r
L
Z0 
C
R  Z 0 
Vi 
 Vr
R  Z0 
 2R 
Vi 
 Vt
R  Z 0 
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Series Termination
• What happens here?
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Penn ESE370 Fall2012 -- DeHon
Simulation
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Penn ESE370 Fall2012 -- DeHon
Series Termination
• Rseries = Z0
• Initial voltage divider
– Half voltage pulse down line
• End of line open circuit
– sees single transition to full voltage
• Reflection returns to source and sees
termination Rseries = Z0
• No further reflections
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Penn ESE370 Fall2012 -- DeHon
Termination Cases
• Parallel at Sink
• Series at Source
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Penn ESE370 Fall2012 -- DeHon
CMOS Driver / Receiver
• Driver: What does a CMOS driver look
like at the source?
– Id,sat=1200A/m @ 45nm
• Receiver: What does a CMOS
inverter look like at the
sink?
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Penn ESE370 Fall2012 -- DeHon
Some Transmission Lines
Characteristics arise form their
geometry
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Penn ESE370 Fall2012 -- DeHon
Coaxial Cable
• Inner core conductor: radius r
• Insulator: out to radius R
• Outer core shield (ground)
   R 
L   ln  
2  r 
 1    R 
Z 0    ln  
2    r 
• RG-58 Z0= 50W – networking, lab
• (RG-59 Z0= 75W – video)
Penn ESE370 Fall2012 -- DeHon

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Printed Circuit Board
• Stripline
– Trace between planes
w
t
b
r


W


1
1  
b


Z 0    ln
t  W 
4    
 b
b 
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Penn ESE370 Fall2012 -- DeHon
Printed Circuit Board
• Microstrip line
– Trace over single supply plane
0
r
w
t
h
 
 1 


4h
ln 
Z 0   



2  0.475 r  0.67 0  0.536W  0.67t 
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Penn ESE370 Fall2012 -- DeHon
Twisted Pair
• Category 5 ethernet cable
– 100W
– V=0.64c0
Source: http://en.wikipedia.org/wiki/File:Cat_5.jpg
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Penn ESE370 Fall2012 -- DeHon
Termination Cases
• Parallel at Sink
• Series at Source
Either: destination sees source
voltage after delay.
Penn ESE370 Fall2012 -- DeHon
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Example
• 25meter category-5e cable (100W, 0.64c)
• Supporting 1Gb/s ethernet
– 4 pairs at 250Mb/s
• Time to send data from one end to the
other?
• Time between bits at 250Mb/s?
• Bits in the cable?
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Penn ESE370 Fall2012 -- DeHon
Pipeline Bits
• For properly terminated transmission line
– Do not need to wait for bits to arrive at sink
– Can stick new bits onto wire
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Penn ESE370 Fall2012 -- DeHon
Limits to Bit Pipelining
• What limits? (why only 250Mb/s)
– Risetime/distortion
– Clocking
• Skew
• Jitter
– For bus
• Wire length differences between lines
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Penn ESE370 Fall2012 -- DeHon
Eye Diagrams
• Watch bits over line on scope
– Look at distortion
– “open” eye clean place to sample
• Consistent timing of transitions
• Well defined high/low voltage levels
http://en.wikipedia.org/wiki/File:On-off_keying_eye_diagram.svg
http://focus.ti.com/analog/docs/gencontent.tsp?familyId=361&genContentId=41762&DCMP=ESD_Solutions&HQS=Other+OT+esd
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Penn ESE370 Fall2012 -- DeHon
Bad “eye”
http://archive.chipcenter.com/knowledge_centers/asic/todays_feature/showArticle.jhtml?articleID=12800254
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Penn ESE370 Fall2012 -- DeHon
Termination / Mismatch
• Wires do look like these transmission lines
• We are terminating them in some way
when we connect to chip (gate)
– Need to be deliberate about how terminate,
if we care about high performance
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Penn ESE370 Fall2012 -- DeHon
Where Mismatch?
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Vias
Wire corners?
Branches
Connectors
Board-to-cable
Cable-to-cable
http://www.fpga4fun.com/Hands-on_Flashy.html
http://wiki.altium.com/display/ADOH/An+Overview+of+Electronic+Product+Development+in+Altium+Designer
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Penn ESE370 Fall2012 -- DeHon
Impedance Change
• What happens if there is an impedance
change in the wire? Z0=75W, Z1=50W
– What reflections and transmission do we get?
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Penn ESE370 Fall2012 -- DeHon
Z0=75, Z1=50
• At junction:
– Reflects
• Vr=(50-75)/(50+75)Vi
– Transmits
• Vt=(100/(50+75))Vi
R  Z 0 
Vi 
 Vr
R  Z0 
 2R 
Vi 
 Vt
R  Z 0 
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Penn ESE370 Fall2012 -- DeHon
Impedance Change
Z0=75, Z1=50
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Penn ESE370 Fall2012 -- DeHon
Lossy Transmission Line
• How do addition of R’s change?
– Concretely, discretely think about
R=0.2W every meter on Z0=100W
• what does each R do?
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Penn ESE370 Fall2012 -- DeHon
Lossy Transmission Line
• R’s cause signal attenuation (loss)
– Voltage divider R Z0
– Reduced signal swing at sink
– Limits length of transmission line before
need to restore signal
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Penn ESE370 Fall2012 -- DeHon
What happens at branch?
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Penn ESE370 Fall2012 -- DeHon
Branch
• Transmission line sees two Z0 in parallel
– Looks like Z0/2
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Penn ESE370 Fall2012 -- DeHon
Z0=50, Z1=25
• At junction:
– Reflects
• Vr=(25-50)/(25+50)Vi
– Transmits
• Vt=(50/(25+50))Vi
R  Z 0 
Vi 
 Vr
R  Z0 
 2R 
Vi 
 Vt
R  Z 0 
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Penn ESE370 Fall2012 -- DeHon
End of Branch
• What happens at end?
• If ends in matched, parallel termination
– No further reflections
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Penn ESE370 Fall2012 -- DeHon
Branch Simulation
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Penn ESE370 Fall2012 -- DeHon
Branch with Open Circuit?
• What happens if branch open circuit?
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Penn ESE370 Fall2012 -- DeHon
Branch with Open Circuit
• Reflects at end of open-circuit stub
• Reflection returns to branch
– …and encounters branch again
– Send transmission pulse to both
• Source and other branch
• Sink sees original pulse as multiple
smaller pulses spread out over time
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Penn ESE370 Fall2012 -- DeHon
Open Branch Simulation
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Penn ESE370 Fall2012 -- DeHon
Open Branch Simulation
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Penn ESE370 Fall2012 -- DeHon
Bus
http://en.wikipedia.org/wiki/File:DIMMs.jpg
• Common to have many modules on a bus
– E.g. PCI slots
– DIMM slots for memory
• High speed  bus lines are trans. lines
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Penn ESE370 Fall2012 -- DeHon
Multi-drop Bus
• Ideal
– Open circuit, no load
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Penn ESE370 Fall2012 -- DeHon
Multi-Drop Bus
• Impact of capacitive load (stub) at drop?
– If tight/regular enough, change Z of line
L
Z0 
C
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Penn ESE370 Fall2012 -- DeHon
Multi-Drop Bus
• Long wire stub?
– Looks like branch
• may produce reflections
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Penn ESE370 Fall2012 -- DeHon
Transmission Line Noise
• Frequency limits
• Imperfect termination
• Mismatched
segments/junctions/vias/connectors
• Loss due to resistance in line
– Limits length
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Penn ESE370 Fall2012 -- DeHon
Idea
• Transmission lines
– high-speed
– high throughput
– long-distance signaling
• Termination
• Signal quality
1
c0
w

LC
 r r
L
Z0 
C
R  Z 0 
Vr  Vi 

 R  Z 0 

Penn ESE370 Fall2012 -- DeHon
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Admin
• HW7 due Thursday
• Last lecture Friday
• Final following Friday (12/14)
– 2011 final available to practice
– 2010 final up with solutions
• Good transmission line problem
• Problem 2 precharge logic (skipped this term)
• Ok crosstalk problem, memory problem
– Review by Udit on Wed. 12/12
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Penn ESE370 Fall2012 -- DeHon