ELEC 7770
Advanced VLSI Design
Spring 2014
Linear Programming – A Mathematical
Optimization Technique
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
1
What is Linear Programming
 Linear programming (LP) is a mathematical

method for selecting the best solution from the
available solutions of a problem.
Method:
 State the problem and define variables whose
values will be determined.
 Develop a linear programming model:
 Write the problem as an optimization formula (a
linear expression to be minimized or maximized)
 Write a set of linear constraints
 An available LP solver (computer program) gives
the values of variables.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
2
Types of LPs
 LP – all variables are real.
 ILP – all variables are integers.
 MILP – some variables are integers, others are

real.
A reference:
 S. I. Gass, An Illustrated Guide to Linear
Programming, New York: Dover, 1990.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
3
A Single-Variable Problem
 Consider variable x
 Problem: find the maximum value of x subject to

constraint, 0 ≤ x ≤ 15.
Solution: x = 15.
Constraint satisfied
0
15
x
Solution
x = 15
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
4
Single Variable Problem (Cont.)
 Consider more complex constraints:
 Maximize x, subject to following constraints:




x≥0
5x ≤ 75
6x ≤ 30
x ≤ 10
0
(1)
(2)
(3)
(4)
5
10
(3)
15
(2)
x
(1)
(4)
All constraints
satisfied
Solution, x = 5
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
5
A Two-Variable Problem
 Manufacture of chairs and tables:
 Resources available:
 Material: 400 boards of wood
 Labor: 450 man-hours
 Profit:
 Chair: $45
 Table: $80
 Resources needed:
 Chair

 5 boards of wood
 10 man-hours
 Table
 20 boards of wood
 15 man-hours
Problem: How many chairs and how many tables should be
manufactured to maximize the total profit?
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
6
Formulating Two-Variable Problem
 Manufacture x1 chairs and x2 tables to maximize
profit:

P = 45x1 + 80x2 dollars
Subject to given resource constraints:
 400 boards of wood,
5x1 + 20x2 ≤ 400
 450 man-hours of labor, 10x1 + 15x2 ≤ 450
 x1 ≥ 0
 x2 ≥ 0
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
(1)
(2)
(3)
(4)
7
Solution: Two-Variable Problem
40
Tables, x2
30
Best solution: 24 chairs, 14 tables
Profit = 45×24 + 80×14 = 2200 dollars
(1) 20
(24, 14)
10
(3)
0
0
(4)
10
20
30
40
50
Chairs, x1
60
70
(2)
80
90
increasing
decresing
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
8
Change Profit of Chair to $64/Unit
 Manufacture x1 chairs and x2 tables to maximize
profit:

P = 64x1 + 80x2 dollars
Subject to given resource constraints:
 400 boards of wood,
5x1 + 20x2 ≤ 400
 450 man-hours of labor, 10x1 + 15x2 ≤ 450
 x1 ≥ 0
 x2 ≥ 0
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
(1)
(2)
(3)
(4)
9
Solution: $64 Profit/Chair
40
Tables, x2
30
Best solution: 45 chairs, 0 tables
Profit = 64×45 + 80×0 = 2880 dollars
(1) 20
(24, 14)
10
(3)
0
0
Spring 2014, Feb 26 . . .
(4)
10
20
30
40
50
Chairs, x1
ELEC 7770: Advanced VLSI Design (Agrawal)
60
(2)
70
80
90
increasing
decresing
10
A Dual Problem
 Explore an alternative.
 Questions:
 Should we make tables and chairs?
 Or, auction off the available resources?
 To answer this question we need to know:
 What is the minimum price for the resources that will

provide us with same amount of revenue from sale as
the profits from tables and chairs?
This is the dual of the original problem.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
11
Formulating the Dual Problem
 Revenue received by selling off resources:
 For each board, w1
 For each man-hour, w2
 Minimize 400w1 + 450w2
 Subject to constraints:
 5w1 + 10w2
≥ 45
 20w1 + 15w2
≥ 80
 w1
≥0
 w2
≥0
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
Resources:
Material: 400 boards
Labor: 450 man-hrs
Profit:
Chair: $45
Table: $80
Resources needed:
Chair
5 boards of wood
10 man-hours
Table
20 boards of wood
15 man-hours
12
The Duality Theorem
 If the primal has a finite optimum solution, so

does the dual, and the optimum values of the
objective functions are equal.
Reference:
G. Strang, Linear Algebra and Its Applications.
Fort Worth: Harcourt Brace Javanovich College
Publishers, third edition, 1988.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
13
Primal-Dual Problems
 Primal problem
 Fixed resources
 Maximize profit
 Variables:
 Dual Problem
 Fixed profit
 Minimize value
 Variables:
 x1 (number of chairs)
 w1 ($ value/board of wood)
 x2 (number of tables)
 w2 ($ value/man-hour)
 Maximize profit 45x1+80x2
 Minimize value 400w1+450w2
 Subject to:
 Subject to:
 5x1 + 20x2
≤ 400
 5w1 + 10w2
≥ 45
 10x1 + 15x2
≤ 450
 20w1 + 15w2 ≥ 80
 x1
≥0
 w1
≥0
 x2
≥0
 w2
≥0
 Solution:
 Solution:
 x1 = 24 chairs, x2 = 14 tables
 w1 = $1, w2 = $4
 Profit = $2200
 value = $2200
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
14
LP for n Variables
n
minimize
Σ
cj xj
Objective function
j =1
n
subject to
Σ aij xj
≤ bi,
i = 1, 2, . . ., m
= di,
i = 1, 2, . . ., p
j =1
n
Σ cij xj
j =1
Variables: xj
Constants: cj, aij, bi, cij, di
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
15
Algorithms for Solving LP
 Simplex method
 G. B. Dantzig, Linear Programming and Extension, Princeton, New
Jersey, Princeton University Press, 1963.
 Ellipsoid method
 L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,”
Soviet Math. Dokl., vol. 20, pp. 191-194, 1984.
 Interior-point method
 N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear
Programming,” Combinatorica, vol. 4, pp. 373-395, 1984.
 Course website of Prof. Lieven Vandenberghe (UCLA),
http://www.ee.ucla.edu/ee236a/ee236a.html
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
16
Basic Ideas of Solution methods
Extreme points
Constraints
Extreme points
Objective
function
Simplex: search on extreme points.
Complexity: polynomial in n, number
of variables
Spring 2014, Feb 26 . . .
Constraints
Objective
function
Interior-point methods: Successively
iterate with interior spaces of analytic
convex boundaries.
Complexity: O(n3.5L), L = no. of int. values
ELEC 7770: Advanced VLSI Design (Agrawal)
17
Integer Linear Programming (ILP)
 Variables are integers.
 Complexity is exponential – higher than LP.
 LP relaxation
 Convert all variables to real, preserve ranges.
 LP solution provides guidance.
 Rounding LP solution can provide a non-optimal
solution.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
18
Traveling Salesperson Problem (TSP)
6
4
12
5
27
1
18
12
15
19
10
3
Spring 2014, Feb 26 . . .
20
2
5
ELEC 7770: Advanced VLSI Design (Agrawal)
19
Solving TSP: Five Cities
Distances (dij) in miles (symmetric TSP, general TSP is asymmetric)
City
j=1
j=2
j=3
j=4
j=5
i=1
0
18
10
12
27
i=2
18
0
5
12
20
i=3
10
5
0
15
19
i=4
12
12
15
0
6
i=5
27
20
19
6
0
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
20
Search Space: No. of Tours
 Asymmetric TSP tours




Five-city problem: 4 × 3 × 2 × 1 = 24 tours
Ten-city problem: 362,880 tours
15-city problem: 87,178,291,200 tours
50-city problem: 49! = 6.08×1062 tours
Time for enumerative search assuming 1 μs per tour
evaluation
=
1.93×1055 years
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
21
A Greedy Heuristic Solution
Tour length = 10 + 5 + 12 + 6 + 27 = 60 miles (non-optimal)
City
j=1
j=2
j=3
j=4
j=5
i=1
(start)
0
18
10
12
27
i=2
18
0
5
12
20
i=3
10
5
0
15
19
i=4
12
12
15
0
6
i=5
27
20
19
6
0
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
22
ILP Variables, Constants and Constraints
x14 ε [0,1]
d14 = 12
4
5
x15 ε [0,1]
d15 = 27
x12 ε [0,1]
d12 = 18
1
x13 ε [0,1]
d13 = 10
3
Integer variables:
xij = 1, travel i to j
xij = 0, do not travel i to j
2
Real constants:
dij = distance from i to j
x12 + x13 + x14 + x15 = 1
four other similar equations
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
23
Objective Function and ILP Solution
5
Minimize ∑
i=1
i-1
∑ xij × dij
j=1
∑ xij = 1 and xii = 0
j≠i
Spring 2014, Feb 26 . . .
for all i
xij
j=1
2
3
4
5
i=1
0
0
1
0
0
2
1
0
0
0
0
3
0
1
0
0
0
4
0
0
0
0
1
5
0
0
0
1
0
ELEC 7770: Advanced VLSI Design (Agrawal)
24
ILP Solution
d54 = 6
4
5
d45 = 6
1
d21 = 18
d13 = 10
3
2
d32 = 5
Total length = 45
but not a single tour
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
25
Additional Constraints for Single Tour
 Following constraints prevent split tours. For any
subset S of cities, the tour must enter and exit
that subset:
∑ xij ≥ 2 for all S, |S| < 5
i ε S
j ε S
Remaining
set
At least two
arrows must cross
this boundary.
Any subset
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
26
ILP Solution
d41 = 12
4
d54 = 6
5
1
d25 = 20
d13 = 10
3
2
d32 = 5
Total length = 53
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
27
ILP Example: Test Minimization
 A combinational circuit has n test vectors that detect m

faults. Each vector detects a subset of faults. Find the
smallest subset of test vectors such that each fault is
detected by at least N vectors.
Simulate vectors without dropping faults.
Faults
Test vectors
T1
T2
.
.
Tj
.
.
.
Tn
F1
1
0
0
1
1
0
1
0
0
F2
0
0
1
1
0
0
0
1
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Fj
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
.
.
.
.
Fm
0
1
1
1
0
0
0
0
1
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
fij = 1, if test Ti
detects fault Fj
28
Test Minimization by ILP
Construct an ILP model:
1. Assign an integer variable ti ε [0,1] to ith test vector
such that ti = 1, if we select ti, otherwise ti= 0.
2. Define an integer constant fij ε [0,1] such that fij = 1, if
ith vector detects jth fault, otherwise fij = 0. Values of
constants fij are determined by fault simulation.
n
minimize
Σ ti
Objective function
i=1
n
subject to
Σ fij ti
≥ N,
j = 1, 2, . . ., m
i=1
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
29
N-Detect Tests (N = 5)
Circuit
Unoptimized vectors
c432
ILP (exact)
Minimum vectors
CPU s
608
197
1.0
c499
379
260
2.3
c880
1,023
127
881.8
c1355
755
420
4.4
c1908
1,055
543
6.9
c2670
959
477
7.2
c3540
1,971
471
20008.5
c5315
1,079
376
40.7
c6288
243
57
34740.0
c7552
2,165
841
114.3
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
30
Why ILP Solution is Exponential?
LP solution
found in
polynomial time
(bound on ILP
solution)
Second variable
Must try all
2n roundoff
points
Constraints
First variable
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
Objective
(maximize)
31
Characteristics of ILP
 Worst-case complexity is exponential in number of


variables.
Linear programming (LP) relaxation, where integer
variables are treated as real, gives a lower bound on the
objective function.
Recursive rounding of relaxed LP solution to nearest
integers gives an approximate solution to the ILP
problem.
 K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity
Algorithm for Minimizing N-Detect Tests,” Proc. 20th International
Conf. VLSI Design, January 2007, pp. 492-497.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
32
Recursive Rounding Algorithm
1. Obtain a relaxed LP solution. Stop if each
variable in the solution is an integer.
2. Round the variable closest to an integer.
3. Remove any constraints that are now
unconditionally satisfied.
4. Go to step 1.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
33
Complexity of Approximation
 Recursive rounding:
 ILP is transformed into k LPs with progressively reducing



number of variables, where k is the size of the solution.
A solution that satisfies all constraints is guaranteed; this
solution is often close to optimal.
Number of LPs, k, is the size of the final solution, i.e., the
number of non-zero variables in the test minimization
problem.
Recursive rounding complexity is k × O(np), where k ≤ n,
n is number of variables.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
34
Four-Bit ALU Circuit
14 inputs, 8 outputs
Initial vectors
ILP
Recursive rounding
Vectors
CPU s
Vectors
CPU s
285
14
0.65
14
0.42
400
13
1.07
13
1.00
500
12
4.38
13
3.00
1,000
12
4.17
12
3.00
5,000
12
12.95
12
9.00
10,000
12
34.61
12
17.0
16,384 = 214
(exhaustive set)
12
87.47
12
37.0
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
35
ILP vs. Recursive Rounding
100
ILP
75
CPU s
Recursive
Rounding
50
25
0
0
Spring 2014, Feb 26 . . .
5,000
10,000
ELEC 7770: Advanced VLSI Design (Agrawal)
15,000 Vectors
36
N-Detect Tests (N = 5)
Relaxed LP/Recur. rounding
ILP (exact)
Circuit
Unoptimized
vectors
c432
608
196.38
197
1.0
197
1.0
c499
379
260.00
260
1.2
260
2.3
c880
1,023
125.97
128
14.0
127
881.8
c1355
755
420.00
420
3.2
420
4.4
c1908
1,055
543.00
543
4.6
543
6.9
c2670
959
477.00
477
4.7
477
7.2
c3540
1,971
467.25
477
72.0
471
20008.5
c5315
1,079
374.33
377
18.0
376
40.7
c6288
243
52.52
57
39.0
57
34740.0
c7552
2,165
841.00
841
52.0
841
114.3
Spring 2014, Feb 26 . . .
Lower
bound
Min.
Min.
CPU s
vectors
vectors
ELEC 7770: Advanced VLSI Design (Agrawal)
CPU s
37
A Primal-Dual Solution (N = 1)
Lower
Recursive LP minimization
Primal-dual minimization
bound
on
Unopt.
LP
Minimized
Unopt.
Total
Minimized
vectors vectors CPU s
vectors
vectors
CPU s
vectors
c432
27
608
2.00
36
983
5.52
31
c499
52
379
1.00
52
221
1.35
52
c880
13
1023
31.00
28
1008
227.21
25
c1355
84
755
5.00
84
507
1.95
84
c1908
106
1055
8.00
107
728
2.50
107
c2670
44
959
9.00
84
1039
17.41
79
c3540
78
1971
197.00
105
2042
276.91
95
c5315
37
1079
464.00
72
1117
524.53
67
c6288
6
243
78.00
18
258
218.9
17
c7552
65
2165
151.00
145
2016
71.21
139
M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Minimal Test Generation
Problem,” Proc. 12th IEEE VLSI Design & Test Symp. (VDAT08), 2008, pp. 269-279.
Circuit
Name
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
38
Finding LP/ILP Solvers
 R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling
Language for Mathematical Programming, South San Francisco,
California: Scientific Press, 1993. Several of programs described in
this book are available to Auburn users.
 B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E.
Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and
Experienced Users, Cambridge University Press, 2006.
 Search the web. Many programs with small number of variables can
be downloaded free.
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
39
A Circuit Optimization Problem
 Given:

 Circuit netlist
 Cell library with multiple versions for each cell
Select cell versions to optimize a specified
characteristic of the circuit. Typical
characteristics are:
 Area
 Power
 Delay
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
40
Example: Cell(X), X = 0 or 1
 X: an integer variable for each gate.
 X=0
 Delay = d
 Power = 3 × p
 X=1
 Delay = 2 × d
 Power = 0.5 × p
 Cell delay = (1 – X) d + 2 X d
 Power = 3(1 – X) p + 0.5 X p
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
41
ILP Model: Minimum Power & Delay
Arrival time = T1
Ti
kth Cell
Arrival time = Tk
 Ti = signal arrival time at ith input; Ti = 0 for all PIs
 Tk = signal arrival time at cell output
 Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all i
Where, dk = nominal delay of gate
Xk = 0 or 1, specifies version of cell
Minimize α TPO + ∑ [3(1 – Xk) pk + 0.5 Xk pk]
all k
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
α is constant
42
Given Clock Specification
 Tj = 0, for all primary inputs j
 Tk ≤ clock period, for all primary outputs k
 Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all gates k
Combinational Logic
Register
Register
with input i
Clock
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
43
Minimum Power Design
 Minimize ∑
3(1 – Xk) pk + 0.5 Xk pk
all k
where
Spring 2014, Feb 26 . . .
pk = nominal power consumption of
kth cell
ELEC 7770: Advanced VLSI Design (Agrawal)
44
Logic Minimization
 Consider a four-variable function, {2,4,6,8,9,10,12,13,15}
 Karnaugh map shows prime implicants (PI) found by

Quine-McCluskey procedure.
Find the minimum number of Pis to cover all minterms.
A
1
EPI’s
1
1
1
1
D
1
C
1
1
1
B
Non-EPI’s
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
Non-EPI’s
45
Select a Minimal Set of PI’s
Covered by EPI →
Minterm →
2
4
6
PI1
PI2
x
PI3
x
x
8
9
x
x
10
x
x
x
12
13
15
x
x
x
x
PI4
x
PI5
x
PI6
x
x
x
x
x
PI7
x
x
1. First select essential prime implicants (EPIs).
2. Cover remaining minterms with smallest number of prime
implicants (Pis).
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
46
Cover Remaining Minterms
Remaining minterms →
2
PI2
x
PI3
x
4
6
10
x
x
PI4
x
PI5
x
PI6
x
x
Integer linear program (ILP): Define integer {0,1} variables, xk = 1, select
PIk; xk = 0, do not select PIk.
Minimize k xk, subject to following constraints:
x2 + x3 ≥ 1
(cover minterm 2)
x4 + x5 ≥ 1
(cover minterm 4)
x2 + x4 ≥ 1
(cover minterm 6)
x3 + x6 ≥ 1
(cover minterm 10)
A solution is x3 = x4 = 1, x2 = x5 = x6 = 0
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47
Minimized Function
 F(A,B,C,D)
=
=
PI1 + PI3 + PI4 + PI7
AC +B CD +A BD + A B D
A
1
EPI’s in MSOP
1
1
1
1
D
1
C
1
1
1
B
Selected PIs
Spring 2014, Feb 26 . . .
ELEC 7770: Advanced VLSI Design (Agrawal)
Pis not selected
48
Comb. Circuit Power Optimization
 Given a set of test vectors
 Reorder vectors to minimize the number of
transitions at primary inputs
01010101
00110011
00001111
11 transitions
Combinational circuit
(tested by exhaustive
vectors)
01111000
Rearranged vector set 00110011
00011110
Spring 2014, Feb 26 . . .
produces 7 transitions
ELEC 7770: Advanced VLSI Design (Agrawal)
49
Reducing Comb. Test Power
Original tests:
V1 V2 V3 V4 V5
1 1 0 0 0
1 0 1 0 0
1 0 1 0 1
1 0 1 1 1
10 input transitions
Reordered tests:
V1 V3 V5 V4 V2
1 0 0 0 1
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
5 input transitions
Spring 2014, Feb 26 . . .
1
V1
3
4
V2
3
3
2
V4
2
1
V3
1
V5
2
Traveling salesperson problem (TSP)
finds the shortest distance closed path
(or cycle) to visit all nodes exactly once.
But, we need an open loop solution.
ELEC 7770: Advanced VLSI Design (Agrawal)
50
Open-Loop TSP
1
0
3
V1
0
0
2
3
V0
0
V4
4
V2
2
1
3
V3
1
V5
2
0
 Add a node V0 at distance 0 from all other nodes.
 Solve TSP for the new graph.
 Delete V0 from the solution.
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ELEC 7770: Advanced VLSI Design (Agrawal)
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Combinational Vector Ordering
 See: P. Wray, “Minimize test power for benchmark circuit c6288 by
optimal ordering of vectors,” ELEC 6270 Class Project Report, Spring
2009, www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/PROJECT/WRAY/
 TSP has exponential complexity; good heuristics are available.
 For other extensions:
 V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy,
“Techniques for Minimizing Power Dissipation in Scan and
Combinational Circuits During Test Application,” IEEE Trans. CAD,
vol. 17, no. 12, pp. 1325-1333, Dec. 1998.
 Typical average power saving:
 30-50%
 50-60% with vector repetition (to satisfy peak power)
 ? ? ? With inserted vectors (to satisfy peak power)
Spring 2014, Feb 26 . . .
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Traveling Salesperson Problem
 A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data


Structures and Algorithms, Reading,
Massachusetts: Addison-Wesley, 1983.
E. Horowitz and S. Sahni, Fundamentals of
Computer Algorithms, Computer Science Press,
1984.
B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K.
R. Coombes, J. E. Osborn and G. J. Stuck, A
Guide to MATLAB for Beginners and
Experienced Users, Cambridge University
Press, 2006.
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