Development of monolithic pixel sensors in
Silicon On Insulator technology
Serena Mattiazzo
University of Padova (Italy)
D. Bisello, P. Giubilato, D. Pantano
INFN & University of Padova (Italy)
M. Battaglia,
UC Santa Cruz (USA)
P. Denes, D. Contarato
Lawrence Berkeley National Laboratory, LBNL (USA)
Outline
Review of Monolithic pixel sensors in Silicon On
Insulator technology
- The SOIPIX collaboration
- SOI pixel detectors from LAPIS
Recent results on the latest chip produced
- Thinning and back-processing
- Test on thin detector with soft X-rays
- Test on thin detector with MIPs
Conclusions
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Monolithic Pixel Sensors in SOI technology
• In the Silicon On
Insulator (SOI) technology,
the CMOS electronics is
implanted on a thin silicon
layer on top of a buried
oxide (BOX)
40nm thin
CMOS layer
200nm thick
BOX
350m thick
high resistivity
substrate
200nm Al
back-contact
• In the SOI technology depleted monolithic pixel sensors can be built by using a high
resistivity substrate and providing some vias to interconnect the substrate through the BOX;
• Pixel implants can be created and a reverse bias can be applied; charge is collected by drift.
 Bonded SOI wafers provided by SOITEC Co with high resistivity “handle wafer”
 LAPIS Semiconductor (former OKI, Japan) provides a commercial 0.20µm Fully Depleted
(FD) SOI process
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SOIPIX collaboration
•University of Hawaii
•Fermi National
Accelerator Laboratory
•Lawrence Berkeley
National Laboratory
• UC Santa Cruz
•INP Krakow
•University of Heidelberg
•Louvain-la-Neuve University
•Padova University & INFN
•KEK
•JAXA
•RIKEN
•AIST
•Osaka University
•Tohoku University
•Tsukuba University
•Kyoto University
Japan
•IHEP/IMECAS (China)
 Collaboration formed in 2005
by KEK Universities (Prof. Y.
Arai representative)
 Regular Multi-Project Wafer
(MPW) runs  twice per year
http://rd.kek.jp/project/soi/
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SOI pixel technology
Monolithic
approach
• Low material budget
• High density
• Low cost
SOI technology
• Low power
• High speed
• Low SEL sensitivity
Backgate effect
• Limited depletion voltage
• Limited depletion width
Handle wafer
resistivity low after
CMOS process
Small sensor chip
size
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• CZ(n)  400-cm
• 21 mm × 21 mm mask size
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Backgate effect
The high field in the depleted substrate causes back-gating of
the CMOS electronics on top of the BOX: the reverse bias,
Vback, applied to the silicon substrate increases the potential at
the surface, so that the buried oxide acts as a second gate for the
CMOS circuitry on top
• Test of single transistors vs. depletion
voltage: shift in the threshold voltage with
increasing substrate voltage
BOX
Buried P-Well (BPW) Implantation
BOX
Peripheral
Pixel
BPW
• low dose implantation through the BOX and through the
electronics
• Suppress the back gate effect.
• Less electric field in the BOX which may improve radiation
hardness.
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High Resistivity Substrates
CZ(n)
- 700 -cm
- 260 µm
FZ(n)
- 7 k-cm
- 500 µm
FZ(p)
- 25 k-cm
- 500 µm
[Y.Arai’s talk at PIXEL2012 Workshop]
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Larger masks and stitching
Larger
reticule size
• Previously 20.8mm ×
20.8mm
• Easier to make larger
sensors and to reduce
the cost per area
31 mm
24.8 mm
Stitching
• Special run for
RIKEN in 2012
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SOI pixel technology: recent progresses
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Limited
Backgate effect
• Buried P-Well proposed
by KEK and now
routinely used
Higher Handle
wafer resistivity
• FZ(n) > 3 k-cm
Larger sensors
• 30 mm × 66 mm
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Applications
X-ray
photons
Synchrotron light
XFEL
X-ray astronomy
Medical imaging
…
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Ionizing
particles
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Belle II
ILC
CLIC
Electron microscopy
…
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A brief history of SOI pixel prototypes
Within an international collaboration between the Lawrence
Berkeley Laboratory, UC Santa Cruz, the University of Padova and
the INFN of Padova, we are developing depleted monolithic pixel
sensors in Silicon On Insulator technology
 LDRD-SOI series: technology demonstration
with high momentum particles on analog and
digital pixels. Limited reverse bias applied
(back-gating effect)
 NIM A 583 (2007) 526
 NIM A 604 (2009) 380
 JINST 4 P04007 (2009)
 SOImager series:
optimization of pixel layout,
test of different substrates
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2009-2012: SOI-Imager series
Optimization of the pixel layout, more effective
solution against back-gating, larger area
SOImager-2
Row Selection
Pixel cell layout

LAPIS 0.20 µm FD-SOI process
Reset Transistor
55 mm2 (active area is 3.5 3.5mm2) 256256
analog 3T pixels, 13.75 µm pitch, 1.8 V operational
voltage

Source Follower
4 parallel analog outputs (64256 pixels each)
read out up to 25 MHz, 655 µs integration time
(serial readout architecture)

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SOImager-2: pixel layout study
Guard-rings
SOImager-2
Buried P-Well (BPW)
Pixel
Peripheral
BPW
Pixel layouts for
the 8 sectors
 NIM A 650 (2011) 184
 NIM A 654 (2011) 258
 NIMA 658 (2011) 125
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Photon detection
Cross section view of an SOI device
9um
• In our technology the total thickness of the
top passivation, metalizations and the CMOS
and the buried oxide layers is 9m
• This is a “dead region”: all photons
converting here are lost!
< 10m
Absorption length () in Silicon
• In order to avoid photon absorption in nonsensitive regions of the device in the soft-Xrays and UV energy range, back-illumination
is required
• But this requires a fully depleted device!
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N x   N 0e

x

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Thinning and back-processing
Breakdown at 130V (no full depletion)
and need to minimize material budget
for precision vertex tracking
A set of sensors has been back-thinned
to 70m using a commercial grinding
technique
The backplane is damaged after the
thinning process
Need good contact to extend electric
field to detector back-plane
Low energy Phosphor implantation
followed by annealing at 500°C (windows
thickness of 100-200nm)
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X-rays characterization at the ALS
• Quantum efficiency for X-rays on the SOImager-2 studied on
data collected at the 5.3.1 beamline of the Advanced Light Source
at LBNL
• In-vacuum test capabilities, reference spectrometer and translation
stages for sample and sensor positioning
• Thin, back-processed SOI-Imager-2 sensor tested with
fluorescence X-rays from metal foils in the energy range 2.1 keV<
x

E < 8.6 keV

N x   N 0e
Element
E (keV)
 (m)
Au
2.12
1.7
Ag
2.98
4.1
Ti
4.50
13
Fe
6.40
37
Ni
7.47
56
Cu
8.08
70
Zn
8.60
86
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Reference
spectrometer
Sample
holder with
thin metal
foilsMattiazzo
Serena
Vacuum test
chamber
DAQ
Detector
backplane
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Results
• Sensor operated in full depletion and overdepletion
•Good pulse height linearity as a function of Xray energy
• Quantum efficiency (continuous black line)
measured by comparing hit rates on SOI sensor
with reference spectrometer accounting for
absorption in Si (dotted line) and transmission
through thin entrance window (dashed line).
Calibration and linearity
Quantum efficiency
 NIM A 674 (2012) 51
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Test on the thin SOImager-2
300 GeV
- at
CERN SPS
•
Detectors arranged in one cemented “doublet” (2
thick detectors, 9 mm spaced) and one “singlet” (1 thin
detector, 33 mm spaced).
•
The doublet is optically aligned with a better than 50
µm precision  easy and precise coincidence cuts in
cluster recognition.
•
Temperature is maintained around 20° C by cool air
flow and continuously monitored.
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MIP detection: thick vs thin sensor
300GeV 70m SOImager-2
Vsub = 50V
MPV: (191 ± 2) ADC cnt
300GeV 260m SOImager-2
Vsub = 50V
• Ratio of Pulse height:
0.61 ± 0.01
MPV: (314 ± 3) ADC cnt
• Ratio of estimated
sensitive thicknesses:
0.62 ± 0.05
Perfect agreement
• NIM A 676 (2012) 50
• NIM A 681 (2012) 61
SOI sensor
Vsub (V)
Cluster <S/N>
Efficiency
point (m)
Thin
30
50
70
90
25.0
28.2
28.8
31.2
0.90 ± 0.04
0.94 ± 0.03
0.96 ± 0.03
0.98 ± 0.02
3.1 ± 0.80
1.7 ± 0.50
1.8 ± 0.60
1.9 ± 0.70
30
50
70
23.3
47.4
52.7
0.89 ± 0.03
1.36 ± 0.04
1.12 ± 0.03
1.07 ± 0.05
Over depletion
Thick
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0.02
 0.04
0.01
 0.05
0.98
0.99
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Summary & Outlook
The SOIPIX collaboration is very active in the development
of monolithic pixels in SOI technology; the process is
improving and the collaboration is growing in size
LBNL, Padova and UC Santa Cruz are involved in SOI
monolithic pixels R&D in LAPIS deep-submicron FD-SOI
technology since about 2007 (with more than 7
prototypes).
We have developed thin sensors with very good
performance both for X-ray imaging and for MIP tracking
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Backup Slides
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New test chips on High Resistivity substrates
VRST
VDD
SF-n
RST-p
RS
RST-n
RS
Vsub
• 0.20 µm LAPIS process, Oct 2011 submission
OUT-n
OUT-p
SF-p
• VRST = 0 for n-type substrate
• VRST = VDD for p-type substrate
• 512 × 320 analog pixels, 13.75 µm pitch
• Complementary architecture for both p-type and n-type substrates
• Devices on CZ substrate (HR1, n-type) and FZ-p arrived in June (evaluation
ongoing). HR3 (n-type) and FZ-n to arrive soon!
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Energy resolution
Vd = 70V
Vd = 70V
Fitted Gaussian width
Fitted Gaussian width
(0.70 ± 0.03) keV
(0.99 ± 0.02) keV
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Pixel multiplicity
Pixel multiplicity in signal
clusters as a function of
Vdep for 980nm laser
pulses (filled squares) and
5.9keV X-rays (open
triangles).
• Cluster size decreases with Vdep as expected
• Signal is distributed among multiple pixels also for large voltages: capacitive coupling?
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Response to inclined tracks
Average pixel multiplicity along rows and columns for clusters associated to a pion track as a function
of the detector angle for Vd = V.
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Charge sharing
 distribution at different values of Vd for (left) 980nm laser pulses and (right) 200GeV .
• Small variation of the  distribution with Vd using the980nm laser and no significant variation
with energetic pions.
• Charge sharing among neighboring pixels is not dominated by the charge carrier cloud size:
instead, the pixel capacitive coupling plays a significant role in determining the observed signal
distribution
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Depletion thickness
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Radiation damage studies on the 0.20 µm process
• X-ray irradiation (10 keV L-line photons.) on single
transistors 0.20 µm FD process). Irradiations in air at room
temperature. Dose rate: 165 rad(SiO2)/sec.
For Vback = 0V the transistor is still working
properly up to doses of ~100krad.
• NMOS and PMOS transistors, each surrounded by 1µm
PSUB guard ring
• NMOS and PMOS Body of Body-Tie transistors at 0V.
Drain and source at 0V, gate NMOS HIGH (1.8V), gate
PMOS LOW (0V).
• Vback = 0V, 5V, 10V with PSUB guard-ring floating; Vback =
10V with PSUB guard-ring at 0V
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The PSUB guard-ring tied at GND during irradiation indeed limits
the electrical field through the BOX and improves the radiation
hardness of the device.
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Y. Arai talk at PIXEL2012
(September 2012, Inawashiro)
Double-SOI
• Shield transistor from
bottom electric field
SEM View of Double SOI (Thickness of Si & SiO2 layer not yet optimized
• Compensate electric
field generated by the
trapped hole in the
BOX
• Reduce
crosstalk
between sensors and
circuits
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LAPIS Semiconductor 0.2um FD-SOI Pixel
Process
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Larger mask
New Mask
Previous Mask
20.8 mm
×
20.8 mm
31 mm
Unit size 5 mm  6 mm
Y. Arai talk at PIXEL2012
(September 2012, Inawashiro)
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24.8 mm
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Stitching
66 mm × 30 mm achieved
130mm × 130mm is possible
Y. Arai talk at PIXEL2012
(September 2012, Inawashiro)
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R&D on back-processing
• Need 100 Å window thickness for an
efficient O(100eV) X-ray sensitivity in
back-illumination
• Several processes under test at LBNL
Process
Window Thickness
Status
Low energy implantation +
500°C annealing
1000-2000 Å
Process dependent, several SOI
prototypes functional
Low energy implantation +
laser annealing
400-700 Å
Several SOI prototypes functional
a-Si (amorphous silicon)
contact deposition by
sputtering
300Å
Prototypes functional after processing,
high leakage
Molecular Beam Epitaxy
50-75 Å
Building in-house capability
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Back-processing: LBNL low-temperature process
Low temperature process developed at
LBNL: phosphorus implant at 33keV using a
cold process at -160°C to create amorphous
layer, followed by annealing @ 500°C (10
minutes in Nitrogen atmosphere), compatible
with CMOS devices; simple process and
equipment needed

Very promising results from tests on PIN
diodes: good yield and low leakage current

Process applied to 70 µm thin SOImager-2
chips, which are fully functional after
processing

Spreading Resistance Analysis (SRA)
measurements show P contact extending to
0.3 – 0.4 μm depth

Distance from back-plane (µm)
SRA data for the implanted contact on a
post-processed chip

Expect detection threshold of 1.5 keV for
0.4 µm thick contact

[from Craig Tindall, LBNL]
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MBE
• Molecular Beam Epitaxy (MBE) system being
acquired, expected to be operational by mid2013
• Conductive implants few atomic layers thin
created by evaporation in ultra-high vacuum
(“delta doping” approach first demonstrated by
NASA/JPL); final contact thickness ~ 10nm
• Low thermal budget (< 450°C) technique,
applicable to full-processed devices
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HEP requirement for radiation hardness
Machine
Luminosity
[cm-2 s-1]
Non Ionizing Fluence
[neq cm-2 yr-1]
Ionizing Fluence
[krad yr-1]
LHC
1034
1.4 × 1014
11300
HL-LHC
1035
1.4 × 1015
71400
CLIC
1034
1.0 × 1011
50
Super B
> 1036
3.5 × 1012
3000
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Lorentz angle
• In the presence of an electric field (E) and a
magnetic field (B), the charge carriers released by
a charged particles in the detector drift along a
direction at an angle L (Lorentz angle) with
respect to the electric field direction

B
• The charge usually spreads over several pixels,
depending on the angle of the incident particle
• The spread is minimum for an incident angle
equal to the Lorentz angle
• Knowledge of this angle is needed to optimize
the spatial resolution by tuning the angular
orientation of the detectors
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Lorentz angle measurement
B=0T
Measurement on a thick
detector at Vsub = 70V
B = 1.5T
Measurement repeated at the
end of July on a thin
detector, but data analysis
still ongoing
B=0T
B = 1.5 T
Vsub = 70V 0.14 ± 0.14 1.71 ± 0.11
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Single Event Upset tests
• We tested the technology for SEU sensitivity.
• The periphery shift register for row-selection
has been used to check for bit-flip through a
dedicated test pad.
• Mind: the design is not hardened in
any special way against SEU!
256 flip flops, 13.75 µm
pitch
FLIP-FLOP layout
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SEU cross section
• A Single Event Upset (SEU) study was performed at the SIRAD
irradiation facility, located at the 15MV Tandem XTU-Accelerator of
the INFN Legnaro National Laboratory.
• A known logical pattern is written in and read back from the row
selection shift register through dedicated pads during irradiation.
Differences between the loaded and read-back pattern highlight a SEU
occurred in the cells
Vback = 0 V
• Irradiation performed with three different ion species and, for each
ion beam, for two substrate bias conditions (Vback = 0V - 7V).
Ion
species
Energy
(MeV)
LET0 in Si
(MeV·cm2/mg)
19F
118
3.67
35Cl
170
12.5
79Br
240
38.6
No apparent difference with or
without bias
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Vback = 7 V
• LETthr  4 MeV·cm2/mg
• sat  10-6 cm2
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Other applications: FemtoPix
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