RF Pulse Modulation and the Digitally
Driven Class C Power Amplifier
R. Uang, J. Keyzer, A. Dalvi, Y. Sugiyama,
M. Iwamoto, I. Galton and P. Asbeck, UCSD
High Speed Devices Group
Introduction
• Digital RF generation
– DSP’s are approaching the microwave
regime:
• Intel Pentium 4 ALU operates at 4 GHz.
– CMOS processes continue to be scaled in
size, reducing power and increasing speed.
• We can use digital RF to improve modern wireless communication
systems by:
– Reducing power dissipation using high efficiency power
amplifiers.
– Using DSP to generate signals such that system can overcome
limitations of PA alone.
– Developing versatile “mostly-CMOS” transmitters with
programmable functionality.
High Speed Devices Group
Overview
• System Overview – RF Digital Pulsewidth Modulation
• The Digitally Driven Class C Power Amplifier
• Simulations and Experimental Results
• Conclusions
High Speed Devices Group
Future RF Transmitters
Present
Microwave
Transmitter
fIF(cos)
I
DSP
Q
DAC
x
+
DAC
Filter
I
DSP
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Digital
Upconverter
Q
fbb=fs/N
Filter
VGA
PA
x
fo
fIF(sin)
Future
Microwave
Transmitter
x
fclk
D-S
Pulse
Modulator
x8
DSP
PA
Analog
filter
Concept: Digital D-S RF Pulse
Modulation
RF t   Re
Desired RF
signal with
AM and PM
RF pulse
modulated
waveform
D-S RF pulse
modulated
waveform
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At  e
j t 
 e 
jt
Concept: Digital D-S RF Pulse
Modulation
RF t   Re
ADS t 

1
At  e
j t 
 e 
jt
(Pulse Wdith)
3
1
RF(t)
DS t  
t
3
4
(Pulse Position)
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6
D-S Pulse Modulator Block Diagram
Phase
Modulation
fclk
DS
Modulator
in(t)
Envelope
Modulation
Ain(t)
3 Bit Word
Pulse
Generator
fclk
DS
Modulator
1.5 Bit Word
Digital pulse
Position
Modulator
Digital Pulse
Width
Modulator
8 fclk
8 fclk
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RF Output
Simulations
Single Tone
• Single tone: spur level typically
below - 55 dBc in desired band.
• Delta-Sigma modulator shapes
quantization noise away from
signal of interest.
CDMA (broad band view)
CDMA: Linearity Test
Meets IS-95
ACPR Specs
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The Digitally Driven Class C Power
Amplifier
Vdd
RFC
Shunt LC
Resonator
Vin
ID
RF Pulse
Digital Input
•
•
L
Vout
C
Load
GaAsFET
t
Replace modulated sinusoidal input with RF
digital pulse modulated signal
• Input is digital pulse train with varying pulse
width and position
• ID assumes pulse shape
Desired output is modulated sinusoid
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t
Digitally Driven Class C PA - Analysis
Efficiency and Output Power vs. Conduction Angle
Imax
0
VD
T/4
T/2
T
t
Vdd
Vmin
0
π
2π ωt
Power at fundamental (W)
0.5
ID
0.4
Traditional PA
Pout
Drain Efficiency
W
T
P1 
70
0.3
60
50
0.2
40
Drain Efficiency
Pout
Digitally Driven PA
Class C
0.1
I max (Vdd - Vmin )
W
V
η  sinc(  )( 1 - min )
T
Vdd
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
90
80
0
Pdc  Vdd I max
100
360
315
sin( 
W
)
T
@ RLopt 
Vdd - Vmin
I1
270
225 180 135 90
45
Conduction Angle (Degrees)
30
20
10
0
0
Drain Efficiency (%)
W < T/2
Simulated PA Performance: RL,opt
3’s
0.30
0.25
0.20
Rlopt for 3’s
0.15
0.10
Drain Efficiency vs. Load Resistance
60
3’s
50
40
30
1’s
20
0.05
0.00
70
Drain Efficiency
Power of fundamental (W)
Power of fundamental vs. Load Resistance
0.35
1’s
0
10
20
30
40
10
Rlopt for 1’s
50
60
70
80
90 100
Rl
0
10
20
30
40
50
60
70
80
90 100
Rl
Pattern
Rlopt ADS
Rlopt Analysis
1’s
49Ω
41Ω
3’s
16Ω
13Ω
Rl,opt coincides with max
voltage swing at output,
max power at fundamental.
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0
•
•
Peak efficiency does not
occur at fixed Rl for
varying pulse widths.
Optimum load occurs
before maximum drain
efficiency is reached.
Experimental Test Setup
Conexant CX60061
OC-192 Serializer
HP16522A
Pattern
Generator
16 bits
16:1
1 bit
3.2 Gbps
200 Mbps
Matlab
Generated
Sequences
Class C PA
under testing
Conexant CX60077
Laser Driver
Amplified
Output
Synchronized
200 MHz /
3.2GHz Clocks
•Pattern generator outputs looping bit sequence
•Serializer multiplexes to high data rate (3.2 Gbps), 900mV signal swing
•Laser driver amplifies signal 2x to 2.5V max swing (adjustable)
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Experimental Results: Pulse Train
Prototype Class C PA
Drain Efficiency
Pattern
•
•
Calculated Simulated
1’s
73%
55%
39%
3’s
59%
63%
74.5%
Measured efficiency for 3’s exceeds calculated value.
Measured efficiency for 1’s is much less than expected.
Switching Mode
Drain Efficiency
100
Drain Efficiency
vs. Output Power
for ideal amplifiers
with modulated
signals
Measured
Digitally Driven Class C
80
Class B
60
Class A
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Pout (Normalized)
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0.8
0.9
1
Experimental Results: CDMA
Linearity Results to Date
Input to PA
Output
5dB/div
30 kHz BW
“CDMA” signal - OQPSK at 400MHz
Po = +17.1 dBm, 22% Drain Efficiency
IS-95 ACPR specifications
overlaid in red
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5dB/div
30 kHz BW
Conclusions
• A novel Digitally Driven Class C Power Amplifier has
been demonstrated using a commercial power
GaAsFET.
• This new variant of the Class C PA presents many
unique challenges in its design and implementation.
• RF Digital Pulsewidth Modulation combined with the
Digitally Driven Class C Power Amplifier may
potentially provide a means for high efficiency, high
linearity, easily reconfigured RF and microwave
transmitters.
High Speed Devices Group
Simulated PA Performance: RL,opt
3’s
0.30
including package model
0.25
0.20
Rlopt for 3’s
0.15
70
Drain Efficiency
Power of fundamental (W)
Power of fundamental vs. Load Resistance
0.35
60
50
0.05
10
0
10
20
30
40
Rlopt for 1’s
50
60
70
80
90 100
Rl
0
1’s
0
10
20
30
40
50
60
70
80
90 100
Rl
Pattern
Rlopt ADS
Rlopt Analysis
1’s
49Ω
41Ω
3’s
16Ω
13Ω
Rl,opt coincides with max
voltage swing at output,
max power at fundamental.
High Speed Devices Group
including
package model
30
20
0.00
3’s
40
0.10
1’s
Drain Efficiency vs. Load Resistance
•
•
Peak efficiency does not
occur at fixed Rl for
varying pulse widths.
Optimum load occurs
before maximum drain
efficiency is reached.