Chapter 9 -- Simplification of
Sequential Circuits
Redundant States in Sequential Circuits
Removal of redundant states is important because
– Cost: the number of memory elements is directly related to the
number of states
– Complexity: the more states the circuit contains, the more
complex the design and implementation becomes
– Aids failure analysis: diagnostic routines are often predicated on
the assumption that no redundant states exist
Equivalent States
• States S1, S2, …, Sj of a completely specified sequential circuit are said
to be equivalent if and only if, for every possible input sequence, the
same output sequence is produced by the circuit regardless of whether
S1, S2, …, Sj is the initial state.
• Let Si and Sj be states of a completely specified sequential circuit. Let
Sk and Sl be the next states of Si and Sj, respectively for input Ip.
Si and Sj are equivalent if and only if for every possible Ip the following
are conditions are satisfied.
– The outputs produced by Si and Sj are the same,
– The next states Sk and Sl are equivalent.
Equivalent States Illustration
x
x
SC
(a)
z
0
1
A
C/1
B/0
B
C/1
E/0
C
B/1
E/0
D
D/0
B/1
E
E/0
A/1
Initial Input Sequences
State 00 01 11 10
A 11 10 01 00
B 11 10 00 01
C 11 10 00 01
D 00 01 11 10
E 00 01 11 10
(c)
(b)
Initial
Input Sequences
State 000 001 010 011 100 101
A
111 110 100 101 011 010
B
111 110 100 101 000 001
C
111 110 100 101 000 001
D
000 001 011 010 111 110
E
000 001 011 010 111 110
(d)
Figure 9.1
110 111
000
011
011
100
101
001
010
010
101
100
Equivalence Relations
• Equivalence relation: let R be a relation on a set S. R is an
equivalence relation on S if and only if it is reflexive, symmetric, and
transitive. An equivalence relation on a set partitions the set into
disjoint equivalence classes.
• Example: let S = {A,B,C,D,E,F,G,H} and R =
{(A,A),(B,B),(B,H),(C,C),(D,D),(D,E),(E,E),(E,D),(F,F),(G,G),(H,H),
(H,B)}. Then P = (A)(BH)(C)(DE)(F)(G)
• Theorem: state equivalence in a sequential circuit is an equivalence
relation on the set of states.
• Theorem: the equivalence classes defined by the state equivalence of a
sequential circuit can be used as the states in an equivalent circuit.
Methods for Finding Equivalent States
• Inspection
• Partitioning
• Implication Tables
Finding Equivalent States By Inspection
x
0
1
A
B/0
C/1
B
C/0
A/1
C
D/1
B/0
D
C/0
A/1
x
x
0
0
1
A
B/0
C/1
B
C/0
A/1
C
B/1
B/0
(b)
(a)
A
B/0 C/1
B
B/0
A/1
C
D/1
B/0
D
D/0
A/1
(c)
x
0
1
C/1
B
B/0
D/0
C
D/1
B/0
D
B/0
A/1
A
A/1
(e)
Figure 9.2
x
1
0
1
A
B/0
C/1
B
A/1
B/0
B/1 B/0
C
(d)
Finding Equivalent States by Partitioning
Partition P0
Output for x = 0
Output for x = 1
Partition P1
Next state for x = 0
Next state for x = 1
Partition P2
Next state for x = 0
Next state for x = 1
Partition P3
Next state for x = 0
Next state for x = 1
Partition P4 = P3
Partition blocks
(ABCDE)
11100
00011
(ABC)
(DE)
CCB
DE
BEE
BA
(A) (BC)
(DE)
C
CB
DE
B
EE
BA
(A) (BC) (D) (E)
C
CB
D
E
B
EE
B
A
(A) (BC) (D) (E)
Action
Separate (ABC) and (DE)
Separate (ABC) and (DE)
Separate (A) and (BC)
Separate (D) and (E)
States B and C are equivalent
Figure 9.3
Example 9.2 -- Partitioning example
x
0
1
A
E/0
D/0
B
A/1
F/0
C
C/0
A/1
D
B/0
A/0
E
D/1
C/0
F
C/0
D/1
G
H/1
G/1
H
C/1
B/1
x
0
A'
1
B'/0 A'/0
B' A'/1 C'/0
C' C'/0 A'/1
D'
E'/1 D'/1
E' C'/1 B'/1
(a)
Figure 9.4
(b)
Example 9.3 -- Another partitioning example
x
0
1
A
A/0
B/0
B
H/1
C/0
A' A'/0 E'/0
C
E/0
B/0
B'
B'/1 D'/1
D
C/1
D/0
C'
F'/0 E'/0
E
C/1
E/0
D'
E'/0 B'/0
F
F/1
G/1
E'
E'/1 C'/0
G
B/0
F/0
F' C'/1 F'/0
H
H/1
C/0
x
0
1
(b)
(a)
Figure 9.5
Example 9.4 -- Yet another partitioning
example
00
01
A
D/0
B
x1x2
11
10
D/0
F/0
A/0
C/1
D/0
E/1
F/0
C
C/1
D/0
E/1
A/0
D
D/0
B/0
A/0
F/0
E
C/1
F/0
E/1
A/0
F
D/0
D/0
A/0
F/0
G
G/0
G/0
A/0
A/0
H
B/1
D/0
E/1
A/0
00
01
x1x2
11
10
A' C'/0 C'/0 A'/0 A'/0
B' B'/1 C'/0 D'/1 A'/0
C' C'/0 B'/0 A'/0 A'/0
D' B'/1 A'/0 D'/1 A'/0
E'
E'/0 E'/0 A'/0 A'/0
(a)
Figure 9.6
(b)
Finding Equivalent States by Implication Tables
x
0
1
A
C/1
B/0
B
C/1
E/0
C
B/1
E/0
D
D/0
B/1
E
E/0
A/1
(a)
B
B
C
C
D
D
E
E
A
B
C
A
D
B
(b)
B
BE
B
C
BC
BE
Ö
C
BC
BE
A
B
C
D
Ö
D
AB
AB
E
A
B
C
(d)
D
BE
D
E
C
(c)
(BC)
-
PK = (A)(BC)(D)(E)
(f)
D
A
B
C
(e)
Figure 9.7
D
Example 9.5 -- Using implication tables to
find equivalent states
x
0
1
A
E/0
D/0
B
A/1
F/0
C
C/0
A/1
D
B/0
A/0
E
D/1
C/0
F
C/0
D/1
G
H/1
G/1
H
C/1
B/1
(a)
A
B
C
D
E
F
G
(AD)
(BE)
(CF)
-
B
C
D
BE
AD
CF
E
AD
F
G
CH
BG
H
A
B
PK = (AD)(BE)(CF)(G)(H)
(c)
Figure 9.8
C
D
(b)
E
F
G
Example 9.6 -- An implication table example
00
01
A
D/0
B
x1x2
11
10
D/0
F/0
A/0
C/1
D/0
E/1
F/0
C
C/1
D/0
E/1
A/0
D
D/0
B/0
A/0
F/0
E
C/1
F/0
E/1
A/0
F
D/0
D/0
A/0
F/0
G
G/0
G/0
A/0
A/0
H
B/1
D/0
E/1
A/0
(a)
A
B
C
D
E
F
G
(AF)
(BC)(BH)
(CH)
-
Note: (BC)(BH)(CH) = (BCH)
PK = (AF)(BCH)(D)(E)(G)
(c)
B
C
D
AF
BD
AF
DF
DF
AF
E
F
G
BD
Ö
DG
BG
AF
H
A
DG
AF
BC
AF
BC
B
C
AF
BC
DF
D
(b)
E
F
G
Incompletely Specified Circuits
•
•
•
•
Next states and/or outputs are not specified for all states
Applicable input sequences: an input sequence is applicable to state, Si, of an
incompletely specified circuit if and only if when the circuit is in state Si and
the input sequence is applied, all next states are specified except for possible
the last input of the sequence.
Compatible states: two states Si and Sj are compatible if and only if for each
input sequence applicable to both states the same output sequence will be
produced when the outputs are specified.
Compatible states: two states Si and Sj are compatible if and only if the
following conditions are satisfied for any possible input Ip
– The outputs produced by Si and Sj are the same, when both are specified
– The next states Sk and Sl are compatible, when both are specified.
•
Incompatible states: two states are said to be incompatible if they are not
compatible.
Compatibility Relations
• Compatibility relation: let R be a relation on a set S. R is a
compatibility relation on S if and only if it is reflexive and symmetric.
A compatibility relation on a set partitions the set into compatibility
classes. They are typically not disjoint.
• Example: let S = {A,B,C,D,E} and
R = {A,A),(B,B),(C,C),(D,D),(E,E),(A,B),(B,A),(A,C),(C,A), (A,D),
(D,A),(A,E),(E,A),(B,D),(D,B),(C,D),(D,C),(C,E),(E,C)}
Then the compatibility classes are
(AB)(AC)(AD)(AE)(BD)(CD)(CE)(ABD)(ACD)(ACE)
The incompatibility classes are (BC)(BE)(DE)
• Compatible pairs may be found using implication tables
• Maximal compatibles may be found using merger diagrams
Examples 9.8 and 9.9 -- Generating Maximal
Compatibles and Incompatibles
B
x
0
1
A
A/-
C/1
B
B/-
A/-
C
G/-
E/0
D
C/1
C/-
E
A/1
C/-
F
D/-
A/-
G
G/-
G/-
H
H/-
D/(a)
AC
BG
AE
C
D
G
F
E
E
D
C
C
B
A
A
A
AC
E
Ö
F
AD
AC
G
CG
H
CD
A
BC
CG
AC CE
AB
AC
BD
AG
AD
AG
DG
AE
EG
GH
DE
B
C
(GH)
(GH)(FG)
(EG)(EH)(GH)(FG)
(FG)(EGH)
(DG)(FG)(EGH)
(CG)(CF)(CE)(CD)(DG)(FG)(EGH)
(CEG)(CDG)(CFG)(EGH)
(BC)(BG)(CEG)(CDG)(CFG)(EGH)
(AE)(AG)(AH)(BC)(BG)(CEG)(CDG)(CFG)(EGH)
(AEG)(AGH)(AEH)(BCG)(CEG)(CDG)(CFG)(EGH)
(AEGH)(BCG)(CDG)(CEG)(CFG)
AC
(c)
CD
AD
AC
AC
CG
CH
CD
D
(b)
AG
CG
DG
AG
AH DH
DG
CD
AD
E
F
G
G
F
E
D
D
C
B
B
B
A
A
(FH)
(FH)(EF)
(FH)(EF)(DH)(DF)(DE)
(FH)(DH)(DEF)
(CH)(FH)(DH)(DEF)
(BH)(BF)(BE)(BD)(CH)(FH)(DH)(DEF)
(BH)(BDEF)(CH)(FH)(DH)
(BDEF)(CH)(BDFH)
(AB)(AC)(AD)(AF)(BDEF)(CH)(BDFH)
(ABDF)(AC)(BDEF)(CH)(BDFH)
(d)
Merger diagrams
B
A
C
B
C
A
D
(a)
(b)
B
C
A
C
E
B
D
A
E
D
F
(d)
(c)
Figure 9.11
Example 9.10 -- Merger diagrams for example
9.8
C
B
C
B
A
D
A
D
H
E
H
E
G
F
G
(a)
F
(b)
Figure 9.12
Minimization Procedure
Select a set of compatibility classes so that the following
conditions are satisfied
• Completeness: all states of the original machine must be covered
• Consistency: the chosen set of compatibility classes must be closed
• Minimality: the smallest number of compatibility classes is used
Bounding the number of states
• Let U be the upper bound on the number of states needed
in the minimized circuit
• Then U = minimum (NSMC, NSOC)
– where NSMC = the number of sets of maximal compatibles
– and NSOC = the number of states in the original circuit
• Let L be the lower bound on the number of states needed in
the minimized circuit
• Then L = maximum(NSMI1, NSMI2,…, NSMIi)
– where NSMIi = the number of states in the ith group of the set of
maximal incompatibles of the original circuit.
State Reduction Algorithm
• Step 1 -- find the maximal compatibles
• Step 2 -- find the maximal incompatibles
• Step 3 -- Find the upper and lower bounds on the number
of states needed
• Step 4 -- Find a set of compatibility classes that is
complete, consistent, and minimal
• Step 5 -- Produce the minimum state table
Example 9.11 -- Reduced state table
corresponding to example 9.8
x
0
x
1
0
1
(AEGH) AGH CDG
A'
A'/1
C'/1
(BCG)
BG AEG
B'
B'/-
A'/0
(CDG)
CG CEG
C' B', C', D', E'/1 D'/0
(CFG)
DG AEG
D'
A'/1
D'/0
(CEG)
AG CEG
E'
C'/-
A'/0
(a)
(b)
Figure 9.13
Example 9.12 -- State reduction problem
x
0
1
A
A/-
-/-
B
C/1
B/0
C
D/0
-/1
D
-/-
B/-
E
A/0
C/1
B
AC
C
AD
B
A
D
Ö
E
Ö
C
Ö
Ö
AD
BC
E
(a)
A
B
C
D
D
(c)
(b)
B
x
A
C
E
D
0
1
(ABD)
AC
B
(ACD)
AD
B
(ACE)
AD
C
(e)
(d)
Figure 9.14
x
0
1
A'
B'/1
A'/0
B'
A'/0
B'/1
(f)
Example 9.13 -- Another state table reduction
problem
B
x
0
BD
C
x
1
A
B/1
D/0
B
-/-
B/0
C
E/0
D/-
D
B/1
A/0
E
-/-
C/1
F
-/0
E/1
C
D
BD
Ö
B
D
AB
CD
E
A
DE
F
CE
0
1
(ABD)
B
ABD
(BC)
E
BD
(E)
-
C
(F)
-
E
E
F
(c)
(d)
(a)
A
B
C
D
E
(b)
C
B
x
D
A
E
F
(e)
0
1
A'
A', B'/1
A'/0
B'
C'/0
A'/0
C'
-/-
B'/1
D'
-/0
C'/1
(f)
Figure 9.15
Example 9.14 -- Yet another state reduction problem
x
0
1
A
D/-
A/-
B
E/0
A/-
C
D/0
B/-
D
C/-
C/-
E
C/1
B/-
B
DE
C
AB
D
AC
CD
E
AB
CD
(a)
B
AB
DE
AC
CE
A
B
C
A
C
BC
BC
A
B
C
E
D
D
E
(c)
(d)
(b)
x
0
1
(ABC)
DE
AB
(ACD)
CD
ABC
(ADE)
CD
ABC
(e)
x
0
x
1
0
1
(ABC) DE
AB
A'
B'/0
A'/-
(DE)
BC
B'
A'/1
A'/-
C
(f)
(g)
D
Figure 9.16
Example 9.15 -- Optimal state assignments
x
Present
0
1
state
A B/0 E/0
B
C/0
G/0
C
D/0
F/0
D
A/1
A/0
E
G/0
C/0
F
A/0
A/1
G
F/0
D/0
Next state/output
Figure 9.17
Unique State Assignments for Four States
x
Present
0
1
state
A A/0 B/0
B
A/0
C/0
C
C/0
D/0
D
C/1
A/0
Assignments
1
2
3
States
y 1 y2
y1 y2
y1 y2
A
B
C
D
00
01
11
10
10
11
01
00
00
10
11
01
(a)
(b)
Figure 9.18
State Assignments for a Four State Machine
x
0
1
A
C/0
D/0
B
C/0
A/0
C
B/0
D/0
D
A/1
B/1
Figure 9.19
D flip-flop realization for assignment 1
x
y2 y 1
0
1
00 11/0 10/0
01 11/0 00/0
11 01/0 10/0
10 00/1 01/1
Y2 Y1/z
(a)
x
x
y2 y 1
0
1
00
0
0
01
0
0
x
x
y2 y1
0
1
00
1
1
01
1
0
11
0
y 2 y1
11
0
0
1
1
z
(b)
1
00
1
0
01
1
0
y1
1
y2
10
0
y1
y1
y2
x
x
11
1
0
10
0
1
y2
10
0
0
D2
(c)
Figure 9.20
D1
(d)
D flip-flop realization for assignment 2
y2 y 1
x
0
1
00 01/0 10/0
01 11/0 10/0
11 01/0 00/0
10 00/1 11/1
Y2 Y1/z
(a)
x
x
y2 y 1
0
1
00
0
0
01
0
0
x
x
y2 y1
0
1
00
0
1
01
1
1
y1
11
0
11
0
1
1
z
(b)
0
1
00
1
0
01
1
0
y1
0
y2
10
y 2 y1
y1
0
y2
x
x
11
1
0
10
0
1
y2
10
0
1
D2
(c)
Figure 9.21
D1
(d)
D flip-flop realization for assignment 3
x
y2 y 1
0
1
00 01/0 11/0
01 10/0 11/0
11 00/1 10/1
10 01/0 00/0
Y2 Y1/z
(a)
x
x
y2 y 1
0
1
00
0
0
01
0
0
x
0
1
00
0
1
00
1
1
01
1
1
01
0
1
y 11
0
1
y 11
0
0
1
0
y2 y1
y1
11
1
1
y2
y
0
0
z
(b)
0
1
1
2
10
x
y2 x
y1
x
1
2
10
0
0
D2
(c)
Figure 9.22
y
10
D1
(d)
State adjacencies for four-state assignments
y1
0
y2
1
y1
0
y2
1
y1
0
y2
1
0
A
D
0
A
D
0
A
B
1
B
C
1
C
B
1
C
D
(a)
(b)
(c)
Assignment 1
Assignment 2
Assignment 3
Figure 9.23
Example 9.18 -- Implication Graphs
x
0
1
A
B/0
C/0
B
D/0
A/1
C
A/1
D/0
D
D/1
B/1
(a)
BD
AB
CD
AC
(b)
Figure 9.24
AD
BC
Example 9.19 -- Closed subgraphs
x
0
1
A
B/0
E/0
B
C/1
D/1
C
B/0
A/0
D
A/0
D/0
E
B/1
A/1
CD
AB
BC
AD
Closed
subgraph
(a)
AC
BD
AE
Closed
subgraph
(b)
Figure 9.24
DE
Example 9.20 -- Optimal state assignment
x
y2 y 1
0
1
A
00 10/0 01/0
C
01 00/1 11/0
D
11 11/1 10/1
B
10 11/0 00/1
Y2 Y1/z
(a)
x
x
y2 y 1
0
1
00
1
0
01
0
1
x
x
y2 y1
0
1
00
0
1
01
0
1
y1
11
1
y 2 y1
11
1
1
0
D2
1
00
0
0
01
1
0
y1
0
y2
10
0
y1
1
y2
x
x
11
1
1
10
0
1
y2
10
1
0
D1
(b)
Figure 9.26
z
Example 9.21 -- Another state assignment problem
BE
CD
AB
x
0
1
A
E/0
B/0
B
A/1
D/1
C
E/0
A/0
D
A/0
B/1
E
D/0
C/0
AE
AD
BC
BD
AC
DE
Closed
subgraph
Closed subgraph
(a)
CE
(b)
y3
y3 y 2
y1
00
0
0
A
1
y1
1
01
2
11
6
D
3
10
4
B
7
C
5
E
y2
(c)
Figure 9.27
A D flip-flop realization of the previous example
y3 y2 y1
x
0
y2 y1
1
y2
11
8
13
9
01
d
3
y2
11
7
d
2
d
15
d
6
14
10
00
4
01
5
1
3
y2
10
d
14
d
10
1
1
11
12
8
13
9
y2 y1
10
d
7
d
00
2
15
6
y1
11
14
1
y3
(d)
Figure 9.28
11
12
13
7
d
2
8
10
1
5
3
y2
1
01
d
11
d
10
1
4
01
d
10
00
1
d
d
x
xy3
0
1
11
d
1
y3
(c)
0
01
y1
11
d
d
y1
11
x
1
1
9
15
6
00
1
5
10
y3
(b)
y2 y1
10
8
d
1
xy3
00
1
d
10
x
12
13
7
2
Y3 Y2 Y1/z
(a)
01
11
12
d
11
E 001 010/0 100/0
4
01
5
3
D 010 000/0 110/1
00
4
01
C 100 001/0 000/0
0
00
1
B 110 000/1 010/1
y2 y1
0
00
A 000 001/0 110/0
xy3
x
xy3
15
d
6
9
d
14
10
y3
(e)
y1
11
d
d
10
Example 9.24 -- Closed partitions
x
0
1
A
D/0
C/0
B
E/0
A/1
C
F/1
B/0
D
A/1
F/1
E
C/0
E/0
F
B/0
D/1
(a)
DF
AB
EF
DE
AC
(b)
Figure 9.29
BC
Example 9.25 -- Cross dependency
Present
block
0,1
Input
0
1
B21
P2: B21
B22
B32
B31
B32
B31
P3: B31
B32
B21
B22
B21
B22
B32
0,1
0,1
B22
(a)
Figure 9.30
B31
0,1
(b)