Mapping Algorithm for Large-scale Field
Programmable Analog Array (FPAA)
Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson Hall, and David Anderson
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, GA 30332
{baskaya, sreddy, limsk, tyson, dva}@ece.gatech.edu
ISPD’2005, San Francisco
April 5, 2005
2
Motivation: Gene’s law*
Gene's Law
DSP Power
CADSP Power
100W
Power / MMAC
1W
Power consumption trends
10mW
0.1mW
Programmable
Analog Power
Savings
in DSP microprocessors
>20 Year Leap
in Technology
1W
Contribution of analog design
10nW
1980
1990
2000
2010
Year
2020
2030
Signal processing systems require low power
 Analog devices are preferred for low power operation

* Gene Frantz, “Digital Signal Processor Trends”, IEEE Micro, Nov 2000
ISPD’2005, San Francisco
April 5, 2005
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Field Programmable Analog Arrays (FPAA)

Array of Computational Analog Blocks (CAB)

Discrete time and continuous time versions

Not LUT based => heterogeneous resources

Interconnect lines not segmented => less routing
options

Device/interconnect constraints different from FPGA
=> existing methods do not easily apply!
ISPD’2005, San Francisco
April 5, 2005
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Previous Work

Discrete Time (switched capacitor based) FPAA



Continuous Time CMOS/Bipolar FPAA




Former IMP EPAC: 150 kHz
Former Motorola MPAA *: 200 kHz
Lee-Gulak’1995: 125 kHz
Fast Analog Solutions TRAC: 4 MHz
Floating-gate based RASP: 11 MHz
CAD tools


Ganesan-Vemuri: DAC’2001
Wang-Vrudhula: Mixed Design of Integrated Circuits and Systems,
2001
*Now distributed by Anadigm
ISPD’2005, San Francisco
April 5, 2005
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Floating gate based FPAA
Vtun
Vfg
Computational Analog Block
(CAB) components
2D array of CABs
Floating gate
PFET switch
ISPD’2005, San Francisco
April 5, 2005
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Interconnect Analysis

Three types of interconnects:



type1: intra-CAB
type2: inter-CAB, intra-column
type3: inter-CAB, inter-column

Clustering determines type1 vs.
types 2&3

Clustering maximizes type1 use

Vertical/horizontal wires are not
segmented (unlike FPGA)
R ~ 10 kW (switch on resistance)
Cx = S (all switch C’s on a line)
ISPD’2005, San Francisco
April 5, 2005
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Layout of a single CAB in FPAA
switch
matrix
components
ISPD’2005, San Francisco
April 5, 2005
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Advantages of floating-gate based FPAA

Larger scale
More components per CAB
 More CABs per chip
 More component variety


Floating gate PFET switch technology
Non-volatile memory unit
 Programmable on resistance
 Linear Voltage-Current characteristics

ISPD’2005, San Francisco
April 5, 2005
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Analog Circuit Modeling
In1
+
max
-
min
4*4
Vector
Multiplier
C4 (SOS)
In
max
Out
min
Out1
In2
In1
Out1
op1
cg1
ps1
mm1
ca1
ps5
ps3
vm1
vcc
cf1
pf1
mm2
ps4
ps2
ps6
Out2
nf1
In2
gnd
Out2
*netlist description
.device fpaa1.dev
vcc 1 0
in1 2 0
in2 3 0
out1 4 0
out2 5 0
op1 2 6 7
cg1 6 0
nf1 3 10 0
cf1 10 11
mm2 11 12 13
vm1 8 9 12 13 x x x x 4 5 x x
.l2constraints op1 ca1 cg1…
.end
Extracting a directed graph from an analog circuit
ISPD’2005, San Francisco
April 5, 2005
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FPAA device modeling

8*8 FPAA and its graph based representation
Small circles => routing switches
 Large circles => CABs

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April 5, 2005
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Problem Formulation

Objective



Minimum number of CABs
Minimum number of inter-CAB connections
Constraints



User constraints: certain components have to be in the
same CAB
Device constraints: each CAB can accommodate certain
number of components of each type
Net constraints: each CAB can have a maximum number
of nets for intra-CAB and inter-CAB connections
ISPD’2005, San Francisco
April 5, 2005
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Overview of FPAA Clustering

Simple (but effective) greedy heuristic
1. Pre-cluster user-defined components
2. Order circuit components
3. For each component in order
1. Find the best CAB
2. Merge the component & CAB
3. If no CAB available
1. allow constraint violation
2. fix it by adding more neighbors
4. Compute utilization
ISPD’2005, San Francisco
April 5, 2005
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FPAA Clustering Algorithm



1. Determine constrained groups
2. Modified Hyper Edge Coarsening (MHEC)
ordering
3. Assign groups/components to the best
available CABs



i. High priority (scarce) components
ii. User defined groups
iii. Remaining components in MHEC ascending order
CAB1
CAB1
ps5
ps5
ps5
ps6
ps6
ps6
vm1
vm1
vm1
CAB3
CAB3
op1
op1
CAB2
CAB4
pf1 nf1
ca1
cg1 mm1 mm2 cf1
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How to select the best CAB?

Check availability of the CAB



If available, rank the CAB in favor of:




Device constrains
Net constraints
Resulting CAB occupancy
Net increase in intra-CAB connections
Net decrease in inter-CAB connections
Select CAB with highest rank
ISPD’2005, San Francisco
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Inter-CAB Interconnect Reduction
cutsize:
before => 6 nets
after => 5 nets

If a component has too many connections to fit in “ANY” CAB:
 Select CAB with smallest violation
 Look for components to reduce inter-CAB interconnects
pkey: number of nets NOT between component and CAB
 skey: number of nets between component and CAB


Pick the lowest pkey & break ties with higher skey
ISPD’2005, San Francisco
April 5, 2005
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Recent Progress


FPAA clustering has been improved to include netdriven, path-driven and a hybrid of net/path-driven
approaches

Net-driven minimizes inter-CAB connections

Path-driven considers path length balance
FPAA Placement has been implemented
ISPD’2005, San Francisco
April 5, 2005
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Experimental Setup
architecture
dimension
local wires
vertical global wires
horizontal global wires
fpaa1
4*4
16*10
4*6
4*8
fpaa2
8*8
64*10
8*15
8*8
fpaa3
12*12
144*10
12*33
12*8
FPAA Architectures
ckt
c1
c2
c3
c4
c5
c6
c7
c8
c9
c10
arch
fpaa1
fpaa1
fpaa1
fpaa2
fpaa2
fpaa1
fpaa2
fpaa2
fpaa2
fpaa2
#cells #nets cabs_opt ckt
10
16
2
c11
21
27
3
c12
20
27
3
c13
32
45
5
c14
44
55
7
c15
42
48
8
c16
110 147
17
c17
112 122
14
c18
118 143
19
c19
220 242
27
c20
arch #cells #nets cabs_opt
fpaa2 217 245
32
fpaa2 199 226
23
fpaa2 326 356
37
fpaa2 328 366
39
fpaa3 395 482
57
fpaa3 440 471
50
fpaa3 438 484
52
fpaa3 444 487
52
fpaa3 534 602
72
fpaa3 525 564
60
benchmarks
We cluster each circuit w/ four different cell ordering methods:
random, net-driven, net-path driven & path-driven
ISPD’2005, San Francisco
April 5, 2005
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Results
number of cabs/optimum number of cabs
1.19
1.18
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.1
1.09
% cab utilization
68
67.5
67
66.5
66
65.5
65
64.5
64
random
net-driven
net/pathdriven
path-driven
random
%intra-CAB interconnect utilization
40
35
30
25
20
15
10
5
0
net-driven
net/pathdriven
path-driven
%inter-CAB interconnect utilization
60
50
40
30
20
10
0
random
net-driven
net/pathdriven
path-driven
random
net-driven
net/pathdriven
path-driven
ISPD’2005, San Francisco
April 5, 2005
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Conclusion

We require low power reconfigurable analog devices
for signal processing applications

Floating gate based FPAA provides a large-scale
solution

We developed an algorithm for clustering targeting
floating gate based FPAA
ISPD’2005, San Francisco
April 5, 2005
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Future Work

Complete FPAA Physical Synthesis Tool including:



Clustering
Placement
Routing

Synthesize circuits => measurements

Elaborate FPAA switch vs wire analysis

Optimal FPAA Architecture Selection
ISPD’2005, San Francisco
April 5, 2005
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Thank you
ISPD’2005, San Francisco
April 5, 2005