Engineering 43
Boolean
Logic Systems
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Analog vs Digital
 Up to know we have examined
ANALOG systems
 In Analog systems the Quantity of
Interest (I or V usually) Varies
continuously with time → U = f(t)
 In the Analog case U plots as a smooth
curve vs t
 Digital signals are discontinuous in time;
ocassionally dU/dt → ∞ (in theory)
Engineering-43: Engineering Circuit Analysis
2
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Analog vs Digital
Analog
Digital
Engineering-43: Engineering Circuit Analysis
3
Smoothly
Varying
Curve
Vertical
Rises &
Falls, Flat
Tops &
Bottoms
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
U
Binary vs MultiLevel Digital
1
U
1
 BInary → TWO Level (0/1, Lo/Hi, N/Y)
with “Bits” (Binary Digits):
t
 TRInary → THREE Level (−1/0/1,
Lo/Med/Hi) with “TRITS”:
t
−1
Engineering-43: Engineering Circuit Analysis
4
Zero Levels are
Significant Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Binary Logic
 Virtually ALL
Electronic-Computer
Logic is BINARY.
 But the Signals are
not always “Clean”
Engineering-43: Engineering Circuit Analysis
5
 A Margin for Error to
account for Noisy
Signals is called the
“Noise Margin”
 A Good “NM” allows
a weak INput to
make a strong
Output
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Binary Logic Noise Margains
 The NOISE MARGIN is parameter that
determines the maximum noise voltage
on the input of a gate that allows the
output to remain stable.
 Two parameters, Low noise margin
(NML) and High noise margin (NMH).
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Binary Noise Margins
 By the Diagram Above
NM H  VOH min  VIH min
NM L  VIL max  VOL max
 Inputs in the range VIHmin<Vin<VILmax
Produce Unpredictable Results
Engineering-43: Engineering Circuit Analysis
7
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Numbering Systems
 Numbering Systems (bases) used in
Electronic Systems
• Binary, Base-2
• Octal, Base-8
• Decimal, Base-10 (Human Base)
• Hexadecimal, Base-16 (Digit “F16” = 1510)
 Examples 46237
in Decimal
 → 168310
Engineering-43: Engineering Circuit Analysis
8
46237  4  7 3  6  7 2  2  71  3  7 0
46237  4  343  6  49  2  7  3 1
46237  1372  294  14  3
1,683
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Numbering Systems
Base 10
10^4
10^3 10^2 10^1 10^0 Decimal
10,000 1,000
100
10
1
4
2
6
426
Decimal
Base 2
2^7
2^6
2^5
2^4
2^3
2^2
2^1
2^0
128
64
32
16
8
4
2
1
1
0
0
1
1
19
Base 16
16^4
16^3 16^2 16^1 16^0 Decimal
65,536 4,096
Engineering-43: Engineering Circuit Analysis
9
256
16
1
1
2
A
298
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Counting: Decimal vs Binary
Decimal
Binary
Decimal
Binary
0
0
13
1101
1
1
14
1110
2
10
15
1111
3
11
16
10000
4
100
17
10001
5
101
18
10010
6
110
19
10011
7
111
20
10100
8
1000
21
10101
9
1001
22
10110
10
1010
23
10111
11
1011
24
11000
12
1100
25
11001
 NOTE that 2510 = 110012
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Decimal to Binary Conversion
 Method-A Sucesive Divisions
Convert the decimal number 192 into a binary number.
192/2= 96
with a remainder of
0
96/2= 48
with a remainder of
0
48/2= 24
with a remainder of
0
24/2= 12
with a remainder of
0
12/2= 6
with a remainder of
0
6/2=
3
with a remainder of
0
3/2=
1
with a remainder of
1
1/2=
0
with a remainder of
1
Write down all the REMAINDERS, backwards, and you have the
binary number 11000000.
Engineering-43: Engineering Circuit Analysis
11
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Decimal to Binary Conversion
 Method-B Successive Subtractions
Convert the decimal number 192 into a binary number. First find the
largest number that is a power of 2 that you can subtract from the
original number. Repeat the process until there is nothing left to
subtract.
192−128 = 64
128’s (27) used
1
64 − 64 = 0
64’s (26) used
1
0−0= 0
32’s (26) used
0
0−0= 0
16’s (24) used
0
0−0= 0
8’s (23) used
0
0−0= 0
4’s (22) used
0
0−0= 0
2’s (21) used
0
0−0= 0
1’s (20) used
0
Write down the 0s & 1s from top to bottom, and you have the
binary number 11000000.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Example: Successive Subtracts
 Successive subtraction is more intuitive
Convert the decimal number 213 into a binary number. First find the
largest number that is a power of 2 that you can subtract from the
original number. Repeat the process until there is nothing left to
subtract.
213-128 =
85-64 =
85
21
*(32 cannot be subtracted from 21)
21-16 =
5
*(8 cannot be subtracted from 5)
5-4=
1
*(2 cannot be subtracted from 1)
1-1 =
0
128’s (27) used
64’s (26) used
32’s (25) used
16’s (24) used
8’s (23) used
4’s (22) used
2’s (21) used
1’s (20) used
1
1
0
1
0
1
0
1
Write down the 0s & 1s from top to bottom, and you
have the binary number 11010101.
Engineering-43: Engineering Circuit Analysis
13
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Binary to Decimal Conversion
 Method-B Sucessive Additions
• Make a “Power of 2” table. From right to
left, write the values of the power of 2
above each binary number. Then add up
the values where a 1 exists. Ex: 101101012
27 26
128 64
1
0
25
32
1
24
16
1
23
8
0
22
4
1
21
2
0
20
1
1
128 + 32 + 16 + 4 + 1 = 181
Engineering-43: Engineering Circuit Analysis
14
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Fractional Binary to Decimal
 Method-B Successive Additions
• Treat Factions the Same way as Integers
using successive Additions. Ex:
0.10011012
2−1 2−2 2−3 2−4 2−5 2−6
2−7
2−8
1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256
1
0
0
1
1
1
0
1
0.5 + 0.0625 + 0.03125 + 0.015625 + 0.0390625 = 0.6133
Engineering-43: Engineering Circuit Analysis
15
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Fractional Decimal to Binary
 0.41710 to N2 by
Successive Subtract
0.417
−
0 0x10
0.417
-1
−
0.25 1x10
0.167
-2
−
0.125 1x10
0.042
-3
−
0 0x10-4
0.042
−
0.03125 1x10-5
0.01075
−
0 0x10-6
0.01075
 Thus after getting to
the High-Precision
of 7 Sig-Figs Find
0.41710  0.01101012
 Luckily Fractional
Conversions are not
often need
− 0.007813 1x10-7
0.002937 rem
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Base-16
 The Numbers in
Base-16 run 0→15
in Decimal
 How do we WRITE
1310 in Base-16
(ONE Symbol) when
we’re used to 0→9?
 Answer: use
LETTERS to
represent 10→15
Engineering-43: Engineering Circuit Analysis
17
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Hexadecimal to Decimal
 Convert 12B16 to Decimal
• Base16
Table
16^4
16^3
16^2
16^1
16^0
65,536
4,096
256
16
1
1
2
B
Decimal
299
• Each number-place represents a power of 16
• Given the hexadecimal number 12B
• 1 X 256 = 256
• 2 X 16 = +32
• B X 1 = +11 (B = 11 in hex)
299
Engineering-43: Engineering Circuit Analysis
18
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
HexaDecimal Numbering
 Hexadecimal is the numbering system that is
used to represent MAC (Media Access
Control) for Internet addresses for example
 Another Conversion Example: Express
2F5A16 as a decimal number
163
162
161
160
4096
256
16
1
2
F
5
A
(2 x 4096) + ([F]15 x 256) + (5 x 16) + ([A]10 x 1) = 12122
Engineering-43: Engineering Circuit Analysis
19
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
HexaDecimal Numbering
 One hexadecimal character can represent any
decimal number between 0 and 15.
 In binary, F (15 decimal) is 1111 and A (10 decimal)
is 1010.
 It follows that 4 bits are required to represent a
single hexadecimal value in binary.
 A MAC address is 48 bits long (6 bytes), which
translates to (48/4 = ) 12 hexadecimal characters
required to express a MAC address.
 You can check YOUR MAC-ID by typing cmd.exe in
Windows-7, and then type in the BlackBox
ipconfig/all
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
MAC ID
Example
 After typing in
the Windows
“Start Box”:
• cmd.exe
• ipconfig/all
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
HexaDecimal Numbering
 The smallest decimal value that can be
represented by four hexadecimal characters
(0000) is 0.
 The largest decimal value that can be
represented by four hexadecimal characters
(FFFF) is 65,535.
 It follows that the range of decimal numbers
that can be represented by four hexadecimal
characters (16 bits) is 0 to 65,535, a total of
65,536 or 216 possible values.
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Combinatorial Logic Circuits
 The Foundation of
Algebra, apart from
number themselves,
depends on only
THREE Operations
1. Negation
 Electronic Circuits
can easily
implement
• Inversion
• OR operations
• AND operations
2. Addition (OR-ing)
3. Multiplication
(AND-ing)
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
The Five Base Logic Gates
 The Operation of
Logic Gates is
Described in
TRUTH TABLES
 Truth Tables Show
the OutPut of a Gate
as function ONLY of
its Inputs
 For Example:
Inversion or
“NOT-ing”
Engineering-43: Engineering Circuit Analysis
24
NOT (inverter)
Input = 1 Output = 0
Input = 0 Output = 1
INput
OUTput
 Notice the Logic
Gate SYMBOL for
an Inverter
• The Triangle with
the Bubble
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
The Five Base Logic Gates
 Inverters performs
Negation
 AND gates perform
Multiplication
AND (all high = high, else low)
OR (any high = high, else low)
Input 1
Input 2
Output
Input 1
Input 2
Output
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
Engineering-43: Engineering Circuit Analysis
25
 OR Gates Implement
the ADDITION
operation
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
The Five Basic Logic Gates
 The INVERTED
form of an AND is
called a Not-AND or
NAND. The Truth
Table:
NAND (all high = low, else high)
NOR (any high = low, else high)
Input 1
Input 2
Output
Input 1
Input 2
Output
0
0
1
0
0
1
0
1
1
0
1
0
1
0
1
1
0
0
1
1
0
1
1
0
Engineering-43: Engineering Circuit Analysis
26
 The INVERTED
form of an OR is
called a Not-OR or
NOR. The Truth
Table:
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
PSPICE Gates
 PSPICE-Student
has 4 of the 5 BaseGates as Built-In
Parts
• NAND → 7400
• NOR → 7402
• INVERT → 7404
• AND → 7408
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
The Inversion “Bubble”
 The presence of a
“Bubble” implies
Inversion
 The Bubble Inverts
INPUTS as well as
Outputs
 For example, a
bubble turns a
BUFFER into an
INVERTER
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
The EXCLUSIVE GATES
 The OR gate
produces a “1” for
one or two high
inputs
 The NOR OR gate
produces a “0” for
one to two low
inputs
 The Exclusive-OR
allows only one
High
 The Exclusive-NOR
allows only one
LOW
Engineering-43: Engineering Circuit Analysis
29
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
NANDs (or NORs) are Enough
 To Build a Functioning logic System
Need only: IVERSION, AND, OR
(alternatively inversion , nand , nor)
 NANDs and NORs are MUCH easier to
make than ANDs and NORs.
 Thus make Invertors
ANDs & ORs from
NANDS or NORs
• NANDS preferred
Engineering-43: Engineering Circuit Analysis
30
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
The Logic Gates Summarized
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
WhiteBoard Work
 Determine the TRUTH TABLE for
 Need 24 (16) entries on the Truth Table
• Next time Write an Equation for the TT
Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
All Done for Today
Media
Access
Control
A Hexadecimal
Number (Note
the “E”)
Engineering-43: Engineering Circuit Analysis
33
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Engineering 43
Appendix
NAND
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
34
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
A
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Out
Engineering-43: Engineering Circuit Analysis
35
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
A
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Out
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
Engineering-43: Engineering Circuit Analysis
36
Solution
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Solution by MATLAB
% Bruce Mayer, PE
% ENGR43 * 25Mar12
% Lec-7a * TruthTable WhiteBoard Problem
% file = Truth_Table_Lec7a_1203.m
%
k = 0; % initialize Vector Counter
for A = 0:1;
for B = 0:1;
for C = 0:1;
for D = 0:1;
k = k+1;
Ai(k) = A; Bi(k) = B;
Ci(k) = C; Di(k) = D;
Out(k) = ~C&~D | C&D | A&B&D;
end
end
end
end
%
Truth_tbl =[Ai',Bi',Ci',Di',Out'];
%
disp('
A
B
C
D
Out')
disp('==================================')
disp(Truth_tbl)
OutVert = Out'; %debug command
Engineering-43: Engineering Circuit Analysis
37
A
B
C
D
Out
================================
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Truth Tables
Engineering-43: Engineering Circuit Analysis
38
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx
Engineering-43: Engineering Circuit Analysis
39
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-06a_Fourier_XferFcn.pptx