Engineering 43
Chp 14-2
Op Amp Circuits
Bruce Mayer, PE
Licensed Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
1
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Circuits
 Introduce Two Very
Important Practical
Circuits Based On
Operational Amplifiers
 Recall the OpAmp
 The “Ideal” Model That
we Use
•
•
•
•
RO = 0
Ri = ∞
Av = ∞
BW = ∞
Engineering-43: Engineering Circuit Analysis
2
 Consequences of Ideality
•
•
•
•
RO = 0  vO = Av(v+−v−)
Ri = ∞  i+ = i− = 0
Av = ∞  v+ = v−
BW = ∞  OpAmp will
follow the very Highest
Frequency Inputs
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Ckt  Integrator
v+ = 0
 KCL At v− node
v1  v
d
+ C2 vo  v  = i
R1
dt
Engineering-43: Engineering Circuit Analysis
3
 By Ideal OpAmp
• Ri = ∞  i+ = i− = 0
• Av = ∞  v+ = v− = 0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Integrator cont
 Separating the Variables
and Integrating Yields
the Solution for vo(t)
 By the Ideal OpAmp
Assumptions
 A simple Differential Eqn
Engineering-43: Engineering Circuit Analysis
4
 Thus the Output is a
(negative) SCALED
TIME INTEGRAL of the
input Signal
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Ckt  Differentiator
+ vC1 
i2
R1
i1
KVL
v+ = 0
 By Ideal OpAmp
• v− = GND = 0V
• i− = 0
Engineering-43: Engineering Circuit Analysis
5
 KCL at v− i1 + i2
 Now the KVL
= i
 v1 + R1i1 + vC1 = 0
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Differentiator cont.
R1
i2
i1
 Recall Ideal OpAmp
Assumptions
• Ri = ∞  i+ = i− = 0
• Av = ∞  v+ = v− = 0
 Then the KCL
vO
i1 + i2 = i1 +
=0
R2
Engineering-43: Engineering Circuit Analysis
6
 Recall the Capacitor
Integral Law
1 t
vC t  =  i  x dx
C 
 Thus the KVL
t
1
v1 (t ) = R1i1 +
i1 ( x)dx

C1 
 Multiply Eqn by C1, then
Take the Time Derivative
of the new Eqn
di1
dv1
R1C1
+ i1 = C1
(t )
dt
dt
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Differentiator cont
0  v0 
 Examination of this Eqn
Reveals That if R1 were
ZERO, Then vO would be
Proportional to the TIME
DERIVATIVE of the input
Signal
R2
R1
i1
 In the Previous
Differential Eqn use
KCL to sub vO for i1
• Using
i1 = 
vO
R2
dvo
dv1
R1C1
+ vo =  R2C1
(t )
dt
dt
Engineering-43: Engineering Circuit Analysis
7
• In Practice An Ideal
Differentiator Amplifies
Electrical Noise And Does
Not Operate well
• The Resistor R1 Introduces
a Filtering Action.
– Its Value Is Kept As Small As
Possible To Approximate
a Differentiator
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Aside → Electrical Noise
 ALL electrical signals
are corrupted by
external,
uncontrollable and
often unmeasurable,
signals. These
undesired signals are
referred to as NOISE
 Simple Model For A
Noisy 1V, 60Hz Sinusoid
Corrupted With One
MicroVolt of 1GHz
Interference
Engineering-43: Engineering Circuit Analysis
8
y(t ) = sin( 120 t ) + 106 sin( 2 109  t )
Signal
Noise
 The Signal-To-Noise Ratio
SN =
signal amplitude
1V
= 106 =
noise amplitude
V
 Use an Ideal Differentiator
dy
(t ) = 120 cos(120t ) + 2000 cos( 2 109  t )
dt
Signal
Noise
 The SN is Degraded Due
to Hi-Frequency Noise
SN =
signal amplitude
120
3
=
=
noise amplitude
2000 50
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Class Exercise  Ideal Differen.
= 1 k
= 2 F
 Given Input v1(t)
• SAWTOOTH Wave
 Let’s Turn on the Lites for
10 minutes for YOU to
Differentiate
 Given the IDEAL
Differentiator Ckt and
INPUT Signal
 Find vo(t) over 0-10 ms
 Recall the Differentiator
Eqn
dvo
dv1
R1C1
+ vo =  R2C1
(t )
dt
dt
R1 = 0; Ideal ckt
Engineering-43: Engineering Circuit Analysis
9
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Differentiator Ex.
= 1 k
= 2 F
 The Slope from 0-5 mS
dv1
10 V
m=
=
dt 5 10 3 s
 For the Ideal Differentiator
 Given Input v1(t)
Engineering-43: Engineering Circuit Analysis
10
dv1
vo =  R2C1
(t )
dt
 Units Analysis
V
V
V s
= =
=
A Q
Q
s
Q
F =   F = s
V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Differentiator cont.
= 1 k
= 2 F
dv1 t 
10 V
vo =  R2C1
= 2  10 3 S 
dt
5 10 3 S
20
vo =  V = 4V
: 0  t  5 in mS
5
 A Similar Analysis for 5-10
mS yields the Complete vO
 Derivative Scalar
PreFactor
R2C1 = 1103   2 106 F = 2 103 s
OutPut
InPut
 Apply the Prefactor
Against the INput Signal
Time-Derivative (slope)
Engineering-43: Engineering Circuit Analysis
11
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Integrator Example
= 0.2 μF
t
5 k =
1
vo (t ) = vo (0) 
vi ( x)dx

R1C2 0
vo (0) = 0V
 Given Input v1(t)
• SQUARE Wave
Engineering-43: Engineering Circuit Analysis
12
 For the Ideal Integrator
 Units Analysis Again
V
V
V s
= =
=
A Q
Q
s
Q
F =   F = s
V
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Integrator Ex. cont.
 0<t<0.1 S
• v1(t) = 20 mV (Const)
t
 R1C2 vo (t ) =  R1C2 vo (0) +  v1 (u )du = 20 mV  t
0
Note :  R1C2 vo (0.1S ) = 20 mV  0.1S = 2 mV  S
 The Integration
PreFactor
1
1
1
=
=
= 1000S 1
R1C2 5k  0.2F 0.001S
 Next Calculate the
Area Under the Curve
to Determine the
Voltage Level At the
Break Points
Engineering-43: Engineering Circuit Analysis
13
 0.1t<0.2 S
• v1(t) = –20 mV (Const)
t
 R1C2vo (t ) =  R1C2vo (0.1) +  v1 ( z )dz
0.1
= 2mV  S +  20 mV   t
 Integrate In Similar
Fashion over
• 0.2t<0.3 S
• 0.3t<0.4 S
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
RC OpAmp Integrator Ex. cont.1
 Apply the 1000/S PreFactor and Plot Piece-Wise
Engineering-43: Engineering Circuit Analysis
14
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Design Example
 Design an OpAmp ckt to implement in
HARDWARE this Math Relation
t
v0 = 5 v1  y dy  2v2
0
 Examine
the Reln to
find an
Integrator
Engineering-43: Engineering Circuit Analysis
15
Summer
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
t
Design Example
v0 = 5 v1  y dy  2v2
0
 The Proposed
Solution
 The by Ideal
OpAmps &
KCL & KVL &
Superposition
t
v0 = 5 v1  y dy  2v2
0
Engineering-43: Engineering Circuit Analysis
16
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
t
Design Example
v0 = 5 v1  y dy  2v2
0
 The Ckt Eqn
 Then the Design
Eqns
R4
R4
5=
; 2=
R1 R2C
R3
 TWO Eqns in
FIVE unknowns
Engineering-43: Engineering Circuit Analysis
17
 This means that we,
as ckt designers, get
to PICK 3 values
 For 1st Cut Choose
• C = 20 μF
• R1 = 100 kΩ
• R4 = 20 kΩ
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
t
Design Example
v0 = 5 v1  y dy  2v2
0
 In the Design Eqns
20k
5=
100kR2 20 F
 R2 = 20k
20k
2=
R3
 R3 = 10k
 Then the DESIGN
Engineering-43: Engineering Circuit Analysis
18
20μ
20k
20k
100k
10k
 If the voltages are
<10V, then all
currents should be
the in mA range,
which should
prevent over-heating
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
LM741 OpAmp Schematic
Engineering-43: Engineering Circuit Analysis
19
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Some LM741 Specs
Engineering-43: Engineering Circuit Analysis
20
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
OpAmp Frequency Response
 The Ideal OpAmp
has infinite BandWidth so NO Matter
how FAST the input
signals
vo t  = AO  v1 t   v2 t 
 However, REAL OpAmps Can NOT
Keep up with very fast signals
• The Open Loop Gain, AO, starts to degrade
with increasing input frequencies
Engineering-43: Engineering Circuit Analysis
21
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
+
vo

Gain∙BandWidth for LM741
AO  10100/ 20 = 105
−20db/Decade
Slope
The Unity Gain
Frequency, ft, is the
BandWidth Spec
f BO  100
Engineering-43: Engineering Circuit Analysis
22
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
BandWidth Limit Implications
 Recall the OpAmp
based Inverting ckt
 Noting That All the
R’s are Constant;
Rewrite above as
vO
=
vS
 The NONideal
Analysis yielded
Engineering-43: Engineering Circuit Analysis
23
  K1 

1

A

1   K 2  2 


 R2 R2 Ro  

 For Very Large A
vO
 K1 
 K1 
= lim A
=
=  K1
vS
1  K 2  A R2 Ro  1    
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
BandWidth Limit Implications
 As Frequency
Increases the OpenLoop gain, A,
declines so the Limit
does NOT hold in:
 If
A
1
 2
R2 Ro R2
 Then the Denom in
the above Eqn ≠ 1
Engineering-43: Engineering Circuit Analysis
24
 Thus significantly
smaller A
DECREASES the
Ideal gain
 For Typical Values
of the R’s the OpenLoop Gain, A,
becomes important
when A is on the
order of about 1000
 
103  20 log 103 = 60 dB
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Gain∙BandWidth for LM741
AO  10100/ 20 = 105
Engineering-43: Engineering Circuit Analysis
25
 Frequency significantly
degrades Amplification
Performance for Source
Frequencies > 10 kHz
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Voltage Swing Limitations
 Real OpAmps Can
NOT deliver
Unlimited VoltageMagnitude Output
 If the Circuit Analysis
Predicts vo of more
than the Swing, the
output will be “Clipped”
 Recall the LM741
Spec Sheet that
show a Voltage
Output Swing of
about ±15V
 Consider the Inverting
Circuit:
• For Source Voltages
of ±20 V
Engineering-43: Engineering Circuit Analysis
26
4.7 k
1 k
5.1 k
4V  cos1.6k  2  t 
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Ideal vs. Real
20
15
Vswing Clipping
VoIdeal (V)
10
5
0
-5
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
20
15
 Since the Real
OutPut can NOT
exceed 15V, the
cosine wave OutPut
is “Clipped Off” at
the Swing Spec of
15V
10
VoReal (V)
5
0
-5
-10
ENGR43_Lec14b_OpAmp_V_Swing_Plot_1204.m
-15
Bruce Mayer, PE
Engineering-43: Engineering Circuit Analysis
-20
0
27
0.5
1
1.5
2
time (mS)
2.5
3
3.5
4
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Short-Ckt Current Limitations
 Real OpAmps Can
NOT deliver
Unlimited CurrentMagnitude Output
 If the Circuit Analysis
Predicts io of more than
This Current, the output
will also be “Clipped”
 Recall the LM741
Spec Sheet that
shows an Output
Short Circuit Current
of about 25mA
 Consider the Inverting
Circuit:
4.7 k
1 k
510 
4V  cos1.6k  2  t 
Engineering-43: Engineering Circuit Analysis
28
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Ideal vs. Real
40
Current
Saturation
30
iL-Ideal (mA)
20
10
0
-10
-20
-30
-40
0
0.5
1
1.5
2
2.5
3
40
30
20
iL-Real (V)
10
 Since the Real
OutPut can NOT
exceed 25mA, the
cosine wave OutPut
is “Clipped Off” at
the Short Circuit
Current spec of
25mA
0
-10
ENGR43_Lec14b_OpAmp_Current_Saturation_
Plot_1204.m
-20
-30
Bruce Mayer, PE
Engineering-43: Engineering Circuit Analysis
-40
029
0.5
1
1.5
time (mS)
2
2.5
3
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Slew Rate = dvo/dt
 For a Real OpAmp
we expect the
OutPut Cannot Rise
or Fall Infinitely
Fast.
 Mathematically the
Slew Rate limitation
 This Rise/Fall
Speed is quantified
as the “Slew Rate”,
SR
 The 741 Specs
indicate a Slew Rate
of
Engineering-43: Engineering Circuit Analysis
30
dv o
 SR
dt
SR = 0.5 V µS OR
SR = 500,000 V S
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Slew Rate = dvo/dt
 If dvin/dt exceeds the
SR at any point in
time, then the output
will NOT be Faithful
to input
• The OpAmp can
NOT “Keep Up” with
the Input
 Consider the
Example at Top
Right
Engineering-43: Engineering Circuit Analysis
31
  105 
2.5V sin 
 t 
 sec

 Then the Time
Slope of the Source
  105   105
dv s
= 2.5V  cos
 t  
dt
 sec
 sec
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Slew Rate = dvo/dt
 The Maximum value
of dvS/dt Occurs at
t=0. Compare the
max to the SR
dv s
dt
dv s
dt
= 2.5V 1
max
max
 105
sec
V
= 785 400
sec
 Thus the source
Rises & Falls Faster
than the SR
Engineering-43: Engineering Circuit Analysis
32
  105 
2.5V sin 
 t 
 sec

 When the Source
Slope exceeds the SR
the OpAmp Output
Rises/Falls at the SR
• This produces a
STRAIGHT-LINE
output with a slope of
the SR when the
source rises/falls
Faster than the SR
until the OpAmp
“Catches Up” with
the Ideal Bruce
OutPut
Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Slew Rate = dvo/dt
  105 
2.5V sin 
 t 
 sec

vo , Ideal
vo ,Real
t µS 
Engineering-43: Engineering Circuit Analysis
33
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Full Power BandWidth
 The Full Power BW
is the Maximum
Frequency that the
OpAmp can Deliver
an Undistorted
Sinusoidal Signal
• The Quantity, fFP, is
limited by the SLEW
RATE
 Determine This
Metric for the LM741
Engineering-43: Engineering Circuit Analysis
34
 The 741 has a max
output, Vom, of ±12V
 Applying a sinusoid
to the input find at full
OutPut power (Full
Output Voltage)
vo t  = Vom sin t 
 Recall the Slew Rate
dv o
 SR
dt
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Full Power BandWidth
 Taking d/dt of the
OpAmp running at
Full Output
d
vo t  = Vom sin t  
dt
dvo t 
= Vom cost 
dt
 Thus the maximum
output change-rate
(slope) in magnitude
Engineering-43: Engineering Circuit Analysis
35
dvo t 
= Vom cosnt 
dt max
dvo t 
or
= Vom
dt max
 Recall ω = 2πf
 Setting |dvo/dt|max =
to the Slew Rate
Vom = 2πfVom = SR
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Full Power BandWidth
 Isolating f in the last
expression yields
SR
fFP:
f FP =
2πVom
 From the LM741
Spec Sheet
• SR = 0.5 V/µS
• |Vomax|min = 12V
 Then fFP:
Engineering-43: Engineering Circuit Analysis
36
0.5 V/µS
f FP,LM741 =
2π
12 V 
cycle
0.0066 cycle
f FP,LM741 =
µS
6631 cycle
f FP,LM741 =
=
S
f FP,LM741  6.63 kHz
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Full Power BandWidth
 Thus the 741
OpAmp can deliver
UNdistorted, Full
Voltage, sinusoidal
Output (±12V) for
input Frequencies
up to about 6.63
kHz
Engineering-43: Engineering Circuit Analysis
37
f FP,LM741  6.63 kHz
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
WhiteBoard Work
 Let’s Work These Probs
 Choose C v =  10 v t dt
o
S
S 
Such That
Find
Energy
Stored
on Cx
+
+
8V
60µF
-
24V
Cx
-
Engineering-43: Engineering Circuit Analysis
38
Figure PFE-3
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
All Done for Today
OpAmp
Circuit
Design
Engineering-43: Engineering Circuit Analysis
39
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering 43
Appendix
Bruce Mayer, PE
Registered Electrical & Mechanical Engineer
BMayer@ChabotCollege.edu
Engineering-43: Engineering Circuit Analysis
40
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering-43: Engineering Circuit Analysis
41
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering-43: Engineering Circuit Analysis
42
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering-43: Engineering Circuit Analysis
43
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering-43: Engineering Circuit Analysis
44
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Engineering-43: Engineering Circuit Analysis
45
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Practical Example
 Simple Circuit Model For a
Dynamic Random Access Memory Cell (DRAM)
 Note How Undesired
Current Leakage is
Modeled as an I-Src
Engineering-43: Engineering Circuit Analysis
46
 Also Note the TINY Value
of the Cell-State
Capacitance (50x10-15 F)
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Practical Example cont
 During a WRITE Cycle the
Cell Cap is Charged to 3V
for a Logic-1
 The Criteria for a
Logic “1”
• Vcell >1.5 V
 Now Recall that
V = Q/C
• Or in terms of Current
t
1
vC = vC (0) +  iC ( x)dx
C0
Engineering-43: Engineering Circuit Analysis
47
• Thus The TIME PERIOD
that the cell can HOLD the
Logic-1 value
Vcell = 3V 
I leak  t
I
 1.5V  leak t  1.5V
Ccell
Ccell
1.5(V )  50 1015 ( F )
3
tH =
=
1
.
5

10
s
12
50 10 A
 Now Can Calculate the
DRAM “Refresh Rate”
1
1
f R ,min =
=
= 667 Hz
t H 1.5mS
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx
Practical Example cont.2
 Consider the Cell at the
Beginning of a READ
Operation
Qcell = 3V  50 fF = 150 fCoul
Qout = 1.5V  450 fF = 675 fCoul
Qtotal = 150 fCoul + 675 fCoul = 825 fCoul
 When the Switch is
Connected Have Caps in
Parallel
Ctotal = 50 + 450 = 500 fF
 Then The Output
 Calc the Best-Case
Change in VI/O at the
READ
Engineering-43: Engineering Circuit Analysis
48
VI / O
Q 825 fCoul
= =
= 1.65V
C
500 fF
Bruce Mayer, PE
BMayer@ChabotCollege.edu • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx