CSCE 212 Computer Architecture
Lecture 10
Y86 – a RISC Architecture
Topics


Feb 16, 2012
Structures from Lec10
Y86, a RISC architecture
Overview
Last Time


Test 1
Time before - Aggregate Data
 Array layout in memory
 Structures
New





Arrays of Structures
Linux Memory Layout
A restricted Intel Architecture Y86 - RISC
HCL
Test 1
Next Time:

–2–
New Lab - datalab
CSCE 212H Spring 2012
What is Computer Architecture?
“Computer Architecture is those aspects of the
instruction set available to programmers,
independent of the hardware on which the
instruction set was implemented.”
The term computer architecture was first used in 1964
by Gene Amdahl, G. Anne Blaauw, and Frederick
Brooks, Jr., the designers of the IBM System/360.
Fred Brooks “Mythical Man-Month”
Y86 is a hypothetical machine that is a simplification of
the IA32 architecture so that we can fully describe its
implementation.
–3–
CSCE 212H Spring 2012
Instruction Set Architecture
Assembly Language View

Processor state
 Registers, memory, …

Instructions
 addl, movl, leal, …
 How instructions are encoded
as bytes
Layer of Abstraction

Above: how to program machine
 Processor executes instructions
Application
Program
Compiler
OS
ISA
CPU
Design
Circuit
Design
in a sequence

Below: what needs to be built
 Use variety of tricks to make it
–4–
run fast
 E.g., execute multiple
instructions simultaneously
Chip
Layout
CSCE 212H Spring 2012
Y86 Processor State
Program
registers
%eax
%esi
%ecx
%edi
%edx
%esp
%ebx
%ebp

Condition
codes
Memory
OF ZF SF
PC
Program Registers
 Same 8 as with IA32. Each 32 bits

Condition Codes
 Single-bit flags set by arithmetic or logical instructions
» OF: Overflow

ZF: Zero
SF:Negative
Program Counter
 Indicates address of instruction

Memory
 Byte-addressable storage array
 Words stored in little-endian byte order
–5–
CSCE 212H Spring 2012
Y86 Instructions
Format

1--6 bytes of information read from memory
 Can determine instruction length from first byte
 Not as many instruction types, and simpler encoding than with
IA32

–6–
Each accesses and modifies some part(s) of the program
state
CSCE 212H Spring 2012
Encoding Registers
Each register has 4-bit ID
%eax
%ecx
%edx
%ebx

0
1
2
3
%esi
%edi
%esp
%ebp
6
7
4
5
Same encoding as in IA32
Register ID 8 indicates “no register”

–7–
Will use this in our hardware design in multiple places
CSCE 212H Spring 2012
Instruction Example
Addition Instruction
Generic Form
Encoded Representation
addl rA, rB

6 0 rA rB
Add value in register rA to that in register rB
 Store result in register rB
 Note that Y86 only allows addition to be applied to register data

Set condition codes based on result
e.g., addl %eax,%esi Encoding: 60 06

Two-byte encoding

 First indicates instruction type
 Second gives source and destination registers
–8–
CSCE 212H Spring 2012
Arithmetic and Logical Operations
Instruction Code
Add
addl rA, rB
Function Code
6 0 rA rB

Refer to generically as
“OPl”

Encodings differ only by
“function code”
Subtract (rA from rB)
subl rA, rB
 Low-order 4 bytes in first
instruction word
6 1 rA rB

And
andl rA, rB
Set condition codes as
side effect
6 2 rA rB
Exclusive-Or
xorl rA, rB
–9–
6 3 rA rB
CSCE 212H Spring 2012
Move Operations
rrmovl rA, rB
Register --> Register
2 0 rA rB
3 0 8 rB
V
rmmovl rA, D(rB) 4 0 rA rB
D
5 0 rA rB
D
irmovl V, rB
mrmovl D(rB), rA
Register --> Memory
Memory --> Register

Like the IA32 movl instruction

Simpler format for memory addresses
Give different names to keep them distinct

– 10 –
Immediate --> Register
CSCE 212H Spring 2012
Move Instruction Examples
IA32
Y86
Encoding
movl $0xabcd, %edx
irmovl $0xabcd, %edx
30 82 cd ab 00 00
movl %esp, %ebx
rrmovl %esp, %ebx
20 43
movl -12(%ebp),%ecx
mrmovl -12(%ebp),%ecx
50 15 f4 ff ff ff
movl %esi,0x41c(%esp)
rmmovl %esi,0x41c(%esp)
40 64 1c 04 00 00
movl $0xabcd, (%eax)
—
movl %eax, 12(%eax,%edx)
—
movl (%ebp,%eax,4),%ecx
—
– 11 –
CSCE 212H Spring 2012
Jump Instructions
Jump Unconditionally
jmp Dest
7 0
Dest

Refer to generically as
“jXX”
Dest

Encodings differ only by
“function code”
Based on values of
condition codes
Same as IA32 counterparts
Encode full destination
address
Jump When Less or Equal
jle Dest
7 1
Jump When Less
jl Dest
7 2
Dest
Jump When Equal
je Dest
7 3

Dest
Jump When Not Equal
jne Dest
7 4
Dest
7 5

 Unlike PC-relative
addressing seen in IA32
Jump When Greater or Equal
jge Dest

Dest
Jump When Greater
jg Dest
– 12 –
7 6
Dest
CSCE 212H Spring 2012
Y86 Program Stack
Stack
“Bottom”



•
Increasing
Addresses
Region of memory holding
program data
Used in Y86 (and IA32) for
supporting procedure calls
Stack top indicated by %esp
 Address of top stack element
•

•
Stack grows toward lower
addresses
 Top element is at highest
%esp
Stack “Top”
– 13 –
address in the stack
 When pushing, must first
decrement stack pointer
 When popping, increment stack
pointer
CSCE 212H Spring 2012
Stack Operations
pushl rA

Decrement %esp by 4
Store word from rA to memory at %esp

Like IA32

popl rA
– 14 –
a 0 rA 8
b 0 rA 8

Read word from memory at %esp


Save in rA
Increment %esp by 4

Like IA32
CSCE 212H Spring 2012
Subroutine Call and Return
call Dest



ret



– 15 –
8 0
Dest
Push address of next instruction onto stack
Start executing instructions at Dest
Like IA32
9 0
Pop value from stack
Use as address for next instruction
Like IA32
CSCE 212H Spring 2012
Miscellaneous Instructions
0 0
nop

Don’t do anything
halt



– 16 –
1 0
Stop executing instructions
IA32 has comparable instruction, but can’t execute it in
user mode
We will use it to stop the simulator
CSCE 212H Spring 2012
Writing Y86 Code
Try to Use C Compiler as Much as Possible

Write code in C
Compile for IA32 with gcc -S

Transliterate into Y86

Coding Example

Find number of elements in null-terminated list
int len1(int a[]);
a
5043
6125
7395
 3
0
– 17 –
CSCE 212H Spring 2012
Y86 Code Generation Example
First Try

Write typical array code
Problem

Hard to do array indexing on
Y86
 Since don’t have scaled
/* Find number of elements in
null-terminated list */
int len1(int a[])
{
int len;
for (len = 0; a[len]; len++)
;
return len;
}

– 18 –
addressing modes
L18:
incl %eax
cmpl $0,(%edx,%eax,4)
jne L18
Compile with gcc -O2 -S
CSCE 212H Spring 2012
Y86 Code Generation Example #2
Second Try

Write with pointer code
/* Find number of elements in
null-terminated list */
int len2(int a[])
{
int len = 0;
while (*a++)
len++;
return len;
}

– 19 –
Result

Don’t need to do indexed
addressing
L24:
movl (%edx),%eax
incl %ecx
L26:
addl $4,%edx
testl %eax,%eax
jne L24
Compile with gcc -O2 -S
CSCE 212H Spring 2012
Y86 Code Generation Example #3
IA32 Code

Setup
len2:
pushl %ebp
xorl %ecx,%ecx
movl %esp,%ebp
movl 8(%ebp),%edx
movl (%edx),%eax
jmp L26
– 20 –
Y86 Code

Setup
len2:
pushl %ebp
#
xorl %ecx,%ecx
#
rrmovl %esp,%ebp
#
mrmovl 8(%ebp),%edx #
mrmovl (%edx),%eax #
jmp L26
#
Save %ebp
len = 0
Set frame
Get a
Get *a
Goto entry
CSCE 212H Spring 2012
Y86 Code Generation Example #4
IA32 Code

Loop + Finish
L24:
movl (%edx),%eax
incl %ecx
L26:
addl $4,%edx
testl %eax,%eax
jne L24
movl %ebp,%esp
movl %ecx,%eax
popl %ebp
ret
– 21 –
Y86 Code

Loop + Finish
L24:
mrmovl (%edx),%eax
irmovl $1,%esi
addl %esi,%ecx
L26:
irmovl $4,%esi
addl %esi,%edx
andl %eax,%eax
jne L24
rrmovl %ebp,%esp
rrmovl %ecx,%eax
popl %ebp
ret
# Get *a
# len++
# Entry:
#
#
#
#
#
a++
*a == 0?
No--Loop
Pop
Rtn len
CSCE 212H Spring 2012
Y86 Program Structure
irmovl Stack,%esp
rrmovl %esp,%ebp
irmovl List,%edx
pushl %edx
call len2
halt
.align 4
List:
.long 5043
.long 6125
.long 7395
.long 0
# Set up stack
# Set up frame
# Push argument
# Call Function
# Halt


Program starts at
address 0
Must set up stack
 Make sure don’t
overwrite code!
# List of elements


Must initialize data
Can use symbolic
names
# Function
len2:
. . .
# Allocate space for stack
.pos 0x100
Stack:
– 22 –
CSCE 212H Spring 2012
Assembling Y86 Program
unix> yas eg.ys

Generates “object code” file eg.yo
 Actually looks like disassembler output
0x000:
0x006:
0x008:
0x00e:
0x010:
0x015:
0x018:
0x018:
0x018:
0x01c:
0x020:
0x024:
– 23 –
308400010000
2045
308218000000
a028
8028000000
10
b3130000
ed170000
e31c0000
00000000
|
|
|
|
|
|
|
|
|
|
|
|
irmovl Stack,%esp
rrmovl %esp,%ebp
irmovl List,%edx
pushl %edx
call len2
halt
.align 4
List:
.long 5043
.long 6125
.long 7395
.long 0
# Set up stack
# Set up frame
# Push argument
# Call Function
# Halt
# List of elements
CSCE 212H Spring 2012
Simulating Y86 Program
unix> yis eg.yo

Instruction set simulator
 Computes effect of each instruction on processor state
 Prints changes in state from original
Stopped in 41 steps at PC = 0x16. Exception 'HLT', CC Z=1 S=0 O=0
Changes to registers:
%eax:
0x00000000
0x00000003
%ecx:
0x00000000
0x00000003
%edx:
0x00000000
0x00000028
%esp:
0x00000000
0x000000fc
%ebp:
0x00000000
0x00000100
%esi:
0x00000000
0x00000004
Changes to memory:
0x00f4:
0x00f8:
0x00fc:
– 24 –
0x00000000
0x00000000
0x00000000
0x00000100
0x00000015
0x00000018
CSCE 212H Spring 2012
CISC Instruction Sets


Complex Instruction Set Computer
Dominant style through mid-80’s
Stack-oriented instruction set


Use stack to pass arguments, save program counter
Explicit push and pop instructions
Arithmetic instructions can access memory

addl %eax, 12(%ebx,%ecx,4)
 requires memory read and write
 Complex address calculation
Condition codes

Set as side effect of arithmetic and logical instructions
Philosophy

– 25 –
Add instructions to perform “typical” programming tasks
CSCE 212H Spring 2012
RISC Instruction Sets


Reduced Instruction Set Computer
Internal project at IBM, later popularized by Hennessy
(Stanford) and Patterson (Berkeley)
Fewer, simpler instructions


Might take more to get given task done
Can execute them with small and fast hardware
Register-oriented instruction set


Many more (typically 32) registers
Use for arguments, return pointer, temporaries
Only load and store instructions can access memory

Similar to Y86 mrmovl and rmmovl
No Condition codes

– 26 –
Test instructions return 0/1 in register
CSCE 212H Spring 2012
HCL Word-Level Examples
Minimum of 3 Words
C
B
A
MIN3
Min3
int Min3 = [
A < B && A < C : A;
B < A && B < C : B;
1
: C;
];



Find minimum of three
input words
HCL case expression
Final case guarantees
match
4-Way Multiplexor
s1
s0
D0
D1
D2
D3
– 27 –
MUX4
Out4
int Out4 = [
!s1&&!s0: D0;
!s1
: D1;
!s0
: D2;
1
: D3;
];

Select one of 4 inputs
based on two control
bits

HCL case expression
Simplify tests by
assuming sequential
matching

CSCE 212H Spring 2012
HCL Word-Level Examples
Minimum of 3 Words
C
B
A
MIN3
Min3
int Min3 = [
A < B && A < C : A;
B < A && B < C : B;
1
: C;
];



Find minimum of three
input words
HCL case expression
Final case guarantees
match
4-Way Multiplexor
s1
s0
D0
D1
D2
D3
– 28 –
MUX4
Out4
int Out4 = [
!s1&&!s0: D0;
!s1
: D1;
!s0
: D2;
1
: D3;
];

Select one of 4 inputs
based on two control
bits

HCL case expression
Simplify tests by
assuming sequential
matching

CSCE 212H Spring 2012
Hardware Control Language


Very simple hardware description language
Can only express limited aspects of hardware operation
 Parts we want to explore and modify
Data Types

bool: Boolean
 a, b, c, …

int: words
 A, B, C, …
 Does not specify word size---bytes, 32-bit words, …
Statements
– 29 –

bool a = bool-expr ;

int A = int-expr ;
CSCE 212H Spring 2012
HCL Operations

Classify by type of value returned
Boolean Expressions

Logic Operations
 a && b, a || b, !a

Word Comparisons
 A == B, A != B, A < B, A <= B, A >= B, A > B

Set Membership
 A in { B, C, D }
» Same as A == B || A == C || A == D
Word Expressions

Case expressions
 [ a : A; b : B; c : C ]
 Evaluate test expressions a, b, c, … in sequence
 Return word expression A, B, C, … for first successful test
– 30 –
CSCE 212H Spring 2012
Y86 Instruction Set
Byte
0
nop
0
0
halt
1
0
rrmovl rA, rB
2
0 rA rB
irmovl V, rB
3
0
8 rB
V
rmmovl rA, D(rB)
4
0 rA rB
D
mrmovl D(rB), rA
OPl rA, rB
jXX Dest
call Dest
ret
pushl rA
popl rA
– 31 –
5
1
2
3
0 rA rB
4
5
addl
6
0
subl
6
1
andl
6
2
xorl
6
3
jmp
7
0
jle
7
1
jl
7
2
je
7
3
jne
7
4
jge
7
5
jg
7
6
D
6 fn rA rB
7
8
9
A
B
fn
0
Dest
Dest
0
0 rA 8
0 rA 8
CSCE 212H Spring 2012
Building Blocks
fun
Combinational Logic






– 32 –
Store bits
Addressable memories
Non-addressable registers
Loaded only as clock rises
=
A
L
U
Compute Boolean functions of
inputs
B
Continuously respond to input
changes
Operate on data and implement
control
Storage Elements

A
0
MUX
1
valA
srcA
A
valW
Register
file
valB
srcB
B
W
dstW
Clock
Clock
CSCE 212H Spring 2012
Hardware Control Language


Very simple hardware description language
Can only express limited aspects of hardware operation
 Parts we want to explore and modify
Data Types

bool: Boolean
 a, b, c, …

int: words
 A, B, C, …
 Does not specify word size---bytes, 32-bit words, …
Statements
– 33 –

bool a = bool-expr ;

int A = int-expr ;
CSCE 212H Spring 2012
HCL Operations

Classify by type of value returned
Boolean Expressions

Logic Operations
 a && b, a || b, !a

Word Comparisons
 A == B, A != B, A < B, A <= B, A >= B, A > B

Set Membership
 A in { B, C, D }
» Same as A == B || A == C || A == D
Word Expressions

Case expressions
 [ a : A; b : B; c : C ]
 Evaluate test expressions a, b, c, … in sequence
 Return word expression A, B, C, … for first successful test
– 34 –
CSCE 212H Spring 2012
SEQ Hardware
Structure
newPC
PC
valE, valM
Write back
valM
State




Program counter register (PC)
Condition code register (CC)
Data
Data
memory
memory
Memory
Addr, Data
Register File
Memories
 Access same memory space
valE
Bch
Execute
CC
CC
aluA, aluB
 Data: for reading/writing program
data
 Instruction: for reading
instructions
Instruction Flow

Read instruction at address
specified by PC

Process through stages
Update program counter

ALU
ALU
valA, valB
srcA, srcB
dstA, dstB
Decode
A
B
Register
RegisterM
file
file
E
icode ifun
rA , rB
valC
valP
,
Fetch
Instruction
Instruction
memory
memory
PC
PC
increment
increment
PC
– 35 –
CSCE 212H Spring 2012
newPC
SEQ Stages
PC
valE, valM
Write back
valM
Fetch

Read instruction from instruction
memory
Data
Data
memory
memory
Memory
Addr, Data
Decode

Read program registers
Execute

valE
Bch
Execute
CC
CC
aluA, aluB
Compute value or address
valA, valB
Memory

Read or write data
icode ifun
rA , rB
valC
B
valP
,
Fetch

A
Register
RegisterM
file
file
E
Write program registers
PC
srcA, srcB
dstA, dstB
Decode
Write Back

ALU
ALU
Instruction
Instruction
memory
memory
PC
PC
increment
increment
Update program counter
PC
– 36 –
CSCE 212H Spring 2012
Instruction Decoding
Optional
5
Optional
0 rA rB
D
icode
ifun
rA
rB
valC
Instruction Format



– 37 –
Instruction byte
icode:ifun
Optional register byte
rA:rB
Optional constant word valC
CSCE 212H Spring 2012
Executing Arith./Logical Operation
OPl rA, rB
Fetch

Memory
Read 2 bytes
Decode

Read operand registers
Execute


– 38 –
6 fn rA rB
Perform operation
Set condition codes

Do nothing
Write back

Update register
PC Update

Increment PC by 2
CSCE 212H Spring 2012
Stage Computation: Arith/Log. Ops
OPl rA, rB
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valP  PC+2
Compute next PC
valA  R[rA]
Read operand A
valB  R[rB]
Read operand B
valE  valB OP valA
Perform ALU operation
Set CC
Set condition code register
Memory
Write
R[rB]  valE
Write back result
back
PC update
PC  valP
Update PC
Fetch
Decode
Execute


– 39 –
Formulate instruction execution as sequence of simple steps
Use same general form for all instructions
CSCE 212H Spring 2012
Executing rmmovl
rmmovl rA, D(rB) 4 0 rA rB
Fetch

Memory
Read 6 bytes
Decode

Read operand registers
Execute

– 40 –
D
Compute effective address

Write to memory
Write back

Do nothing
PC Update

Increment PC by 6
CSCE 212H Spring 2012
Stage Computation: rmmovl
rmmovl rA, D(rB)
Fetch
Decode
Execute
Memory
Write
back
PC update

– 41 –
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valC  M4[PC+2]
Read displacement D
valP  PC+6
Compute next PC
valA  R[rA]
Read operand A
valB  R[rB]
Read operand B
valE  valB + valC
Compute effective address
M4[valE]  valA
Write value to memory
PC  valP
Update PC
Use ALU for address computation
CSCE 212H Spring 2012
Executing popl
popl rA
Fetch

Memory
Read 2 bytes
Decode

Read stack pointer
Execute

b 0 rA 8
Increment stack pointer by 4

Write back

Update stack pointer

Write result to register
PC Update

– 42 –
Read from old stack pointer
Increment PC by 2
CSCE 212H Spring 2012
Stage Computation: popl
popl rA
icode:ifun  M1[PC]
Read instruction byte
rA:rB  M1[PC+1]
Read register byte
valP  PC+2
valA  R[%esp]
Compute next PC
valB  R [%esp]
Read stack pointer
valE  valB + 4
Increment stack pointer
Memory
Write
valM  M4[valA]
R[%esp]  valE
Read from stack
back
PC update
R[rA]  valM
Write back result
PC  valP
Update PC
Fetch
Decode
Execute


Read stack pointer
Update stack pointer
Use ALU to increment stack pointer
Must update two registers
 Popped value
– 43 –
 New stack pointer
CSCE 212H Spring 2012
Executing Jumps
jXX Dest
7 fn
fall thru:
XX XX
Not taken
target:
XX XX
Taken
Fetch


Memory
Read 5 bytes
Increment PC by 5
Decode

Do nothing
Execute

– 44 –
Dest
Determine whether to take
branch based on jump
condition and condition
codes

Do nothing
Write back

Do nothing
PC Update

Set PC to Dest if branch
taken or to incremented PC
if not branch
CSCE 212H Spring 2012
Stage Computation: Jumps
jXX Dest
Fetch
icode:ifun  M1[PC]
Read instruction byte
valC  M4[PC+1]
Read destination address
valP  PC+5
Fall through address
Bch  Cond(CC,ifun)
Take branch?
PC  Bch ? valC : valP
Update PC
Decode
Execute
Memory
Write
back
PC update


– 45 –
Compute both addresses
Choose based on setting of condition codes and branch
condition
CSCE 212H Spring 2012
Executing call
8 0
call Dest
return:
XX XX
target:
XX XX
Fetch
Memory

Read 5 bytes

Increment PC by 5
Decode

Read stack pointer
Execute

– 46 –
Dest
Decrement stack pointer by
4

Write incremented PC to
new value of stack pointer
Write back

Update stack pointer
PC Update

Set PC to Dest
CSCE 212H Spring 2012
Stage Computation: call
call Dest
icode:ifun  M1[PC]
Read instruction byte
valC  M4[PC+1]
Read destination address
valP  PC+5
Compute return point
valB  R[%esp]
Read stack pointer
valE  valB + –4
Decrement stack pointer
Memory
Write
M4[valE]  valP
R[%esp]  valE
Write return value on stack
back
PC update
PC  valC
Set PC to destination
Fetch
Decode
Execute


– 47 –
Update stack pointer
Use ALU to decrement stack pointer
Store incremented PC
CSCE 212H Spring 2012
Executing ret
9 0
ret
return:
XX XX
Fetch

Memory
Read 1 byte

Decode

Read stack pointer
Execute

Increment stack pointer by 4
Write back

Update stack pointer
PC Update

– 48 –
Read return address from
old stack pointer
Set PC to return address
CSCE 212H Spring 2012
Stage Computation: ret
ret
icode:ifun  M1[PC]
Read instruction byte
valA  R[%esp]
Read operand stack pointer
valB  R[%esp]
Read operand stack pointer
valE  valB + 4
Increment stack pointer
Memory
Write
valM  M4[valA]
R[%esp]  valE
Read return address
back
PC update
PC  valM
Set PC to return address
Fetch
Decode
Execute


– 49 –
Update stack pointer
Use ALU to increment stack pointer
Read return address from memory
CSCE 212H Spring 2012
Computation Steps
OPl rA, rB
Fetch
Decode
Execute
icode:ifun  M1[PC]
Read instruction byte
rA,rB
rA:rB  M1[PC+1]
Read register byte
valC
[Read constant word]
valP
valP  PC+2
Compute next PC
valA, srcA
valA  R[rA]
Read operand A
valB, srcB
valB  R[rB]
Read operand B
valE
valE  valB OP valA
Perform ALU operation
Cond code Set CC
Set condition code register
Memory
Write
valM
[Memory read/write]
back
PC update
dstM


– 50 –
icode,ifun
dstE
PC
R[rB]  valE
Write back ALU result
[Write back memory result]
PC  valP
Update PC
All instructions follow same general pattern
Differ in what gets computed on each step
CSCE 212H Spring 2012
Computation Steps
call Dest
icode,ifun
Fetch
Decode
Execute
Read instruction byte
[Read register byte]
valC
valC  M4[PC+1]
Read constant word
valP
valP  PC+5
Compute next PC
valA, srcA
[Read operand A]
valB, srcB
valB  R[%esp]
Read operand B
valE
valE  valB + –4
Perform ALU operation
Cond code
valM
back
PC update
dstM

– 51 –
rA,rB
Memory
Write

icode:ifun  M1[PC]
dstE
PC
[Set condition code reg.]
M4[valE]  valP
R[%esp]  valE
[Memory read/write]
[Write back ALU result]
Write back memory result
PC  valC
Update PC
All instructions follow same general pattern
Differ in what gets computed on each step
CSCE 212H Spring 2012
Computed Values
Fetch
Execute
icode
ifun
Instruction code
Instruction function
rA
rB
valC
valP
Instr. Register A
Instr. Register B
Instruction constant
Incremented PC


valE
Bch
ALU result
Branch flag
Memory

valM Value from
memory
Decode
– 52 –
srcA
srcB
dstE
Register ID A
Register ID B
Destination Register E
dstM
valA
valB
Destination Register M
Register value A
Register value B
CSCE 212H Spring 2012
newPC
SEQ Hardware
New
PC
PC
Key
valM
data out

Blue boxes:
predesigned hardware
blocks
read
write
Addr
 E.g., memories, ALU

Gray boxes:
control logic
Data
Data
memory
memory
Mem.
control
Memory
Execute
Bch
valE
CC
CC
ALU
ALU
ALU
A
Data
ALU
fun.
ALU
B
 Describe in HCL




– 53 –
White ovals:
labels for signals
Thick lines:
32-bit word values
Thin lines:
4-8 bit values
Dotted lines:
1-bit values
valA
Decode
A
valB
dstE dstM srcA
srcB
dstE dstM srcA
srcB
B
Register
Register M
file
file E
Write back
icode
Fetch
ifun
rA
rB
Instruction
Instruction
memory
memory
valC
valP
PC
PC
increment
increment
PC
CSCE 212H Spring 2012
Fetch Logic
icode
ifun
rA
rB
valC
valP
Need
valC
Instr
valid
Need
regids
Split
Split
PC
PC
increment
increment
Align
Align
Byte 0
Bytes 1-5
Instruction
Instruction
memory
memory
Predefined Blocks




– 54 –
PC
PC: Register containing PC
Instruction memory: Read 6 bytes (PC to PC+5)
Split: Divide instruction byte into icode and ifun
Align: Get fields for rA, rB, and valC
CSCE 212H Spring 2012
Fetch Logic
icode
ifun
rA
rB
valC
valP
Need
valC
Instr
valid
Need
regids
Split
Split
PC
PC
increment
increment
Align
Align
Byte 0
Bytes 1-5
Instruction
Instruction
memory
memory
PC
Control Logic



– 55 –
Instr. Valid: Is this instruction valid?
Need regids: Does this instruction have a register byte?
Need valC: Does this instruction have a constant word?
CSCE 212H Spring 2012
Fetch Control
Logic
nop
0
0
halt
1
0
rrmovl rA, rB
2
0 rA rB
irmovl V, rB
3
0
8 rB
V
rmmovl rA, D(rB)
4
0 rA rB
D
mrmovl D(rB), rA
5
0 rA rB
D
OPl rA, rB
6
fn rA rB
jXX Dest
7
fn
Dest
call Dest
8
0
Dest
ret
9
0
pushl rA
A
0 rA 8
popl rA
B
0 rA 8
bool need_regids =
icode in { IRRMOVL, IOPL, IPUSHL, IPOPL,
IIRMOVL, IRMMOVL, IMRMOVL };
bool instr_valid = icode in
{ INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL,
IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };
– 56 –
CSCE 212H Spring 2012
Decode Logic
valA
valB
A
B
valM valE
Register File



Read ports A, B
Write ports E, M
Addresses are register IDs or
8 (no access)
Register
Register
file
file
dstE
dstM
srcA
M
E
srcB
dstE dstM srcA srcB
Control Logic


– 57 –
srcA, srcB: read port
addresses
dstA, dstB: write port
addresses
icode
rA
rB
CSCE 212H Spring 2012
A Source
Decode
OPl rA, rB
valA  R[rA]
Read operand A
rmmovl rA, D(rB)
Decode
valA  R[rA]
Read operand A
popl rA
Decode
valA  R[%esp]
Read stack pointer
jXX Dest
Decode
No operand
call Dest
Decode
No operand
ret
Decode
valA  R[%esp]
Read stack pointer
int srcA = [
icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL
icode in { IPOPL, IRET } : RESP;
1 : RNONE; # Don't need register
];
– 58 –
} : rA;
CSCE 212H Spring 2012
E Destination
OPl rA, rB
Write-back R[rB]  valE
Write back result
rmmovl rA, D(rB)
Write-back
None
popl rA
Write-back R[%esp]  valE
Update stack pointer
jXX Dest
Write-back
None
call Dest
Write-back R[%esp]  valE
Update stack pointer
ret
Write-back R[%esp]  valE
Update stack pointer
int dstE = [
icode in { IRRMOVL, IIRMOVL, IOPL} : rB;
icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP;
1 : RNONE; # Don't need register
];
– 59 –
CSCE 212H Spring 2012
Execute Logic
Units

ALU
 Implements 4 required functions
 Generates condition code values

Bch
CC
 Register with 3 condition code
bcond
bcond
bits

valE
CC
CC
bcond
ALU
fun.
ALU
ALU
 Computes branch flag
Set
CC
Control Logic




– 60 –
Set CC: Should condition code
register be loaded?
ALU A: Input A to ALU
icode ifun
ALU
A
valC
ALU
B
valA
valB
ALU B: Input B to ALU
ALU fun: What function should
ALU compute?
CSCE 212H Spring 2012
ALU A Input
Execute
OPl rA, rB
valE  valB OP valA
Perform ALU operation
rmmovl rA, D(rB)
Execute
valE  valB + valC
Compute effective address
popl rA
Execute
valE  valB + 4
Increment stack pointer
jXX Dest
Execute
No operation
call Dest
Execute
valE  valB + –4
Decrement stack pointer
ret
Execute
valE  valB + 4
Increment stack pointer
int aluA = [
icode in { IRRMOVL, IOPL } : valA;
icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC;
icode in { ICALL, IPUSHL } : -4;
icode in { IRET, IPOPL } : 4;
# Other instructions don't need ALU
– 61 –
CSCE 212H Spring 2012
];
ALU Operation
OPl rA, rB
Execute
valE  valB OP valA
Perform ALU operation
rmmovl rA, D(rB)
Execute
valE  valB + valC
Compute effective address
popl rA
Execute
valE  valB + 4
Increment stack pointer
jXX Dest
Execute
No operation
call Dest
Execute
valE  valB + –4
Decrement stack pointer
ret
Execute
– 62 –
valE  valB + 4
Increment stack pointer
int alufun = [
icode == IOPL : ifun;
1 : ALUADD;
];
CSCE 212H Spring 2012
Memory Logic
Memory

valM
Reads or writes memory
word
data out
Mem.
read
Mem.
write
Control Logic




– 63 –
Mem. read: should word be
read?
Mem. write: should word be
written?
Mem. addr.: Select address
Mem. data.: Select data
read
Data
Data
memory
memory
write
data in
Mem
addr
icode
valE
Mem
data
valA valP
CSCE 212H Spring 2012
Memory Address
OPl rA, rB
Memory
No operation
rmmovl rA, D(rB)
Memory
M4[valE]  valA
Write value to memory
popl rA
Memory
valM  M4[valA]
Read from stack
jXX Dest
Memory
No operation
call Dest
Memory
M4[valE]  valP
Write return value on stack
ret
Memory
valM  M4[valA]
Read return address
int mem_addr = [
icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE;
icode in { IPOPL, IRET } : valA;
# Other instructions don't need address
– 64 – ];
CSCE 212H Spring 2012
Memory Read
OPl rA, rB
Memory
No operation
rmmovl rA, D(rB)
Memory
M4[valE]  valA
Write value to memory
popl rA
Memory
valM  M4[valA]
Read from stack
jXX Dest
Memory
No operation
call Dest
Memory
M4[valE]  valP
Write return value on stack
ret
Memory
valM  M4[valA]
Read return address
bool mem_read = icode in { IMRMOVL, IPOPL, IRET };
– 65 –
CSCE 212H Spring 2012
PC Update Logic
PC
New PC

New
PC
Select next value of PC
icode
– 66 –
Bch
valC
valM
valP
CSCE 212H Spring 2012
PC
Update
OPl rA, rB
PC update
PC  valP
Update PC
rmmovl rA, D(rB)
PC update
PC  valP
Update PC
popl rA
PC update
PC  valP
Update PC
jXX Dest
PC update
PC  Bch ? valC : valP
Update PC
call Dest
PC update
PC  valC
Set PC to destination
ret
PC update
– 67 –
PC  valM
Set PC to return address
int new_pc = [
icode == ICALL : valC;
icode == IJXX && Bch : valC;
icode == IRET : valM;
1 : valP;
];
CSCE 212H Spring 2012
SEQ Operation
State
PC register
 Cond. Code register
 Data memory
 Register file
All updated as clock rises

Combinational
Logic
Read
Write
Data
Data
memory
memory
CC
CC
Read
Ports
Write
Ports
Register
Register
file
file
Combinational Logic


PC
0x00c

ALU
Control logic
Memory reads
 Instruction memory
 Register file
 Data memory
– 68 –
CSCE 212H Spring 2012
SEQ
Operation
#2
Combinational
Logic
CC
CC
100
100
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Clock
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write

Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file

state set according to
second irmovl
instruction
combinational logic
starting to react to
state changes
%ebx
%ebx == 0x100
0x100
PC
0x00c
– 69 –
CSCE 212H Spring 2012
SEQ
Operation
#3
Combinational
Logic
CC
CC
100
100
000
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Clock
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write

Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file

state set according to
second irmovl
instruction
combinational logic
generates results for
addl instruction
%ebx
%ebx == 0x100
0x100
0x00e
PC
0x00c
– 70 –
CSCE 212H Spring 2012
SEQ
Operation
#4
Cycle 1
Cycle 3
Cycle 4
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write

Combinational
Logic
CC
CC
000
000
Cycle 2
Clock
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x300
0x300

state set
according to addl
instruction
combinational
logic starting to
react to state
changes
PC
0x00e
– 71 –
CSCE 212H Spring 2012
SEQ
Operation
#5
Cycle 1
Cycle 3
Cycle 4
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write

Combinational
Logic
CC
CC
000
000
Cycle 2
Clock
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x300
0x300

state set
according to addl
instruction
combinational
logic generates
results for je
instruction
0x013
PC
0x00e
– 72 –
CSCE 212H Spring 2012
SEQ Summary
Implementation




Express every instruction as series of simple steps
Follow same general flow for each instruction type
Assemble registers, memories, predesigned combinational
blocks
Connect with control logic
Limitations




– 73 –
Too slow to be practical
In one cycle, must propagate through instruction memory,
register file, ALU, and data memory
Would need to run clock very slowly
Hardware units only active for fraction of clock cycle
CSCE 212H Spring 2012