Real-Time Simulation:
Applications to More Electric Aircrafts
Embraer
March 10, 2010
Christian Dufour, Ph.D.
Senior Simulation Specialist, Power Systems and Drives
Lecture Plan
About More Electric Aircraft
Real-Time Simulator Technology update
Onboard Ship Power System example.
Tools for Electric System Simulation
Power Electronic Simulation on RT-LAB
Test Automation and Sequencer
Conclusions
2
 About more electric aircrafts
3
Why More Electric Aircrafts?
 Efficiency
 Bleedless engine design can provide for
energy saving during flight.
 Not so obvious: MEA is heavier than
normal plane
4
Classic airplane power distribution (A320)


Propulsion (trust): 20MW
Electrical (200kW)


Pneumatic 1.2MW


Cabin pressurization, Air conditioning, Icing
protection
Hydraulics (240 kW, at peaks)


Avionics, lights, fans, In-flight entertainment
Surface actuation, landing gear operation,
braking, doors
Mechanical

Fuel and oil pump local engine
5
Example of a More Electric Aircraft: Boeing 787
 Boeing 787
 All onboard systems are electric: APU, Brakes,
Cabin pressurization, Wing ice protection
 With 4 primary 230 VAC, 3ph, variable
frequency Generators with 230/115V AC and 28
VDC busses.
 Bleedless engines
6
Possible all-DC Bus MEA


Highly redundant configuration
Composed of many power converters
Source: Virginia Polytechnic
7
 Real-time simulation basics
8
Real-Time Simulation : Introduction
Free Running Simulation
Faster than real-time
Computation
f(t)
f(tn ) f(tn+1 )
tn-1
tn
Time
tn+1
Time
Slower than real-time
Computation
f(t)
f(tn)
tn-1
f(tn+1)
tn
tn+1
Time
Time
9
Real-Time Simulation : Introduction
Real-Time Simulation
Computation
f(t)
f(tn )
f(tn+1 )
Time
Clock
tn-1
tn
tn+1
Time
DataPosting
Sine equa none conditions for real-time algorithms
Non-iterative
Fixed –step (disqualify Spice-type or Saber simulation
algorithm for example)
IMPORTANT DISTINCTION
In real-time simulation, ALL time step must complete below Ts
Consequently, even if the total calculation time is smaller than
the real time to compute, it may not meet real-time criteria
10
Main Real-Time Simulation Applications: RCP and HIL
Controlled Process: a plant and its controller
Rapid Control Prototyping
Hardware-in-the-Loop
Controller
+
-
Motor
+-
RT-LAB


RT-LAB
RCP: the controller is implemented using a Real-Time Simulator
HIL: the controller is tested with a plant model on a Real-Time Simulator
Evolution of Real-Time Simulator Technology
2009: 1 cabinet, 3 PC with 24 core in total
RT-LAB
32 to 64 cores would be required to
simulate the detailed HQ network
COTS
Sim-On-Chip
Digital COTS
Simulators
1975
30000 square feet Hybrid Simulator
Digital Custom
Simulators
Hybrid (Analog/Digital)
Simulators
Analog
Simulators
Model Based Design
1960
1970
1980
1990
2000
13
About the Concept of Model-based Design (simplified)
Controller Model
Design
(Simulink Block
Diagram)
Generate
Software from
Model
Correct
Design
Iteratively
Test
Upload Software to
Real-Time Simulation
Platform
14
Example #1: Off-Highway Vehicle (GE-OHV)
Chopper Assembly
Dissipates superfluous energy during breaking
AC Control Group
Controls engine load and power flow
Motorized Wheels
Deliver Traction effort
Alternator
Generates the electrical power
Example #1: Off-Highway Vehicle (GE-OHV)
Actual ECU
I/O
Truck model include:

Dynamics

Inverters

Motors Drives (IM)

Alternator

DC-bus

DC-bus choppers

Etc..
RT-LAB TestDrive (LabView Based Interface)
Example #2: All electric ship
Characteristics:

Highly redundant reconfigurable power system

Composed of many drives including propulsion

Many power converters and switches
Zone 1
Port Bus
Load Group2
on Port Side
NV ac
load
PCM
NV dc
load
PCM
Vital
load
Generator
Group
SW-G1
Load Group1
on Port Side
PCM
Zone 2
Fault Location 2
SW-P1
PCM
NV ac
load
PCM
NV dc
load
EPM
PCM
SW-P3
Load Group 1
on Port Side
Load Group 1
on Port Side
Load Group 1
on Port Side
Load Group 2
on Port Side
Load Group 2
on Port Side
Load Group 2
on Port Side
Generator
Group
Generator
Group
Generator
Group
Load Group 1 on
Starboard Side
Load Group 1 on
Starboard Side
Load Group 1 on
Starboard Side
Load Group 2 on
Starboard Side
Load Group 2 on
Starboard Side
Load Group 2 on
Starboard Side
PCM
PCM
EPM
M
NV dc
load
PCM
PCM
NV dc
load
NV ac
load
PCM
PCM
NV ac
load
SW-G2
Vital
load
Load Group1 on
Starboard Side
SW-P2
Zone 4
M
PGM
Fault
Location 1
Zone 3
Load Group2 on
Starboard Side
SW-S1
SW-S2
SW-S3
Starboard Bus
Yanhui Xie Seenumani, G. Jing Sun Yifei Liu Zhen Li , “A PC-Cluster Based Real-Time Simulator for AllElectric Ship Integrated Power Systems Analysis and Optimization”, Electric Ship Technologies
Symposium, 2007. ESTS '07. IEEE , Arlington, VA., 21-23 May 2007 pp. 396 - 401
17
Test case: ZONE 1 - PORT BUS - DC FAULT
Port Bus
ZONE
Zone 11
Port Bus
Load Group2
on Port Side
NV ac
load
PCM
NV dc
load
PCM
Vital
load
Generator
Group
SW-G1
Load Group1
on Port Side
PCM
ZONE
Zone 2 2
Fault Location 2
SW-P1
PCM
NV ac
load
PCM
NV dc
load
EPM
SW-P2
Zone 4
SW-P3
Load Group 1
on Port Side
Load Group 1
on Port Side
Load Group 1
on Port Side
Load Group 2
on Port Side
Load Group 2
on Port Side
Load Group 2
on Port Side
Generator
Group
Generator
Group
Generator
Group
Load Group 1 on
Starboard Side
Load Group 1 on
Starboard Side
Load Group 1 on
Starboard Side
Load Group 2 on
Starboard Side
Load Group 2 on
Starboard Side
Load Group 2 on
Starboard Side
M
PCM
PGM
Fault
Location 1
Zone 3
PCM
ZONE 1
PCM
EPM
M
NV dc
load
PCM
PCM
NV dc
load
NV ac
load
PCM
PCM
NV ac
load
Load Group1 on
Starboard Side
SW-G2
Vital
load
Load Group2 on
Starboard Side
SW-S1
SW-S2
SW-S3
Starboard Bus
Starboard Bus
Fault applied from t = 0.1s to t = 0.4s
18
All-Electric Ship Real-time Simulation Performance
Ts = 50 μs
Target 1
Target 2
CPU2
CPU3
CPU1
CPU2
CPU3
Zone 1
Load
Group 1
Zone 1
Generator
Group
Zone 1
Load
Group 2
Zone 3
Load
Group 1
Zone 3
Generator
Group
Zone 3
Load
Group 2
Shared Memory
Zone 2
Load
Group 1
Zone 2
Generator
Group
Zone 2
Load
Group 2
CPU4
CPU5
CPU6
PCI Express
CPU1
Shared Memory
Zone 4
Load
Group 1
Zone 4
Generator
Group
Zone 4
Load
Group 2
CPU4
CPU5
CPU6
Test 1:
Test 2:









2 Zone AES
1 eMEGAsim target
6 (of 8) processor cores used
Minimum achievable Ts = 32 μs
4 Zone AES
2 eMEGAsim targets
Dolphin PCI-SCI comm. link
12 (of 16) processor cores used
Minimum achievable Ts = 33 μs
19
Components of a real-time simulator
 Real-time simulator components
Sequencer
Applications
Models
Solvers
Inputs/Outputs
Real-Time Platform
Communication
Processing
20
RT-LAB solutions for power systems

OPAL-RT provides various tools for the simulation of
power systems, motor drives and power electronic
converter are provided
Simulink
MATLAB
Simulink
RTeDRIVE


Sequencer
SimPowerSystems
ARTEMiS
ARTEMiS: Real-time enabler for SimPowerSystems
RTeDRIVE: Power Electronics and motor drives toolbox
21
Opal-RT Toolboxes for electric system simulation
 ARTEMiS
 Plug-in to SimPowerSystems
 Makes pre-computation of circuit modes to
allow real-time performance
 Increase stability and precision
22
Opal-RT Toolboxes for electric system simulation
 RTeDRIVE
 A specialized library of IGBT/GTO/MOSFET
inverters/choppers (2- and 3-level)
 Use interpolated switching functions
 Compatible with SPS or Simulink only
23
 RT-LAB features
24
RT-LAB eMEGAsim Simulator Hardware Architecture
 Host/Target Architecture


Simulink
Model
Single-,
Dual-, or
Quad-Core
CPU
PCI EXPRESS

Windows
QNX & RT-Linux RTOS
SIMULINK/RTW based
Multi-core support
Simulink
Model
Sh.Mem.
CPU
PCI

HILBox PC1
25
RT-LAB eMEGAsim Simulator Hardware Architecture
 Host/Target Architecture


Windows
QNX & RT-Linux RTOS
SIMULINK/RTW based
 Multi-core Processors


Shared-Memory
Multi-CPU board
Simulink
Model
Single-,
Dual-, or
Quad-Core

User has the possibility
to add PCI cards to the
simulator with standard
Protocol like TCP/IP,
UDP/IP, RS-232
Or to develop and study
advanced protocols (ex:
IEC-6185)
PCI
PCI PCIe Extension

CPU
PCI EXPRESS

Simulink
Model
Sh.Mem.
CPU
RS-232, CAN, TCP/IP
IEC61850, LoadRunner
HILBox PC1
26
RT-LAB eMEGAsim Simulator Hardware Architecture
 Host/Target Architecture



Windows
QNX & RT-Linux RTOS
SIMULINK/RTW based
 Multi-core processors
Digital IO requirements
For power Electronics

Must be capable of
sampling Thyristor/
IGBT/GTO/MOSFET
gate with great accuracy

The latency must also
be very low so it does
not to slow down the
simulation (PCI Express)
CPU
16 DO
Sh.Mem.
CPU
PCI Express
FPGA (op5142)

Shared-Memory
Multi-CPU board
PCI EXPRESS

Carrier (op5210)
16 AO
16 AI
Carrier w (op511x)
16 AO
16 AI
Carrier w (op511x)
16 DO
FastCom
16 DI
16 DI
Carrier (op5210)
HILBox PC1
27
Sampling of fast PWM gate signals



For this purpose, PWM
pulse are captured on
the FPGA card by
100MHz counters
Normalized ratio (Time
stamp) is send to the
inverter models on the
CPU
The model on the CPU
use the Time Stamps to
compute interpolated
voltages
28
Effect of switch gate sampling and interpolation

RTeDRIVE inverter model use the time stamps to
produce very accurate results



Example: a simple DC chopper (PWM=10kHz, Ts=10µs)
Bad sampling (like if we use regular SPS) causes
important non-linearity in the input-output characteristic
But very linear caracteristic with RTeDrive TSB inverters
SimPowerSystems
EMTP, PLECS
TSB
Tcarrier/Ts=10
Effect of switch gate sampling and interpolation

Precise enough to take into account
deadtime effect smaller that the
sample Time

Below is the effect of dead time increment
of 2 µs (with a sample time of 10µs!)
Hardware Architecture (FPGA models)
 Host/Target Architecture


Windows
QNX & RT-Linux RTOS
SIMULINK/RTW based
Xilinx System
Generator Blockset
CPU Model
 Multi-core processors



FPGA user programmability
Sh.Mem.
for advanced model design
The FPGA card can be programmed by
the user using Xilinx System Generator CPU
No VHDL language skill required.
PCI Express
It is a Simulink
blockset
FastCom
PCI EXPRESS

Shared-Memory, Multi-CPU board
Models with 10
ns sample rate
can be coded on
this card!
16 DO
FPGA (op5142)

16 DI
Carrier (op5210)
16 AO
16 AI
Carrier w (op511x)
16 AO
16 AI
Carrier w (op511x)
16 DO
16 DI
Xilinx SG model
Carrier (op5210)
HILBox PC1
31
Simulator Hardware Architecture (Expandability)
 Host/Target Architecture



Windows
QNX & RT-Linux RTOS
SIMULINK/RTW based
 Multi-core processors

Shared-Memory
Multi-CPU board
CPU
 Expandability

FireWire
INFINIBAND switch
DOLPHIN SCI /PCIe
(2 to 5 us latency)
CPU
PCI Express
PCI

PCI EXPRESS

16 DO
Sh.Mem.
Dolphin
FPGA (op5142)

16 DI
Carrier (op5210)
16 AO
16 AI
Carrier w (op511x)
16 AO
16 AI
Carrier w (op511x)
16 DO
16 DI
Carrier (op5210)
HILBox PC1
Dolphin
HILBox PC2
32
About the necessity for testing
 Real-Time Solvers for Power Systems
33
Simulation solvers for power systems
 Key characteristics of power systems
 Contains a wide range of frequency modes


Requires ‘stiff’ fixed-step solvers. Stiff solver remains
stable even with mode above the simulation Nyquist
limit.
Contains a lot of PWM-driven power electronics

The simulator must avoid sampling effect when
computing IGBT pulse ‘events’ internally or when
reading PWM pulses from its I/Os
34
Stiff solvers methods for power system simulation
 Simulation methods electric systems:
 State-Space (SimPowerSystems)
 Switching-function (Power Electronics &
converters)
 FPGA-based methods
Stiff solvers methods for power system simulation
 State-Space approach of SimPowerSystems

We can also find the exact state-space solution
x  Ak x  Bk u



y  Ck x  Dk u
With k, matrix set index for switch permutations
This can be discretized with the trapezoidal method like
in SimPowerSystems for Simulink

Trapezoidal method: order 2.
It can also be discretized by higher order methods

Higher order methods (order 5) implemented in
ARTEMiS, a solver package of eMEGAsim.
Stiff solvers methods for power system simulation
 State-Space approach

Continuous time state-space expression x  Ak x  Bk u

Solution for time step T:
xn1  e
AT
t
xn  
t T
e A( t  ) Bu ( )d
How to compute the ‘matrix exponential’ eAT ?


I  AT / 2
e 
I  AT / 2
ARTEMiS art5 method (order 5)
2
2
1
I

AT

(
AT
)
5
20
e AT 
2
3
3
3
1
I  5 AT  20 ( AT )  60 ( AT )
Trapezoidal method (order 2)
TALYOR
EXPENSION
e
AT
AT
AT AT 2 AT 3 AT 4 AT 5
AT n
I




 ... 
...
1!
2!
3!
4!
5!
n!
Effect of higher order discretization
Simple case of RLC circuit energization
Artemis ART5 solver
more precise than
Trapezoidal solver at
100 us
Numerical stability issues

Discretized systems is not guarantied to be stable


It depends on how Laplace poles are ‘mapped’ in the z
domain. Ex: Forward Euler has poor stability
A-stability (Stiff stability) (ex: trapeze method) guaranty
discrete stability (for linear systems)
Laplace pole (s) mapping
Im{l}
Trapeze
Stability Region
-2/T
Forward Euler
Stability Region
RLC network Euler
T=0.01µs
Trapeze
T=100µs
y’=ly
Re{l}
Numerical stability issues with trapezoidal integration

Even if it is stable, the
trapezoidal rule (tustin) is
prone to numerical oscillations

The z-domain mapping is stable
but oscillatory for high
frequency Laplace poles
Numerical stability issues with trapezoidal integration

A-stable methods can be highly oscillatory
How are mapped high frequency poles?

It depends on the ‘stability function’ again
ARTEMiS art5 (L-stable)
Trapeze (A-stable)
2
2
1
I

AT

(
AT
)
I  AT / 2
5
20
lim AT 
0
lim AT 
 1
2
3
3
3
1
I  5 AT  20 ( AT )  60 ( AT )
I  AT / 2

Laplace map
Im{l}
y’=ly
Z- domain map
Im{z}
y(n+1)=zy(n)
Re{l}
Re{z}
-1
z mapping near -1
means oscillations
RTeDRIVE approach: interpolated switching function
 Switching function approach




A special solver method for power electronic system
using high-frequency PWM.
It is a ‘simple’ controlled voltage source!
Interpolation methods are used to obtain high accuracy
in the Opal-RT RTeDRIVE package
High impedance mode supported now.
~100V
V_load
~0
V_load
1
gate
0
*
*
Gup
*
Glow
* V_load near zero for positive I_load by lower anti-parallel diode action if both GIBT are turned off
Effect of switch gate sampling and interpolation

RTeDRIVE inverter model use the time stamps to
produce very accurate results



Example: a simple DC chopper (PWM=10kHz, Ts=10µs)
Bad sampling (like if we use regular SPS) causes
important non-linearity in the input-output characteristic
But very linear caracteristic with RTeDrive TSB inverters
SimPowerSystems
EMTP, PLECS
TSB
Tcarrier/Ts=10
Effect of switch gate sampling and interpolation

Precise enough to take into account
deadtime effect smaller that the
sample Time

Below is the effect of dead time increment
of 2 µs (with a sample time of 10µs!)
Interpolated switching functions: example case 1
Motor Current [A]
Japan, 2004
ARTEMiS used for rectifier side
RTeDRIVE used for inverter
HIL Simulation
20
10
0
PWM
2.25kHz
-10
-20
0
0.003
0.006
0.009
Physical System
20
Motor Current [A]
Mitsubishi Electric Co
0.012
10
0
-10
-20
0
0.003
CPU 1: (Ts= 80 us)
CPU 2: (Ts= 10 us)
© Opal-RT © Opal-RT
x6
S
x6
(Fpwm =9 kHz)
IGBT
pulses
Currents
Quadrature
encoder signals
10
0
PWM
4.5kHz
-10
-20
External controller (sampling rate =55 s)
Motor Current [A]
N
0
0.003
0.006
0.009
0.012
MITSUBISHI
0
-10
-20
0
0.003
0.006
0.009
0.012
0.009
0.012
Time [sec]
20
Motor Current [A]
0.012
10
Time [sec]
20
10
0
PWM
9kHz
-10
-20
0.009
20
20
Motor Current [A]
PWM
inverter
permanent
magnet motor Tload
Motor Current [A]
3-phase
diode
source
rectifier
reactor
0.006
Time [sec]
Time [sec]
0
0.003
0.006
Time [sec]
0.009
0.012
10
0
-10
-20
0
0.003
0.006
Time [sec]
45
Example 2 – Industrial Motor Drives
Multi Level Inverter Drive
CONVERTEAM-ALSTOM
(France)
RT-LAB Electric Drive Simulator
12-PULSE
RECTIFIER
3-LEVEL NEUTRAL CLAMPED
BRIDGE
dV/dt
FILTER
HV
NETWORK
INDUCTION MOTOR
12MW-6600V
M
~
3~
PEC CONTROLLER
~
PRECHARGE
LV NETWORK
line voltage wave form
1200V
This Controller is connected
Externally to the Simulator
46
Example 3 – Industrial Motor Drives
Multi Level Inverter Drive
CONVERTEAM-ALSTOM (France)
12-PULSE
RECTIFIER
3-LEVEL NEUTRAL CLAMPED
BRIDGE

dV/dt
FILTER
HV
NETWORK
INDUCTION MOTOR
12MW-6600V
M
~
3~

PEC CONTROLLER
~
PRECHARGE
LV NETWORK
Pulse shutdown modeled
with the help of Converteam
Required the design of an
hybrid switching-function
with high-impedance
capability
Results of Hardware-In-the-Loop Tests
Motor Acceleration
Emergency Pulse shutdown
47
Importance of Interpolation (again)


Interpolation is important because the Real-Time Simulator
is a sampled system
The above figure shows the typical effect of neglecting
‘interpolation’ during the simulation.
EM Torque
5
2
DEAD-TIME
Torque in N.m
1
0
-1
-2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.4
1.6
1.8
2
Currents
Inverter Currents
1500
1000
Current in A
Converteam case

Ts=40us

Deadtime=20us

Fpwm=400Hz

Interpolation disabled
@ 1 second
Electromagnetic Torque
x 10
500
0
-500
-1000
-1500
0
0.2
0.4
0.6
0.8
1
Time in s
1.2
WITH INTERPOLATION
WITHOUT INTERPOLATION
C. Bordas, C. Dufour, O. Rudloff, “A 3-Level Neutral-Clamped Inverter Model with Natural Switching Mode
Support for the Real-Time Simulation of Variable Speed Drives”, Proceedings of the 8th International
Symposium on Advanced Electromechanical Motion Systems (ELECTROMOTION-2009), Lille, France, July
1-3, 2009
Interpolated switching functions: how high can you get?
3-level STATCOM with 72 IGBT (Mitsubishi Electric)



20 µs, 3 CPU with the controller
1000 time faster than conventional
simulation software
Actual diode/IGBT count: 10*6*3=180
Reference model
In EMTP/RV (3us)
vs Simulink/SPS/ RT-LAB (50 us)
IPST 2009, Kyoto - Japan
49
Simulation On Chip (FPGA)

RT-LAB XSG permits to use Xilinx System Generator
models inside RT-LAB frame work

Enables complex model to run on the FPGA of RT-LAB
Examples:

PMSM motor

IGBT inverter,

PWM modulator

Power electronics
Simulation On Chip (FPGA)

No need to know VHDL language


But you need to know fixed-point arithmetic
Real-life example: Rotary Variable Differential
Transformer (RVDT) designed for Embraer in
one week using XSG!
A typical XSG model in RT-LAB
Simulation On Chip (FPGA) Example: PMSM Drive
 PMSM drive built on FPGA using only XSG
 PMSM, BLDC and FEA-Based PMSM
 Include: test modulator, quad enc., resolver
External Digital Inputs
Internal PWM test source
internal 3-phase
voltage source
Analog Outputs
IGBT inverter
iabc
modulator
upper IGBT
pulses
N
S
lower IGBT
pulses
Fmod :10-200 kHz
Permanent
magnet motor
[ L]1  (Vabc 
d abc
 RI abc )dt  I abc
dt
shift
Dead time
Modulation index
IGBT gate source selection
Phase shift of Vsource rotor & Vsource
*C. Dufour et al. “Real-Time Simulation of Finite-Element Analysis Permanent Magnet Synchronous Machine Drives
on a FPGA card”, Proceedings of 2007 European Conference on Power Electronics and Applications (EPE-07) ,
Aalborg, Danemark , Sept 2007
Test sequencer
 Test sequencer
53
Test sequencer: a key part of real-time simulator
 Test sequencer
requirement




Capability to launch test
automatically
Capability to record and
analyze data
Capability to manage
models
Use the full power of
MATLAB and Python
languages
54
Test sequencer: a key part of real-time simulator
 Usage case: Monte-Carlo testing
 How to dimension correctly some power system
component considering switching surges?
55
Test Automation with Python script


Test algorithm coded
in Python
Fault application and
breaker reclosing are
randomized
56
Test sequencer: a key part of real-time simulator
By making automated randomized tests (MonteCarlo), we can obtain probabilistic characteristics
of overvoltages.
1
Number of occurences
A-GND FAULT
A-GND
100 2000 runs
0.8
80
0.6
60
0.4
40
0.2
20
0
1.8
2
2.2
2.4
2.6
Voltage peak during fault (pu)
2.8
0
3
2
1
Voltage (pu)
120
Cumulative probability (CDF)

0
-1
Phase A
Phase B
Phase C
-2
0
0.1
0.05
0.15
time (s)
57
PHIL
 Power Hardware-In-the-Loop
58
Example of PHIL testing (L2EP, Lilles)



Distributed Energy Storage Systems Application
Used for frequency control on islanded network
Real power electronic device connected to a
simulated grid!
H. Fakham, A. Doniec, F. Colas, X. Guillaud, “A Multi-agents System for a Distributed Power Management
of Micro Turbine Generators Connected to a Grid”, Conference on Control Methodologies and
Technologies for Energy Efficiency (CMTEE 2010) Vilamoura, Portugal http://www.cmtee.org/
62
Frequency regulation tests
 The higher the energy storage capacity, the
lower the frequency deviation during fault
Impact of ultracapacitor-based DESS on the frequency response of
an isolated power system after a major generation loss
63
Key References

University of Alberta Power Systems Laboratory
based on RT-LAB


Power Hardware-In-The-Loop Testing of Grid Systems


D. Ocnasu, S. Bacha, I. Munteanu, C. Dufour, D. Roye, “Real-Time PowerHardware-In-the-Loop Facility for Shunt and Serial Power Electronics
Benchmarking”, Proceedings of the 13th European Conference on Power
Electronics and Applications (EPE-2009), Barcelona, Spain, Sept. 8-10, 2009
Advanced Motor Drive Simulation


L.-F. Pak, O. Faruque, X. Nie, V. Dinavahi, “A Versatile Cluster-Based RealTime Digital Simulator for Power Engineering Research”, IEEE Transactions on
Power Systems, Vol. 21, No. 2, pp. 455-465, May 2006.
M. Harakawa, C. Dufour, S. Nishimura, T.Nagano, “Real-Time Simulation of a
PMSM Drive in Faulty Modes with Validation Against an Actual Drive System”,
Proceedings of the 13th European Conference on Power Electronics and
Applications (EPE-2009), Barcelona, Spain, Sept. 8-10, 2009
RT-LAB application booklet with over 30 applications explained
from motor drives and power electronics to large power systems.
Opal-RT Partial Customer List
Opal-RT Technologies
2006.09.28
65
Opal-RT Clients involved in Electric Motor Drive and
Power Grid Studies
Ford
66
Please contact me if you have any questions
christian.dufour@opal-rt.com
67
 Appendix 1: How to use RT-LAB for
power system applications?
68
How to use RT-LAB for power system applications?




1- Design your model in Simulink
and SimPowerSystems
2- Identify natural delay in your
model (ex: transmission lines)
3- Make top-level groups in your
Simulink model, these will be
assigned to different CPUs of the
simulator
4- Add I/O block in the model if
necessary
69
How to use RT-LAB for power system applications?

1- Design your model in Simulink and SimPowerSystems

We choose here a SPS demo named: power_PSS.mdl
70
How to use RT-LAB for power system applications?

2- Identify power line to make parallel distributed simulation
71
How to use RT-LAB for power system applications?

3- Choose a task separation and make Subsystems
CPU #1
CPU #2
72
How to use RT-LAB for power system applications?

4- Some optimizations: put controllers in a separate CPU
because it can run at slower rate

Also put monitoring in a separate subsystem
Controls
Monitoring
73
How to use RT-LAB for power system applications?
You can put your own ‘C’ code in any of the cores
 You just have to use a S-function ‘wrapper’

int main()
{
printf("hello, world");
printf(“I want to do real-time simulations");
return 0;
}
74
How to use RT-LAB for power system applications?

5- Adding I/Os

Let’s add an analog output from the RT-LAB library
75
How to use RT-LAB for power system applications?

Let’s output the Alternator Excitation voltage
76
How to use RT-LAB for power system applications?

The alternator excitation voltage can now be read on the
front panel of the simulator
77
How to use RT-LAB for power system applications?


Most commercial I/O
cards can be supported
Opal can supply the
source code of
communication driver
examples to enable users
to implement their own
protocols through
Ethernet for Internet
78