CS 152
Computer Architecture and Engineering
Lecture 9 -- Memory
2014-2-18
John Lazzaro
(not a prof - “John” is always OK)
TA: Eric Love
www-inst.eecs.berkeley.edu/~cs152/
Play:
CS 152 L9: Memory
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DRAM chip capacity: from 1Kb (1971) to 4Gb (2013)
CS 152 L14: Cache I
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Gordon
Moore
UCB B.S.
Chemistry
1950.
CS 152 L9: Memory
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CS 152 L9: Memory
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Today: State Storage Tools on Silicon ICs
Capacitance: Holds state as charge
Transistors: How to move charge
DRAM: 1 Transistor + 1 Capacitor
Architecture: Arrays and interfaces
VLSI == “Very Large Scale
Integration”
The tall thin designer, with feet on the
ground and head in the sky.
The ground: Physics and IC Fabrication
The sky: Architecture and Applications
CS 152 L9: Memory
Carver Mead
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Today’s Lecture: DRAM
DRAM: Bottom-up
DRAM: Top-down
DRAM: Systems
CS 152 L9: Memory
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Capacitance and memory
Intel Micron 8 GB NAND flash device, 2 bit per cell, 25 nm minimum feature, 16.5 mm by 10.1 mm.
CS 152 L14: Cache I
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Recall: Building a capacitor
Top
Plate
Dielectric
Bottom
Plate
CS 152 L9: Memory
Conducts electricity well.
(metal, doped polysilicon)
An insulator. Does not
conducts electricity at all.
(air, glass (silicon dioxide))
Conducts electricity well
(metal, doped polysilicon)
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Recall: Capacitors in action
Because the
dielectric is an
insulator, and
does not conduct.
++++++
I=0
--- ---
After circuit “settles” ...
Q = C V = C * 1.5 Volts (D cell)
Q: Charge stored on capacitor
C: The capacitance of the
device: function of device
shape and type of dielectric.
1.5V
After battery is removed:
++++++
Still, Q = C * 1.5 Volts
--- --Capacitor “remembers” charge
CS 152 L9: Memory
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Storing computational state as charge
State is coded as the
amount of energy stored
by a device.
++++++
--- ---
1.5V
++++++
--- ---
State is read by
sensing the amount
of energy
Problems: noise changes Q (up or down),
parasitics leak or source Q. Fortunately,
Q cannot change instantaneously, but that only
gets us in the ballpark.
CS 152 L9: Memory
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How do we fight noise and win?
Store more energy
than we expect
from the noise.
Q = CV. To store more
charge, use a bigger V
or make a bigger C.
Cost: Power, chip size.
Example: 1 bit per capacitor.
Represent state
Write 1.5 volts on
as charge in ways that
To
C.read C, measure V.
are robust to noise.
V > 0.75 volts is a “1”.
V < 0.75 volts is a “0”.
Cost: Could have stored many bits on that
capacitor.
Correct small state errors thatEx: read C every 1 ms
Is V > 0.75 volts?
are introduced by noise.
Write back 1.5V
Cost: Complexity.
(yes) or 0V (no).
CS 152 L9: Memory
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MOS Transistors
Two diodes and a capacitor in an
interesting arrangement. So, we
begin with a diode review ...
CS 152 L9: Memory
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Diodes in action ...
Resistor
Light emitting
diode (LED)
Light on?
Yes!
Light on?
No!
CS 152 L9: Memory
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Diodes: Current vs Voltage
Diode is off
I ≈ - Io
Anode
+
I
Diode is on
I ≈ Io exp(V/Vo)
V
Cathode
I = Io [exp(V/Vo) - 1]
Io range: 1fA to 1nA
CS 152 L9: Memory
Vo range: 25mV to 60 mV
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Making a diode on a silicon wafer
CS 152 L9: Memory
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A pure (”intrinsic”) silicon crystal ...
Conducts electricity
better than an insulator,
worse than a conductor.
Why? Most electrons
(dots) are in a full
“valence” band. Moving in
the band is difficult.
Especially near 0 degrees
Lots of room, K.
but few electrons.
Forbidden “band
gap”
CS 152 L9: Memory
Conduction
band
Valence
band
Many electrons, but packed too tight to
e
l
e
c
t
r
o
n
e
n
e
r
g
y
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Intrinsic silicon crystal as T rises ...
Some valence band
electrons diffuse into
the conduction band.
These electrons leave
behind “holes” in the
valence band, allowing
remaining electrons to
move easier.
More electrons,
better conduction
CS 152 L9: Memory
Conduction
band
Valence
band
We think of “holes” as positive carriers ...
e
l
e
c
t
r
o
n
e
n
e
r
g
y
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We “engineer” crystal with impurities ...
CS 152 L9: Memory
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N-type silicon: add donor atoms
Use diffusion or ion
implantation to replace
some of the Si atoms with
As
Arsensic has an extra
electron that is “donates”
to the conduction band.
n+ : heavy doping. n- : light
doping.
Electrons
from donor atoms.
Improves
conductivy.
CS 152 L9: Memory
Conduction
band
Donor energy
Valence
band
No change in the number of holes
e
l
e
c
t
r
o
n
e
n
e
r
g
y
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P-type silicon: add acceptor atoms
Use diffusion or ion
implantation to replace
some of the Si atoms with
Boron
Boron has
one fewer
electron than Si. It can
accept valence band
electrons, creating holes.
p+ : heavy doping. p- : light
doping.
No change in
conduction band
electron count
Conduction
band
Acceptor
energy
Valence
band
Number of holes increased, conductivity
CS 152 L9: Memory
e
l
e
c
t
r
o
n
e
n
e
r
g
y
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How to make a silicon diode ...
Wafer cross-section
Cathode: -
-
n+
V
p-
Anode: +
+
pregion
Wafer doped p-type
depletion At V ≈ 0, “hill” too high
for electrons to diffuse
region
up. n+
region
no
carriers
For holes, going
“downhill” is hard. V controls hill.
CS 152 L9: Memory
depletion
region
e
l
e
c
t
r
o
n
e
n
e
r
g
y
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Diodes: Current vs Voltage
Diode is off
I ≈ - Io
Anode
+
I
Diode is on
I ≈ Io exp(V/Vo)
V
Cathode
I = Io [exp(V/Vo) - 1]
Io range: 1fA to 1nA
CS 152 L9: Memory
Vo range: 25mV to 60 mV
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Note: IC Diodes are biased “off”!
V1
V2
V1
V2
n+
n+
p0 V - “ground”
V1, V2 > 0V. Diodes “off”, only current is Io
“leakage”.
I = Io [exp(V/Vo) - 1]
Anodes of all diodes on wafer connected to ground.
CS 152 L9: Memory
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MOS Transistors
Two diodes and a capacitor in an
interesting arrangement ...
CS 152 L9: Memory
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What we want: the perfect switch.
V1
Switch is off.
V1 is not
connected to V2.
p-
We want to turn
a p-type region
into an n-type
region under
voltage control.
Switch is on.
V1 is connected
to V2.
We need
electrons to fill
valence holes and
add conduction
band electrons
n+
V1
V2
n+
n+
V2
++++++
p-
--- --CS 152 L9: Memory
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An n-channel MOS transistor (nFET)
Vg = 0V
Vd = 1V
I ≈ nA
n+
Vs = 0V Polysilicon gate,
dielectric
n+
dielectric, and
substrate form a
capacitor.
pnFet is off
(I is “leakage”)
Vg = 1V
Vd = 1V
+++++++++
I ≈ μA dielectric
------------------n+
pCS 152 L9: Memory
Vs = 0V
n+
Vg = 1V, small
region near the
surface turns
from p-type to ntype.
nFet is on
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Mask set for an n-Fet (circa 1986)
Vg = 0V
Vd = 1V
I ≈ nA
n+
dielectric
n+
p-
Top-down view:
CS 152 L9: Memory
Vs = 0V
Masks
#1: n+ diffusion
#2: poly (gate)
#3: diff contact
#4: metal
Layers to do
p-Fet not
shown. Modern
processes have
6 to 10 metal
layers (or more)
(in 1986: 2).
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“Design rules” for masks, 1986 ...
Poly
overhang.
So that if
masks are
misaligned
, we still
get “---” in
channel.
Minimum gate
length. So that the
source and drain
depletion regions do
not meet!
length
#1: n+ diffusion
#2: poly (gate)
CS 152 L9: Memory
Metal rules:
Contact
separation from
channel, one
fixed contact
size, overlap
rules with
metal, etc ...
#3: diff contact
#4: metal
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Fabrication
CS 250 L1: Fab/Design Interface
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Mask set for an n-Fet ...
Vg = 1V
Vd = 1V
I ≈ μA
n+
Vd
Vs = 0V
dielectric
n+
Vg
Ids
Vs
pMasks
Top-down view:
CS 152 L11: VLSI
#1: n+ diffusion
#2: poly (gate)
#3: diff contact
#4: metal
How does a fab
use a mask set
to make an IC?
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Start with an un-doped wafer ...
UV hardens exposed resist. A wafe
wash leaves only hard resist.
oxide
p-
Steps
#1: dope wafer p-
#2: grow gate
oxide
#3: grow undoped
polysilicon
#4: spin on
photoresist
CS 152 L11: VLSI
#5: place positive
poly mask and
expose with UV.
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Wet etch to remove unmasked ...
HF acid etches through poly and
oxide, but not hardened resist.
oxide
p-
oxide
After etch and
resist removal
pCS 152 L11: VLSI
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Use diffusion mask to implant n-type
accelerated donor atoms
oxide
n+
n+
p-
CS 152 L11: VLSI
Notice how
donor atoms are
blocked by gate
and do not enter
channel.
Thus, the
channel is “selfaligned”,
precise mask
alignment is not
needed!
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Metallization completes device
oxide
n+
n+
p-
oxide
n+
n+
p-
oxide
n+
n+
p-
CS 152 L11: VLSI
Grow a thick
oxide on top
of the wafer.
Mask and etch
to make
contact holes
Put a layer of
metal on chip.
Be sure to fill
in the holes!
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Final product ...
Vd
Vs
oxide
n+
n+
p-
Top-down view:
CS 152 L11: VLSI
“The planar
process”
Jean Hoerni,
Fairchild
Semiconductor
1958
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p-channel Transistors
CS 152 L11: VLSI
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p-Fet: Change polarity of everything
Vwell = Vs = 1V
I ≈ μA
p+
Vg = 0V
Vs
Vd = 0V
dielectric
p+
n-well
p-
New “n-well” mask
Vg
Isd
Vd
“Mobility” of
holes is slower
than electrons.
p-Fets drive less
current than nFets, all else
being equal
CS 152 L11: VLSI
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Dynamic Memory Cells
CS 152 L9: Memory
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Recall: Capacitors in action
Because the
dielectric is an
insulator, and
does not conduct.
++++++
I=0
--- ---
After circuit “settles” ...
Q = C V = C * 1.5 Volts (D cell)
Q: Charge stored on capacitor
C: The capacitance of the
device: function of device
shape and type of dielectric.
1.5V
After battery is removed:
++++++
Still, Q = C * 1.5 Volts
--- --Capacitor “remembers” charge
CS 152 L9: Memory
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DRAM cell: 1 transistor, 1 capacitor
“Bit Line” “Word Line”
Vdd
Word
Line
Vdd
Capacitor
“Bit Line”
“Bit Line”
oxide
n+
oxide
n+
------
pWord Line and Vdd run on “z-axis”
CS 152 L9: Memory
Why
Vcap
values
start
out at
ground.
Vdd
Vcap
Diode
leakage
current.
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A 4 x 4 DRAM array (16 bits) ....
CS 152 L9: Memory
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Invented after SRAM, by Robert Dennard
CS 152 L9: Memory
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DRAM Circuit Challenge #1: Writing
Vdd
Vdd
Vgs
+
+
+
+
+
+
+
Vdd
Vc
Vdd - Vth. Bad, we store less
charge. Q. Why do we not get
Vdd?
Because
NFETs ,only pass “0”
kA.[Vgs
-Vth]^2
well.
Ids =
but “turns off” when Vgs <=
Vgs = Vdd - Vc. When Vdd
- Vc == Vth, charging effectively
Vth!
stops!
CS 152 L9: Memory
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DRAM Challenge #2: Destructive Reads
+++++++ (stored charge from
Bit Line
cell)
Word Line
+
(initialized
+
+
to a low
+
+
Vdd
voltage)
+
+
0 -> Vdd Vc ->
0
Raising the word line removes the
charge from every cell it connects to!
DRAMs write back after each read.
CS 152 L9: Memory
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DRAM Circuit Challenge #3a: Sensing
Assume Ccell = 1 fF
Bit line may have 2000 nFet drains,
assume bit line C of 100 fF, or
100*Ccell
100*Ccell.
Ccell holds Q =
Ccell*(Vdd-Vth)
When we dump this charge onto
Ccell
the bit line, what voltage do we
see?
dV = [Ccell*(Vdd-Vth)] / [100*Ccell]
dV = (Vdd-Vth) / 100 ≈ tens of millivolts!
In practice, scale array to get a 60mV signal.
CS 152 L9: Memory
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DRAM Circuit Challenge #3b: Sensing
...
How do we reliably sense a 60mV signal?
Compare the bit line against the voltage
on a “dummy” bit line.
“sense
Bit line to sense
+ amp”
?
“Dummy” bit line.
Dummy bit line
Cells hold no
charge.
CS 152 L9: Memory
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DRAM Challenge #4: Leakage ...
Bit Line
Word Line
+
+
+
+
+
+
+
Vdd
Parasitic currents
leak away charge.
Solution: “Refresh”, by rewriting cells at
regular intervals (tens of milliseconds)
oxide
n+ ------
n+
pCS 152 L9: Memory
oxide
Diode leakage ...
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DRAM Challenge #5: Cosmic Rays ...
Bit Line
Word Line
+
+
+
+
+
+
+
Vdd
This cell capacitor holds 25,000
electrons (today, less). Cosmic rays
that constantly bombard us can release
Solution: Store extra bits to detect and
the charge!
correct random bit flips (ECC).
oxide
n+ ------
n+
pCS 152 L9: Memory
oxide
Cosmic ray hit.
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DRAM Challenge 6: Yield
If one bit is bad, do we throw chip away?
...
Solution: add extra bit lines (i.e. 80 when
you only need 64). During testing, find
the bad bit lines, and use high current to
Extra bit lines.
Used for “sparing”. burn away “fuses” put on chip to remove
them.
CS 152 L9: Memory
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DRAM Challenge 7: Scaling
Recall:
Process Scaling
(“Moore’s Law”)
Due to
reducing V
and C (length
and width of
Cs decrease,
but plate
distance gets
smaller).
Recent slope
more shallow
because V is
being scaled
From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005.
CS 152 L9: Memory
lessUC Regents Spring 2014 © UCB
DRAM Challenge 7: Scaling
Each generation of IC technology,
we shrink width and length of cell.
If Ccell and drain capacitances scale
together, number of bits per bit line stays
constant.
dV ≈ 60 mV= [Ccell*(Vdd-Vth)] /
[100*Ccell]
Problem 1: Number of arrays per chip
grows!
Problem 2: Vdd may need to scale down
too!
Solution: Constant Innovation of Cell
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Poly-diffusion Ccell is ancient history
“Bit Line” “Word Line”
Vdd
Word
Line
Vdd
Capacitor
“Bit Line”
“Bit Line”
oxide
oxide
n+ ------
n+
p-
Word Line and Vdd run on “z-axis”
CS 152 L9: Memory
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Early replacement: “Trench” capacitors
CS 152 L9: Memory
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Final generation of trench capacitors
The
companies
that kept
scaling trench
capacitors
for commodity
DRAM chips
went out of
business.
CS 152 L14: Cache I
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Modern cells: “stacked” capacitors
CS 152 L9: Memory
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Micron 50nm 1-Gbit DDR2 die photo
CS 152 L9: Memory
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Samsung
90nm
stacked
capacitor
bitcell.
DRAM: the field for material and process innovation
ArabindaCSDas
152 L14: Cache I
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Cell access transistors for the 4 leading vendors
Chipmakers turn to new process for sub-nm DRAM cells
Jeongdong
CS Choe,
152 L14: TechInsights
Cache I
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Samsung 30nm
From JSSC, and
Arabinda
Das
CS 152
L14: Cache I
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In the labs: Vertical cell transistors ...
CS 152 L9: Memory
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Break
Play:
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Today’s Lecture: DRAM
DRAM: Bottom-up
DRAM: Top-down
DRAM: Systems
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Memory Arrays
CS 152 L9: Memory
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Bit Line
“Column”
“Word Line”
“Row”
People
buy DRAM
for the
bits.
“Edge”
circuits
are
overhead.
CS 152 L9: Memory
So, we
amortize
the edge
circuits
over big
arrays.
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A “bank” of 128 Mb (512Mb chip -> 4 banks)
1
13-bit
row
address
input
of
In reality, 16384 columns are
divided into 64 smaller arrays.
81
92
de
co
de
r
16384
columns
8192 rows
134 217 728 usable bits
(tester found good bits in bigger array)
16384 bits delivered by sense
amps
Select requested bits, send off the
chip
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Recall DRAM Challenge #3b: Sensing
How do we reliably sense a 60mV signal?
Compare the bit line against the voltage
on a “dummy” bit line.
[...]
“sense
Bit line to sense
+ amp”
?
“Dummy” bit line.
Dummy bit line
Cells hold no
charge.
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
“Sensing” is row read into sense amps
Slow! This 2.5ns period DRAM (400 MT/s)
can do row reads at only 55 ns ( 18 MHz).
1
13-bit
row
address
input
of
81
92
DRAM has high latency to first bit out. A fact of life
de
co
de
r
16384
columns
8192 rows
134 217 728 usable bits
(tester found good bits in bigger array)
16384 bits delivered by sense
amps
Select requested bits, send off the
chip
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
An ill-timed refresh may add to latency
Bit Line
Word Line
+
+
+
+
+
+
+
Vdd
Parasitic currents
leak away charge.
Solution: “Refresh”, by rewriting cells at
regular intervals (tens of milliseconds)
oxide
n+ ------
n+
pCS 152 L9: Memory
oxide
Diode leakage ...
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Latency is not the same as bandwidth!
Thus, push to
faster DRAM
interfaces
1
13-bit
row
address
input
of
81
92
de
co
de
r
What if we want all of the 16384 bits?
In row access time (55 ns) we can do
22 transfers at 400 MT/s.
16-bit chip bus -> 22 x 16 = 352 bits <<
Now the row access
16384time looks fast!
16384
columns
8192 rows
134 217 728 usable bits
(tester found good bits in bigger array)
16384 bits delivered by sense
amps
Select requested bits, send off the
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Sadly, it’s rarely this good ...
1
13-bit
row
address
input
of
81
92
de
co
de
r
What if we want all of the 16384 bits?
The “we” for a CPU would be the
program running on the CPU.
Recall Amdalh’s law: If 20% of the memory
accesses need a new row access ... not
good.
16384
columns
8192 rows
134 217 728 usable bits
(tester found good bits in bigger array)
16384 bits delivered by sense
amps
Select requested bits, send off the
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
DRAM latency/bandwidth chip features
Columns: Design the right interface
for CPUs to request the subset of a
column of data it wishes:
16384 bits delivered by sense
amps
Select requested bits, send off the
chip
Interleaving: Design the right interface
to the 4 memory banks on the chip, so
several row requests run in parallel.
Bank 1
CS 152 L9: Memory
Bank 2
Bank 3
Bank 4
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Off-chip interface for the Micron part ...
A clocked bus:
200 MHz clock,
data transfers on
both edges
(DDR).
DRAM is controlled
via commands
(READ, WRITE,
REFRESH, ...)
CS 152 L9: Memory
Note! This example is best-case!
To access a new row, a slow ACTIVE
command must run before the
READ.
Synchronous data
output.
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Opening a row before reading
15 ns
CS 152 L9: Memory
Auto-Precharge
... READ
15 ns
55 ns between row opens.
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However, we can read columns quickly
Note: This is a “normal read” (not Auto-Precharge).
Both READs are to the same bank, but different columns.
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Why can we read columns quickly?
1
13-bit
row
address
input
Column reads select from the 16384 bits here
of
81
92
de
co
de
r
16384
columns
8192 rows
134 217 728 usable bits
(tester found good bits in bigger array)
16384 bits delivered by sense
amps
Select requested bits, send off the
chip
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Interleave: Access all 4 banks in parallel
Interleaving: Design the right interface
to the 4 memory banks on the chip, so
several row requests run in parallel.
Bank a
Bank b
Bank c
Bank d
Can also do other commands on banks concurrently.
CS 152 L9: Memory
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Only part of a bigger story ...
CS 152 L9: Memory
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Only part of a bigger story ...
CS 152 L9: Memory
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DRAM controllers: reorder requests
From:
CS 152 L9: Memory
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Today’s Lecture: DRAM
DRAM: Bottom-up
DRAM: Top-down
DRAM: Systems
CS 152 L9: Memory
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Installing a Dual Inline Memory Module (DIMM)
CS 152 L14: Cache I
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DDR2 SO-DIMM Module
DRAM chips
are wired in
parallel and run
in lockstep.
CS 152 L9: Memory
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From DRAM chip to DIMM module ...
Each RAM chip
responsible for 8
lines of the 64
bit data bus (U5
holds the check
bits).
Commands sent
to all 9 chips,
qualified by
per-chip
select lines.
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
How DIMMs talk to CPU
Integrated
Memory
Controller
(IMC)
On the
same die as
CPU.
SDRAM
bus:
Parallel
bus with a
single
master.
CS 152 L9: Memory
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Intel Core i5: Sandy Bridge
All on chip:
x86 cores
GPU
North
Bridge
DRAM
controller
CS 152 L9: Memory
On chip ring
network
UC Regents Spring 2014 © UCB
Lower levels of DRAM bus specification
Transaction Protocols
Signal Timing on Wires
Wires
Electrical Properties
Mechanical Properties
Ideally, DIMMs made by any
manufacturer should fit into any
compliant socket, and work.
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Upper levels of DRAM bus specification
Collaboration
between DRAM
manufacturers
(Samsung, Micron)
and DRAM users
(Intel, Cisco, ... ).
Transaction Protocols
Signal Timing on Wires
Wires
Electrical Properties
Mechanical Properties
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Bus wires shared between many DIMMS
Apple Xserve G5 - has 8 DIMM
slots, to support 8GB.
DIMMs respond to transaction
requests. Since memory controller
is the only bus master, and there
are a small number of DIMM slots,
bus sharing is easy: use DIMMselect signal wires to each slot.
Memory controller is the only “bus master” - it can start
transactions on the bus, but the DIMMs cannot.
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Sony PS 4
Uses graphics
DRAM for all
8GB of RAM
(very high
bandwidth).
4 core
Jaguar
x86
176 GB/s Mem BW
1152 GPU Cores
1.84 TeraFLOP
Tradeoff:
GDDR5 chips
connect to
CPU with
dedicated
wires. Not via
a shared bus.
More system
pins, thus higher
cost.
4 core
Jaguar
x86
Focus is on
“serious gamer”
not
“media center”.
5.5 GHz GDDR5
MacBook Air ... too thin to use DIMMs
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Mainboard: fills
about battery
25% of ...
the laptop
Non-removable,
“form-fit”
35 W-h battery: Fills most of the volume ...
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Macbook Air
Top
Core i5: CPU + DRAM controller
Bottom
4GB DRAM soldered to the main board
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
CS 152 L14: Cache I
UC Regents Spring 2005 © UCB
Original iPad (2010)
“Package-in-Package”
128MB SDRAM dies (2)
Apple A4 SoC
Cut-away
side view
Dies connect using bond wires and solder balls ...
CS 152 L14: Cache I
UC Regents Spring 2005 © UCB
3-D memory stack
Thru-silicon-vias (TSVs)
CS 152 L9: Memory
UC Regents Spring 2014 © UCB
Sony Playstation Vita ...
CS 152 L14: Cache I
UC Regents Spring 2005 © UCB
1 Gb Samsung Wide I/O DRAM + Toshiba/Sony ARM CPU
1080 pads with 40 µm
spacing, face-to-face.
“Face-to-face” limits this scheme to two chips,
but avoids thru-silicon-vias (TSVs).
CS 152 L14: Cache I
UC Regents Spring 2005 © UCB
On Thursday
Caching, part one ...
Have fun in section !