Gentest: An Automatic
Test-Generation System for
Sequential Circuits
Mohamed Abougabal,
Wael Hermas,
Tarek Saad,
Rami Abielmona
ELG 5194
Wednesday November 22, 2000
Prof. Sunil Das
Presentor: Mohamed
Abougabal
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Introduction Gentest
Definition
Converting Sequential to Combinational circuit
Gentest Architecture
Introduction to Gentest
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Definition:
– Gentest is an automatic Test-Generation System for
sequential Circuits.
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Gentest:
– Was introduced because of the rapid growth of VLSI chips,
we certainly know that these chips contains faults. Therefore
we need Gentest to help us achieve the high fault coverage.
– It Overcomes the inefficiency of previous ATG methods for
sequential circuits by combining a sequential test generator
with a concurrent fault simulator.
Test Generation
Techniques (1)
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1. Manually write test vectors (write a sequence of
values provided to the circuit input)
– Disadvantage:
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It’s tedious and time-consuming process
2. BIST : Built-In-Self test Circuit
The circuit itself create test vectors . The circuit generates
random patterns that can thoroughly test a combinational circuit.
– Disadvantage:
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It requires more circuitry.
The cost of chip is higher because of the area.
It causes the chip to be slower
Finding the exact fault coverage for test vector is difficult.
Test Generation
Techniques (2)
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3. ATG: Automatic Test Generation.
– Given the description of a circuit , ATG programs deliver a
set of vectors.
A complete ATG algorithm guarantee finding a test for a fault
if one exists.
– Disadvantage:
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It’s not practical for every circuit
Since most of the sequential circuits are practical circuits we
can use Scan Design Techniques to convert sequential circuits
into combinational circuits.
The difficulty of sequential test generation lies on the large
number of decision steps.
Converting Sequential to
Combinational Circuits (1)
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The First Sequential Test Generation Algorithm were
just an extension of the combinational test algorithm.
Those Algorithm are:
– D- Algorithm
– Podem (Path-Oriented Decision making.)
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We can model Sequential circuits by two blocks
(Combinational and Memory)
Converting Sequential to
Combinational Circuits (2)
Figure 1. Sequential circuit model
Iterative Logic Array
Method (1)
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Now use this same concept and expanding on it we
can model a Sequential circuits into Combinational in
time Domain and this method is known as The
Iterative Logic Array Method.
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In Figure 2: Each copy corresponds to the circuit
behavior at one time frame. Therefore D-Algorithm
and Podem can be applied because these are
combinational circuits.
Iterative Logic Array
Method (2)
Figure 2. Iterative logic array model
Iterative Logic Array
Method (3)
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Problems:
– Inefficient in dealing with repeated faults sites.
– Excessive memory usage because the circuit must be saved
for each time frame in test sequence.
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Solution:
– Mallela and Wu have introduced STG2 (sequential test
generator using the Back algorithm)
– Then Gentest was introduced. Gentest is combination of
STG2 and Csim ( Concurrent fault simulator).
Gentest Architecture (1)
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Functionality of:
– STG2: Generates a test sequence for every target fault
selected by Gentest
– Csim : Determines which faults are detected by the STG2generated test sequences.
– Gentest: Submits the vectors created for fault detection to a
fault simulator.
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Now the overall operation of Gentest .
– 1. The user can provide a fault list; otherwise, Gentest
creates one after collapsing all equivalent faults.
– 2. User can set a time limit or let it be generated by an
experimental formula in SGT2.
– 3. User can provide some initializing vectors that Csim will
simulate to initialize the circuit
Gentest Architecture (2)
– 4. Gentest selects an untried and undetermined fault as a
target fault for SGT2.
– 5. SGT2 tries to generate a test sequence for the target fault.
– 6. So by looking at steps 1 to 5. Test sequence can be
generated in one of the three cases:
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Test sequence can be generated to detect the target fault
The target fault can prove untestable
Time limit can be reached.
In either of these cases Gentest returns to step 4.
Presentor: Wael Hermas
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Iterative Logic Array Model
Podem Algorithm
Putzolu and Roth Test Method
STG2 Discussion
Back Algorithm
The Test Generator
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Problems of previous test generation method
– Iterative Logic Array Model
– Podem Algorithm
– Putzolu and Roth Test Method
Iterative Logic Array
Model (1)
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The following figure (refer to figure 3) shows a
sequential circuit with a single stuck-at fault.
Each “*” is the fault site in each time frame.
Using the iterative logic array model, this fault has a
repeated fault effect at every time frame.
Iterative Logic Array
Model (2)
Figure 3. General model of a test sequence
Podem Algorithm
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Assume that the fault, in the previous example, can
only be tested by a test sequence with eight test
vectors
Lets us say that the Podem algorithm needs to know
that the propagation of fault effects should start after
time frame 5 (Podem algorithm will stop at frame 4)
since all the sensitized paths are blocked
Without knowing the test sequence, having this
information would be impossible, therefore we can
conclude that Podem algorithm can be very inefficient
in generating test sequence for sequential circuits.
Putzolu and Roth Test
Method (1)
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Uses the two-step approach of the D-algorithm to
generate the test sequence.
Their method has the same problem as Podem at
time frames 1-4.
To solve this problem, the five-valued model of the Dalgorithm was extended to be the nine-valued model
Table 1 compares the five-valued and nine-valued
models
Putzolu and Roth Test
Method (2)
Table 1. Comparison of 5-valued and 9-valued models
The nine-valued model
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The nine-valued model lets us use single-path
sensitization in the D-algorithm.
– The nine-valued model is very inefficient during justification
– The nine-valued model has the following efficiency problems
– To justify an N-input gate's output value, there are N*N
choices
– No simple testability guidance can rank these N*N choices.
Sequential Test Generator
(STG2)
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Because of the efficiency problems in the previous
test generators, a complete test generator STG2,
without excessive memory requirements, is
developed.
Uses the Back Algorithm and the Split value model
The Back Algorithm (1)
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The Back Algorithm proceeds as follows:
– the algorithm selects the primary output with the sensitized
value
– this is accomplished through a new testability measurement
called derivability
– the fault is not testable if no primary output can have a
sensitized value
– the algorithm justifies the values required at the current time
frame
– the test sequence has been found if the state input
requirements of the current time frame match the initial state
values
The Back Algorithm (2)
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Continued:
– the back algorithm justifies time frame by time frame (all the
requirements of one time frame can be handled
simultaneously)
– during test generation, the circuit status has to contain at
most two time frames: the current and previous time frames.
– Hence, we can conclude the Back Algorithm's memory
requirements is minimal.
Presentor: Tarek Saad
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Fault simulation
Sequential circuit fault simulation
Nine-valued model
Split value model
Testability guidances
Fault Simulation
Good machine
A logic model of the circuit-under test without any faults inserted
Faulty machines
A logic model of the circuit-under-test with one or more fault
models inserted
Fault specification
Defining the set of modeled faults and performing fault
collapsing
Fault insertion
Selecting a subset of the faults to be simulated and creating the
data structures to indicate the presence of the faults
Sequential Circuit Fault
Simulation
Figure 4. Sequential circuit test simulation model
Nine-valued Model (1)
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The good machine and bad machine are
two independent sub-circuits with the
same primary inputs.
It combines the values of the two sub
circuits to reduce memory needed to
store circuit status.
In this arrangement the two circuits must
be justified simultaneously.
Figure 5. Realization of a
Sequential circuit
Figure 6. The nine-valued model
Nine-valued Model (2)
Inefficiencies:
 Justifying two independent sub circuits simultaneously
increases the number of backtracks and the time
wasted.
 Split value algorithm will solve this problem.
Split Value Model (1)
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Extension to nine-value model to
improve it’s performance during
justification.
It splits the nine values into two sets
of three values for the good, and bad
machine.
Separate storage for the circuit
statuses, good/bad machine can be
justified separately.
Figure 7. The split value
model
Split Value Model (2)
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Each machine is justified separately, we can use testability
measurement of each circuit to rank available choices.
Split model uses default value to reduce backtracks significantly.
Definitions:
Good value. Value at the good machine.
Bad value. Value at the bad machine.
Relation. Relation between good and bad value.
Good/bad values can be 0, 1, x(don’t care), or z(high
impedance).
Sensitized lines. Lines with unequal good and bad values.
Non-sensitized lines. Lines with equal good and bad value, not
affected by fault site.
Relation.Could be sensitized, non-sensitized, or unknown.
Split Value Model (3)
Dynamic identification of relation information proceeds
as follows:
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If all input of an element are non sensitized lines, then all
outputs must be non-sensitized.
If any output of an element is a sensitized line, then at
least one input must be a sensitized line.
Advantages:
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The high impedance value is used in bus element
containing circuits to avoid bus conflicts.
Testability Guidance
Two testability measurements guide decision making in
conventional test generators:
Controllability: measures the difficulty of placing a specific logic
(0or1) value on that line.
Observability: measures.The difficulty of observing the fault effect
at that line from the primary outputs.
• Both are calculated based on the good machine.
• Observability guides the sensitized-path selection while
controllability guides the line value justification.
• Back algorithm (as mentioned) uses drivrablitiy similar to
observabilityand measures the dificulty of driving the fault effect
from the fault site to a line.
Presentor: Rami
Abielmona
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Experimental results
STG2 Analysis
Gentest Analysis
Conclusions
Future Work and Biographies
Experimental Results
Sequential Test Generators
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STG2 is an extension of STG1, described by Mallela
and Wu
STG2 uses the Back algorithm and the Split value
model, while STG1 utilizes the extended backtrace
method and the nine-valued model.
STG1.5 uses the D-algorithm and the Split value
model.
From the experimental results that will be presented
next, STG2 was chosen for implementation in
Gentest, because it has shown the best fault
coverage and total test-generation time.
Experimental Results
STG2 Analysis (1)
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The three sequential test generators were
compared by live-testing them on a Convex
C-1 computer using a myriad of circuits, the
latters’ characteristics shown in Table 2
Looking at that table, a few definitions are in
order:
–
–
–
–
–
Gates
p1,p0
I/O pins
FF
Faults
>>>
>>>
>>>
>>>
>>>
The number of gates in the circuit;
The primary inputs and outputs;
Either input or output, but not both;
The number of flip-flops in the circuit
The number of faults in the circuit.
Experimental Results
STG2 Analysis (2)
Table 2. Characteristics of the circuits
Experimental Results
STG2 Analysis (3)
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Table 3 shows the detailed results of the analysis of
STG2
The definitions are as follows:
– Time
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The sum of the test-generation time in
seconds for all the target faults;
– Detected/Untestable/Dropped
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The number of tests in each category;
– Efficiency
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The sum of detected and untestable faults divided by the
total faults.
Experimental Results
STG2 Analysis (4)
Table 3. Results for STG2
Experimental Results
STG2 Analysis (5)
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Table 4 compares efficiency and time for all three test
generators.
As we can see from the results, STG2 spent more
time than STG1.5 for circuits c499 and c880, but
overall, as the number of gates and faults in the
circuit increase, the efficiency of STG2 is much higher
than that of STG1.5, with a lower time factor as well.
The latter observation leads us to the conclusion that
test-generation overall time is much better using
STG2, thus was chosen for incorporation in Gentest.
Experimental Results
STG2 Analysis (6)
Table 4. Comparison for STG1, STG1.5 and STG2
Experimental Results
Gentest Analysis (1)
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Another set of experiments were carried out on a Sun
3/60 workstation, using the Gentest test generation
algorithm
The set of circuits implemented this time vary from
the previous ones, but still are represented by the
same characteristics as the previous ones (See table
5, for a brief reference).
Experimental Results
Gentest Analysis (2)
Table 5. Characteristics of the circuits
Experimental Results
Gentest Analysis (3)
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Table 6 shows the detailed results of the analysis of
Gentest
The definitions are as follows:
– Time
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The sum of the test-generation time, fault-simulation time
and communication time between the CPU and the circuit in
seconds for all the target faults;
– Trial/Untestable/Sequences
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The number of tests or sequences in each category;
– Vectors/Detected
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The number of vectors is the size of the final test sequence,
while the detected column lists the faults detected by CSim;
– Fault Coverage
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The sum of untestable faults identified by STG2 and detected
faults identified by Csim, divided by the total number of
faults.
Experimental Results
Gentest Analysis (4)
Table 6. Results for Gentest
Experimental Results
Gentest Analysis (5)
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Observations of the results are as follows:
– The number of sequences generated by STG2 is always
much smaller than the faults detected by CSim;
– The number of runs needed by STG2 to identify all the
untestable faults cannot be reduced, hence is on the critical
path of the total test-generation time;
– The CPU time limit was set to two seconds per fault, thus for
circuits “logic6” and “mickey”, the fault coverage was very
low due to the amount of target faults in these circuits; and
– The total average fault coverage did increase as the Gentest
algorithm was applied, as opposed to the results in table 3,
which showed the circuits after STG2 alone was applied.
Paper Conclusions
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Gentest has proven to be a very efficient automatic
test-generation system for sequential circuits
It minimizes the total time needed for testgeneration, as well as maximizes the efficiency
Gentest also demonstrates an improved, but not
ideal, test fault coverage
Future Work
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Future work on test-generation algorithms will
concentrate on large functional units, and more
complex circuitries
To do so, the test-generation process has to be sped
up, through the use of high-level models or functional
units, such as instantiating behavioral models of a
circuit (e.g. ALU, shift register, binary counter), rather
than their gate- or even switch-level implementations
Such an algorithm had not yet been well defined
Author Biographies