®
NiosTM 2.0
Altera’s embedded Processor Solution
© 2001
1
Nios Embedded Processor

Configurable Soft Core
Embedded Processor
 Optimized for Altera®
Programmable Logic Device
(PLD) Architecture
 32-Bit RISC Architecture
 License & Royalty Free
 Over 6,000 Kits Sold
© 2001
2
®
Nios Device Support
Device Family
Features
Stratix™
Highest Speed (0.13-µm, All-Layer Copper)
DSP Blocks
Very High Speed I/O
Very High Density
Mercury™
Very High-Speed I/O with Clock-Data Recovery (CDR)
Medium Density
ARM®-Based Excalibur
High Speed
Multi-Processor Systems (ARM + Nios)
Medium-to-High Density
APEX™ II
High-Speed Differential I/O
Very High Density
APEX 20KE
APEX 20KC
High-Speed Differential I/O
Low-to-High Density
FLEX® 10K
Low Cost
Low-to-Medium Density
ACEX® 1K
Low Cost
Low Density
© 2001
3
®
Combines Altera Strengths

High-Density, HighPerformance Devices





Stratix
APEX II
Mercury
ARM-Based
Excalibur
Software
Development
Tools
 Compiler
 Debugger
 RTOS
SOPC
Builder

Hardware
Development Tools




Quartus® II
LeonardoSpectrum™
ModelSim®
Development Boards

Robust IP Offerings
 Processor
 DSP
 Communication

Bus Interface
© 2001
4
®
®
SOPC_BUILDER
© 2001
5
A powerful friendly GUI
Hardware
Environment
Software
Environment
Simulation
Environment
Hardware
Team
Software
Team
© 2001
6
®
The NiosTM System Architecture
Nios
Flash
Tri-State
Bridge
UART 0
Arbiter
Interrupt
Controler
Arbiter
@
decoder
Timer 0
OCD
AMBA / AVALON
Port Interface
7
Arbiter
© 2001
Dynamic
Bus Sizing
Arbiter
STRIPE
Data In
Multiplexer
Arbiter
Wait State
Generation
User
Tri_State
Device
Nios
SRAM
AVALON (Bus Peripheral Module)
UART n
Timer n
SPI 0
GPIO 0
DMA 0
SPI n
GPIO n
DMA n
Memory
Interface
User-Defined
Interface
®
SOPC Builder Ready Components
ARM922T™
Processor
DMA
USB 1.1
SDRAM
Nios™ Embedded
Processor
PCI
USB 2.0
SSRAM
ARM®-to-Nios Bridge GPIO
(AMBA AHB-to-Avalon)
SPI
SRAM
Interface to User
Logic
Timer
CAN 2.0
FLASH
10/100 Ethernet
Watchdog
16550S UART On-Chip ROM
On-Chip RAM
The List Keeps Growing . . .
© 2001
8
®
A Lego's like system
The 2.0 CPU core
Peripherals
Available
Options
© 2001
9
®
A modular generation
Software Environment
Hardware Environment
Netlist Generation
Simulation Environment
Sources for the Synthesis
and simulation are
available in both VHDL
and verilog languages.
All PLD families
supported
© 2001
10
®
®
NiosTM
Hardware Description
1- The Core,
2- Custom Instruction
3- Multi-Mastering
© 2001
11
NiosTM processor Features

1/2
32-Bits or 16-Bits RISC Architecture
 5 Stage Pipeline
 Fully-Synchronous Interface
 Same 16-bits instruction Set for both Data Path sizes.

Windowed Register File
 Configurable to 512 Registers.
 Fast Context Switching.

Integrated Interrupt Controller
 64 Vectored Interrupts.

Selectable Reset Address
© 2001
12
®
NiosTM processor Features

Dynamic Bus Sizing mechanism

Arithmetic's functions for the ALU.
2/2
 Fixed Barrel-Shifter that executes all shift instructions in 2 clock cycles,
regardless of the shift-distance.
 MSTEP multiplier or 16x16 Bits multiplier.

Optimized Data Processing
 Custom CPU Instructions
 >2X Acceleration (e.g. MAC, MP3, Bit Swap)

Optimized Data Flow
 Simultaneous Multi-master Bus Capability
 Gbps Throughput
© 2001
13
®
Nios RISC Processor Block Diagram

Standard RISC Components
 Fully-Synchronous Interface
 Native Verilog
 Native VHDL
© 2001
14
®
Custom Instruction Block Diagram
Optional FIFO, Memory, Other Logic

Extends Nios Instruction Set
 Up to 5 Instructions

Nios System Module
System Builder:
 Adds User Logic to Nios ALU
 Assigns Op-Code
 Generates C & Assembly
Macros

Profiler Tools.
© 2001
15
®
Traditional Data Flow for Multi-Masters

Direct Memory Access (DMA)
 Processor Waits For Bus During DMA
Masters
System CPU
(Master 1)
DMA
(Master 2)
Bottleneck
DMA
Bus
Arbiter
DMA
Arbitor
Arbiter Determines
Which Master Has
Access To Shared
Bus
System Bus
Slaves
Program
Memory
I/O
1
I/O
2
Data
Memory
© 2001
16
®
Simultaneous Multi-Master Avalon Bus
Master 1
(Nios CPU)
I
Master 2
(100Base-T)
D
Masters
Avalon Bus
Avalon Bus
Slaves
Arbiter
Program
Memory
I/O
1
I/O
2
Data
Memory
1
Multiple Arbitration
Schemes
 Round Robin
 Priority Based
© 2001
17
®
Simultaneous Multi-Master Bus
Master 1
(Nios CPU)
I
Master 2
(100Base-T)
Master n
(100Base-T)
D
Masters
Multi-Master Avalon
Avalon Bus
Avalon Bus
Avalon Bus
Arbiter
Arbiter
Data
Memory
1
Data
Memory
n
Slaves
Program
Memory
I/O
1
I/O
2
© 2001
18
®
Simultaneous Multi-Master Bus
Master 1
(Nios CPU)
I
Master 2
(100Base-T)
D
Fetch Code
Receive Packets
Avalon Bus
Program
Memory
I/O
1
Master n
(100Base-T)
Send Packets
Avalon Bus
I/O
2
Avalon Bus
Arbiter
Arbiter
Data
Memory
1
Data
Memory
n
© 2001
19
®
DMA Peripheral support
Master 1
(Nios CPU)
I
DMA
Master 2
(SPI)
D
Avalon Bus
Avalon Bus
Arbiter
Program
Memory
I/O
1
I/O
2
Data
Memory
1
© 2001
20
®
SOPC Builder Design Flow
Define System
CPU
Peripherals
Memory
User Logic
Generate
Software
Simulate
Hardware
Header File
Custom Library
OS Kernel
HDL
Simulation
Application
Hardware
SignalTap™
Logic Analysis
Download
Debug/Profile
Finished
System
Application
Software
Download
© 2001
21
®
®
HDL Simulation
© 2001
22
Memory Device Simulation Models

Applies to the following Nios Memories
 On Chip Memory (ROM or RAM)
 SRAM (one or two IDT71V016 chips)
 Flash Memory
Source files (*.c & *.s) are compiled.
Data files (*.mif & *.srec) are converted
File is used in raw format
Useful for non-standard build eg
nios-build –cc –O0 hello.c
String is used in raw format
© 2001
23
®
UART Simulation

UART rx and tx transmissions are echoed to ModelSim
Console
© 2001
24
®
RTL Simulation

Nios SOPC Builder Automatically creates simulation
model plus




ModelSim Project
Testbench
Simulation Scripts
Formatted Wave Window
Start ModelSim
© 2001
25
®
Nios TestBench
Included
Nios
32 Bit
RAM
Nios
SRAM
Nios
Flash
User
Tri_State
Device
Not Included
Data (32)
Address (32)
Nios Processor
TriState
Bridge
Address (32)
Clock
Read
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
UART
© 2001
26
SDRAM
PIO
User Device
SPI
User Device
On Chip
ROM
User-Defined
Peripheral
User Device
On Chip
RAM
User-Defined
Interface
User
Peripheral
Write
Timer
Avalon Bus
Reset
32-Bit
Nios
Processor
SDRAM
Controller
User Device
®
Simulation Scripts

When ModelSim is started from the SOPC Builder a
set-up script is run automatically which creates
aliases for simulation scripts
 The set up script can be run independently as follows:
 do setup_sim.do

Simulation Scripts
 s
 c
Compiles HDL source code and loads design
Rebuilds memory contents based on software code
Includes changes since Nios generation
 w
Opens Wave window with “useful” signals
Will have to add user signals
 h
Displays help message describing scripts
© 2001
27
®
Wave Window

Adds UART and CPU signals by default
 CPU Opcodes are decoded and displayed to help trace software execution
© 2001
28
®
®
Nios Debugging Solutions
© 2001
29
Nios Debug Solutions
Provider
Product
Description
Viosoft
Arriba!
IDE with Integrated Support for Nios On-Chip Debug Module Hardware Breakpoints & Processor Trace
Microtronix
Debugger Module
External Memory Daughter Card for Use as Software Trace
Capture Buffer
Redhat
GDB / Insight *
Software Debugger
Altera
Tracelink *
Interface to Nios On-Chip Debug Module
Hardware Breakpoints & Processor Trace
* Included in Excalibur Development Kit Featuring Nios Processor
© 2001
30
®
Red Hat GNU Debugger (GDB)

Run Control
 Breakpoints, Watchpoints, Catchpoints
 Stack Frame Analysis
 List & Search Source Files
 Examine Memory, Constants, Variables
 Disassemble Machine Code
 Examine Expressions Using C / C++
Operators
© 2001
31
®
Red Hat Insight Debugger

Graphical User Interface for GDB
 Windows









Source
Stack
Register
Memory
Watch Expression
Local Variables
Breakpoints
Console
Function Browser
© 2001
32
®
Altera Tracelink


Baseline Support for Nios Processor Ver. 2.0 On-Chip Debug &
Software Trace Capabilities
Captures Instructions and Data Executing in Nios CPU
 Up to 1.2 Million Instructions


Captures Trace Data at Full System Speed
Uses External Trace Memory Debugger Module
 Available from Microtronix
© 2001
33
®
Hardware for Trace


Enable On-Chip Debug Logic in SOPC Builder
Connect Nios OCD Ports to External Memory on Debugger Module
Program
Memory
Simultaneous
Multi-Master
Avalon Bus
Nios System Module
Nios
CPU
O
C
D
UART
Other…
© 2001
34
®
®
NiosTM Ethernet
Development Kit
(NEDK)
© 2001
35
Nios Ethernet Development Kit

Supports Wide Range of Applications
 Factory Floor Automation
 Basic Ethernet Connectivity
 Internet Upgradeable Hardware

Supports All PLD Families

Development Board
 External 10Mbyte MAC/Phy
 Support for 2 Ports

Software Included
 TCP/IP Stack

Reference Design
 Hardware (Quartus™ Project)
 Software (Web Server Application)

Price $495
© 2001
36
®
®
Linux Development Kit,
by Microtronix
© 2001
37
What do you get in the LDK box?

µCLinux kernel source code

Three daughter boards to enable Linux
development on NDK board





Operating System
Support Board
Memory Expansion: SDRAM & flash
OS Support: Real-time Clock & IDE interface
Ethernet Connectivity: NEDK daughter card
Serial Y-cable for debug
Software & reference application
Memory Expansion Board
Ethernet
Connectivity Board
 Web server
 Linux command shell
 µCLibC & Kernel open source

Hardware reference design
 Linux works out of the box, no Quartus compile
necessary

Open Source. No licensing fees.
No Royalties.

List Price: $2,495
© 2001
38
®
®
PCI32 Nios Target
MegaCore Function
© 2001
39
Ver 1.0
PCI32 Nios Target MegaCore® Function

PCI Interface to Nios via Avalon™ Bus Bridge

Nios System Builder Interface

Behavioural Simulation Models

PCI Testbench for PCI32 Nios Target Core

Low-Level Driver Routines in C Source Code for Nios
Embedded Processor

Reference Design for Use with Nios Embedded Processor

Complete Documentation
© 2001
40
®
®
Nios Operating System
(OS) Support
© 2001
41
Nios™ OS / RTOS Support
Provider Product
Accelerated
Technology
Nucleus
PLUS
Description
Royalty-Free, Source-Available RTOS
Mapusoft
OSChanger
Technologies
Tool to Convert pSOS / VxWorks Applications to
Nucleus PLUS
Microtronix
µCLinux
Open-Source OS
Shugyo
Design
KROS
Small-Footprint, Royalty-Free, POSIX-Compliant
RTOS
© 2001
42
®
Nucleus PLUS

Multi-Tasking Real-Time Kernel
 Priority, Pre-Emptive Scheduler
 Inter-Task Communication
 Pipes, Queues, Mailboxes

Inter-Task Synchronization
 Semaphores, Signals, Events

Memory Management
 Fixed or Variable

Dynamic Creation/Deletion of All Objects
© 2001
43
®
uCLinux

Linux Development Kit
 Software




Linux Kernel & uClibc Library – Nios™ Port
Nios Linux Driver Support
70+ Applications
30-Day Installation Support
 Hardware


10BaseT Ethernet Card
Operating System Support Board
 CompactFlash Connector
 Real-Time Clock
 IDE Interface

SDRAM/Flash Expansion Board
© 2001
44
®
To add or set up the Software Components, you need to go to the
More “[cpu module]” Settings Tab.
The Software
Components section
on this page will look
a lot like the System
Contents page (first
image) but with
software instead of
hardware
components. The
functionality is the
same.
© 2001
45
®
The first of several pages will show up. All the typical options for configuring the kernel
are presented as a list of radio buttons and/or checkboxes.
Once the settings are finished, they are saved and ready to be used during the compile
process. The final screen will present the “Microtronix Make Console”.
© 2001
46
®
Since this is a new project, there is no actual source
tree for us to compile. The source code repository
files (included with the Microtronix Software
Component) need to be copied.
The files are copied by clicking the “Copy Files”
button.
Assuming this is cpu component “nios_0”,
the source tree will be copied to the
“Altera Projects\Excalibur\nios_0\uClinux” directory.
© 2001
47
®
Once the Copy Files button has been pressed, a small console will pop up and begin the copying of
files. The “Make Dependencies” button will now be enabled and ready for use.
After the copying is done, pressing the Make Dependencies button will cause a “make clean”
command to be executed followed by the “make dep”.
© 2001
48
®
Once finished, the file
“linux.srec” will be ready for
you to upload to your
Excalibur Board.
© 2001
49
®
KROS

Real-Time Operating System
 Features




Tiny Footprint, 16K to 64K
POSIX Interface
GNU Compiler Support
Supports Altera Nios CPU
 Advantages



Low Cost
Source Code Provided
Royalty Free
© 2001
50
®
KROS Latency

POSIX 1c compliant
 About 6K foot print
 Based on a very simple Nios Variation (UART & Timer)
 The WVALID register have to be modified
 Latency values:
© 2001
51
®
®
Roadmap
© 2001
52
SOPC Builder Roadmap
2002
Q1
Q2
Q3
Q4
SOPC Builder 2.5
SOPC Builder 2.6
SOPC Builder 2.7
 Released with Nios 2.0
 Multi-Master Buses
with Slave-Side
Arbitration
 Avalon Support
 Stand-Alone Tool
 Excalibur ARM Support
 AHB Support
 Multiple Clock
Domains
 Software Acceleration
Libraries
© 2001
53
®
Nios Roadmap 2002
Q1 2002
Q2 2002
Nios 2.0
Nios 2.1
 Stratix Support





Smaller / Faster CPU
Simultaneous Multi-Master
Custom Instruction
On-Chip Debug
SOPC Builder 2.5
Q3 2002
Q4 2002
Nios 2.2
 Instruction Cache
 JTAG UART
 Quartus II LE Ver 2.0
 Bug Fixes
SOPC Builder 2.6
 Included in Quartus II 2.1
 Consistent ARM / Nios
 Nios OpenCore Plus
SOPC Builder 2.7
 Web Update
 Multi-Clock Domain
 Software Components
NIOS Ethernet Kit
 10/100 MAC/PHY
 SMSC LAN91C111
 Updated Protocol Lib
 Interrupt Support
© 2001
54
®
Options Roadmap
1. Ethernet links
 10Mbits available now.
 10/100Mbits on going to be released (WW18)
•
Port plugs library to new HW
2. µClinux
 Available for Nios 1.1 – Kernel 2.0
 The port for Nios 2.0 is on going – Kernel 2.4 (WW25)
•
The LDK has been included in the SOPC_BUILDER.
Evaluation CD will be shipped with Nios2.1 update kits.
•
Upgrade subscription for $2000.
© 2001
55
®
®
Summarize
© 2001
56
A Step Beyond...
NiosTM has a more than 1 year lead on the competition






The NiosTM 1.0 has been released in July 2000.
The NiosTM 2.1 released with Stratix support.
More than 6000 kits sold all over the world.
In many market places, NiosTM is become the flexible solution.
A WYSIWYG (What You Select Is What You Get) hardware solution
 Parameterize the Core and built your peripheral image.
 All ATERA PLD devices supported
 Royalty free. No obsolescence.

A complete SW, HW development tools set.
 Development Tools, Existing Flows
 Development Board, target debug support.
 Application demos, Real-Time Operating Systems.

Advanced Training Sessions available
© 2001
57
®
Nios 2.0 Systems Overview.
Family
ACEX 1K
APEX 20KE
APEX 20KC
APEX II
CPU
Features
LEs / ESBs
MHz
Device
Nios 16-bits
1K Internal ROM, 32K External SRAM, 16K External FLASH
1 Timer, 1 UART, 8 INs, 8 OUTs
1400 / 2
30MHz (-3)
50MHz (-1)
1K30
Nios 32-bits
1K Internal ROM, 256K External SRAM, 1M Extenal FLASH
1 Timer, 1 UART, 8 INs, 8 OUTS
2600 / 8
22MHz (-3)
46MHz(-1)
1K100
Nios 16-bits
1K Internal ROM, 32K External SRAM, 16K External FLASH
1 Timer, 1 UART, 32 INs, 32 OUTs
1700 / 7
46MHz (-3)
75MHz(-1)
20K100E
Nios 32-bits
1K Internal ROM, 256K External SRAM, 1M Extenal FLASH
1 Timer, 1 UART, 8 INs, 8 OUTS
2360 / 13
46MHz(-3)
70MHz(-1)
20K100E
1K Internal ROM, 256K External SRAM, 1M Extenal FLASH
1 Timer, 1 UART, 8 INs, 8 OUTS
DMA, Ethernet 10Mbits
3100 / 13
38MHz(-3)
60MHz(-1)
20K100E
Nios 16-bits
1K Internal ROM, 32K External SRAM, 16K External FLASH
1 Timer, 1 UART, 32 INs, 32 OUTs
1700 / 7
52MHz(-9)
80MHz(-7)
20K200C
Nios 32-bits
1K Internal ROM, 6K Internal RAM, 256K External SRAM,
1M Extenal FLASH, 512Mbits SDRAM
3 Timers, 2 UARTs, 32 INs, 32 OUTS
DMA, SDRAM Ctrl
5400 / 35
34MHz(-9)
49MHz(-7)
Nios 32-bits
1K Internal ROM, 256K External SRAM, 1M Extenal FLASH
1 Timer, 2 UARTs, 8 INs, 8 OUTS
85MHz(-5)
1K Internal ROM, 6K Internal RAM, 256K External SRAM,
1M Extenal FLASH, 512Mbits SDRAM
3 Timers, 2 UARTs, 32 INs, 32 OUTS
DMA, SDRAM Ctrl
36MHz(-9)
49MHz(-5)
5400 / 20
20K400C
2A15
2A15
© 2001
58
®