Oregon Institute of Technology
Embedded Systems Engineering Technology
CST 407
Lab
Design with SOPC
JTAG Interface
By Sam Mancill
SOPC Pitfalls and Errors
Objectives:
1) Learn common errors encountered in SOPC builder and NIOS II IDE and
possible solutions to them.
Starting off with SOPC builder there are a number of errors whose cause is not immediately obvious and
that can be frustrating. The following compilation of errors our SOPC class encountered will be useful to
future students:
Not enough on-chip memory when compiling in NIOS II IDE
SRAM component won’t work
After moving your NIOS project between computers, it will not compile
NIOS won’t allow a project to be created, saying a system library of similar name already exists
SOPC builder generates a time-limited .sof file
NIOS IDE cannot connect to board when you try to run your software
Quartus wont compile, giving a “database error”
Empty while loop won’t work
Adding/modifying components doesn’t work
What is the “altera_europa_support” file?
Not enough on-chip memory when compiling in NIOS II IDE
Example:
ld: region onchip_mem is full (nios_control.elf section .rodata). Region needs to be 392 bytes larger.
The simplest memory to use in SOPC builder is the on-chip ram, as it does not need a core to control it
like SDRAM, SRAM, or Flash but it is much smaller than those. Some sort of memory must be provided
for NIOS to place code on. It is easy for even simple programs to be larger than the default 4K on-chip
memory size. As programs grow, it is inefficient to keep making the on-chip memory larger, as it uses up
chip real estate and requires a lengthy regeneration and compile in Quartus. By default, project
properties in NIOS II make your program much larger than it needs to be. To minimize size, right click on
the project name in the Projects window and select System Library Properties. In the resulting dialogue
box, uncheck “Support C++” and check “Small C library.” I found this made program sizes as much as 10
times smaller.
Your program may not fit in memory yet. At this point you should add SRAM or SDRAM to your system
as detailed in other labs.
SRAM component won’t work
The SRAM core that comes with NIOS II doesn’t work with the SRAM on the DE2 board. Custom changes
must be made to the controller for it. The included component needs to be updated and runs off a
cross-clock bridge. Sean McClain has made a custom SRAM core that works off a tristate bridge and
more information can be found in that lab.
After moving your NIOS project between computers, it will not compile
The NIOS IDE has some bugs with file paths. A general solution to issues like this is to clean the project.
This is done by selecting Clean… from the Project menu. Another problem is that there CANNOT BE A
SPACE in the folder path. If you moved it into such a place, move or rename to eliminate all spaces.
NIOS won’t allow a project to be created, saying a system library of similar name already exists.
By default, NIOS saves all software in the “software” folder relative to your Quartus project and its .ptf
file. If you try to make a second project with that .ptf file, NIOS will get confused by the existing project.
For example, if you use the default hello_world template for the first and second projects, there will be
a folder called “hello_world_0_syslib” created in the software folder for both of them, even if the
project names are different. As NIOS tries to make the second copy of that folder, it will error and you
can’t make a project. To avoid this, do not make multiple projects in the same directory.
SOPC builder generates a time-limited .sof file
This is a licensing issue you will encounter using the Web Edition of Quartus. When you download the
Quartus software, you also apply for a license file. It does not have the privileges to fully instantiate the
NIOS II software core. The free edition is stuck with this issue, but lab computers have full license
privileges and will not make a time-limited file. The lab and web edition may be slightly different. Be
aware the same VHDL files compiled at home and lab have exhibited slightly different behavior and can
cause language that works on one version to have errors on the other.
The Web Edition Quartus is contradictory about time limited files. Some documentation says it will stop
running after an hour, but when you program your board with Quartus, it has a dialogue box that
specifies unlimited time and has a cancel button. The hardware will work as long as this dialogue box is
open. You can use NIOS II IDE to upload and run code with Quartus still running.
NIOS IDE cannot connect to board when you try to run your software
This error indicates a problem communicating with the board for several possible reasons. First, make
sure you programmed your SOPC project with all pins correct. If the Cyclone II FPGA has bad pin
assignments to the processor core, the NIOS IDE will not connect to the JTAG module in that core. In
Quartus, view pin assignments. Import the pin file for the DE2(or appropriate board) and verify that all
signals from your top level module connect to appropriate DE2 pins. When making your top level file,
there is a DE2 Reference pdf describing the pin names that correspond to the DE2 pin file. I have
included these documents. Another possible cause of this is that the RESET pin in that pin file is mapped
to one of the switches and that switch is constantly resetting the board so the NIOS software can’t
maintain a connection.
Quartus wont compile, giving a “database error”
This is likely a problem with the z: drive here in lab. You can get to your project file directly through the z
drive or through my documents. These have different file paths as shown here:
Direct to Z from my computer:
Z:\Lab0
Accessed through my documents
\\rei.students.cset.oit.edu\zdrive\samuel.mancill\Lab0
Quartus doesn’t like the second method. To avoid this, do not double click your project icon to open
Quartus nor access it through my documents. Use the Quartus file menu and navigate to the z drive and
open from there. Alternatively, copy your project folder to the c: drive, work with it, then copy back to
your z drive when done.
Empty while loop won’t work
It has been documented that empty while loops need an inline assembly nop. This may change as new
versions of NIOS are released.
while (1) {
asm("nop"); };
Adding/modifying components doesn’t work
The current component editor is buggy. The new version of SOPC builder has compatibility issues with
the old one. In general, if you want to upgrade an existing component, it is easier to modify its .v and
.vhdl files and make a whole new component, then delete the existing component and add the new one.
To add components (.tcl files), place them in the same folder as your project and .ptf file, then select
“Refresh Component List” from the SOPC Builder File menu. Keep in mind that if you cannot get a SOPC
component to work, you can connect to Verilog and VHDL files through a PIO. This is easier for parallel
communications, but could be done with serial components by adding extra hardware. Tim Endicott’s
Display hardware lab is an example of using a PIO to connect to components.
What is the “altera_europa_support” file?
This is a testbench file provided for each SOPC project you make. It doesn’t exist but is included in your
project files. Ignore it and all warnings its generates. You can remove it from your project if you want.