Fall 2008 EE 410/510:
Microfabrication and Semiconductor Processes
M W 12:45 PM – 2:20 PM
EB 239 Engineering Bldg.
Instructor: John D. Williams, Ph.D.
Assistant Professor of Electrical and Computer Engineering
Associate Director of the Nano and Micro Devices Center
University of Alabama in Huntsville
406 Optics Building
Huntsville, AL 35899
Phone: (256) 824-2898
Fax: (256) 824-2898
email: williams@eng.uah.edu
High Volume MEMS:
Devices, Stability, Packaging
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Place MEMS die onto dip chip
package, wire bond, and vacuum seal
Issues:
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Dip chip packages are plastic
Ceramic dip chip packages are difficult
to seal
Long term metal to metal packaging fails
Difficult to achieve high vacuum for
device performance and maintain it over
years
Solution: Encapsulate the MEMS
device on chip then package the
MEMS/IC chip using standard
technologies
Figures taken from:
DMD commercial Success
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Robust Manufacturing with high yield and
single release process allows for
fabrication of Texas Instruments DLPs
Anodic Bond Package to transparent
Pyrex 7740 Glass provides sufficient
vacuum for DLP response
Package is sealed over large area with
wide bond seam to prevent long term
failure
Figures taken from:
Motorola / Freescale
Pressure Sensor
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Single Crystal sensor mounted in
injection molded thermoplastic case
Machined cap
Silicone oil (most tested oil in the
history of mankind)
No direct IC package integration.
Simple wire bonds from the package
are sufficient
Process utilizes 25 years of experience
in pressure sensors at Motorola
Very little work in novel MEMS process
development
No vacuum sealing of MEMS
component required
Figures taken from:
AMD Accelerometers
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First integrated surface microdevice on the market (1993)
Perhaps the largest market device in MEMS today
Package does not include MEMS encapsulation. Entire die is vacuumed hermetically sealed in IC package
Figures taken from:
Motorola’s MMA Air Bag Sensor
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3 layer poly process proven over
multiple years of preproduction
Complete IC integration
Packaging still performed at the die
level
No independent MEMS encapsulation
Figures taken from:
SOI Based Optical MEMS
by Analog Devices
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CNP and silicon bonding of multiple SOI
wafers allows for complete IC integration of
tilt mirror optics
SOI integration allows for low voltage
electronics and high voltage MEMS mirrors to
be integrated directly on the same die
Independence of MEMS is provided by
multilayer device fabrication and bonding
Encapsulation is still performed at the die
level
Figures taken from:
Package Protection from Dicing
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Dicing Problems with MEMS
MEMS components can be easily
damaged or destroyed by water and
particles present during the dicing
process
This is overcome by a number of
methods
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Release is often performed after dicing
Motorola and Bosch use glass frit is
used to seal MEMS components prior to
dicing then etched away after.
TI DLPs required a different solution
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First mirrors are released
Protective organic film placed on mirrors
allows for normal cleaning processes
Dicing occurs
Singulated chips are mounted on
ceramic packages prior to dry etching
organic layers
Figures taken from:
Packaging MEMS that need
Separate Encapsulation
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Conventional MEMS devices are fabricated,
packaged, and connected to IC control
circuits for commercial use
The more compatible the fabrication scheme
is with IC processing, the easier the device is
to integrate
However, some devices such as the one
pictured, are not directly compatible with IC
processing at all
In both cases, MEMS are manufactured,
packaged, integrated either on chip or off
chip with an IC, then packaged using dip chip
technology and released to the market
Problem: MEMS encapsulation is not simple
or easy
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Issues with bond seams
Issues with material compatibility
Issues with vacuum
Today: DARPA BAA call currently out to
generate a low power MEMS based high
vacuum device for integration directly into
MEMS packages. Cost will probably be
$2- 15M per team over 3 years depending
on nature of team and requirements for
industrial success
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The Big Question: How does one get the
MEMS component sealed from the remainder
of the IC and device package while still
providing sufficient interaction with the
sensing environment?????
Figures taken from:
Various Bonding Mechanisms
Figures taken from:
Permeability of Materials for
Packaging to Water
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Although some polymers such as BCB
are better than others, packaging with
polymers does not provide a long term
solution for commercial devices
Glasses provide relatively long term
seals if the width of the bond seam is
sufficient.
– bond seams are 0.25 -1mm wide
Metals provide best long term
hermiticity
– Al-to nitride
– Au eutectic:
• 0.08 mm bond seam for 320oC
• >0.25 mm bond seam for Temp
below 250 um
– AuIn eutectic: >0.3 mm bond seam
BCB Polymer bonding
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Advantages
– Low bond temp
– No metals
– Elastic (less worry about CTE
mismatches)
Disadvantages
– Long term permeability of water
– High vapor pressure
– Poor mechanical properties
Ideal upper limit: 1*10-9 mbar l/s
Sealant used was Si3N4
Gold Compression Bonding
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Au/Au eutectic:
0.08 mm bond seam for 320oC
>0.25 mm bond seam for Temp at
220oC
S.M. Spearing, C.H.Tau, M.A.Schmidt, “Gold
Thermocompression Bonding,” AMMNS 2008
K. Entesari, G. Rebeiz, “Allow-loss microstrip Surface
Mount K-band Package,” 36 European Microwave
Conference, 2006.
Anodic Bonding
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Bonds alkali glass such as Pyrex 7740
to Silicon
Best performance when CTE of glass
and substrate match
Stresses induced by thermal strains
can fracture device
Reasonably hermetic
Electrically insulated
Common process conditions
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Figures taken from:
200-300 oC
200-1000 V (400-600 V is usually
sufficient for 200 um seals)
Silicon Fusion Bonding
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Bonding performed in EV520 at 600oC
First bonded for 5 hrs
– Razor used to test bond strength at
side and base of wafer
Second bond for 12 hrs
– IR transmission measurements made
– About 5 or 6 measurable voids in the
wafer stack
– Only 1 over the devices near the
center of the wafer
Next Steps:
– Anneal in furnace for at least 2 hrs at
1100oC
– Perform CSAM measurements
– Dice stack
Issues: voids and stress cracks in complex
shapes
No long term testing of hermeticity
published to date
Void/ Newton fringe
Cracks in the
pattern
JDW/SNL
DARPA-NAV
PSG Packaging
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Process developed in early 90’s
Unable to meet long term cycling
demands
Very difficult to create high vacuum
seal in PSG packages
Figures taken from:
Aluminum Packaging
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Figures taken from:
High temperature processing of
Aluminum films on SiO2 or Si3N4 yields
hermetic seam between structures
Bond strength is estimated to be 270
MPA which is stronger than the glass
fracture strength
Al-to-Si3N4 RTP bonding
Figures taken from:
Combining PSG and Glass-Al-Poly
Figures taken from:
Resonator Performance
in MEMS Packaging
Figures taken from:
Previous Process uses Localized
Polysilicon Heater to Create Bond
Figures taken from:
Failure of Rapid Thermal
Processes Packages
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Predictions of the mean and standard deviation
time to failure (MTTF)
For worst case scenario 4 in 31 samples failed
by the end of the test
– 90% chance based on worst case that the
package will fail in 0.57 years
Figures taken from:
Accelerated Lifetime Testing
Figures taken from:
Example of Failed Package
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In all bond processes, localized
stresses lead to cracks and defects
The size of these defect regions
varies based on the process
capability of the bond scheme and
the process development team
Here one can see how stresses
might originate and the type of
failure that occurs over time
Figures taken from: