Virtex-5 FXT Platform
Press Backgrounder
March 31, 2008
Virtex-5 FXT FPGA – The Ultimate System Integration Platform
The age of digital convergence, with its tendency toward the proliferation and evolution of standards,
demanding processing requirements and ever-diminishing cost and time budgets, has accelerated the
world’s dependency upon the fundamental value propositions of the FPGA: flexibility, field upgradeability,
superior signal processing, faster time-to-market, risk mitigation, adaptability to evolving standards, and
lower system costs. Add high-speed serial connectivity and embedded processing to this robust list and
you have the makings for the ultimate system integration platform – the Virtex®-5 platform.
The Virtex-5 FXT platform is the only FPGA technology that combines industry-standard 550MHz
PowerPC® 440 embedded processor cores, DSP and high-speed serial I/O capabilities to deliver
unparalleled system integration for driving high-performance applications in the Communications, Audio
Video Broadcast, Military and Aerospace, Industrial, Scientific, and Medical markets. Using the Virtex-5
FXT platform, designers working on these applications can improve overall system performance,
minimize board complexity and reduce system costs.
Virtex-5 Family
The Virtex-5 family of platform FPGAs are the industry’s leading high-density 65nm FPGAs, both in terms
of product availability and the choices offered to customers. The Virtex-5 family is the fifth generation in
the Virtex series of FPGAs. Built on the unique ASMBL architecture, the Virtex-5 family offers customers
a choice of four domain-optimized platforms comprising 24 devices:
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LX – optimized for the logic domain
LXT – optimized for the logic domain with low-power serial connectivity
SXT – optimized for the DSP domain with serial connectivity
FXT – optimized for the embedded processing domain with high-speed serial connectivity
The family delivers a host of innovative features including:
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Ultra-fast ExpressFabric™ technology with new CLB and enhanced routing
Fully integrated PCI Express® Endpoint Blocks on LXT, SXT, and FXT platforms
Fully integrated Tri-Mode (10/100/1000 Mbps) Ethernet MAC blocks on LXT, SXT, FXT platforms
36Kbit dual-port BRAM/FIFO blocks with ECC option
550Mhz Clock Management Tile (CMT) with PLLs
SelectIO with ChipSync technology
Second generation sparse chevron packaging technology with enhanced pinout
Multi-bitstream management and more granular frame size for easier partial reconfiguration
The Virtex-5 FXT Platform adds key features for system integration:
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Fully integrated PowerPC 440 Processor block and 128-bit interconnect
High-performance GTX 6.5 Gbps serial I/Os
Optimum mix of XtremeDSP™ slices (DSP48E slices)
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Table 1 – The Virtex-5 FXT Product Offering
PowerPC 440 Processor Block
The PowerPC 440 processor is tried and proven in system applications in numerous market segments
served by Xilinx high-density FPGAs. The Virtex-5 FXT FPGAs are the first to provide up to two industrystandard PowerPC 440 processors with enhanced system performance capabilities to enable designers
to rapidly and easily implement advanced scalable, embedded processing applications. Each processor
delivers up to 1,100 DMIPS @ 550MHz, with integrated 32KB instruction and 32KB data caches.
The key to unlocking increased processing system performance is the ability to increase overall data
throughput via multiple, efficient, concurrent high-speed data accesses. To that end, the new integrated
5x2 cross bar processor interconnect architecture tightly coupled to the PowerPC 440 processor provides
simultaneous access to I/O and memory (Figure 1). This highly integrated architecture supports five
master and two slave PLB (processor local bus) interfaces, four DMA ports with separate Transmit and
Receive channels for full-duplex operation, and a dedicated memory bus interface, thereby increasing
memory bandwidth by up to 5X over previous solutions. The new “hardened’ crossbar switch manages
the system data to enable simultaneous accesses to the multiple busses that handle 128-bit transactions
(previous 64-bit) to further maximize system throughput. The advanced PLB architecture maximizes data
transfers between the processor, crossbar and soft IP (Intellectual Property) logic with high-throughput
128-bit interfaces to help minimize system bottlenecks.
Figure 1 – The PowerPC 440 Block includes PowerPC 440 core and new interconnect architecture
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To complement the new architecture, the platform’s enhanced high-performance Auxiliary Processor
Control Unit (APU) interface allows users to build an auxiliary processor to execute instructions that are
not part of the PowerPC 440 instruction set. This support provides added connectivity for dedicated coprocessing engines or custom, user-defined instructions for applications such as video processing, 3D
data processing and floating-point math.
High-Speed Serial Connectivity
Supporting the hottest trend in digital I/O, multi-gigabit serial I/O, the Virtex-5 FXT platform provides up to
24 full-featured RocketIO™ Gigabit transceivers (GTXs). The enhanced transceivers now support data
rates from 500Mbps up to 6.5Gbps. Extending the proven transceiver architecture available in the
Virtex-5 LXT and SXT FPGAs, the Virtex-5 FXT GTX transceivers are the fastest available within the
Virtex-5 family and provide the facility to easily migrate between Virtex-5 LXT, SXT & FXT platforms.
The additional high data-rate gains are provided while constraining power consumption to just 200mW
typical power per channel at 6.5Gbps. Running at the lower 3.75 Gbps, power is a mere 100mW per
channel.
Along with higher serial I/O performance, a few key features have also been enhanced. To improve signal
integrity at these high speeds, a 4-tap Decision Feedback Equalizer (DFE), linear equalizer and transmit
pre-emphasis have been included. A DFE is a nonlinear equalizer that uses previous detector decision to
eliminate the Inter-symbol Interference (ISI) on pulses that are currently being demodulated. The
advantage of a DFE implementation is that it operates on noiseless quantized levels, and thus its output
is free of channel noise.
The GTX transceivers provide a new flexible rate converter, or gearbox, that supports 8B/10B, 64B/66B
and 64B/67B encoding and synchronization for leading-edge protocols. Independent transmit and receive
data streams allow full-duplex operation.
Complete protocol packs for PCI Express®, Gigabit Ethernet and XAUI provide a low-risk path to design
success. The packs also offer protocol-specific characterization reports for SONET OC-48/SDH STM-16
and CPRI (Common Public Radio Interface), enabling customers to adopt a new serial protocol with
confidence. Each standard protocol pack includes protocol-specific PHY characterization reports,
interoperability and compliance reports, IP cores and documentation to facilitate low-risk and efficient
implementation of standardized high-speed serial protocols in Virtex-5 FPGAs.
System-Level Digital Signal Processing
The Virtex-5 FXT platform’s DSP performance is a major contributor to its value as the ultimate system
integration platform. Fundamentally, FPGAs offer orders-of-magnitude higher DSP performance than the
fixed architectures of traditional DSP processors, at a time when a growing number of communications
and multimedia systems require DSP performance well above 4 mega-samples per second (MSPS),
thereby exceeding the limits of most stand-alone DSP processors.
FPGAs facilitate the creation of highly parallel processing architectures that can perform complex
algorithms in a single clock cycle, literally delivering hundreds of MSPS with a single device. At these
DSP performance levels, the system designer can choose to lower the clock rate of the FPGA to save
power or implement more channels to lower system cost and reduce the bill of materials (BOM).
The key to the Virtex-5 FPGA family DSP capabilities is the DSP48E slice which performs the multiplyaccumulate operation underlying most digital filters. FPGAs with built-in multiplier blocks enable DSP
designers to achieve high performance by implementing dedicated hardware for wide filters. Virtex-5 FXT
FPGAs provide a high ratio of DSP slices comprising up to 384 built-in 18x25 DSP slices and delivering
up to 192 GMACs/second at 500MHz. The Virtex-5 DSP48E slice also features a larger multiplier size—
25x18 vs. 18x18 in Virtex-4. Matched with a wider data path and a 96-bit accumulated output to enable
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higher precision, single-precision floating point operation, the DSP48E slice consumes fewer resources
for high-precision filter operations.
In addition to fast logic execution, a high-performance system requires the ability to move large amounts
of data in and out of the processing element. Virtex FPGAs offer two complimentary approaches for
building efficient memory structures:
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Distributed RAM built from memory cells in the look-up-table (LUT) logic structures support the
implementation of 64-bit shift-registers
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Embedded BlockRAM structures offer up to 16.5 Mbits of memory in 36-Kbit blocks
Since the embedded BlockRAM structures are on chip alongside the DSP48E slices, they provide an
ultra-high-bandwidth means of delivering data to filter architectures. The FXT platform offers up to 16.5Mb
of internal memory, and total IO bandwidth of 163 GBytes/s aggregate IO performance to address
system-level requirements.
System Integration Enhancements Increase Performance
The performance benefits derived from the system integration enhancements of the Virtex-5 FXT FPGA
are best understood as a composite effect of improvements to the platform’s processing subsystem.
Overall system performance is improved by moving away from a single shared-bus interconnect paradigm
to a crossbar interconnect with a network of multiple independent buses that move data around in
parallel. Multiple operations occur concurrently to enable a performance increase (reduces stalls and
waiting). Using 128-bit data transfers provides additional throughput increase.
Figure 2 – On the Virtex-5 FXT platform, the new PowerPC 440 processor block interfaces with a hard Tri-mode Ethernet
MAC via the hard Crossbar interconnect.
As an example, the Gigabit Ethernet design in Figure 2 shows a typical connection of the Memory
Controller (soft, in fabric) to the Memory Controller Interface (MCI) in the crossbar switch. Overall latency
and bandwidth is improved as this is a dedicated port independent of other access such as peripheral
transaction. Peripherals (soft) are attached to the PLB46 Bus and connected to an independent Master
PLB (MPLB) port on the crossbar switch.
The Gigabit Ethernet connection to the system is through one of the new hardened DMA controllers. The
DMA engine also interfaces to the crossbar switch, which serves as the pathway from the DMA engine to
main memory when needed. The Gigabit Ethernet design also uses the hardened Gigabit Ethernet MAC
integrated in the Virtex-5 FXT platform, thereby using fewer resources and reducing power consumption.
The performance of the above Gigabit Ethernet example on a Virtex-5 FXT platform-based system
compared with an equivalent system running on the Virtex-4 FX platform delivers a 2.7X increase in
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performance. This performance improvement is total system level throughput – not just for the processor,
peripherals or I/O.
Applications
The composite of sophisticated Virtex-5 FXT platform’s system integration capabilities derives from the
increasingly stringent and highly diversified requirements arising from a variety of complex applications in
four key industries—Wired and Wireless Communications, Audio/Video Broadcast, Aerospace and
Defense, and the Industrial, Scientific and Medical markets. Xilinx customers in these markets have
contributed substantially to the definition of the FXT product line, and have helped drive the device
configurations where FPGA logic, embedded processing, DSP, memory and Serial IO requirements all
meet.
Communications
The wireless communication market is a fast changing and challenging environment. System designers
are constantly challenged to provide new solutions, either to achieve cost reductions for existing products
or to provide a risk-free infrastructure migration methodology that ensures cost-effective support for both
the current and next generation of technology, i.e., 3GPP-LTE and WiMAX.
Figure 4- A Next-Generation Wireless Basestation (LTE) built with a Virtex-5 FX100T device.
Using the Xilinx Virtex-5 FXT FPGA in this application provides a tightly-coupled integration of processor
subsystem, DSP-enabled FPGA fabric, and high-speed communication. Both the hardware and software
elements of the LTE Baseband Reference System are integrated on a single Xilinx Virtex-5 FX100T
device using standard hardware boards.
Audio/Video Broadcast
Video-Over-IP systems encode a video stream using compression standards such as MPEG-2. The
system then utilizes an Internet Protocol (IP) to transmit the encoded bit stream between points on the
network. Unlike other traffic on a network that is non-time-critical, video data must adhere to strict Quality
of Service (QoS) requirement to fulfill video needs.
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A discrete implementation to achieve these requirements can be built today using a video processor,
programmable logic to accelerate or perform real-time algorithms, and an Ethernet solution for
communication to the network. The Virtex-5 FXT FPGA is the first to address all of these types of
functions in a single programmable SOC.
Figure 4 – A Video-Over-IP system integration example illustrates the advanced requirements.
Ultimate Design Solutions
The ultimate system integration platform clearly necessitates the creation of a unified design
environment—one that delivers the ultimate in productivity and performance for the full spectrum of
system-level platform elements and capabilities available through Xilinx FPGAs.
To this end, Xilinx has created ISE™ Design Suite 10.1 to deliver all of the development and debug tools
required for a systems team to create a sophisticated end solution that integrates flexible FPGA logic,
embedded processing, high-speed serial IO, DSP, on-board memory design and interfacing, and
customizable blocks of IP. The ISE Design Suite integrates several award winning design tools and
technologies to facilitate and streamline system development. The suite encompasses the following:
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FPGA Design Environment
- ISE Foundation™ Software and ISE WebPACK™ Software (Free Download)
- PlanAhead™ Design and Analysis Tool and PlanAhead Lite
- SmartXplorer™
Embedded Processing Design Environment
- Xilinx Platform Studio and the Embedded Development Kit (EDK)
DSP Design Environment
- System Generator for DSP
- AccelDSP™ Synthesis Tool
Platform Debug Support
- ChipScope™ Pro Tool
- ChipScope Pro Serial I/O Toolkit
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To start the overview of the ISE Design Suite, ISE Foundation Software is the industry’s premier FPGA
logic design tool set. Coupled with ISE Foundation is the Xilinx PlanAhead Design Analysis tool that
provides an environment to analyze and floorplan a design targeting any of Xilinx industry leading
FPGAs. In addition, SmartXplorer Technology enables designers to complete more implementation runs
per day, and up to 38 percent faster performance.
For embedded system design, Xilinx Platform Studio and the Embedded Development Kit (EDK) delivers
an integrated HW and SW design environment to accelerate embedded system design.
The XtremeDSP Development Tools Package includes System Generator for DSP and the AccelDSP
Synthesis Tool. These tools provide an FPGA implementation path for DSP algorithms developed using
the popular MATLAB® and Simulink® DSP modeling environments from The MathWorks™.
ChipScope Pro performs “platform” debug that can find those tricky embedded bugs that live somewhere
between HW & SW. The ChipScope Pro Serial I/O Toolkit enables users to rapidly evaluate and measure
the Bit Error Ratio (BER) of high-speed serial I/O channels.
Summary
System integration is a phenomenon that has remained consistently and strategically invaluable to the
electronics industry as a fundamental means for reducing cost, improving performance, and migrating
system-level technologies to the next milestone—shrinking boxes to boards and boards to ICs (ASICs
and ASSPs).
When added to the fundamental FPGA value propositions, the powerful blend of embedded processing
capabilities, DSP performance and high-speed serial connectivity afforded by this latest addition to the
Xilinx product offering sets Virtex-5 FXT FPGAs apart as the ultimate system integration platform.
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