Electrical Engineering Department EE115C
Having been armed with the skills to do Layout ( Tutorial 3 ) and produce Schematic-Driven Layout
( Tutorial 4 ) in Cadence 6, you should be able and are strongly encourages to follow the
Hierarchical Design portion of Cadence 5 Tutorial 5 (up to Extraction). This will help you grasp how bigger layouts (that are composed of smaller cells) are put together.
*This tutorial is different from the Cadence 5 tutorial 5 . The layout extraction flow has been updated and additional information on post-layout simulation of a testbench including different cell views has been provide. (Which will help with your project).
For this tutorial we create a sample test bench in our ee115c library and call it tb_INVX1 . Here is how your testbench should look like:
This is a simple testbench that instantiates cells we have previously made in our ee115c library:
INVX1 (Schematic in Tutorial 1 and layout in Tutorial 3 ), and FO4_inv_stage (Schematic in
Tutorial 2 ). Other components ( VDD , GND , and Vpulse ) are standard items from analogLib / basic libraries.
Before we can perform post-layout simulation, we need to extract layout of the INVX1 cell.
To do this open the layout view for INVX1 from the Library Manager .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 1

Electrical Engineering Department EE115C
Before extraction, both DRC and LVS checks need to be passed. Perform these checks to make sure your layout is clean (see Tutorials 3 and 4 for reference):
Now QRC can be used to extract the layout. Run QRC from QRC > Run Assura-QRC .
If you get the following warning, click close .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 2

Electrical Engineering Department
Following Window will pop-up:
EE115C
In the Setup tab , choose Extracted View for Output . Make sure Setup Dir is checked and set as the following:
/usr/public.2/ee115c/cadence-labs/gpdk090_v3.4/assura/rcx
Click on the Extraction tab .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 3

Electrical Engineering Department EE115C
Choose RC as the Extraction Mode (both resistance and capacitance) and Schematic
Names as the Name Space . Also make sure the Ref Node is gnd .
Walk through other tabs just for exercise, but don’t change anything. Click OK .
You can monitor your run throughout the
Progress Form .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 4

Electrical Engineering Department
When your run is completed, the following window will pop-up.
Click Close .
This will be part of the run report (sitting in your directory): rcx.INVX1.log
EE115C
Now let’s go to the Library Manager window and open av_extracted cell view. (Shown on the right).
You can see layout annotated with transistor symbols indicating extracted components.
Also by zooming in (at the input pin for example), you will see parasitic components that are extracted. (See below).
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 5

Electrical Engineering Department EE115C
Now we have both the schematic and av_extracted views for our INVX1 cell (or your project design). How can we simulate to see the performance difference?
From the Cadence 5 Tutorial 5 , the idea of doing this is covered for an example of ring oscillator.
However, you may find that you cannot directly follow the same steps to simulate your project design. In the ring oscillator example, we have both views for the ring oscillator and simulate from the cell itself. While in the Absolute-Value Detector case, we have both views for
Abs_Value_Detector cell but simulate from the cell tb_project . Such complicated situation requires a complicated solution !!
For demonstration here, consider the sample testbench introduced in the beginning of this tutorial.
The figure below is the schematic of tb_INVX1 . You can see that it includes multiple circuit elements. Among them, only INVX1 has both schematic and av_extracted views. The others have just schematic view.
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 6

Electrical Engineering Department EE115C
Here are the steps that we need to follow:
1.
Create a config view tb_INVX1 .
To do this, choose File > New > Cellview… from Library Manager .
Change View Name to config . Then tool should automatically change the Type to config , and Application to Hierarchy-Editor , as shown below.
Click OK .
Two windows should pop up:
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 7

Electrical Engineering Department EE115C
In the New Configuration window, click Use Template . The following window appears.
Specify Name as spectre and click OK .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 8

Electrical Engineering Department EE115C
Then change View to schematic (instead of myView ) in the New Configuration window.
Click OK again.
Now a list of included circuit elements is shown below.
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 9

Electrical Engineering Department EE115C
You can see that by default we use schematic view for INVX1 . Save and exit this window.
Now you can find a new config view of tb_INVX1 in Library Manager .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 10

Electrical Engineering Department EE115C
2.
Run Simulation from config view.
If we double click on config view from Library Manager , the following window appears. Since right now we do not want to change the previously saved configuration, we choose no in the first row and yes in the second row. This means that we are opening the schematic of tb_INVX1 with configuration we set.
And schematic shows up. You can simulate your circuit the same as you did before.
Recall that the current configuration uses the schematic view of INVX1 , so it is a schematic simulation.
If you wish to do a post-layout simulation , double click on config view again. This time, we choose yes in the first row and no in the second row and click ok .
Change configuration by right clicking on the row with cell INVX1 and choosing Set Cell
View > av_extracted .
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 11

Electrical Engineering Department EE115C
Save and exit the Hierarchy Editor . With this configuration, you switch to use the av_extracted view of INVX1 to run simulation, which gives a different performance.
Double click config view and open schematic of tb_INVX1 to run simulation with new configuration. By editing with Hierarchy Editor, you can always change the view to be used back and forth.
Hope you have had fun with Cadence!!
Good luck finishing up your project 
Cadence 6 Tutorial 5*: Layout Extraction & Post-Layout Verification 12