Transistor Basics - MOSFETs
© Bob York
Transistors, Conceptually
So far we have considered two-terminal devices that are described by a
current-voltage relationship I=f(V)
I V / R
I  C dV
• Capacitors:
dt
• Inductors:
I  1 Vdt
L
• Diodes:
I  I s eV / nVT  1
• Resistors:

I(V)
V
Transistors add a third terminal to control the current flow through the device.
The two most common types of transistors are:
• Field-Effect Transistors (FETs):
voltage-controlled current flow
• Bipolar Junction Transistors (BJTs):
current-controlled current flow
I(V, Vc) FETs
Control
Terminal
Vc or Ic
or
V
I(V, Ic) BJTs
In ECE 2, we will not discuss the physics of device operation in depth.
The transistor is simply a black box with certain well-defined terminal properties.
© Bob York
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MOSFETs
There are many types of FETs but all share some
common features and nomenclature.
Drain
NMOS
Drain
Key points:
• Every FET has a gate, drain, and source
• Current flows between the drain and source.
• The gate is the control terminal.
• The DC gate “leakage” current is negligible, Ig≈0
Gate
Gate
Source
Vds
Ids(Vgs,Vds)
Vgs
Source
Start with n-channel enhancement MOS (NMOS)
(MOS=Metal-Oxide-Semiconductor).
Current-Voltage Characteristic for NMOS
Ig ≈ 0
D
Id
G
Vds
Vgs
S
Id
Drain Current
If we take the source as the voltage reference
(ground), the drain current will depend on the
gate voltage and drain voltage as shown :
Vgs
Ga
te
“Common-source” configuration
© Bob York
Vo
l ta
ge
ge
olta
V
in
Dra
Vds
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Common-Source NMOS Characteristic
Ig = 0
Id vs Vds for specific values of Vgs
ID
Vds= Vgs-Vt
Ohmic or
Triode region
Saturation region
D
Vgs= Vtn + 1.0
Vgs= Vtn + 0.5
Vds  Vgs  Vtn
Vds
Vgs
S
ID
Increasing Vgs
I d  K n (Vgs  Vtn ) 2
Vgs ≤ Vtn (cutoff)
Vds
I-V Curves are described analytically by:
 K n  2(Vgs  Vtn )Vds  Vds2  Vds  Vgs  Vtn

 

Id  
K n (Vgs  Vtn ) 2
Vds  Vgs  Vtn


0
Vgs  Vtn

© Bob York
Id vs Vgs in saturation:
G
Vgs= Vtn + 2.0
Vgs= Vtn + 1.5
Id
Device is “off”
no current flows
N-channel Enhancement MOS
Vt
Vgs
Important observations:
• No current flows for Vgs< Vtn. Vtn is called the
“Threshold voltage”
• Once the drain voltage exceeds Vgs-Vtn, a
constant current flows that depends on Vgs
• For enhancement-mode NMOS the gate
threshold voltage is positive Vtn>0
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MOSFET Saturation Region
The saturation region is especially important.
The NMOS device is in saturation when the following conditions are satisfied:
Vds  Vgs  Vt
Vgs  Vt
When the device is in saturation the drain current is given by:
ID
Kn depends on some material constants and
the device size/geometry
Device #2
Vgs
It is difficult to control Kn and Vt precisely, so
two different discrete devices may have
significant differences in these parameters
Later we will explore some circuit techniques
to deal with this issue
Note: state-of-the-art devices may follow a different behavior:
where α is closer to 1
© Bob York

2
Kn and Vt are the important device parameters.
Device #1
Vt1 Vt2

I d  K n Vgs  Vt

I d  K n Vgs  Vt


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NMOS Saturation - Examples
Vt  1V
In the following, the devices have parameters:
Consider:
Here we have: Vds  10 V
+10 V
Vg=3V
Id
Vds
+5 V
Thus device is in saturation and


Here we have:
5 mA
Vout
Vds
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Vgs  Vt
I d  5mA/V 2  3V  1V   20 mA
Vgs
Vgs
Vgs  3V
Vds  Vgs  Vt and
so
K n  5mA/V 2
so
2
Vds  Vgs  Vout
Vds  Vgs  Vt

Device is in saturation so I d  5mA= 5mA/V
From this we find
2

Vgs  1V

2
Vgs  2 V
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Common-Source PMOS Characteristic
Similar characteristics to PMOS except
currents and voltages are reversed
S
D
Vsg= Vtp + 1.0
Id
By convention the threshold voltage for
enhancement-mode PMOS is taken as negative
 K p  2(Vsg  Vtp )Vsd  Vsd2  Vsd  Vsg  Vtp

 

Id  
K p (Vsg  Vtp ) 2
Vsd  Vsg  Vtp


Vsg  Vtp
0

© Bob York
Vsg= Vtp + 1.5
Vsd
G
Ig = 0
Vsg= Vtp + 2.0
Vsg= Vtp + 0.5
Vsg ≤ Vtp (cutoff)
Vsd
Id vs Vsg in saturation:
ID
Device is “off”
no current flows
Vsg
ID
Vsd= Vsg+Vtp
Ohmic or
Triode region
Saturation region
Increasing Vsg
P-channel Enhancement MOS
I d  K p (Vsg  Vtp ) 2
-Vtp
Vsg
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PMOS Saturation - Examples
Vtp  1V
In the following, the devices have parameters:
Consider:
Here we have: Vsd  10 V
+10 V
Vg=6V
Id
Vsg
Vsd
K p  5mA/V 2
Vsg  4 V
Vsd  Vsg  Vtp and Vsg  Vtp
so
Thus device is in saturation and


I d  5mA/V 2  4 V  1V   45mA
+5 V
Here we have:
Vsg
Vsd
so
2
Vsd  Vsg  Vout
Vsd  Vsg  Vtp

Device is in saturation so I d  20 mA= 5mA/V
20 mA
© Bob York
Vout
From this we find
Vsg  3V
2

Vsg  1V

2
Vout  5V  3V  2 V
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Depletion-Mode FETs
Enhancement-mode devices are “normally off” devices, since no current flows when Vgs=0. A
certain applied gate voltage is required to “turn on” the device and get current flowing
Depletion-mode devices are “normally on”. They conduct current at Vgs=0, and an applied
gate voltage is required to stop the current flow and turn them “off”
N-channel Depletion-mode MOS
D
Ig = 0
P-channel Depletion-mode MOS
Id
Vsg
G
Vds
Vgs
Ig = 0
S
Id vs Vsg in saturation:
I dss
Vgs
I d  K p (Vsg  Vtp )
2
Id
ID
I dss
Device is “off”
no current flows
Threshold
voltage has the
opposite sign in
comparison to
enhancement
devices.
Otherwise the
characteristics
are similar.
I d  K n (Vgs  Vtn ) 2
Device is “off”
no current flows
D
symbol
Id vs Vgs in saturation: ID
© Bob York
Vsd
G
symbol
Vtn
S
-Vtp
Vsg
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MOSFET Construction
Source
Gate
Lg
Gate oxide
Drain
Key parameters: Lg : gate length
Wg : gate width
cox : oxide capacitance density
 : carrier mobility in semiconductor
Wg
Saturation current parameter:
Semiconducting substrate
N-channel
“Body” connection
Kn 
P-channel
Wg 1 Wg
1
 kn
n cox
2
Lg 2 Lg
Kp 
Wg 1 Wg
1
 k p
 p cox
2
Lg 2
Lg
Engineers control whether a device is an enhancement or depletion device by adding
carefully-controlled amounts of impurities (‘dopants”) in the semiconductor
Enhancement Devices
Vgs  0
No charge carriers exist
under the gate, so no
current flow is possible
© Bob York
Vgs  Vt
An applied field allows
charge to accumulate
under the gate allowing
current to flow
Depletion Devices
Vgs  0
Charge carriers
naturally accumulate
under the gate, allowing
current to flow
Vgs  Vt
The applied field
depletes the charge in
the channel, cutting off
the flow of current
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JFETs
Drain
N-ch JFET
Drain
Gate
Gate
Vds
Ids(Vgs,Vds)
Vgs
Source
JFETs are another type of depletion-mode FET. They are
constructed differently but otherwise behave much like a
depletion MOSFET, except that Vgs can never exceed zero
volts. The maximum current at Vgs=0 is Idss.
JFETs can be made in both n-channel and p-channel
versions. Some high-speed compound semiconductor
devices (GaAs MESFETs and HEMTs) behave like JFETs
Source
N-ch JFET
ID
Ohmic or
Triode region
Saturation region
Vgs= 0
Idss
Vgs= Vt + 1.5
G
Vgs
Id
Vds
Vgs= Vt + 1.0
S
Increasing Vgs
D
Ig = 0
Vgs= Vt + 0.5
Vgs ≤ Vt (cutoff)
© Bob York
Vds
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FET Family Tree
Field-Effect Transistors
JFET, MESFET
Depletion-mode
(normally on)
n-ch
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p-ch
MOSFET
Enhancement-mode
(normally off)
n-ch
p-ch
Depletion-mode
(normally on)
n-ch
p-ch
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Discrete Device Example: 2N7000
This is a popular discrete NMOS device
that we will use in the ECE 2 lab.
2N7000
From the data sheet:
A
ID
Drain
Gate
Vds
Vgs
Vds
Source
2N7000Data
Measured
120
Vt  2.35V
100
K n  220mA/V
Data
2
The data sheet specifies that Vt is between
0.8V and 3V, with a typical value of 2.1V.
Model
Id, mA
80
Such a wide range of expected Vt is typical
of many discrete devices.
60
40
Representative data for small currents is
shown at left
20
0
2.2
© Bob York
2.4
2.6
2.8
Vgs, Volts
3.0
3.2
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